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mlx4_en: Fix BQL reset TX queue call point
[linux-2.6/btrfs-unstable.git] / drivers / watchdog / sp5100_tco.c
blob2b0e000d4377de2714cbadcfb557c32c33a16321
1 /*
2 * sp5100_tco : TCO timer driver for sp5100 chipsets
3 *
4 * (c) Copyright 2009 Google Inc., All Rights Reserved.
5 *
6 * Based on i8xx_tco.c:
7 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
8 * Reserved.
9 * http://www.kernelconcepts.de
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
17 * AMD Publication 45482 "AMD SB800-Series Southbridges Register
18 * Reference Guide"
19 */
20
21 /*
22 * Includes, defines, variables, module parameters, ...
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/types.h>
30 #include <linux/miscdevice.h>
31 #include <linux/watchdog.h>
32 #include <linux/init.h>
33 #include <linux/fs.h>
34 #include <linux/pci.h>
35 #include <linux/ioport.h>
36 #include <linux/platform_device.h>
37 #include <linux/uaccess.h>
38 #include <linux/io.h>
39
40 #include "sp5100_tco.h"
41
42 /* Module and version information */
43 #define TCO_VERSION "0.03"
44 #define TCO_MODULE_NAME "SP5100 TCO timer"
45 #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
46
47 /* internal variables */
48 static u32 tcobase_phys;
49 static u32 resbase_phys;
50 static u32 tco_wdt_fired;
51 static void __iomem *tcobase;
52 static unsigned int pm_iobase;
53 static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
54 static unsigned long timer_alive;
55 static char tco_expect_close;
56 static struct pci_dev *sp5100_tco_pci;
57 static struct resource wdt_res = {
58 .name = "Watchdog Timer",
59 .flags = IORESOURCE_MEM,
60 };
61
62 /* the watchdog platform device */
63 static struct platform_device *sp5100_tco_platform_device;
64
65 /* module parameters */
66
67 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
68 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
69 module_param(heartbeat, int, 0);
70 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
71 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
72
73 static bool nowayout = WATCHDOG_NOWAYOUT;
74 module_param(nowayout, bool, 0);
75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
76 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
77
78 static unsigned int force_addr;
79 module_param(force_addr, uint, 0);
80 MODULE_PARM_DESC(force_addr, "Force the use of specified MMIO address."
81 " ONLY USE THIS PARAMETER IF YOU REALLY KNOW"
82 " WHAT YOU ARE DOING (default=none)");
83
84 /*
85 * Some TCO specific functions
86 */
87 static void tco_timer_start(void)
88 {
89 u32 val;
90 unsigned long flags;
91
92 spin_lock_irqsave(&tco_lock, flags);
93 val = readl(SP5100_WDT_CONTROL(tcobase));
94 val |= SP5100_WDT_START_STOP_BIT;
95 writel(val, SP5100_WDT_CONTROL(tcobase));
96 spin_unlock_irqrestore(&tco_lock, flags);
97 }
98
99 static void tco_timer_stop(void)
100 {
101 u32 val;
102 unsigned long flags;
103
104 spin_lock_irqsave(&tco_lock, flags);
105 val = readl(SP5100_WDT_CONTROL(tcobase));
106 val &= ~SP5100_WDT_START_STOP_BIT;
107 writel(val, SP5100_WDT_CONTROL(tcobase));
108 spin_unlock_irqrestore(&tco_lock, flags);
109 }
110
111 static void tco_timer_keepalive(void)
112 {
113 u32 val;
114 unsigned long flags;
115
116 spin_lock_irqsave(&tco_lock, flags);
117 val = readl(SP5100_WDT_CONTROL(tcobase));
118 val |= SP5100_WDT_TRIGGER_BIT;
119 writel(val, SP5100_WDT_CONTROL(tcobase));
120 spin_unlock_irqrestore(&tco_lock, flags);
121 }
122
123 static int tco_timer_set_heartbeat(int t)
124 {
125 unsigned long flags;
126
127 if (t < 0 || t > 0xffff)
128 return -EINVAL;
129
130 /* Write new heartbeat to watchdog */
131 spin_lock_irqsave(&tco_lock, flags);
132 writel(t, SP5100_WDT_COUNT(tcobase));
133 spin_unlock_irqrestore(&tco_lock, flags);
134
135 heartbeat = t;
136 return 0;
137 }
138
139 static void tco_timer_enable(void)
140 {
141 int val;
142
143 if (sp5100_tco_pci->revision >= 0x40) {
144 /* For SB800 or later */
145 /* Set the Watchdog timer resolution to 1 sec */
146 outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
147 val = inb(SB800_IO_PM_DATA_REG);
148 val |= SB800_PM_WATCHDOG_SECOND_RES;
149 outb(val, SB800_IO_PM_DATA_REG);
150
151 /* Enable watchdog decode bit and watchdog timer */
152 outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
153 val = inb(SB800_IO_PM_DATA_REG);
154 val |= SB800_PCI_WATCHDOG_DECODE_EN;
155 val &= ~SB800_PM_WATCHDOG_DISABLE;
156 outb(val, SB800_IO_PM_DATA_REG);
157 } else {
158 /* For SP5100 or SB7x0 */
159 /* Enable watchdog decode bit */
160 pci_read_config_dword(sp5100_tco_pci,
161 SP5100_PCI_WATCHDOG_MISC_REG,
162 &val);
163
164 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
165
166 pci_write_config_dword(sp5100_tco_pci,
167 SP5100_PCI_WATCHDOG_MISC_REG,
168 val);
169
170 /* Enable Watchdog timer and set the resolution to 1 sec */
171 outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
172 val = inb(SP5100_IO_PM_DATA_REG);
173 val |= SP5100_PM_WATCHDOG_SECOND_RES;
174 val &= ~SP5100_PM_WATCHDOG_DISABLE;
175 outb(val, SP5100_IO_PM_DATA_REG);
176 }
177 }
178
179 static void tco_timer_disable(void)
180 {
181 int val;
182
183 if (sp5100_tco_pci->revision >= 0x40) {
184 /* For SB800 or later */
185 /* Enable watchdog decode bit and Disable watchdog timer */
186 outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
187 val = inb(SB800_IO_PM_DATA_REG);
188 val |= SB800_PCI_WATCHDOG_DECODE_EN;
189 val |= SB800_PM_WATCHDOG_DISABLE;
190 outb(val, SB800_IO_PM_DATA_REG);
191 } else {
192 /* For SP5100 or SB7x0 */
193 /* Enable watchdog decode bit */
194 pci_read_config_dword(sp5100_tco_pci,
195 SP5100_PCI_WATCHDOG_MISC_REG,
196 &val);
197
198 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
199
200 pci_write_config_dword(sp5100_tco_pci,
201 SP5100_PCI_WATCHDOG_MISC_REG,
202 val);
203
204 /* Disable Watchdog timer */
205 outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
206 val = inb(SP5100_IO_PM_DATA_REG);
207 val |= SP5100_PM_WATCHDOG_DISABLE;
208 outb(val, SP5100_IO_PM_DATA_REG);
209 }
210 }
211
212 /*
213 * /dev/watchdog handling
214 */
215
216 static int sp5100_tco_open(struct inode *inode, struct file *file)
217 {
218 /* /dev/watchdog can only be opened once */
219 if (test_and_set_bit(0, &timer_alive))
220 return -EBUSY;
221
222 /* Reload and activate timer */
223 tco_timer_start();
224 tco_timer_keepalive();
225 return nonseekable_open(inode, file);
226 }
227
228 static int sp5100_tco_release(struct inode *inode, struct file *file)
229 {
230 /* Shut off the timer. */
231 if (tco_expect_close == 42) {
232 tco_timer_stop();
233 } else {
234 pr_crit("Unexpected close, not stopping watchdog!\n");
235 tco_timer_keepalive();
236 }
237 clear_bit(0, &timer_alive);
238 tco_expect_close = 0;
239 return 0;
240 }
241
242 static ssize_t sp5100_tco_write(struct file *file, const char __user *data,
243 size_t len, loff_t *ppos)
244 {
245 /* See if we got the magic character 'V' and reload the timer */
246 if (len) {
247 if (!nowayout) {
248 size_t i;
249
250 /* note: just in case someone wrote the magic character
251 * five months ago... */
252 tco_expect_close = 0;
253
254 /* scan to see whether or not we got the magic character
255 */
256 for (i = 0; i != len; i++) {
257 char c;
258 if (get_user(c, data + i))
259 return -EFAULT;
260 if (c == 'V')
261 tco_expect_close = 42;
262 }
263 }
264
265 /* someone wrote to us, we should reload the timer */
266 tco_timer_keepalive();
267 }
268 return len;
269 }
270
271 static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
272 unsigned long arg)
273 {
274 int new_options, retval = -EINVAL;
275 int new_heartbeat;
276 void __user *argp = (void __user *)arg;
277 int __user *p = argp;
278 static const struct watchdog_info ident = {
279 .options = WDIOF_SETTIMEOUT |
280 WDIOF_KEEPALIVEPING |
281 WDIOF_MAGICCLOSE,
282 .firmware_version = 0,
283 .identity = TCO_MODULE_NAME,
284 };
285
286 switch (cmd) {
287 case WDIOC_GETSUPPORT:
288 return copy_to_user(argp, &ident,
289 sizeof(ident)) ? -EFAULT : 0;
290 case WDIOC_GETSTATUS:
291 case WDIOC_GETBOOTSTATUS:
292 return put_user(0, p);
293 case WDIOC_SETOPTIONS:
294 if (get_user(new_options, p))
295 return -EFAULT;
296 if (new_options & WDIOS_DISABLECARD) {
297 tco_timer_stop();
298 retval = 0;
299 }
300 if (new_options & WDIOS_ENABLECARD) {
301 tco_timer_start();
302 tco_timer_keepalive();
303 retval = 0;
304 }
305 return retval;
306 case WDIOC_KEEPALIVE:
307 tco_timer_keepalive();
308 return 0;
309 case WDIOC_SETTIMEOUT:
310 if (get_user(new_heartbeat, p))
311 return -EFAULT;
312 if (tco_timer_set_heartbeat(new_heartbeat))
313 return -EINVAL;
314 tco_timer_keepalive();
315 /* Fall through */
316 case WDIOC_GETTIMEOUT:
317 return put_user(heartbeat, p);
318 default:
319 return -ENOTTY;
320 }
321 }
322
323 /*
324 * Kernel Interfaces
325 */
326
327 static const struct file_operations sp5100_tco_fops = {
328 .owner = THIS_MODULE,
329 .llseek = no_llseek,
330 .write = sp5100_tco_write,
331 .unlocked_ioctl = sp5100_tco_ioctl,
332 .open = sp5100_tco_open,
333 .release = sp5100_tco_release,
334 };
335
336 static struct miscdevice sp5100_tco_miscdev = {
337 .minor = WATCHDOG_MINOR,
338 .name = "watchdog",
339 .fops = &sp5100_tco_fops,
340 };
341
342 /*
343 * Data for PCI driver interface
344 *
345 * This data only exists for exporting the supported
346 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
347 * register a pci_driver, because someone else might
348 * want to register another driver on the same PCI id.
349 */
350 static DEFINE_PCI_DEVICE_TABLE(sp5100_tco_pci_tbl) = {
351 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
352 PCI_ANY_ID, },
353 { 0, }, /* End of list */
354 };
355 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
356
357 /*
358 * Init & exit routines
359 */
360 static unsigned char sp5100_tco_setupdevice(void)
361 {
362 struct pci_dev *dev = NULL;
363 const char *dev_name = NULL;
364 u32 val;
365 u32 index_reg, data_reg, base_addr;
366
367 /* Match the PCI device */
368 for_each_pci_dev(dev) {
369 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
370 sp5100_tco_pci = dev;
371 break;
372 }
373 }
374
375 if (!sp5100_tco_pci)
376 return 0;
377
378 pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision);
379
380 /*
381 * Determine type of southbridge chipset.
382 */
383 if (sp5100_tco_pci->revision >= 0x40) {
384 dev_name = SB800_DEVNAME;
385 index_reg = SB800_IO_PM_INDEX_REG;
386 data_reg = SB800_IO_PM_DATA_REG;
387 base_addr = SB800_PM_WATCHDOG_BASE;
388 } else {
389 dev_name = SP5100_DEVNAME;
390 index_reg = SP5100_IO_PM_INDEX_REG;
391 data_reg = SP5100_IO_PM_DATA_REG;
392 base_addr = SP5100_PM_WATCHDOG_BASE;
393 }
394
395 /* Request the IO ports used by this driver */
396 pm_iobase = SP5100_IO_PM_INDEX_REG;
397 if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
398 pr_err("I/O address 0x%04x already in use\n", pm_iobase);
399 goto exit;
400 }
401
402 /*
403 * First, Find the watchdog timer MMIO address from indirect I/O.
404 */
405 outb(base_addr+3, index_reg);
406 val = inb(data_reg);
407 outb(base_addr+2, index_reg);
408 val = val << 8 | inb(data_reg);
409 outb(base_addr+1, index_reg);
410 val = val << 8 | inb(data_reg);
411 outb(base_addr+0, index_reg);
412 /* Low three bits of BASE are reserved */
413 val = val << 8 | (inb(data_reg) & 0xf8);
414
415 pr_debug("Got 0x%04x from indirect I/O\n", val);
416
417 /* Check MMIO address conflict */
418 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
419 dev_name))
420 goto setup_wdt;
421 else
422 pr_debug("MMIO address 0x%04x already in use\n", val);
423
424 /*
425 * Secondly, Find the watchdog timer MMIO address
426 * from SBResource_MMIO register.
427 */
428 if (sp5100_tco_pci->revision >= 0x40) {
429 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
430 outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
431 val = inb(SB800_IO_PM_DATA_REG);
432 outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
433 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
434 outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
435 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
436 outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
437 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
438 } else {
439 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
440 pci_read_config_dword(sp5100_tco_pci,
441 SP5100_SB_RESOURCE_MMIO_BASE, &val);
442 }
443
444 /* The SBResource_MMIO is enabled and mapped memory space? */
445 if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
446 SB800_ACPI_MMIO_DECODE_EN) {
447 /* Clear unnecessary the low twelve bits */
448 val &= ~0xFFF;
449 /* Add the Watchdog Timer offset to base address. */
450 val += SB800_PM_WDT_MMIO_OFFSET;
451 /* Check MMIO address conflict */
452 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
453 dev_name)) {
454 pr_debug("Got 0x%04x from SBResource_MMIO register\n",
455 val);
456 goto setup_wdt;
457 } else
458 pr_debug("MMIO address 0x%04x already in use\n", val);
459 } else
460 pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);
461
462 /*
463 * Lastly re-programming the watchdog timer MMIO address,
464 * This method is a last resort...
465 *
466 * Before re-programming, to ensure that the watchdog timer
467 * is disabled, disable the watchdog timer.
468 */
469 tco_timer_disable();
470
471 if (force_addr) {
472 /*
473 * Force the use of watchdog timer MMIO address, and aligned to
474 * 8byte boundary.
475 */
476 force_addr &= ~0x7;
477 val = force_addr;
478
479 pr_info("Force the use of 0x%04x as MMIO address\n", val);
480 } else {
481 /*
482 * Get empty slot into the resource tree for watchdog timer.
483 */
484 if (allocate_resource(&iomem_resource,
485 &wdt_res,
486 SP5100_WDT_MEM_MAP_SIZE,
487 0xf0000000,
488 0xfffffff8,
489 0x8,
490 NULL,
491 NULL)) {
492 pr_err("MMIO allocation failed\n");
493 goto unreg_region;
494 }
495
496 val = resbase_phys = wdt_res.start;
497 pr_debug("Got 0x%04x from resource tree\n", val);
498 }
499
500 /* Restore to the low three bits, if chipset is SB8x0(or later) */
501 if (sp5100_tco_pci->revision >= 0x40) {
502 u8 reserved_bit;
503 reserved_bit = inb(base_addr) & 0x7;
504 val |= (u32)reserved_bit;
505 }
506
507 /* Re-programming the watchdog timer base address */
508 outb(base_addr+0, index_reg);
509 /* Low three bits of BASE are reserved */
510 outb((val >> 0) & 0xf8, data_reg);
511 outb(base_addr+1, index_reg);
512 outb((val >> 8) & 0xff, data_reg);
513 outb(base_addr+2, index_reg);
514 outb((val >> 16) & 0xff, data_reg);
515 outb(base_addr+3, index_reg);
516 outb((val >> 24) & 0xff, data_reg);
517
518 /*
519 * Clear unnecessary the low three bits,
520 * if chipset is SB8x0(or later)
521 */
522 if (sp5100_tco_pci->revision >= 0x40)
523 val &= ~0x7;
524
525 if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
526 dev_name)) {
527 pr_err("MMIO address 0x%04x already in use\n", val);
528 goto unreg_resource;
529 }
530
531 setup_wdt:
532 tcobase_phys = val;
533
534 tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
535 if (!tcobase) {
536 pr_err("failed to get tcobase address\n");
537 goto unreg_mem_region;
538 }
539
540 pr_info("Using 0x%04x for watchdog MMIO address\n", val);
541
542 /* Setup the watchdog timer */
543 tco_timer_enable();
544
545 /* Check that the watchdog action is set to reset the system */
546 val = readl(SP5100_WDT_CONTROL(tcobase));
547 /*
548 * Save WatchDogFired status, because WatchDogFired flag is
549 * cleared here.
550 */
551 tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;
552 val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
553 writel(val, SP5100_WDT_CONTROL(tcobase));
554
555 /* Set a reasonable heartbeat before we stop the timer */
556 tco_timer_set_heartbeat(heartbeat);
557
558 /*
559 * Stop the TCO before we change anything so we don't race with
560 * a zeroed timer.
561 */
562 tco_timer_stop();
563
564 /* Done */
565 return 1;
566
567 unreg_mem_region:
568 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
569 unreg_resource:
570 if (resbase_phys)
571 release_resource(&wdt_res);
572 unreg_region:
573 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
574 exit:
575 return 0;
576 }
577
578 static int sp5100_tco_init(struct platform_device *dev)
579 {
580 int ret;
581 char addr_str[16];
582
583 /*
584 * Check whether or not the hardware watchdog is there. If found, then
585 * set it up.
586 */
587 if (!sp5100_tco_setupdevice())
588 return -ENODEV;
589
590 /* Check to see if last reboot was due to watchdog timeout */
591 pr_info("Last reboot was %striggered by watchdog.\n",
592 tco_wdt_fired ? "" : "not ");
593
594 /*
595 * Check that the heartbeat value is within it's range.
596 * If not, reset to the default.
597 */
598 if (tco_timer_set_heartbeat(heartbeat)) {
599 heartbeat = WATCHDOG_HEARTBEAT;
600 tco_timer_set_heartbeat(heartbeat);
601 }
602
603 ret = misc_register(&sp5100_tco_miscdev);
604 if (ret != 0) {
605 pr_err("cannot register miscdev on minor=%d (err=%d)\n",
606 WATCHDOG_MINOR, ret);
607 goto exit;
608 }
609
610 clear_bit(0, &timer_alive);
611
612 /* Show module parameters */
613 if (force_addr == tcobase_phys)
614 /* The force_addr is vaild */
615 sprintf(addr_str, "0x%04x", force_addr);
616 else
617 strcpy(addr_str, "none");
618
619 pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d, "
620 "force_addr=%s)\n",
621 tcobase, heartbeat, nowayout, addr_str);
622
623 return 0;
624
625 exit:
626 iounmap(tcobase);
627 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
628 if (resbase_phys)
629 release_resource(&wdt_res);
630 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
631 return ret;
632 }
633
634 static void sp5100_tco_cleanup(void)
635 {
636 /* Stop the timer before we leave */
637 if (!nowayout)
638 tco_timer_stop();
639
640 /* Deregister */
641 misc_deregister(&sp5100_tco_miscdev);
642 iounmap(tcobase);
643 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
644 if (resbase_phys)
645 release_resource(&wdt_res);
646 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
647 }
648
649 static int sp5100_tco_remove(struct platform_device *dev)
650 {
651 if (tcobase)
652 sp5100_tco_cleanup();
653 return 0;
654 }
655
656 static void sp5100_tco_shutdown(struct platform_device *dev)
657 {
658 tco_timer_stop();
659 }
660
661 static struct platform_driver sp5100_tco_driver = {
662 .probe = sp5100_tco_init,
663 .remove = sp5100_tco_remove,
664 .shutdown = sp5100_tco_shutdown,
665 .driver = {
666 .owner = THIS_MODULE,
667 .name = TCO_MODULE_NAME,
668 },
669 };
670
671 static int __init sp5100_tco_init_module(void)
672 {
673 int err;
674
675 pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
676
677 err = platform_driver_register(&sp5100_tco_driver);
678 if (err)
679 return err;
680
681 sp5100_tco_platform_device = platform_device_register_simple(
682 TCO_MODULE_NAME, -1, NULL, 0);
683 if (IS_ERR(sp5100_tco_platform_device)) {
684 err = PTR_ERR(sp5100_tco_platform_device);
685 goto unreg_platform_driver;
686 }
687
688 return 0;
689
690 unreg_platform_driver:
691 platform_driver_unregister(&sp5100_tco_driver);
692 return err;
693 }
694
695 static void __exit sp5100_tco_cleanup_module(void)
696 {
697 platform_device_unregister(sp5100_tco_platform_device);
698 platform_driver_unregister(&sp5100_tco_driver);
699 pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
700 }
701
702 module_init(sp5100_tco_init_module);
703 module_exit(sp5100_tco_cleanup_module);
704
705 MODULE_AUTHOR("Priyanka Gupta");
706 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
707 MODULE_LICENSE("GPL");
708 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
(deprecated) Btrfs devel tree