2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
32 const char *pci_power_names
[] = {
33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
35 EXPORT_SYMBOL_GPL(pci_power_names
);
37 int isa_dma_bridge_buggy
;
38 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
41 EXPORT_SYMBOL(pci_pci_problems
);
43 unsigned int pci_pm_d3_delay
;
45 static void pci_pme_list_scan(struct work_struct
*work
);
47 static LIST_HEAD(pci_pme_list
);
48 static DEFINE_MUTEX(pci_pme_list_mutex
);
49 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
51 struct pci_pme_device
{
52 struct list_head list
;
56 #define PME_TIMEOUT 1000 /* How long between PME checks */
58 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
60 unsigned int delay
= dev
->d3_delay
;
62 if (delay
< pci_pm_d3_delay
)
63 delay
= pci_pm_d3_delay
;
68 #ifdef CONFIG_PCI_DOMAINS
69 int pci_domains_supported
= 1;
72 #define DEFAULT_CARDBUS_IO_SIZE (256)
73 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
74 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
75 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
76 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
78 #define DEFAULT_HOTPLUG_IO_SIZE (256)
79 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
80 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
81 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
82 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
84 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
87 * The default CLS is used if arch didn't set CLS explicitly and not
88 * all pci devices agree on the same value. Arch can override either
89 * the dfl or actual value as it sees fit. Don't forget this is
90 * measured in 32-bit words, not bytes.
92 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
93 u8 pci_cache_line_size
;
96 * If we set up a device for bus mastering, we need to check the latency
97 * timer as certain BIOSes forget to set it properly.
99 unsigned int pcibios_max_latency
= 255;
101 /* If set, the PCIe ARI capability will not be used. */
102 static bool pcie_ari_disabled
;
105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
106 * @bus: pointer to PCI bus structure to search
108 * Given a PCI bus, returns the highest PCI bus number present in the set
109 * including the given PCI bus and its list of child PCI buses.
111 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
114 unsigned char max
, n
;
116 max
= bus
->busn_res
.end
;
117 list_for_each_entry(tmp
, &bus
->children
, node
) {
118 n
= pci_bus_max_busnr(tmp
);
124 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
126 #ifdef CONFIG_HAS_IOMEM
127 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
129 struct resource
*res
= &pdev
->resource
[bar
];
132 * Make sure the BAR is actually a memory resource, not an IO resource
134 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
135 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
138 return ioremap_nocache(res
->start
, resource_size(res
));
140 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
142 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
145 * Make sure the BAR is actually a memory resource, not an IO resource
147 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
151 return ioremap_wc(pci_resource_start(pdev
, bar
),
152 pci_resource_len(pdev
, bar
));
154 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
158 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
159 u8 pos
, int cap
, int *ttl
)
164 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
170 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
182 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
185 int ttl
= PCI_FIND_CAP_TTL
;
187 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
190 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
192 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
193 pos
+ PCI_CAP_LIST_NEXT
, cap
);
195 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
197 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
198 unsigned int devfn
, u8 hdr_type
)
202 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
203 if (!(status
& PCI_STATUS_CAP_LIST
))
207 case PCI_HEADER_TYPE_NORMAL
:
208 case PCI_HEADER_TYPE_BRIDGE
:
209 return PCI_CAPABILITY_LIST
;
210 case PCI_HEADER_TYPE_CARDBUS
:
211 return PCI_CB_CAPABILITY_LIST
;
218 * pci_find_capability - query for devices' capabilities
219 * @dev: PCI device to query
220 * @cap: capability code
222 * Tell if a device supports a given PCI capability.
223 * Returns the address of the requested capability structure within the
224 * device's PCI configuration space or 0 in case the device does not
225 * support it. Possible values for @cap:
227 * %PCI_CAP_ID_PM Power Management
228 * %PCI_CAP_ID_AGP Accelerated Graphics Port
229 * %PCI_CAP_ID_VPD Vital Product Data
230 * %PCI_CAP_ID_SLOTID Slot Identification
231 * %PCI_CAP_ID_MSI Message Signalled Interrupts
232 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
233 * %PCI_CAP_ID_PCIX PCI-X
234 * %PCI_CAP_ID_EXP PCI Express
236 int pci_find_capability(struct pci_dev
*dev
, int cap
)
240 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
242 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
246 EXPORT_SYMBOL(pci_find_capability
);
249 * pci_bus_find_capability - query for devices' capabilities
250 * @bus: the PCI bus to query
251 * @devfn: PCI device to query
252 * @cap: capability code
254 * Like pci_find_capability() but works for pci devices that do not have a
255 * pci_dev structure set up yet.
257 * Returns the address of the requested capability structure within the
258 * device's PCI configuration space or 0 in case the device does not
261 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
266 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
268 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
270 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
274 EXPORT_SYMBOL(pci_bus_find_capability
);
277 * pci_find_next_ext_capability - Find an extended capability
278 * @dev: PCI device to query
279 * @start: address at which to start looking (0 to start at beginning of list)
280 * @cap: capability code
282 * Returns the address of the next matching extended capability structure
283 * within the device's PCI configuration space or 0 if the device does
284 * not support it. Some capabilities can occur several times, e.g., the
285 * vendor-specific capability, and this provides a way to find them all.
287 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
291 int pos
= PCI_CFG_SPACE_SIZE
;
293 /* minimum 8 bytes per capability */
294 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
296 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
302 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
306 * If we have no capabilities, this is indicated by cap ID,
307 * cap version and next pointer all being 0.
313 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
316 pos
= PCI_EXT_CAP_NEXT(header
);
317 if (pos
< PCI_CFG_SPACE_SIZE
)
320 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
326 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
329 * pci_find_ext_capability - Find an extended capability
330 * @dev: PCI device to query
331 * @cap: capability code
333 * Returns the address of the requested extended capability structure
334 * within the device's PCI configuration space or 0 if the device does
335 * not support it. Possible values for @cap:
337 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
338 * %PCI_EXT_CAP_ID_VC Virtual Channel
339 * %PCI_EXT_CAP_ID_DSN Device Serial Number
340 * %PCI_EXT_CAP_ID_PWR Power Budgeting
342 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
344 return pci_find_next_ext_capability(dev
, 0, cap
);
346 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
348 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
350 int rc
, ttl
= PCI_FIND_CAP_TTL
;
353 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
354 mask
= HT_3BIT_CAP_MASK
;
356 mask
= HT_5BIT_CAP_MASK
;
358 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
359 PCI_CAP_ID_HT
, &ttl
);
361 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
362 if (rc
!= PCIBIOS_SUCCESSFUL
)
365 if ((cap
& mask
) == ht_cap
)
368 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
369 pos
+ PCI_CAP_LIST_NEXT
,
370 PCI_CAP_ID_HT
, &ttl
);
376 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @pos: Position from which to continue searching
379 * @ht_cap: Hypertransport capability code
381 * To be used in conjunction with pci_find_ht_capability() to search for
382 * all capabilities matching @ht_cap. @pos should always be a value returned
383 * from pci_find_ht_capability().
385 * NB. To be 100% safe against broken PCI devices, the caller should take
386 * steps to avoid an infinite loop.
388 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
390 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
392 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
395 * pci_find_ht_capability - query a device's Hypertransport capabilities
396 * @dev: PCI device to query
397 * @ht_cap: Hypertransport capability code
399 * Tell if a device supports a given Hypertransport capability.
400 * Returns an address within the device's PCI configuration space
401 * or 0 in case the device does not support the request capability.
402 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
403 * which has a Hypertransport capability matching @ht_cap.
405 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
409 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
411 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
415 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
418 * pci_find_parent_resource - return resource region of parent bus of given region
419 * @dev: PCI device structure contains resources to be searched
420 * @res: child resource record for which parent is sought
422 * For given resource region of given device, return the resource
423 * region of parent bus the given region is contained in.
425 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
426 struct resource
*res
)
428 const struct pci_bus
*bus
= dev
->bus
;
432 pci_bus_for_each_resource(bus
, r
, i
) {
435 if (res
->start
&& resource_contains(r
, res
)) {
438 * If the window is prefetchable but the BAR is
439 * not, the allocator made a mistake.
441 if (r
->flags
& IORESOURCE_PREFETCH
&&
442 !(res
->flags
& IORESOURCE_PREFETCH
))
446 * If we're below a transparent bridge, there may
447 * be both a positively-decoded aperture and a
448 * subtractively-decoded region that contain the BAR.
449 * We want the positively-decoded one, so this depends
450 * on pci_bus_for_each_resource() giving us those
458 EXPORT_SYMBOL(pci_find_parent_resource
);
461 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
462 * @dev: the PCI device to operate on
463 * @pos: config space offset of status word
464 * @mask: mask of bit(s) to care about in status word
466 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
468 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
472 /* Wait for Transaction Pending bit clean */
473 for (i
= 0; i
< 4; i
++) {
476 msleep((1 << (i
- 1)) * 100);
478 pci_read_config_word(dev
, pos
, &status
);
479 if (!(status
& mask
))
487 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
488 * @dev: PCI device to have its BARs restored
490 * Restore the BAR values for a given device, so as to make it
491 * accessible by its driver.
493 static void pci_restore_bars(struct pci_dev
*dev
)
497 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
498 pci_update_resource(dev
, i
);
501 static struct pci_platform_pm_ops
*pci_platform_pm
;
503 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
505 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
508 pci_platform_pm
= ops
;
512 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
514 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
517 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
520 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
523 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
525 return pci_platform_pm
?
526 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
529 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
531 return pci_platform_pm
?
532 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
535 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
537 return pci_platform_pm
?
538 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
541 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
543 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
547 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
549 * @dev: PCI device to handle.
550 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
553 * -EINVAL if the requested state is invalid.
554 * -EIO if device does not support PCI PM or its PM capabilities register has a
555 * wrong version, or device doesn't support the requested state.
556 * 0 if device already is in the requested state.
557 * 0 if device's power state has been successfully changed.
559 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
562 bool need_restore
= false;
564 /* Check if we're already there */
565 if (dev
->current_state
== state
)
571 if (state
< PCI_D0
|| state
> PCI_D3hot
)
574 /* Validate current state:
575 * Can enter D0 from any state, but if we can only go deeper
576 * to sleep if we're already in a low power state
578 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
579 && dev
->current_state
> state
) {
580 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
581 dev
->current_state
, state
);
585 /* check if this device supports the desired state */
586 if ((state
== PCI_D1
&& !dev
->d1_support
)
587 || (state
== PCI_D2
&& !dev
->d2_support
))
590 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
592 /* If we're (effectively) in D3, force entire word to 0.
593 * This doesn't affect PME_Status, disables PME_En, and
594 * sets PowerState to 0.
596 switch (dev
->current_state
) {
600 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
605 case PCI_UNKNOWN
: /* Boot-up */
606 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
607 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
609 /* Fall-through: force to D0 */
615 /* enter specified state */
616 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
618 /* Mandatory power management transition delays */
619 /* see PCI PM 1.1 5.6.1 table 18 */
620 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
621 pci_dev_d3_sleep(dev
);
622 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
623 udelay(PCI_PM_D2_DELAY
);
625 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
626 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
627 if (dev
->current_state
!= state
&& printk_ratelimit())
628 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
632 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
633 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
634 * from D3hot to D0 _may_ perform an internal reset, thereby
635 * going to "D0 Uninitialized" rather than "D0 Initialized".
636 * For example, at least some versions of the 3c905B and the
637 * 3c556B exhibit this behaviour.
639 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
640 * devices in a D3hot state at boot. Consequently, we need to
641 * restore at least the BARs so that the device will be
642 * accessible to its driver.
645 pci_restore_bars(dev
);
648 pcie_aspm_pm_state_change(dev
->bus
->self
);
654 * pci_update_current_state - Read PCI power state of given device from its
655 * PCI PM registers and cache it
656 * @dev: PCI device to handle.
657 * @state: State to cache in case the device doesn't have the PM capability
659 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
665 * Configuration space is not accessible for device in
666 * D3cold, so just keep or set D3cold for safety
668 if (dev
->current_state
== PCI_D3cold
)
670 if (state
== PCI_D3cold
) {
671 dev
->current_state
= PCI_D3cold
;
674 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
675 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
677 dev
->current_state
= state
;
682 * pci_power_up - Put the given device into D0 forcibly
683 * @dev: PCI device to power up
685 void pci_power_up(struct pci_dev
*dev
)
687 if (platform_pci_power_manageable(dev
))
688 platform_pci_set_power_state(dev
, PCI_D0
);
690 pci_raw_set_power_state(dev
, PCI_D0
);
691 pci_update_current_state(dev
, PCI_D0
);
695 * pci_platform_power_transition - Use platform to change device power state
696 * @dev: PCI device to handle.
697 * @state: State to put the device into.
699 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
703 if (platform_pci_power_manageable(dev
)) {
704 error
= platform_pci_set_power_state(dev
, state
);
706 pci_update_current_state(dev
, state
);
710 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
711 dev
->current_state
= PCI_D0
;
717 * pci_wakeup - Wake up a PCI device
718 * @pci_dev: Device to handle.
719 * @ign: ignored parameter
721 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
723 pci_wakeup_event(pci_dev
);
724 pm_request_resume(&pci_dev
->dev
);
729 * pci_wakeup_bus - Walk given bus and wake up devices on it
730 * @bus: Top bus of the subtree to walk.
732 static void pci_wakeup_bus(struct pci_bus
*bus
)
735 pci_walk_bus(bus
, pci_wakeup
, NULL
);
739 * __pci_start_power_transition - Start power transition of a PCI device
740 * @dev: PCI device to handle.
741 * @state: State to put the device into.
743 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
745 if (state
== PCI_D0
) {
746 pci_platform_power_transition(dev
, PCI_D0
);
748 * Mandatory power management transition delays, see
749 * PCI Express Base Specification Revision 2.0 Section
750 * 6.6.1: Conventional Reset. Do not delay for
751 * devices powered on/off by corresponding bridge,
752 * because have already delayed for the bridge.
754 if (dev
->runtime_d3cold
) {
755 msleep(dev
->d3cold_delay
);
757 * When powering on a bridge from D3cold, the
758 * whole hierarchy may be powered on into
759 * D0uninitialized state, resume them to give
760 * them a chance to suspend again
762 pci_wakeup_bus(dev
->subordinate
);
768 * __pci_dev_set_current_state - Set current state of a PCI device
769 * @dev: Device to handle
770 * @data: pointer to state to be set
772 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
774 pci_power_t state
= *(pci_power_t
*)data
;
776 dev
->current_state
= state
;
781 * __pci_bus_set_current_state - Walk given bus and set current state of devices
782 * @bus: Top bus of the subtree to walk.
783 * @state: state to be set
785 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
788 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
792 * __pci_complete_power_transition - Complete power transition of a PCI device
793 * @dev: PCI device to handle.
794 * @state: State to put the device into.
796 * This function should not be called directly by device drivers.
798 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
804 ret
= pci_platform_power_transition(dev
, state
);
805 /* Power off the bridge may power off the whole hierarchy */
806 if (!ret
&& state
== PCI_D3cold
)
807 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
810 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
813 * pci_set_power_state - Set the power state of a PCI device
814 * @dev: PCI device to handle.
815 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
817 * Transition a device to a new power state, using the platform firmware and/or
818 * the device's PCI PM registers.
821 * -EINVAL if the requested state is invalid.
822 * -EIO if device does not support PCI PM or its PM capabilities register has a
823 * wrong version, or device doesn't support the requested state.
824 * 0 if device already is in the requested state.
825 * 0 if device's power state has been successfully changed.
827 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
831 /* bound the state we're entering */
832 if (state
> PCI_D3cold
)
834 else if (state
< PCI_D0
)
836 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
838 * If the device or the parent bridge do not support PCI PM,
839 * ignore the request if we're doing anything other than putting
840 * it into D0 (which would only happen on boot).
844 /* Check if we're already there */
845 if (dev
->current_state
== state
)
848 __pci_start_power_transition(dev
, state
);
850 /* This device is quirked not to be put into D3, so
851 don't put it in D3 */
852 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
856 * To put device in D3cold, we put device into D3hot in native
857 * way, then put device into D3cold with platform ops
859 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
862 if (!__pci_complete_power_transition(dev
, state
))
867 EXPORT_SYMBOL(pci_set_power_state
);
870 * pci_choose_state - Choose the power state of a PCI device
871 * @dev: PCI device to be suspended
872 * @state: target sleep state for the whole system. This is the value
873 * that is passed to suspend() function.
875 * Returns PCI power state suitable for given device and given system
879 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
886 ret
= platform_pci_choose_state(dev
);
887 if (ret
!= PCI_POWER_ERROR
)
890 switch (state
.event
) {
893 case PM_EVENT_FREEZE
:
894 case PM_EVENT_PRETHAW
:
895 /* REVISIT both freeze and pre-thaw "should" use D0 */
896 case PM_EVENT_SUSPEND
:
897 case PM_EVENT_HIBERNATE
:
900 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
906 EXPORT_SYMBOL(pci_choose_state
);
908 #define PCI_EXP_SAVE_REGS 7
910 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
911 u16 cap
, bool extended
)
913 struct pci_cap_saved_state
*tmp
;
915 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
916 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
922 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
924 return _pci_find_saved_cap(dev
, cap
, false);
927 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
929 return _pci_find_saved_cap(dev
, cap
, true);
932 static int pci_save_pcie_state(struct pci_dev
*dev
)
935 struct pci_cap_saved_state
*save_state
;
938 if (!pci_is_pcie(dev
))
941 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
943 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
947 cap
= (u16
*)&save_state
->cap
.data
[0];
948 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
949 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
950 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
951 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
952 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
953 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
954 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
959 static void pci_restore_pcie_state(struct pci_dev
*dev
)
962 struct pci_cap_saved_state
*save_state
;
965 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
969 cap
= (u16
*)&save_state
->cap
.data
[0];
970 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
971 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
972 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
973 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
974 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
975 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
976 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
980 static int pci_save_pcix_state(struct pci_dev
*dev
)
983 struct pci_cap_saved_state
*save_state
;
985 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
989 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
991 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
995 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
996 (u16
*)save_state
->cap
.data
);
1001 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1004 struct pci_cap_saved_state
*save_state
;
1007 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1008 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1009 if (!save_state
|| !pos
)
1011 cap
= (u16
*)&save_state
->cap
.data
[0];
1013 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1018 * pci_save_state - save the PCI configuration space of a device before suspending
1019 * @dev: - PCI device that we're dealing with
1021 int pci_save_state(struct pci_dev
*dev
)
1024 /* XXX: 100% dword access ok here? */
1025 for (i
= 0; i
< 16; i
++)
1026 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1027 dev
->state_saved
= true;
1029 i
= pci_save_pcie_state(dev
);
1033 i
= pci_save_pcix_state(dev
);
1037 return pci_save_vc_state(dev
);
1039 EXPORT_SYMBOL(pci_save_state
);
1041 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1042 u32 saved_val
, int retry
)
1046 pci_read_config_dword(pdev
, offset
, &val
);
1047 if (val
== saved_val
)
1051 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1052 offset
, val
, saved_val
);
1053 pci_write_config_dword(pdev
, offset
, saved_val
);
1057 pci_read_config_dword(pdev
, offset
, &val
);
1058 if (val
== saved_val
)
1065 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1066 int start
, int end
, int retry
)
1070 for (index
= end
; index
>= start
; index
--)
1071 pci_restore_config_dword(pdev
, 4 * index
,
1072 pdev
->saved_config_space
[index
],
1076 static void pci_restore_config_space(struct pci_dev
*pdev
)
1078 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1079 pci_restore_config_space_range(pdev
, 10, 15, 0);
1080 /* Restore BARs before the command register. */
1081 pci_restore_config_space_range(pdev
, 4, 9, 10);
1082 pci_restore_config_space_range(pdev
, 0, 3, 0);
1084 pci_restore_config_space_range(pdev
, 0, 15, 0);
1089 * pci_restore_state - Restore the saved state of a PCI device
1090 * @dev: - PCI device that we're dealing with
1092 void pci_restore_state(struct pci_dev
*dev
)
1094 if (!dev
->state_saved
)
1097 /* PCI Express register must be restored first */
1098 pci_restore_pcie_state(dev
);
1099 pci_restore_ats_state(dev
);
1100 pci_restore_vc_state(dev
);
1102 pci_restore_config_space(dev
);
1104 pci_restore_pcix_state(dev
);
1105 pci_restore_msi_state(dev
);
1107 /* Restore ACS and IOV configuration state */
1108 pci_enable_acs(dev
);
1109 pci_restore_iov_state(dev
);
1111 dev
->state_saved
= false;
1113 EXPORT_SYMBOL(pci_restore_state
);
1115 struct pci_saved_state
{
1116 u32 config_space
[16];
1117 struct pci_cap_saved_data cap
[0];
1121 * pci_store_saved_state - Allocate and return an opaque struct containing
1122 * the device saved state.
1123 * @dev: PCI device that we're dealing with
1125 * Return NULL if no state or error.
1127 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1129 struct pci_saved_state
*state
;
1130 struct pci_cap_saved_state
*tmp
;
1131 struct pci_cap_saved_data
*cap
;
1134 if (!dev
->state_saved
)
1137 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1139 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1140 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1142 state
= kzalloc(size
, GFP_KERNEL
);
1146 memcpy(state
->config_space
, dev
->saved_config_space
,
1147 sizeof(state
->config_space
));
1150 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1151 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1152 memcpy(cap
, &tmp
->cap
, len
);
1153 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1155 /* Empty cap_save terminates list */
1159 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1162 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1163 * @dev: PCI device that we're dealing with
1164 * @state: Saved state returned from pci_store_saved_state()
1166 int pci_load_saved_state(struct pci_dev
*dev
,
1167 struct pci_saved_state
*state
)
1169 struct pci_cap_saved_data
*cap
;
1171 dev
->state_saved
= false;
1176 memcpy(dev
->saved_config_space
, state
->config_space
,
1177 sizeof(state
->config_space
));
1181 struct pci_cap_saved_state
*tmp
;
1183 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1184 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1187 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1188 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1189 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1192 dev
->state_saved
= true;
1195 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1198 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1199 * and free the memory allocated for it.
1200 * @dev: PCI device that we're dealing with
1201 * @state: Pointer to saved state returned from pci_store_saved_state()
1203 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1204 struct pci_saved_state
**state
)
1206 int ret
= pci_load_saved_state(dev
, *state
);
1211 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1213 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1215 return pci_enable_resources(dev
, bars
);
1218 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1221 struct pci_dev
*bridge
;
1225 err
= pci_set_power_state(dev
, PCI_D0
);
1226 if (err
< 0 && err
!= -EIO
)
1229 bridge
= pci_upstream_bridge(dev
);
1231 pcie_aspm_powersave_config_link(bridge
);
1233 err
= pcibios_enable_device(dev
, bars
);
1236 pci_fixup_device(pci_fixup_enable
, dev
);
1238 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1241 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1243 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1244 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1245 pci_write_config_word(dev
, PCI_COMMAND
,
1246 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1253 * pci_reenable_device - Resume abandoned device
1254 * @dev: PCI device to be resumed
1256 * Note this function is a backend of pci_default_resume and is not supposed
1257 * to be called by normal code, write proper resume handler and use it instead.
1259 int pci_reenable_device(struct pci_dev
*dev
)
1261 if (pci_is_enabled(dev
))
1262 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1265 EXPORT_SYMBOL(pci_reenable_device
);
1267 static void pci_enable_bridge(struct pci_dev
*dev
)
1269 struct pci_dev
*bridge
;
1272 bridge
= pci_upstream_bridge(dev
);
1274 pci_enable_bridge(bridge
);
1276 if (pci_is_enabled(dev
)) {
1277 if (!dev
->is_busmaster
)
1278 pci_set_master(dev
);
1282 retval
= pci_enable_device(dev
);
1284 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1286 pci_set_master(dev
);
1289 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1291 struct pci_dev
*bridge
;
1296 * Power state could be unknown at this point, either due to a fresh
1297 * boot or a device removal call. So get the current power state
1298 * so that things like MSI message writing will behave as expected
1299 * (e.g. if the device really is in D0 at enable time).
1303 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1304 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1307 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1308 return 0; /* already enabled */
1310 bridge
= pci_upstream_bridge(dev
);
1312 pci_enable_bridge(bridge
);
1314 /* only skip sriov related */
1315 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1316 if (dev
->resource
[i
].flags
& flags
)
1318 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1319 if (dev
->resource
[i
].flags
& flags
)
1322 err
= do_pci_enable_device(dev
, bars
);
1324 atomic_dec(&dev
->enable_cnt
);
1329 * pci_enable_device_io - Initialize a device for use with IO space
1330 * @dev: PCI device to be initialized
1332 * Initialize device before it's used by a driver. Ask low-level code
1333 * to enable I/O resources. Wake up the device if it was suspended.
1334 * Beware, this function can fail.
1336 int pci_enable_device_io(struct pci_dev
*dev
)
1338 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1340 EXPORT_SYMBOL(pci_enable_device_io
);
1343 * pci_enable_device_mem - Initialize a device for use with Memory space
1344 * @dev: PCI device to be initialized
1346 * Initialize device before it's used by a driver. Ask low-level code
1347 * to enable Memory resources. Wake up the device if it was suspended.
1348 * Beware, this function can fail.
1350 int pci_enable_device_mem(struct pci_dev
*dev
)
1352 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1354 EXPORT_SYMBOL(pci_enable_device_mem
);
1357 * pci_enable_device - Initialize device before it's used by a driver.
1358 * @dev: PCI device to be initialized
1360 * Initialize device before it's used by a driver. Ask low-level code
1361 * to enable I/O and memory. Wake up the device if it was suspended.
1362 * Beware, this function can fail.
1364 * Note we don't actually enable the device many times if we call
1365 * this function repeatedly (we just increment the count).
1367 int pci_enable_device(struct pci_dev
*dev
)
1369 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1371 EXPORT_SYMBOL(pci_enable_device
);
1374 * Managed PCI resources. This manages device on/off, intx/msi/msix
1375 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1376 * there's no need to track it separately. pci_devres is initialized
1377 * when a device is enabled using managed PCI device enable interface.
1380 unsigned int enabled
:1;
1381 unsigned int pinned
:1;
1382 unsigned int orig_intx
:1;
1383 unsigned int restore_intx
:1;
1387 static void pcim_release(struct device
*gendev
, void *res
)
1389 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1390 struct pci_devres
*this = res
;
1393 if (dev
->msi_enabled
)
1394 pci_disable_msi(dev
);
1395 if (dev
->msix_enabled
)
1396 pci_disable_msix(dev
);
1398 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1399 if (this->region_mask
& (1 << i
))
1400 pci_release_region(dev
, i
);
1402 if (this->restore_intx
)
1403 pci_intx(dev
, this->orig_intx
);
1405 if (this->enabled
&& !this->pinned
)
1406 pci_disable_device(dev
);
1409 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1411 struct pci_devres
*dr
, *new_dr
;
1413 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1417 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1420 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1423 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1425 if (pci_is_managed(pdev
))
1426 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1431 * pcim_enable_device - Managed pci_enable_device()
1432 * @pdev: PCI device to be initialized
1434 * Managed pci_enable_device().
1436 int pcim_enable_device(struct pci_dev
*pdev
)
1438 struct pci_devres
*dr
;
1441 dr
= get_pci_dr(pdev
);
1447 rc
= pci_enable_device(pdev
);
1449 pdev
->is_managed
= 1;
1454 EXPORT_SYMBOL(pcim_enable_device
);
1457 * pcim_pin_device - Pin managed PCI device
1458 * @pdev: PCI device to pin
1460 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1461 * driver detach. @pdev must have been enabled with
1462 * pcim_enable_device().
1464 void pcim_pin_device(struct pci_dev
*pdev
)
1466 struct pci_devres
*dr
;
1468 dr
= find_pci_dr(pdev
);
1469 WARN_ON(!dr
|| !dr
->enabled
);
1473 EXPORT_SYMBOL(pcim_pin_device
);
1476 * pcibios_add_device - provide arch specific hooks when adding device dev
1477 * @dev: the PCI device being added
1479 * Permits the platform to provide architecture specific functionality when
1480 * devices are added. This is the default implementation. Architecture
1481 * implementations can override this.
1483 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1489 * pcibios_release_device - provide arch specific hooks when releasing device dev
1490 * @dev: the PCI device being released
1492 * Permits the platform to provide architecture specific functionality when
1493 * devices are released. This is the default implementation. Architecture
1494 * implementations can override this.
1496 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1499 * pcibios_disable_device - disable arch specific PCI resources for device dev
1500 * @dev: the PCI device to disable
1502 * Disables architecture specific PCI resources for the device. This
1503 * is the default implementation. Architecture implementations can
1506 void __weak
pcibios_disable_device (struct pci_dev
*dev
) {}
1509 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1510 * @irq: ISA IRQ to penalize
1511 * @active: IRQ active or not
1513 * Permits the platform to provide architecture-specific functionality when
1514 * penalizing ISA IRQs. This is the default implementation. Architecture
1515 * implementations can override this.
1517 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1519 static void do_pci_disable_device(struct pci_dev
*dev
)
1523 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1524 if (pci_command
& PCI_COMMAND_MASTER
) {
1525 pci_command
&= ~PCI_COMMAND_MASTER
;
1526 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1529 pcibios_disable_device(dev
);
1533 * pci_disable_enabled_device - Disable device without updating enable_cnt
1534 * @dev: PCI device to disable
1536 * NOTE: This function is a backend of PCI power management routines and is
1537 * not supposed to be called drivers.
1539 void pci_disable_enabled_device(struct pci_dev
*dev
)
1541 if (pci_is_enabled(dev
))
1542 do_pci_disable_device(dev
);
1546 * pci_disable_device - Disable PCI device after use
1547 * @dev: PCI device to be disabled
1549 * Signal to the system that the PCI device is not in use by the system
1550 * anymore. This only involves disabling PCI bus-mastering, if active.
1552 * Note we don't actually disable the device until all callers of
1553 * pci_enable_device() have called pci_disable_device().
1555 void pci_disable_device(struct pci_dev
*dev
)
1557 struct pci_devres
*dr
;
1559 dr
= find_pci_dr(dev
);
1563 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1564 "disabling already-disabled device");
1566 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1569 do_pci_disable_device(dev
);
1571 dev
->is_busmaster
= 0;
1573 EXPORT_SYMBOL(pci_disable_device
);
1576 * pcibios_set_pcie_reset_state - set reset state for device dev
1577 * @dev: the PCIe device reset
1578 * @state: Reset state to enter into
1581 * Sets the PCIe reset state for the device. This is the default
1582 * implementation. Architecture implementations can override this.
1584 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1585 enum pcie_reset_state state
)
1591 * pci_set_pcie_reset_state - set reset state for device dev
1592 * @dev: the PCIe device reset
1593 * @state: Reset state to enter into
1596 * Sets the PCI reset state for the device.
1598 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1600 return pcibios_set_pcie_reset_state(dev
, state
);
1602 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1605 * pci_check_pme_status - Check if given device has generated PME.
1606 * @dev: Device to check.
1608 * Check the PME status of the device and if set, clear it and clear PME enable
1609 * (if set). Return 'true' if PME status and PME enable were both set or
1610 * 'false' otherwise.
1612 bool pci_check_pme_status(struct pci_dev
*dev
)
1621 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1622 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1623 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1626 /* Clear PME status. */
1627 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1628 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1629 /* Disable PME to avoid interrupt flood. */
1630 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1634 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1640 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1641 * @dev: Device to handle.
1642 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1644 * Check if @dev has generated PME and queue a resume request for it in that
1647 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1649 if (pme_poll_reset
&& dev
->pme_poll
)
1650 dev
->pme_poll
= false;
1652 if (pci_check_pme_status(dev
)) {
1653 pci_wakeup_event(dev
);
1654 pm_request_resume(&dev
->dev
);
1660 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1661 * @bus: Top bus of the subtree to walk.
1663 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1666 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1671 * pci_pme_capable - check the capability of PCI device to generate PME#
1672 * @dev: PCI device to handle.
1673 * @state: PCI state from which device will issue PME#.
1675 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1680 return !!(dev
->pme_support
& (1 << state
));
1682 EXPORT_SYMBOL(pci_pme_capable
);
1684 static void pci_pme_list_scan(struct work_struct
*work
)
1686 struct pci_pme_device
*pme_dev
, *n
;
1688 mutex_lock(&pci_pme_list_mutex
);
1689 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1690 if (pme_dev
->dev
->pme_poll
) {
1691 struct pci_dev
*bridge
;
1693 bridge
= pme_dev
->dev
->bus
->self
;
1695 * If bridge is in low power state, the
1696 * configuration space of subordinate devices
1697 * may be not accessible
1699 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1701 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1703 list_del(&pme_dev
->list
);
1707 if (!list_empty(&pci_pme_list
))
1708 schedule_delayed_work(&pci_pme_work
,
1709 msecs_to_jiffies(PME_TIMEOUT
));
1710 mutex_unlock(&pci_pme_list_mutex
);
1714 * pci_pme_active - enable or disable PCI device's PME# function
1715 * @dev: PCI device to handle.
1716 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1718 * The caller must verify that the device is capable of generating PME# before
1719 * calling this function with @enable equal to 'true'.
1721 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1725 if (!dev
->pme_support
)
1728 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1729 /* Clear PME_Status by writing 1 to it and enable PME# */
1730 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1732 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1734 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1737 * PCI (as opposed to PCIe) PME requires that the device have
1738 * its PME# line hooked up correctly. Not all hardware vendors
1739 * do this, so the PME never gets delivered and the device
1740 * remains asleep. The easiest way around this is to
1741 * periodically walk the list of suspended devices and check
1742 * whether any have their PME flag set. The assumption is that
1743 * we'll wake up often enough anyway that this won't be a huge
1744 * hit, and the power savings from the devices will still be a
1747 * Although PCIe uses in-band PME message instead of PME# line
1748 * to report PME, PME does not work for some PCIe devices in
1749 * reality. For example, there are devices that set their PME
1750 * status bits, but don't really bother to send a PME message;
1751 * there are PCI Express Root Ports that don't bother to
1752 * trigger interrupts when they receive PME messages from the
1753 * devices below. So PME poll is used for PCIe devices too.
1756 if (dev
->pme_poll
) {
1757 struct pci_pme_device
*pme_dev
;
1759 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1762 dev_warn(&dev
->dev
, "can't enable PME#\n");
1766 mutex_lock(&pci_pme_list_mutex
);
1767 list_add(&pme_dev
->list
, &pci_pme_list
);
1768 if (list_is_singular(&pci_pme_list
))
1769 schedule_delayed_work(&pci_pme_work
,
1770 msecs_to_jiffies(PME_TIMEOUT
));
1771 mutex_unlock(&pci_pme_list_mutex
);
1773 mutex_lock(&pci_pme_list_mutex
);
1774 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1775 if (pme_dev
->dev
== dev
) {
1776 list_del(&pme_dev
->list
);
1781 mutex_unlock(&pci_pme_list_mutex
);
1785 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1787 EXPORT_SYMBOL(pci_pme_active
);
1790 * __pci_enable_wake - enable PCI device as wakeup event source
1791 * @dev: PCI device affected
1792 * @state: PCI state from which device will issue wakeup events
1793 * @runtime: True if the events are to be generated at run time
1794 * @enable: True to enable event generation; false to disable
1796 * This enables the device as a wakeup event source, or disables it.
1797 * When such events involves platform-specific hooks, those hooks are
1798 * called automatically by this routine.
1800 * Devices with legacy power management (no standard PCI PM capabilities)
1801 * always require such platform hooks.
1804 * 0 is returned on success
1805 * -EINVAL is returned if device is not supposed to wake up the system
1806 * Error code depending on the platform is returned if both the platform and
1807 * the native mechanism fail to enable the generation of wake-up events
1809 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1810 bool runtime
, bool enable
)
1814 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1817 /* Don't do the same thing twice in a row for one device. */
1818 if (!!enable
== !!dev
->wakeup_prepared
)
1822 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1823 * Anderson we should be doing PME# wake enable followed by ACPI wake
1824 * enable. To disable wake-up we call the platform first, for symmetry.
1830 if (pci_pme_capable(dev
, state
))
1831 pci_pme_active(dev
, true);
1834 error
= runtime
? platform_pci_run_wake(dev
, true) :
1835 platform_pci_sleep_wake(dev
, true);
1839 dev
->wakeup_prepared
= true;
1842 platform_pci_run_wake(dev
, false);
1844 platform_pci_sleep_wake(dev
, false);
1845 pci_pme_active(dev
, false);
1846 dev
->wakeup_prepared
= false;
1851 EXPORT_SYMBOL(__pci_enable_wake
);
1854 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1855 * @dev: PCI device to prepare
1856 * @enable: True to enable wake-up event generation; false to disable
1858 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1859 * and this function allows them to set that up cleanly - pci_enable_wake()
1860 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1861 * ordering constraints.
1863 * This function only returns error code if the device is not capable of
1864 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1865 * enable wake-up power for it.
1867 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1869 return pci_pme_capable(dev
, PCI_D3cold
) ?
1870 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1871 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1873 EXPORT_SYMBOL(pci_wake_from_d3
);
1876 * pci_target_state - find an appropriate low power state for a given PCI dev
1879 * Use underlying platform code to find a supported low power state for @dev.
1880 * If the platform can't manage @dev, return the deepest state from which it
1881 * can generate wake events, based on any available PME info.
1883 static pci_power_t
pci_target_state(struct pci_dev
*dev
)
1885 pci_power_t target_state
= PCI_D3hot
;
1887 if (platform_pci_power_manageable(dev
)) {
1889 * Call the platform to choose the target state of the device
1890 * and enable wake-up from this state if supported.
1892 pci_power_t state
= platform_pci_choose_state(dev
);
1895 case PCI_POWER_ERROR
:
1900 if (pci_no_d1d2(dev
))
1903 target_state
= state
;
1905 } else if (!dev
->pm_cap
) {
1906 target_state
= PCI_D0
;
1907 } else if (device_may_wakeup(&dev
->dev
)) {
1909 * Find the deepest state from which the device can generate
1910 * wake-up events, make it the target state and enable device
1913 if (dev
->pme_support
) {
1915 && !(dev
->pme_support
& (1 << target_state
)))
1920 return target_state
;
1924 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1925 * @dev: Device to handle.
1927 * Choose the power state appropriate for the device depending on whether
1928 * it can wake up the system and/or is power manageable by the platform
1929 * (PCI_D3hot is the default) and put the device into that state.
1931 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1933 pci_power_t target_state
= pci_target_state(dev
);
1936 if (target_state
== PCI_POWER_ERROR
)
1939 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1941 error
= pci_set_power_state(dev
, target_state
);
1944 pci_enable_wake(dev
, target_state
, false);
1948 EXPORT_SYMBOL(pci_prepare_to_sleep
);
1951 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1952 * @dev: Device to handle.
1954 * Disable device's system wake-up capability and put it into D0.
1956 int pci_back_from_sleep(struct pci_dev
*dev
)
1958 pci_enable_wake(dev
, PCI_D0
, false);
1959 return pci_set_power_state(dev
, PCI_D0
);
1961 EXPORT_SYMBOL(pci_back_from_sleep
);
1964 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1965 * @dev: PCI device being suspended.
1967 * Prepare @dev to generate wake-up events at run time and put it into a low
1970 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
1972 pci_power_t target_state
= pci_target_state(dev
);
1975 if (target_state
== PCI_POWER_ERROR
)
1978 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
1980 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
1982 error
= pci_set_power_state(dev
, target_state
);
1985 __pci_enable_wake(dev
, target_state
, true, false);
1986 dev
->runtime_d3cold
= false;
1993 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1994 * @dev: Device to check.
1996 * Return true if the device itself is capable of generating wake-up events
1997 * (through the platform or using the native PCIe PME) or if the device supports
1998 * PME and one of its upstream bridges can generate wake-up events.
2000 bool pci_dev_run_wake(struct pci_dev
*dev
)
2002 struct pci_bus
*bus
= dev
->bus
;
2004 if (device_run_wake(&dev
->dev
))
2007 if (!dev
->pme_support
)
2010 while (bus
->parent
) {
2011 struct pci_dev
*bridge
= bus
->self
;
2013 if (device_run_wake(&bridge
->dev
))
2019 /* We have reached the root bus. */
2021 return device_run_wake(bus
->bridge
);
2025 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2028 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2029 * @pci_dev: Device to check.
2031 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2032 * reconfigured due to wakeup settings difference between system and runtime
2033 * suspend and the current power state of it is suitable for the upcoming
2034 * (system) transition.
2036 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2038 struct device
*dev
= &pci_dev
->dev
;
2040 if (!pm_runtime_suspended(dev
)
2041 || (device_can_wakeup(dev
) && !device_may_wakeup(dev
))
2042 || platform_pci_need_resume(pci_dev
))
2045 return pci_target_state(pci_dev
) == pci_dev
->current_state
;
2048 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2050 struct device
*dev
= &pdev
->dev
;
2051 struct device
*parent
= dev
->parent
;
2054 pm_runtime_get_sync(parent
);
2055 pm_runtime_get_noresume(dev
);
2057 * pdev->current_state is set to PCI_D3cold during suspending,
2058 * so wait until suspending completes
2060 pm_runtime_barrier(dev
);
2062 * Only need to resume devices in D3cold, because config
2063 * registers are still accessible for devices suspended but
2066 if (pdev
->current_state
== PCI_D3cold
)
2067 pm_runtime_resume(dev
);
2070 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2072 struct device
*dev
= &pdev
->dev
;
2073 struct device
*parent
= dev
->parent
;
2075 pm_runtime_put(dev
);
2077 pm_runtime_put_sync(parent
);
2081 * pci_pm_init - Initialize PM functions of given PCI device
2082 * @dev: PCI device to handle.
2084 void pci_pm_init(struct pci_dev
*dev
)
2089 pm_runtime_forbid(&dev
->dev
);
2090 pm_runtime_set_active(&dev
->dev
);
2091 pm_runtime_enable(&dev
->dev
);
2092 device_enable_async_suspend(&dev
->dev
);
2093 dev
->wakeup_prepared
= false;
2096 dev
->pme_support
= 0;
2098 /* find PCI PM capability in list */
2099 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2102 /* Check device's ability to generate PME# */
2103 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2105 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2106 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2107 pmc
& PCI_PM_CAP_VER_MASK
);
2112 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2113 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2114 dev
->d3cold_allowed
= true;
2116 dev
->d1_support
= false;
2117 dev
->d2_support
= false;
2118 if (!pci_no_d1d2(dev
)) {
2119 if (pmc
& PCI_PM_CAP_D1
)
2120 dev
->d1_support
= true;
2121 if (pmc
& PCI_PM_CAP_D2
)
2122 dev
->d2_support
= true;
2124 if (dev
->d1_support
|| dev
->d2_support
)
2125 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2126 dev
->d1_support
? " D1" : "",
2127 dev
->d2_support
? " D2" : "");
2130 pmc
&= PCI_PM_CAP_PME_MASK
;
2132 dev_printk(KERN_DEBUG
, &dev
->dev
,
2133 "PME# supported from%s%s%s%s%s\n",
2134 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2135 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2136 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2137 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2138 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2139 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2140 dev
->pme_poll
= true;
2142 * Make device's PM flags reflect the wake-up capability, but
2143 * let the user space enable it to wake up the system as needed.
2145 device_set_wakeup_capable(&dev
->dev
, true);
2146 /* Disable the PME# generation functionality */
2147 pci_pme_active(dev
, false);
2151 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2152 struct pci_cap_saved_state
*new_cap
)
2154 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2158 * _pci_add_cap_save_buffer - allocate buffer for saving given
2159 * capability registers
2160 * @dev: the PCI device
2161 * @cap: the capability to allocate the buffer for
2162 * @extended: Standard or Extended capability ID
2163 * @size: requested size of the buffer
2165 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2166 bool extended
, unsigned int size
)
2169 struct pci_cap_saved_state
*save_state
;
2172 pos
= pci_find_ext_capability(dev
, cap
);
2174 pos
= pci_find_capability(dev
, cap
);
2179 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2183 save_state
->cap
.cap_nr
= cap
;
2184 save_state
->cap
.cap_extended
= extended
;
2185 save_state
->cap
.size
= size
;
2186 pci_add_saved_cap(dev
, save_state
);
2191 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2193 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2196 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2198 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2202 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2203 * @dev: the PCI device
2205 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2209 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2210 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2213 "unable to preallocate PCI Express save buffer\n");
2215 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2218 "unable to preallocate PCI-X save buffer\n");
2220 pci_allocate_vc_save_buffers(dev
);
2223 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2225 struct pci_cap_saved_state
*tmp
;
2226 struct hlist_node
*n
;
2228 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2233 * pci_configure_ari - enable or disable ARI forwarding
2234 * @dev: the PCI device
2236 * If @dev and its upstream bridge both support ARI, enable ARI in the
2237 * bridge. Otherwise, disable ARI in the bridge.
2239 void pci_configure_ari(struct pci_dev
*dev
)
2242 struct pci_dev
*bridge
;
2244 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2247 bridge
= dev
->bus
->self
;
2251 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2252 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2255 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2256 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2257 PCI_EXP_DEVCTL2_ARI
);
2258 bridge
->ari_enabled
= 1;
2260 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2261 PCI_EXP_DEVCTL2_ARI
);
2262 bridge
->ari_enabled
= 0;
2266 static int pci_acs_enable
;
2269 * pci_request_acs - ask for ACS to be enabled if supported
2271 void pci_request_acs(void)
2277 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2278 * @dev: the PCI device
2280 static int pci_std_enable_acs(struct pci_dev
*dev
)
2286 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2290 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2291 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2293 /* Source Validation */
2294 ctrl
|= (cap
& PCI_ACS_SV
);
2296 /* P2P Request Redirect */
2297 ctrl
|= (cap
& PCI_ACS_RR
);
2299 /* P2P Completion Redirect */
2300 ctrl
|= (cap
& PCI_ACS_CR
);
2302 /* Upstream Forwarding */
2303 ctrl
|= (cap
& PCI_ACS_UF
);
2305 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2311 * pci_enable_acs - enable ACS if hardware support it
2312 * @dev: the PCI device
2314 void pci_enable_acs(struct pci_dev
*dev
)
2316 if (!pci_acs_enable
)
2319 if (!pci_std_enable_acs(dev
))
2322 pci_dev_specific_enable_acs(dev
);
2325 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2330 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2335 * Except for egress control, capabilities are either required
2336 * or only required if controllable. Features missing from the
2337 * capability field can therefore be assumed as hard-wired enabled.
2339 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2340 acs_flags
&= (cap
| PCI_ACS_EC
);
2342 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2343 return (ctrl
& acs_flags
) == acs_flags
;
2347 * pci_acs_enabled - test ACS against required flags for a given device
2348 * @pdev: device to test
2349 * @acs_flags: required PCI ACS flags
2351 * Return true if the device supports the provided flags. Automatically
2352 * filters out flags that are not implemented on multifunction devices.
2354 * Note that this interface checks the effective ACS capabilities of the
2355 * device rather than the actual capabilities. For instance, most single
2356 * function endpoints are not required to support ACS because they have no
2357 * opportunity for peer-to-peer access. We therefore return 'true'
2358 * regardless of whether the device exposes an ACS capability. This makes
2359 * it much easier for callers of this function to ignore the actual type
2360 * or topology of the device when testing ACS support.
2362 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2366 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2371 * Conventional PCI and PCI-X devices never support ACS, either
2372 * effectively or actually. The shared bus topology implies that
2373 * any device on the bus can receive or snoop DMA.
2375 if (!pci_is_pcie(pdev
))
2378 switch (pci_pcie_type(pdev
)) {
2380 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2381 * but since their primary interface is PCI/X, we conservatively
2382 * handle them as we would a non-PCIe device.
2384 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2386 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2387 * applicable... must never implement an ACS Extended Capability...".
2388 * This seems arbitrary, but we take a conservative interpretation
2389 * of this statement.
2391 case PCI_EXP_TYPE_PCI_BRIDGE
:
2392 case PCI_EXP_TYPE_RC_EC
:
2395 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2396 * implement ACS in order to indicate their peer-to-peer capabilities,
2397 * regardless of whether they are single- or multi-function devices.
2399 case PCI_EXP_TYPE_DOWNSTREAM
:
2400 case PCI_EXP_TYPE_ROOT_PORT
:
2401 return pci_acs_flags_enabled(pdev
, acs_flags
);
2403 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2404 * implemented by the remaining PCIe types to indicate peer-to-peer
2405 * capabilities, but only when they are part of a multifunction
2406 * device. The footnote for section 6.12 indicates the specific
2407 * PCIe types included here.
2409 case PCI_EXP_TYPE_ENDPOINT
:
2410 case PCI_EXP_TYPE_UPSTREAM
:
2411 case PCI_EXP_TYPE_LEG_END
:
2412 case PCI_EXP_TYPE_RC_END
:
2413 if (!pdev
->multifunction
)
2416 return pci_acs_flags_enabled(pdev
, acs_flags
);
2420 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2421 * to single function devices with the exception of downstream ports.
2427 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2428 * @start: starting downstream device
2429 * @end: ending upstream device or NULL to search to the root bus
2430 * @acs_flags: required flags
2432 * Walk up a device tree from start to end testing PCI ACS support. If
2433 * any step along the way does not support the required flags, return false.
2435 bool pci_acs_path_enabled(struct pci_dev
*start
,
2436 struct pci_dev
*end
, u16 acs_flags
)
2438 struct pci_dev
*pdev
, *parent
= start
;
2443 if (!pci_acs_enabled(pdev
, acs_flags
))
2446 if (pci_is_root_bus(pdev
->bus
))
2447 return (end
== NULL
);
2449 parent
= pdev
->bus
->self
;
2450 } while (pdev
!= end
);
2456 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2457 * @dev: the PCI device
2458 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2460 * Perform INTx swizzling for a device behind one level of bridge. This is
2461 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2462 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2463 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2464 * the PCI Express Base Specification, Revision 2.1)
2466 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
2470 if (pci_ari_enabled(dev
->bus
))
2473 slot
= PCI_SLOT(dev
->devfn
);
2475 return (((pin
- 1) + slot
) % 4) + 1;
2478 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2486 while (!pci_is_root_bus(dev
->bus
)) {
2487 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2488 dev
= dev
->bus
->self
;
2495 * pci_common_swizzle - swizzle INTx all the way to root bridge
2496 * @dev: the PCI device
2497 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2499 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2500 * bridges all the way up to a PCI root bus.
2502 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2506 while (!pci_is_root_bus(dev
->bus
)) {
2507 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2508 dev
= dev
->bus
->self
;
2511 return PCI_SLOT(dev
->devfn
);
2513 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
2516 * pci_release_region - Release a PCI bar
2517 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2518 * @bar: BAR to release
2520 * Releases the PCI I/O and memory resources previously reserved by a
2521 * successful call to pci_request_region. Call this function only
2522 * after all use of the PCI regions has ceased.
2524 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2526 struct pci_devres
*dr
;
2528 if (pci_resource_len(pdev
, bar
) == 0)
2530 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2531 release_region(pci_resource_start(pdev
, bar
),
2532 pci_resource_len(pdev
, bar
));
2533 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2534 release_mem_region(pci_resource_start(pdev
, bar
),
2535 pci_resource_len(pdev
, bar
));
2537 dr
= find_pci_dr(pdev
);
2539 dr
->region_mask
&= ~(1 << bar
);
2541 EXPORT_SYMBOL(pci_release_region
);
2544 * __pci_request_region - Reserved PCI I/O and memory resource
2545 * @pdev: PCI device whose resources are to be reserved
2546 * @bar: BAR to be reserved
2547 * @res_name: Name to be associated with resource.
2548 * @exclusive: whether the region access is exclusive or not
2550 * Mark the PCI region associated with PCI device @pdev BR @bar as
2551 * being reserved by owner @res_name. Do not access any
2552 * address inside the PCI regions unless this call returns
2555 * If @exclusive is set, then the region is marked so that userspace
2556 * is explicitly not allowed to map the resource via /dev/mem or
2557 * sysfs MMIO access.
2559 * Returns 0 on success, or %EBUSY on error. A warning
2560 * message is also printed on failure.
2562 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
2563 const char *res_name
, int exclusive
)
2565 struct pci_devres
*dr
;
2567 if (pci_resource_len(pdev
, bar
) == 0)
2570 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2571 if (!request_region(pci_resource_start(pdev
, bar
),
2572 pci_resource_len(pdev
, bar
), res_name
))
2574 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2575 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2576 pci_resource_len(pdev
, bar
), res_name
,
2581 dr
= find_pci_dr(pdev
);
2583 dr
->region_mask
|= 1 << bar
;
2588 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2589 &pdev
->resource
[bar
]);
2594 * pci_request_region - Reserve PCI I/O and memory resource
2595 * @pdev: PCI device whose resources are to be reserved
2596 * @bar: BAR to be reserved
2597 * @res_name: Name to be associated with resource
2599 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2600 * being reserved by owner @res_name. Do not access any
2601 * address inside the PCI regions unless this call returns
2604 * Returns 0 on success, or %EBUSY on error. A warning
2605 * message is also printed on failure.
2607 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2609 return __pci_request_region(pdev
, bar
, res_name
, 0);
2611 EXPORT_SYMBOL(pci_request_region
);
2614 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2615 * @pdev: PCI device whose resources are to be reserved
2616 * @bar: BAR to be reserved
2617 * @res_name: Name to be associated with resource.
2619 * Mark the PCI region associated with PCI device @pdev BR @bar as
2620 * being reserved by owner @res_name. Do not access any
2621 * address inside the PCI regions unless this call returns
2624 * Returns 0 on success, or %EBUSY on error. A warning
2625 * message is also printed on failure.
2627 * The key difference that _exclusive makes it that userspace is
2628 * explicitly not allowed to map the resource via /dev/mem or
2631 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
2632 const char *res_name
)
2634 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2636 EXPORT_SYMBOL(pci_request_region_exclusive
);
2639 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2640 * @pdev: PCI device whose resources were previously reserved
2641 * @bars: Bitmask of BARs to be released
2643 * Release selected PCI I/O and memory resources previously reserved.
2644 * Call this function only after all use of the PCI regions has ceased.
2646 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2650 for (i
= 0; i
< 6; i
++)
2651 if (bars
& (1 << i
))
2652 pci_release_region(pdev
, i
);
2654 EXPORT_SYMBOL(pci_release_selected_regions
);
2656 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2657 const char *res_name
, int excl
)
2661 for (i
= 0; i
< 6; i
++)
2662 if (bars
& (1 << i
))
2663 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2669 if (bars
& (1 << i
))
2670 pci_release_region(pdev
, i
);
2677 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2678 * @pdev: PCI device whose resources are to be reserved
2679 * @bars: Bitmask of BARs to be requested
2680 * @res_name: Name to be associated with resource
2682 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2683 const char *res_name
)
2685 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2687 EXPORT_SYMBOL(pci_request_selected_regions
);
2689 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
2690 const char *res_name
)
2692 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2693 IORESOURCE_EXCLUSIVE
);
2695 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2698 * pci_release_regions - Release reserved PCI I/O and memory resources
2699 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2701 * Releases all PCI I/O and memory resources previously reserved by a
2702 * successful call to pci_request_regions. Call this function only
2703 * after all use of the PCI regions has ceased.
2706 void pci_release_regions(struct pci_dev
*pdev
)
2708 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2710 EXPORT_SYMBOL(pci_release_regions
);
2713 * pci_request_regions - Reserved PCI I/O and memory resources
2714 * @pdev: PCI device whose resources are to be reserved
2715 * @res_name: Name to be associated with resource.
2717 * Mark all PCI regions associated with PCI device @pdev as
2718 * being reserved by owner @res_name. Do not access any
2719 * address inside the PCI regions unless this call returns
2722 * Returns 0 on success, or %EBUSY on error. A warning
2723 * message is also printed on failure.
2725 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2727 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
2729 EXPORT_SYMBOL(pci_request_regions
);
2732 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2733 * @pdev: PCI device whose resources are to be reserved
2734 * @res_name: Name to be associated with resource.
2736 * Mark all PCI regions associated with PCI device @pdev as
2737 * being reserved by owner @res_name. Do not access any
2738 * address inside the PCI regions unless this call returns
2741 * pci_request_regions_exclusive() will mark the region so that
2742 * /dev/mem and the sysfs MMIO access will not be allowed.
2744 * Returns 0 on success, or %EBUSY on error. A warning
2745 * message is also printed on failure.
2747 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
2749 return pci_request_selected_regions_exclusive(pdev
,
2750 ((1 << 6) - 1), res_name
);
2752 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2755 * pci_remap_iospace - Remap the memory mapped I/O space
2756 * @res: Resource describing the I/O space
2757 * @phys_addr: physical address of range to be mapped
2759 * Remap the memory mapped I/O space described by the @res
2760 * and the CPU physical address @phys_addr into virtual address space.
2761 * Only architectures that have memory mapped IO functions defined
2762 * (and the PCI_IOBASE value defined) should call this function.
2764 int __weak
pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
2766 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2767 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
2769 if (!(res
->flags
& IORESOURCE_IO
))
2772 if (res
->end
> IO_SPACE_LIMIT
)
2775 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
2776 pgprot_device(PAGE_KERNEL
));
2778 /* this architecture does not have memory mapped I/O space,
2779 so this function should never be called */
2780 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2785 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
2789 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
2791 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
2793 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
2794 if (cmd
!= old_cmd
) {
2795 dev_dbg(&dev
->dev
, "%s bus mastering\n",
2796 enable
? "enabling" : "disabling");
2797 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2799 dev
->is_busmaster
= enable
;
2803 * pcibios_setup - process "pci=" kernel boot arguments
2804 * @str: string used to pass in "pci=" kernel boot arguments
2806 * Process kernel boot arguments. This is the default implementation.
2807 * Architecture specific implementations can override this as necessary.
2809 char * __weak __init
pcibios_setup(char *str
)
2815 * pcibios_set_master - enable PCI bus-mastering for device dev
2816 * @dev: the PCI device to enable
2818 * Enables PCI bus-mastering for the device. This is the default
2819 * implementation. Architecture specific implementations can override
2820 * this if necessary.
2822 void __weak
pcibios_set_master(struct pci_dev
*dev
)
2826 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2827 if (pci_is_pcie(dev
))
2830 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
2832 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
2833 else if (lat
> pcibios_max_latency
)
2834 lat
= pcibios_max_latency
;
2838 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
2842 * pci_set_master - enables bus-mastering for device dev
2843 * @dev: the PCI device to enable
2845 * Enables bus-mastering on the device and calls pcibios_set_master()
2846 * to do the needed arch specific settings.
2848 void pci_set_master(struct pci_dev
*dev
)
2850 __pci_set_master(dev
, true);
2851 pcibios_set_master(dev
);
2853 EXPORT_SYMBOL(pci_set_master
);
2856 * pci_clear_master - disables bus-mastering for device dev
2857 * @dev: the PCI device to disable
2859 void pci_clear_master(struct pci_dev
*dev
)
2861 __pci_set_master(dev
, false);
2863 EXPORT_SYMBOL(pci_clear_master
);
2866 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2867 * @dev: the PCI device for which MWI is to be enabled
2869 * Helper function for pci_set_mwi.
2870 * Originally copied from drivers/net/acenic.c.
2871 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2873 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2875 int pci_set_cacheline_size(struct pci_dev
*dev
)
2879 if (!pci_cache_line_size
)
2882 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2883 equal to or multiple of the right value. */
2884 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2885 if (cacheline_size
>= pci_cache_line_size
&&
2886 (cacheline_size
% pci_cache_line_size
) == 0)
2889 /* Write the correct value. */
2890 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
2892 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
2893 if (cacheline_size
== pci_cache_line_size
)
2896 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
2897 pci_cache_line_size
<< 2);
2901 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
2904 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2905 * @dev: the PCI device for which MWI is enabled
2907 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2909 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2911 int pci_set_mwi(struct pci_dev
*dev
)
2913 #ifdef PCI_DISABLE_MWI
2919 rc
= pci_set_cacheline_size(dev
);
2923 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2924 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
2925 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
2926 cmd
|= PCI_COMMAND_INVALIDATE
;
2927 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2932 EXPORT_SYMBOL(pci_set_mwi
);
2935 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2936 * @dev: the PCI device for which MWI is enabled
2938 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2939 * Callers are not required to check the return value.
2941 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2943 int pci_try_set_mwi(struct pci_dev
*dev
)
2945 #ifdef PCI_DISABLE_MWI
2948 return pci_set_mwi(dev
);
2951 EXPORT_SYMBOL(pci_try_set_mwi
);
2954 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2955 * @dev: the PCI device to disable
2957 * Disables PCI Memory-Write-Invalidate transaction on the device
2959 void pci_clear_mwi(struct pci_dev
*dev
)
2961 #ifndef PCI_DISABLE_MWI
2964 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
2965 if (cmd
& PCI_COMMAND_INVALIDATE
) {
2966 cmd
&= ~PCI_COMMAND_INVALIDATE
;
2967 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
2971 EXPORT_SYMBOL(pci_clear_mwi
);
2974 * pci_intx - enables/disables PCI INTx for device dev
2975 * @pdev: the PCI device to operate on
2976 * @enable: boolean: whether to enable or disable PCI INTx
2978 * Enables/disables PCI INTx for device dev
2980 void pci_intx(struct pci_dev
*pdev
, int enable
)
2982 u16 pci_command
, new;
2984 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
2987 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
2989 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
2991 if (new != pci_command
) {
2992 struct pci_devres
*dr
;
2994 pci_write_config_word(pdev
, PCI_COMMAND
, new);
2996 dr
= find_pci_dr(pdev
);
2997 if (dr
&& !dr
->restore_intx
) {
2998 dr
->restore_intx
= 1;
2999 dr
->orig_intx
= !enable
;
3003 EXPORT_SYMBOL_GPL(pci_intx
);
3006 * pci_intx_mask_supported - probe for INTx masking support
3007 * @dev: the PCI device to operate on
3009 * Check if the device dev support INTx masking via the config space
3012 bool pci_intx_mask_supported(struct pci_dev
*dev
)
3014 bool mask_supported
= false;
3017 if (dev
->broken_intx_masking
)
3020 pci_cfg_access_lock(dev
);
3022 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
3023 pci_write_config_word(dev
, PCI_COMMAND
,
3024 orig
^ PCI_COMMAND_INTX_DISABLE
);
3025 pci_read_config_word(dev
, PCI_COMMAND
, &new);
3028 * There's no way to protect against hardware bugs or detect them
3029 * reliably, but as long as we know what the value should be, let's
3030 * go ahead and check it.
3032 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
3033 dev_err(&dev
->dev
, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3035 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
3036 mask_supported
= true;
3037 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
3040 pci_cfg_access_unlock(dev
);
3041 return mask_supported
;
3043 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
3045 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3047 struct pci_bus
*bus
= dev
->bus
;
3048 bool mask_updated
= true;
3049 u32 cmd_status_dword
;
3050 u16 origcmd
, newcmd
;
3051 unsigned long flags
;
3055 * We do a single dword read to retrieve both command and status.
3056 * Document assumptions that make this possible.
3058 BUILD_BUG_ON(PCI_COMMAND
% 4);
3059 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3061 raw_spin_lock_irqsave(&pci_lock
, flags
);
3063 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3065 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3068 * Check interrupt status register to see whether our device
3069 * triggered the interrupt (when masking) or the next IRQ is
3070 * already pending (when unmasking).
3072 if (mask
!= irq_pending
) {
3073 mask_updated
= false;
3077 origcmd
= cmd_status_dword
;
3078 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3080 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3081 if (newcmd
!= origcmd
)
3082 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3085 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3087 return mask_updated
;
3091 * pci_check_and_mask_intx - mask INTx on pending interrupt
3092 * @dev: the PCI device to operate on
3094 * Check if the device dev has its INTx line asserted, mask it and
3095 * return true in that case. False is returned if not interrupt was
3098 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3100 return pci_check_and_set_intx_mask(dev
, true);
3102 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3105 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3106 * @dev: the PCI device to operate on
3108 * Check if the device dev has its INTx line asserted, unmask it if not
3109 * and return true. False is returned and the mask remains active if
3110 * there was still an interrupt pending.
3112 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3114 return pci_check_and_set_intx_mask(dev
, false);
3116 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3118 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
3120 return dma_set_max_seg_size(&dev
->dev
, size
);
3122 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
3124 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
3126 return dma_set_seg_boundary(&dev
->dev
, mask
);
3128 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
3131 * pci_wait_for_pending_transaction - waits for pending transaction
3132 * @dev: the PCI device to operate on
3134 * Return 0 if transaction is pending 1 otherwise.
3136 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3138 if (!pci_is_pcie(dev
))
3141 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3142 PCI_EXP_DEVSTA_TRPND
);
3144 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3146 static int pcie_flr(struct pci_dev
*dev
, int probe
)
3150 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3151 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3157 if (!pci_wait_for_pending_transaction(dev
))
3158 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
3160 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3165 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3170 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3174 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3175 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3182 * Wait for Transaction Pending bit to clear. A word-aligned test
3183 * is used, so we use the conrol offset rather than status and shift
3184 * the test bit to match.
3186 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
3187 PCI_AF_STATUS_TP
<< 8))
3188 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3190 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3196 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3197 * @dev: Device to reset.
3198 * @probe: If set, only check if the device can be reset this way.
3200 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3201 * unset, it will be reinitialized internally when going from PCI_D3hot to
3202 * PCI_D0. If that's the case and the device is not in a low-power state
3203 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3205 * NOTE: This causes the caller to sleep for twice the device power transition
3206 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3207 * by default (i.e. unless the @dev's d3_delay field has a different value).
3208 * Moreover, only devices in D0 can be reset by this function.
3210 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3214 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
3217 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3218 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3224 if (dev
->current_state
!= PCI_D0
)
3227 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3229 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3230 pci_dev_d3_sleep(dev
);
3232 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3234 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3235 pci_dev_d3_sleep(dev
);
3240 void pci_reset_secondary_bus(struct pci_dev
*dev
)
3244 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
3245 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3246 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3248 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3249 * this to 2ms to ensure that we meet the minimum requirement.
3253 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3254 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3257 * Trhfa for conventional PCI is 2^25 clock cycles.
3258 * Assuming a minimum 33MHz clock this results in a 1s
3259 * delay before we can consider subordinate devices to
3260 * be re-initialized. PCIe has some ways to shorten this,
3261 * but we don't make use of them yet.
3266 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
3268 pci_reset_secondary_bus(dev
);
3272 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3273 * @dev: Bridge device
3275 * Use the bridge control register to assert reset on the secondary bus.
3276 * Devices on the secondary bus are left in power-on state.
3278 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
3280 pcibios_reset_secondary_bus(dev
);
3282 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
3284 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3286 struct pci_dev
*pdev
;
3288 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
3289 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3292 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3299 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
3304 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
3308 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
3311 if (hotplug
->ops
->reset_slot
)
3312 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
3314 module_put(hotplug
->ops
->owner
);
3319 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
3321 struct pci_dev
*pdev
;
3323 if (dev
->subordinate
|| !dev
->slot
||
3324 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3327 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3328 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
3331 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
3334 static int __pci_dev_reset(struct pci_dev
*dev
, int probe
)
3340 rc
= pci_dev_specific_reset(dev
, probe
);
3344 rc
= pcie_flr(dev
, probe
);
3348 rc
= pci_af_flr(dev
, probe
);
3352 rc
= pci_pm_reset(dev
, probe
);
3356 rc
= pci_dev_reset_slot_function(dev
, probe
);
3360 rc
= pci_parent_bus_reset(dev
, probe
);
3365 static void pci_dev_lock(struct pci_dev
*dev
)
3367 pci_cfg_access_lock(dev
);
3368 /* block PM suspend, driver probe, etc. */
3369 device_lock(&dev
->dev
);
3372 /* Return 1 on successful lock, 0 on contention */
3373 static int pci_dev_trylock(struct pci_dev
*dev
)
3375 if (pci_cfg_access_trylock(dev
)) {
3376 if (device_trylock(&dev
->dev
))
3378 pci_cfg_access_unlock(dev
);
3384 static void pci_dev_unlock(struct pci_dev
*dev
)
3386 device_unlock(&dev
->dev
);
3387 pci_cfg_access_unlock(dev
);
3391 * pci_reset_notify - notify device driver of reset
3392 * @dev: device to be notified of reset
3393 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3396 * Must be called prior to device access being disabled and after device
3397 * access is restored.
3399 static void pci_reset_notify(struct pci_dev
*dev
, bool prepare
)
3401 const struct pci_error_handlers
*err_handler
=
3402 dev
->driver
? dev
->driver
->err_handler
: NULL
;
3403 if (err_handler
&& err_handler
->reset_notify
)
3404 err_handler
->reset_notify(dev
, prepare
);
3407 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
3409 pci_reset_notify(dev
, true);
3412 * Wake-up device prior to save. PM registers default to D0 after
3413 * reset and a simple register restore doesn't reliably return
3414 * to a non-D0 state anyway.
3416 pci_set_power_state(dev
, PCI_D0
);
3418 pci_save_state(dev
);
3420 * Disable the device by clearing the Command register, except for
3421 * INTx-disable which is set. This not only disables MMIO and I/O port
3422 * BARs, but also prevents the device from being Bus Master, preventing
3423 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3424 * compliant devices, INTx-disable prevents legacy interrupts.
3426 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3429 static void pci_dev_restore(struct pci_dev
*dev
)
3431 pci_restore_state(dev
);
3432 pci_reset_notify(dev
, false);
3435 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3442 rc
= __pci_dev_reset(dev
, probe
);
3445 pci_dev_unlock(dev
);
3451 * __pci_reset_function - reset a PCI device function
3452 * @dev: PCI device to reset
3454 * Some devices allow an individual function to be reset without affecting
3455 * other functions in the same device. The PCI device must be responsive
3456 * to PCI config space in order to use this function.
3458 * The device function is presumed to be unused when this function is called.
3459 * Resetting the device will make the contents of PCI configuration space
3460 * random, so any caller of this must be prepared to reinitialise the
3461 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3464 * Returns 0 if the device function was successfully reset or negative if the
3465 * device doesn't support resetting a single function.
3467 int __pci_reset_function(struct pci_dev
*dev
)
3469 return pci_dev_reset(dev
, 0);
3471 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3474 * __pci_reset_function_locked - reset a PCI device function while holding
3475 * the @dev mutex lock.
3476 * @dev: PCI device to reset
3478 * Some devices allow an individual function to be reset without affecting
3479 * other functions in the same device. The PCI device must be responsive
3480 * to PCI config space in order to use this function.
3482 * The device function is presumed to be unused and the caller is holding
3483 * the device mutex lock when this function is called.
3484 * Resetting the device will make the contents of PCI configuration space
3485 * random, so any caller of this must be prepared to reinitialise the
3486 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3489 * Returns 0 if the device function was successfully reset or negative if the
3490 * device doesn't support resetting a single function.
3492 int __pci_reset_function_locked(struct pci_dev
*dev
)
3494 return __pci_dev_reset(dev
, 0);
3496 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3499 * pci_probe_reset_function - check whether the device can be safely reset
3500 * @dev: PCI device to reset
3502 * Some devices allow an individual function to be reset without affecting
3503 * other functions in the same device. The PCI device must be responsive
3504 * to PCI config space in order to use this function.
3506 * Returns 0 if the device function can be reset or negative if the
3507 * device doesn't support resetting a single function.
3509 int pci_probe_reset_function(struct pci_dev
*dev
)
3511 return pci_dev_reset(dev
, 1);
3515 * pci_reset_function - quiesce and reset a PCI device function
3516 * @dev: PCI device to reset
3518 * Some devices allow an individual function to be reset without affecting
3519 * other functions in the same device. The PCI device must be responsive
3520 * to PCI config space in order to use this function.
3522 * This function does not just reset the PCI portion of a device, but
3523 * clears all the state associated with the device. This function differs
3524 * from __pci_reset_function in that it saves and restores device state
3527 * Returns 0 if the device function was successfully reset or negative if the
3528 * device doesn't support resetting a single function.
3530 int pci_reset_function(struct pci_dev
*dev
)
3534 rc
= pci_dev_reset(dev
, 1);
3538 pci_dev_save_and_disable(dev
);
3540 rc
= pci_dev_reset(dev
, 0);
3542 pci_dev_restore(dev
);
3546 EXPORT_SYMBOL_GPL(pci_reset_function
);
3549 * pci_try_reset_function - quiesce and reset a PCI device function
3550 * @dev: PCI device to reset
3552 * Same as above, except return -EAGAIN if unable to lock device.
3554 int pci_try_reset_function(struct pci_dev
*dev
)
3558 rc
= pci_dev_reset(dev
, 1);
3562 pci_dev_save_and_disable(dev
);
3564 if (pci_dev_trylock(dev
)) {
3565 rc
= __pci_dev_reset(dev
, 0);
3566 pci_dev_unlock(dev
);
3570 pci_dev_restore(dev
);
3574 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
3576 /* Do any devices on or below this bus prevent a bus reset? */
3577 static bool pci_bus_resetable(struct pci_bus
*bus
)
3579 struct pci_dev
*dev
;
3581 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3582 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3583 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3590 /* Lock devices from the top of the tree down */
3591 static void pci_bus_lock(struct pci_bus
*bus
)
3593 struct pci_dev
*dev
;
3595 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3597 if (dev
->subordinate
)
3598 pci_bus_lock(dev
->subordinate
);
3602 /* Unlock devices from the bottom of the tree up */
3603 static void pci_bus_unlock(struct pci_bus
*bus
)
3605 struct pci_dev
*dev
;
3607 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3608 if (dev
->subordinate
)
3609 pci_bus_unlock(dev
->subordinate
);
3610 pci_dev_unlock(dev
);
3614 /* Return 1 on successful lock, 0 on contention */
3615 static int pci_bus_trylock(struct pci_bus
*bus
)
3617 struct pci_dev
*dev
;
3619 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3620 if (!pci_dev_trylock(dev
))
3622 if (dev
->subordinate
) {
3623 if (!pci_bus_trylock(dev
->subordinate
)) {
3624 pci_dev_unlock(dev
);
3632 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
3633 if (dev
->subordinate
)
3634 pci_bus_unlock(dev
->subordinate
);
3635 pci_dev_unlock(dev
);
3640 /* Do any devices on or below this slot prevent a bus reset? */
3641 static bool pci_slot_resetable(struct pci_slot
*slot
)
3643 struct pci_dev
*dev
;
3645 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3646 if (!dev
->slot
|| dev
->slot
!= slot
)
3648 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3649 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3656 /* Lock devices from the top of the tree down */
3657 static void pci_slot_lock(struct pci_slot
*slot
)
3659 struct pci_dev
*dev
;
3661 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3662 if (!dev
->slot
|| dev
->slot
!= slot
)
3665 if (dev
->subordinate
)
3666 pci_bus_lock(dev
->subordinate
);
3670 /* Unlock devices from the bottom of the tree up */
3671 static void pci_slot_unlock(struct pci_slot
*slot
)
3673 struct pci_dev
*dev
;
3675 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3676 if (!dev
->slot
|| dev
->slot
!= slot
)
3678 if (dev
->subordinate
)
3679 pci_bus_unlock(dev
->subordinate
);
3680 pci_dev_unlock(dev
);
3684 /* Return 1 on successful lock, 0 on contention */
3685 static int pci_slot_trylock(struct pci_slot
*slot
)
3687 struct pci_dev
*dev
;
3689 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3690 if (!dev
->slot
|| dev
->slot
!= slot
)
3692 if (!pci_dev_trylock(dev
))
3694 if (dev
->subordinate
) {
3695 if (!pci_bus_trylock(dev
->subordinate
)) {
3696 pci_dev_unlock(dev
);
3704 list_for_each_entry_continue_reverse(dev
,
3705 &slot
->bus
->devices
, bus_list
) {
3706 if (!dev
->slot
|| dev
->slot
!= slot
)
3708 if (dev
->subordinate
)
3709 pci_bus_unlock(dev
->subordinate
);
3710 pci_dev_unlock(dev
);
3715 /* Save and disable devices from the top of the tree down */
3716 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
3718 struct pci_dev
*dev
;
3720 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3721 pci_dev_save_and_disable(dev
);
3722 if (dev
->subordinate
)
3723 pci_bus_save_and_disable(dev
->subordinate
);
3728 * Restore devices from top of the tree down - parent bridges need to be
3729 * restored before we can get to subordinate devices.
3731 static void pci_bus_restore(struct pci_bus
*bus
)
3733 struct pci_dev
*dev
;
3735 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3736 pci_dev_restore(dev
);
3737 if (dev
->subordinate
)
3738 pci_bus_restore(dev
->subordinate
);
3742 /* Save and disable devices from the top of the tree down */
3743 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
3745 struct pci_dev
*dev
;
3747 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3748 if (!dev
->slot
|| dev
->slot
!= slot
)
3750 pci_dev_save_and_disable(dev
);
3751 if (dev
->subordinate
)
3752 pci_bus_save_and_disable(dev
->subordinate
);
3757 * Restore devices from top of the tree down - parent bridges need to be
3758 * restored before we can get to subordinate devices.
3760 static void pci_slot_restore(struct pci_slot
*slot
)
3762 struct pci_dev
*dev
;
3764 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3765 if (!dev
->slot
|| dev
->slot
!= slot
)
3767 pci_dev_restore(dev
);
3768 if (dev
->subordinate
)
3769 pci_bus_restore(dev
->subordinate
);
3773 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
3777 if (!slot
|| !pci_slot_resetable(slot
))
3781 pci_slot_lock(slot
);
3785 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
3788 pci_slot_unlock(slot
);
3794 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3795 * @slot: PCI slot to probe
3797 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3799 int pci_probe_reset_slot(struct pci_slot
*slot
)
3801 return pci_slot_reset(slot
, 1);
3803 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
3806 * pci_reset_slot - reset a PCI slot
3807 * @slot: PCI slot to reset
3809 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3810 * independent of other slots. For instance, some slots may support slot power
3811 * control. In the case of a 1:1 bus to slot architecture, this function may
3812 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3813 * Generally a slot reset should be attempted before a bus reset. All of the
3814 * function of the slot and any subordinate buses behind the slot are reset
3815 * through this function. PCI config space of all devices in the slot and
3816 * behind the slot is saved before and restored after reset.
3818 * Return 0 on success, non-zero on error.
3820 int pci_reset_slot(struct pci_slot
*slot
)
3824 rc
= pci_slot_reset(slot
, 1);
3828 pci_slot_save_and_disable(slot
);
3830 rc
= pci_slot_reset(slot
, 0);
3832 pci_slot_restore(slot
);
3836 EXPORT_SYMBOL_GPL(pci_reset_slot
);
3839 * pci_try_reset_slot - Try to reset a PCI slot
3840 * @slot: PCI slot to reset
3842 * Same as above except return -EAGAIN if the slot cannot be locked
3844 int pci_try_reset_slot(struct pci_slot
*slot
)
3848 rc
= pci_slot_reset(slot
, 1);
3852 pci_slot_save_and_disable(slot
);
3854 if (pci_slot_trylock(slot
)) {
3856 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
3857 pci_slot_unlock(slot
);
3861 pci_slot_restore(slot
);
3865 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
3867 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
3869 if (!bus
->self
|| !pci_bus_resetable(bus
))
3879 pci_reset_bridge_secondary_bus(bus
->self
);
3881 pci_bus_unlock(bus
);
3887 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3888 * @bus: PCI bus to probe
3890 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3892 int pci_probe_reset_bus(struct pci_bus
*bus
)
3894 return pci_bus_reset(bus
, 1);
3896 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
3899 * pci_reset_bus - reset a PCI bus
3900 * @bus: top level PCI bus to reset
3902 * Do a bus reset on the given bus and any subordinate buses, saving
3903 * and restoring state of all devices.
3905 * Return 0 on success, non-zero on error.
3907 int pci_reset_bus(struct pci_bus
*bus
)
3911 rc
= pci_bus_reset(bus
, 1);
3915 pci_bus_save_and_disable(bus
);
3917 rc
= pci_bus_reset(bus
, 0);
3919 pci_bus_restore(bus
);
3923 EXPORT_SYMBOL_GPL(pci_reset_bus
);
3926 * pci_try_reset_bus - Try to reset a PCI bus
3927 * @bus: top level PCI bus to reset
3929 * Same as above except return -EAGAIN if the bus cannot be locked
3931 int pci_try_reset_bus(struct pci_bus
*bus
)
3935 rc
= pci_bus_reset(bus
, 1);
3939 pci_bus_save_and_disable(bus
);
3941 if (pci_bus_trylock(bus
)) {
3943 pci_reset_bridge_secondary_bus(bus
->self
);
3944 pci_bus_unlock(bus
);
3948 pci_bus_restore(bus
);
3952 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
3955 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3956 * @dev: PCI device to query
3958 * Returns mmrbc: maximum designed memory read count in bytes
3959 * or appropriate error value.
3961 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
3966 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3970 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
3973 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
3975 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
3978 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3979 * @dev: PCI device to query
3981 * Returns mmrbc: maximum memory read count in bytes
3982 * or appropriate error value.
3984 int pcix_get_mmrbc(struct pci_dev
*dev
)
3989 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
3993 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
3996 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
3998 EXPORT_SYMBOL(pcix_get_mmrbc
);
4001 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4002 * @dev: PCI device to query
4003 * @mmrbc: maximum memory read count in bytes
4004 * valid values are 512, 1024, 2048, 4096
4006 * If possible sets maximum memory read byte count, some bridges have erratas
4007 * that prevent this.
4009 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4015 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4018 v
= ffs(mmrbc
) - 10;
4020 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4024 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4027 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4030 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4033 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4035 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4038 cmd
&= ~PCI_X_CMD_MAX_READ
;
4040 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4045 EXPORT_SYMBOL(pcix_set_mmrbc
);
4048 * pcie_get_readrq - get PCI Express read request size
4049 * @dev: PCI device to query
4051 * Returns maximum memory read request in bytes
4052 * or appropriate error value.
4054 int pcie_get_readrq(struct pci_dev
*dev
)
4058 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4060 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4062 EXPORT_SYMBOL(pcie_get_readrq
);
4065 * pcie_set_readrq - set PCI Express maximum memory read request
4066 * @dev: PCI device to query
4067 * @rq: maximum memory read count in bytes
4068 * valid values are 128, 256, 512, 1024, 2048, 4096
4070 * If possible sets maximum memory read request in bytes
4072 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4076 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4080 * If using the "performance" PCIe config, we clamp the
4081 * read rq size to the max packet size to prevent the
4082 * host bridge generating requests larger than we can
4085 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4086 int mps
= pcie_get_mps(dev
);
4092 v
= (ffs(rq
) - 8) << 12;
4094 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4095 PCI_EXP_DEVCTL_READRQ
, v
);
4097 EXPORT_SYMBOL(pcie_set_readrq
);
4100 * pcie_get_mps - get PCI Express maximum payload size
4101 * @dev: PCI device to query
4103 * Returns maximum payload size in bytes
4105 int pcie_get_mps(struct pci_dev
*dev
)
4109 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4111 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
4113 EXPORT_SYMBOL(pcie_get_mps
);
4116 * pcie_set_mps - set PCI Express maximum payload size
4117 * @dev: PCI device to query
4118 * @mps: maximum payload size in bytes
4119 * valid values are 128, 256, 512, 1024, 2048, 4096
4121 * If possible sets maximum payload size
4123 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
4127 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
4131 if (v
> dev
->pcie_mpss
)
4135 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4136 PCI_EXP_DEVCTL_PAYLOAD
, v
);
4138 EXPORT_SYMBOL(pcie_set_mps
);
4141 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4142 * @dev: PCI device to query
4143 * @speed: storage for minimum speed
4144 * @width: storage for minimum width
4146 * This function will walk up the PCI device chain and determine the minimum
4147 * link width and speed of the device.
4149 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
4150 enum pcie_link_width
*width
)
4154 *speed
= PCI_SPEED_UNKNOWN
;
4155 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
4159 enum pci_bus_speed next_speed
;
4160 enum pcie_link_width next_width
;
4162 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
4166 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
4167 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
4168 PCI_EXP_LNKSTA_NLW_SHIFT
;
4170 if (next_speed
< *speed
)
4171 *speed
= next_speed
;
4173 if (next_width
< *width
)
4174 *width
= next_width
;
4176 dev
= dev
->bus
->self
;
4181 EXPORT_SYMBOL(pcie_get_minimum_link
);
4184 * pci_select_bars - Make BAR mask from the type of resource
4185 * @dev: the PCI device for which BAR mask is made
4186 * @flags: resource type mask to be selected
4188 * This helper routine makes bar mask from the type of resource.
4190 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
4193 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
4194 if (pci_resource_flags(dev
, i
) & flags
)
4198 EXPORT_SYMBOL(pci_select_bars
);
4201 * pci_resource_bar - get position of the BAR associated with a resource
4202 * @dev: the PCI device
4203 * @resno: the resource number
4204 * @type: the BAR type to be filled in
4206 * Returns BAR position in config space, or 0 if the BAR is invalid.
4208 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
4212 if (resno
< PCI_ROM_RESOURCE
) {
4213 *type
= pci_bar_unknown
;
4214 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
4215 } else if (resno
== PCI_ROM_RESOURCE
) {
4216 *type
= pci_bar_mem32
;
4217 return dev
->rom_base_reg
;
4218 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
4219 /* device specific resource */
4220 *type
= pci_bar_unknown
;
4221 reg
= pci_iov_resource_bar(dev
, resno
);
4226 dev_err(&dev
->dev
, "BAR %d: invalid resource\n", resno
);
4230 /* Some architectures require additional programming to enable VGA */
4231 static arch_set_vga_state_t arch_set_vga_state
;
4233 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
4235 arch_set_vga_state
= func
; /* NULL disables */
4238 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
4239 unsigned int command_bits
, u32 flags
)
4241 if (arch_set_vga_state
)
4242 return arch_set_vga_state(dev
, decode
, command_bits
,
4248 * pci_set_vga_state - set VGA decode state on device and parents if requested
4249 * @dev: the PCI device
4250 * @decode: true = enable decoding, false = disable decoding
4251 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4252 * @flags: traverse ancestors and change bridges
4253 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4255 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
4256 unsigned int command_bits
, u32 flags
)
4258 struct pci_bus
*bus
;
4259 struct pci_dev
*bridge
;
4263 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
4265 /* ARCH specific VGA enables */
4266 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
4270 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
4271 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4273 cmd
|= command_bits
;
4275 cmd
&= ~command_bits
;
4276 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4279 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
4286 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4289 cmd
|= PCI_BRIDGE_CTL_VGA
;
4291 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
4292 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4300 bool pci_device_is_present(struct pci_dev
*pdev
)
4304 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
4306 EXPORT_SYMBOL_GPL(pci_device_is_present
);
4308 void pci_ignore_hotplug(struct pci_dev
*dev
)
4310 struct pci_dev
*bridge
= dev
->bus
->self
;
4312 dev
->ignore_hotplug
= 1;
4313 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4315 bridge
->ignore_hotplug
= 1;
4317 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
4319 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4320 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
4321 static DEFINE_SPINLOCK(resource_alignment_lock
);
4324 * pci_specified_resource_alignment - get resource alignment specified by user.
4325 * @dev: the PCI device to get
4327 * RETURNS: Resource alignment if it is specified.
4328 * Zero if it is not specified.
4330 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
4332 int seg
, bus
, slot
, func
, align_order
, count
;
4333 resource_size_t align
= 0;
4336 spin_lock(&resource_alignment_lock
);
4337 p
= resource_alignment_param
;
4340 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
4346 if (sscanf(p
, "%x:%x:%x.%x%n",
4347 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
4349 if (sscanf(p
, "%x:%x.%x%n",
4350 &bus
, &slot
, &func
, &count
) != 3) {
4351 /* Invalid format */
4352 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
4358 if (seg
== pci_domain_nr(dev
->bus
) &&
4359 bus
== dev
->bus
->number
&&
4360 slot
== PCI_SLOT(dev
->devfn
) &&
4361 func
== PCI_FUNC(dev
->devfn
)) {
4362 if (align_order
== -1)
4365 align
= 1 << align_order
;
4369 if (*p
!= ';' && *p
!= ',') {
4370 /* End of param or invalid format */
4375 spin_unlock(&resource_alignment_lock
);
4380 * This function disables memory decoding and releases memory resources
4381 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4382 * It also rounds up size to specified alignment.
4383 * Later on, the kernel will assign page-aligned memory resource back
4386 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
4390 resource_size_t align
, size
;
4393 /* check if specified PCI is target device to reassign */
4394 align
= pci_specified_resource_alignment(dev
);
4398 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
4399 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
4401 "Can't reassign resources to host bridge.\n");
4406 "Disabling memory decoding and releasing memory resources.\n");
4407 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
4408 command
&= ~PCI_COMMAND_MEMORY
;
4409 pci_write_config_word(dev
, PCI_COMMAND
, command
);
4411 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
4412 r
= &dev
->resource
[i
];
4413 if (!(r
->flags
& IORESOURCE_MEM
))
4415 size
= resource_size(r
);
4419 "Rounding up size of resource #%d to %#llx.\n",
4420 i
, (unsigned long long)size
);
4422 r
->flags
|= IORESOURCE_UNSET
;
4426 /* Need to disable bridge's resource window,
4427 * to enable the kernel to reassign new resource
4430 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4431 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
4432 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
4433 r
= &dev
->resource
[i
];
4434 if (!(r
->flags
& IORESOURCE_MEM
))
4436 r
->flags
|= IORESOURCE_UNSET
;
4437 r
->end
= resource_size(r
) - 1;
4440 pci_disable_bridge_window(dev
);
4444 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
4446 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
4447 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
4448 spin_lock(&resource_alignment_lock
);
4449 strncpy(resource_alignment_param
, buf
, count
);
4450 resource_alignment_param
[count
] = '\0';
4451 spin_unlock(&resource_alignment_lock
);
4455 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
4458 spin_lock(&resource_alignment_lock
);
4459 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
4460 spin_unlock(&resource_alignment_lock
);
4464 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
4466 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
4469 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
4470 const char *buf
, size_t count
)
4472 return pci_set_resource_alignment_param(buf
, count
);
4475 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
4476 pci_resource_alignment_store
);
4478 static int __init
pci_resource_alignment_sysfs_init(void)
4480 return bus_create_file(&pci_bus_type
,
4481 &bus_attr_resource_alignment
);
4483 late_initcall(pci_resource_alignment_sysfs_init
);
4485 static void pci_no_domains(void)
4487 #ifdef CONFIG_PCI_DOMAINS
4488 pci_domains_supported
= 0;
4492 #ifdef CONFIG_PCI_DOMAINS
4493 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
4495 int pci_get_new_domain_nr(void)
4497 return atomic_inc_return(&__domain_nr
);
4500 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4501 void pci_bus_assign_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
4503 static int use_dt_domains
= -1;
4504 int domain
= of_get_pci_domain_nr(parent
->of_node
);
4507 * Check DT domain and use_dt_domains values.
4509 * If DT domain property is valid (domain >= 0) and
4510 * use_dt_domains != 0, the DT assignment is valid since this means
4511 * we have not previously allocated a domain number by using
4512 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4513 * 1, to indicate that we have just assigned a domain number from
4516 * If DT domain property value is not valid (ie domain < 0), and we
4517 * have not previously assigned a domain number from DT
4518 * (use_dt_domains != 1) we should assign a domain number by
4521 * pci_get_new_domain_nr()
4523 * API and update the use_dt_domains value to keep track of method we
4524 * are using to assign domain numbers (use_dt_domains = 0).
4526 * All other combinations imply we have a platform that is trying
4527 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4528 * which is a recipe for domain mishandling and it is prevented by
4529 * invalidating the domain value (domain = -1) and printing a
4530 * corresponding error.
4532 if (domain
>= 0 && use_dt_domains
) {
4534 } else if (domain
< 0 && use_dt_domains
!= 1) {
4536 domain
= pci_get_new_domain_nr();
4538 dev_err(parent
, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4539 parent
->of_node
->full_name
);
4543 bus
->domain_nr
= domain
;
4549 * pci_ext_cfg_avail - can we access extended PCI config space?
4551 * Returns 1 if we can access PCI extended config space (offsets
4552 * greater than 0xff). This is the default implementation. Architecture
4553 * implementations can override this.
4555 int __weak
pci_ext_cfg_avail(void)
4560 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
4563 EXPORT_SYMBOL(pci_fixup_cardbus
);
4565 static int __init
pci_setup(char *str
)
4568 char *k
= strchr(str
, ',');
4571 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
4572 if (!strcmp(str
, "nomsi")) {
4574 } else if (!strcmp(str
, "noaer")) {
4576 } else if (!strncmp(str
, "realloc=", 8)) {
4577 pci_realloc_get_opt(str
+ 8);
4578 } else if (!strncmp(str
, "realloc", 7)) {
4579 pci_realloc_get_opt("on");
4580 } else if (!strcmp(str
, "nodomains")) {
4582 } else if (!strncmp(str
, "noari", 5)) {
4583 pcie_ari_disabled
= true;
4584 } else if (!strncmp(str
, "cbiosize=", 9)) {
4585 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
4586 } else if (!strncmp(str
, "cbmemsize=", 10)) {
4587 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
4588 } else if (!strncmp(str
, "resource_alignment=", 19)) {
4589 pci_set_resource_alignment_param(str
+ 19,
4591 } else if (!strncmp(str
, "ecrc=", 5)) {
4592 pcie_ecrc_get_policy(str
+ 5);
4593 } else if (!strncmp(str
, "hpiosize=", 9)) {
4594 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
4595 } else if (!strncmp(str
, "hpmemsize=", 10)) {
4596 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
4597 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
4598 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
4599 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
4600 pcie_bus_config
= PCIE_BUS_SAFE
;
4601 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
4602 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
4603 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
4604 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
4605 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
4606 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
4608 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
4616 early_param("pci", pci_setup
);