?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
netlink: revert broken, broken "2-clause nla_ok()"
[linux-2.6/btrfs-unstable.git] / include / linux / nvme.h
blobfc3c2420659395039be1288a82e8d62d98aefab3
1 /*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19
20 /* NQN names in commands fields specified one size */
21 #define NVMF_NQN_FIELD_LEN 256
22
23 /* However the max length of a qualified name is another size */
24 #define NVMF_NQN_SIZE 223
25
26 #define NVMF_TRSVCID_SIZE 32
27 #define NVMF_TRADDR_SIZE 256
28 #define NVMF_TSAS_SIZE 256
29
30 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
31
32 #define NVME_RDMA_IP_PORT 4420
33
34 enum nvme_subsys_type {
35 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
36 NVME_NQN_NVME = 2, /* NVME type target subsystem */
37 };
38
39 /* Address Family codes for Discovery Log Page entry ADRFAM field */
40 enum {
41 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
42 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
43 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
44 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
45 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
46 };
47
48 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
49 enum {
50 NVMF_TRTYPE_RDMA = 1, /* RDMA */
51 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
52 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
53 NVMF_TRTYPE_MAX,
54 };
55
56 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
57 enum {
58 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
59 NVMF_TREQ_REQUIRED = 1, /* Required */
60 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
61 };
62
63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
64 * RDMA_QPTYPE field
65 */
66 enum {
67 NVMF_RDMA_QPTYPE_CONNECTED = 0, /* Reliable Connected */
68 NVMF_RDMA_QPTYPE_DATAGRAM = 1, /* Reliable Datagram */
69 };
70
71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
72 * RDMA_QPTYPE field
73 */
74 enum {
75 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 0, /* No Provider Specified */
76 NVMF_RDMA_PRTYPE_IB = 1, /* InfiniBand */
77 NVMF_RDMA_PRTYPE_ROCE = 2, /* InfiniBand RoCE */
78 NVMF_RDMA_PRTYPE_ROCEV2 = 3, /* InfiniBand RoCEV2 */
79 NVMF_RDMA_PRTYPE_IWARP = 4, /* IWARP */
80 };
81
82 /* RDMA Connection Management Service Type codes for Discovery Log Page
83 * entry TSAS RDMA_CMS field
84 */
85 enum {
86 NVMF_RDMA_CMS_RDMA_CM = 0, /* Sockets based enpoint addressing */
87 };
88
89 #define NVMF_AQ_DEPTH 32
90
91 enum {
92 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
93 NVME_REG_VS = 0x0008, /* Version */
94 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
95 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
96 NVME_REG_CC = 0x0014, /* Controller Configuration */
97 NVME_REG_CSTS = 0x001c, /* Controller Status */
98 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
99 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
100 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
101 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
102 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
103 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
104 };
105
106 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
107 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
108 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
109 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
110 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
111 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
112
113 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
114 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
115 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
116 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
117
118 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
119 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
120 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
121 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
122 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
123
124 /*
125 * Submission and Completion Queue Entry Sizes for the NVM command set.
126 * (In bytes and specified as a power of two (2^n)).
127 */
128 #define NVME_NVM_IOSQES 6
129 #define NVME_NVM_IOCQES 4
130
131 enum {
132 NVME_CC_ENABLE = 1 << 0,
133 NVME_CC_CSS_NVM = 0 << 4,
134 NVME_CC_MPS_SHIFT = 7,
135 NVME_CC_ARB_RR = 0 << 11,
136 NVME_CC_ARB_WRRU = 1 << 11,
137 NVME_CC_ARB_VS = 7 << 11,
138 NVME_CC_SHN_NONE = 0 << 14,
139 NVME_CC_SHN_NORMAL = 1 << 14,
140 NVME_CC_SHN_ABRUPT = 2 << 14,
141 NVME_CC_SHN_MASK = 3 << 14,
142 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
143 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
144 NVME_CSTS_RDY = 1 << 0,
145 NVME_CSTS_CFS = 1 << 1,
146 NVME_CSTS_NSSRO = 1 << 4,
147 NVME_CSTS_SHST_NORMAL = 0 << 2,
148 NVME_CSTS_SHST_OCCUR = 1 << 2,
149 NVME_CSTS_SHST_CMPLT = 2 << 2,
150 NVME_CSTS_SHST_MASK = 3 << 2,
151 };
152
153 struct nvme_id_power_state {
154 __le16 max_power; /* centiwatts */
155 __u8 rsvd2;
156 __u8 flags;
157 __le32 entry_lat; /* microseconds */
158 __le32 exit_lat; /* microseconds */
159 __u8 read_tput;
160 __u8 read_lat;
161 __u8 write_tput;
162 __u8 write_lat;
163 __le16 idle_power;
164 __u8 idle_scale;
165 __u8 rsvd19;
166 __le16 active_power;
167 __u8 active_work_scale;
168 __u8 rsvd23[9];
169 };
170
171 enum {
172 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
173 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
174 };
175
176 struct nvme_id_ctrl {
177 __le16 vid;
178 __le16 ssvid;
179 char sn[20];
180 char mn[40];
181 char fr[8];
182 __u8 rab;
183 __u8 ieee[3];
184 __u8 cmic;
185 __u8 mdts;
186 __le16 cntlid;
187 __le32 ver;
188 __le32 rtd3r;
189 __le32 rtd3e;
190 __le32 oaes;
191 __le32 ctratt;
192 __u8 rsvd100[156];
193 __le16 oacs;
194 __u8 acl;
195 __u8 aerl;
196 __u8 frmw;
197 __u8 lpa;
198 __u8 elpe;
199 __u8 npss;
200 __u8 avscc;
201 __u8 apsta;
202 __le16 wctemp;
203 __le16 cctemp;
204 __le16 mtfa;
205 __le32 hmpre;
206 __le32 hmmin;
207 __u8 tnvmcap[16];
208 __u8 unvmcap[16];
209 __le32 rpmbs;
210 __u8 rsvd316[4];
211 __le16 kas;
212 __u8 rsvd322[190];
213 __u8 sqes;
214 __u8 cqes;
215 __le16 maxcmd;
216 __le32 nn;
217 __le16 oncs;
218 __le16 fuses;
219 __u8 fna;
220 __u8 vwc;
221 __le16 awun;
222 __le16 awupf;
223 __u8 nvscc;
224 __u8 rsvd531;
225 __le16 acwu;
226 __u8 rsvd534[2];
227 __le32 sgls;
228 __u8 rsvd540[228];
229 char subnqn[256];
230 __u8 rsvd1024[768];
231 __le32 ioccsz;
232 __le32 iorcsz;
233 __le16 icdoff;
234 __u8 ctrattr;
235 __u8 msdbd;
236 __u8 rsvd1804[244];
237 struct nvme_id_power_state psd[32];
238 __u8 vs[1024];
239 };
240
241 enum {
242 NVME_CTRL_ONCS_COMPARE = 1 << 0,
243 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
244 NVME_CTRL_ONCS_DSM = 1 << 2,
245 NVME_CTRL_VWC_PRESENT = 1 << 0,
246 };
247
248 struct nvme_lbaf {
249 __le16 ms;
250 __u8 ds;
251 __u8 rp;
252 };
253
254 struct nvme_id_ns {
255 __le64 nsze;
256 __le64 ncap;
257 __le64 nuse;
258 __u8 nsfeat;
259 __u8 nlbaf;
260 __u8 flbas;
261 __u8 mc;
262 __u8 dpc;
263 __u8 dps;
264 __u8 nmic;
265 __u8 rescap;
266 __u8 fpi;
267 __u8 rsvd33;
268 __le16 nawun;
269 __le16 nawupf;
270 __le16 nacwu;
271 __le16 nabsn;
272 __le16 nabo;
273 __le16 nabspf;
274 __u16 rsvd46;
275 __u8 nvmcap[16];
276 __u8 rsvd64[40];
277 __u8 nguid[16];
278 __u8 eui64[8];
279 struct nvme_lbaf lbaf[16];
280 __u8 rsvd192[192];
281 __u8 vs[3712];
282 };
283
284 enum {
285 NVME_ID_CNS_NS = 0x00,
286 NVME_ID_CNS_CTRL = 0x01,
287 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
288 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
289 NVME_ID_CNS_NS_PRESENT = 0x11,
290 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
291 NVME_ID_CNS_CTRL_LIST = 0x13,
292 };
293
294 enum {
295 NVME_NS_FEAT_THIN = 1 << 0,
296 NVME_NS_FLBAS_LBA_MASK = 0xf,
297 NVME_NS_FLBAS_META_EXT = 0x10,
298 NVME_LBAF_RP_BEST = 0,
299 NVME_LBAF_RP_BETTER = 1,
300 NVME_LBAF_RP_GOOD = 2,
301 NVME_LBAF_RP_DEGRADED = 3,
302 NVME_NS_DPC_PI_LAST = 1 << 4,
303 NVME_NS_DPC_PI_FIRST = 1 << 3,
304 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
305 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
306 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
307 NVME_NS_DPS_PI_FIRST = 1 << 3,
308 NVME_NS_DPS_PI_MASK = 0x7,
309 NVME_NS_DPS_PI_TYPE1 = 1,
310 NVME_NS_DPS_PI_TYPE2 = 2,
311 NVME_NS_DPS_PI_TYPE3 = 3,
312 };
313
314 struct nvme_smart_log {
315 __u8 critical_warning;
316 __u8 temperature[2];
317 __u8 avail_spare;
318 __u8 spare_thresh;
319 __u8 percent_used;
320 __u8 rsvd6[26];
321 __u8 data_units_read[16];
322 __u8 data_units_written[16];
323 __u8 host_reads[16];
324 __u8 host_writes[16];
325 __u8 ctrl_busy_time[16];
326 __u8 power_cycles[16];
327 __u8 power_on_hours[16];
328 __u8 unsafe_shutdowns[16];
329 __u8 media_errors[16];
330 __u8 num_err_log_entries[16];
331 __le32 warning_temp_time;
332 __le32 critical_comp_time;
333 __le16 temp_sensor[8];
334 __u8 rsvd216[296];
335 };
336
337 enum {
338 NVME_SMART_CRIT_SPARE = 1 << 0,
339 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
340 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
341 NVME_SMART_CRIT_MEDIA = 1 << 3,
342 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
343 };
344
345 enum {
346 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
347 };
348
349 struct nvme_lba_range_type {
350 __u8 type;
351 __u8 attributes;
352 __u8 rsvd2[14];
353 __u64 slba;
354 __u64 nlb;
355 __u8 guid[16];
356 __u8 rsvd48[16];
357 };
358
359 enum {
360 NVME_LBART_TYPE_FS = 0x01,
361 NVME_LBART_TYPE_RAID = 0x02,
362 NVME_LBART_TYPE_CACHE = 0x03,
363 NVME_LBART_TYPE_SWAP = 0x04,
364
365 NVME_LBART_ATTRIB_TEMP = 1 << 0,
366 NVME_LBART_ATTRIB_HIDE = 1 << 1,
367 };
368
369 struct nvme_reservation_status {
370 __le32 gen;
371 __u8 rtype;
372 __u8 regctl[2];
373 __u8 resv5[2];
374 __u8 ptpls;
375 __u8 resv10[13];
376 struct {
377 __le16 cntlid;
378 __u8 rcsts;
379 __u8 resv3[5];
380 __le64 hostid;
381 __le64 rkey;
382 } regctl_ds[];
383 };
384
385 enum nvme_async_event_type {
386 NVME_AER_TYPE_ERROR = 0,
387 NVME_AER_TYPE_SMART = 1,
388 NVME_AER_TYPE_NOTICE = 2,
389 };
390
391 /* I/O commands */
392
393 enum nvme_opcode {
394 nvme_cmd_flush = 0x00,
395 nvme_cmd_write = 0x01,
396 nvme_cmd_read = 0x02,
397 nvme_cmd_write_uncor = 0x04,
398 nvme_cmd_compare = 0x05,
399 nvme_cmd_write_zeroes = 0x08,
400 nvme_cmd_dsm = 0x09,
401 nvme_cmd_resv_register = 0x0d,
402 nvme_cmd_resv_report = 0x0e,
403 nvme_cmd_resv_acquire = 0x11,
404 nvme_cmd_resv_release = 0x15,
405 };
406
407 /*
408 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
409 *
410 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
411 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
412 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
413 * request subtype
414 */
415 enum {
416 NVME_SGL_FMT_ADDRESS = 0x00,
417 NVME_SGL_FMT_OFFSET = 0x01,
418 NVME_SGL_FMT_INVALIDATE = 0x0f,
419 };
420
421 /*
422 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
423 *
424 * For struct nvme_sgl_desc:
425 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
426 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
427 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
428 *
429 * For struct nvme_keyed_sgl_desc:
430 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
431 */
432 enum {
433 NVME_SGL_FMT_DATA_DESC = 0x00,
434 NVME_SGL_FMT_SEG_DESC = 0x02,
435 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
436 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
437 };
438
439 struct nvme_sgl_desc {
440 __le64 addr;
441 __le32 length;
442 __u8 rsvd[3];
443 __u8 type;
444 };
445
446 struct nvme_keyed_sgl_desc {
447 __le64 addr;
448 __u8 length[3];
449 __u8 key[4];
450 __u8 type;
451 };
452
453 union nvme_data_ptr {
454 struct {
455 __le64 prp1;
456 __le64 prp2;
457 };
458 struct nvme_sgl_desc sgl;
459 struct nvme_keyed_sgl_desc ksgl;
460 };
461
462 /*
463 * Lowest two bits of our flags field (FUSE field in the spec):
464 *
465 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
466 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
467 *
468 * Highest two bits in our flags field (PSDT field in the spec):
469 *
470 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
471 * If used, MPTR contains addr of single physical buffer (byte aligned).
472 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
473 * If used, MPTR contains an address of an SGL segment containing
474 * exactly 1 SGL descriptor (qword aligned).
475 */
476 enum {
477 NVME_CMD_FUSE_FIRST = (1 << 0),
478 NVME_CMD_FUSE_SECOND = (1 << 1),
479
480 NVME_CMD_SGL_METABUF = (1 << 6),
481 NVME_CMD_SGL_METASEG = (1 << 7),
482 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
483 };
484
485 struct nvme_common_command {
486 __u8 opcode;
487 __u8 flags;
488 __u16 command_id;
489 __le32 nsid;
490 __le32 cdw2[2];
491 __le64 metadata;
492 union nvme_data_ptr dptr;
493 __le32 cdw10[6];
494 };
495
496 struct nvme_rw_command {
497 __u8 opcode;
498 __u8 flags;
499 __u16 command_id;
500 __le32 nsid;
501 __u64 rsvd2;
502 __le64 metadata;
503 union nvme_data_ptr dptr;
504 __le64 slba;
505 __le16 length;
506 __le16 control;
507 __le32 dsmgmt;
508 __le32 reftag;
509 __le16 apptag;
510 __le16 appmask;
511 };
512
513 enum {
514 NVME_RW_LR = 1 << 15,
515 NVME_RW_FUA = 1 << 14,
516 NVME_RW_DSM_FREQ_UNSPEC = 0,
517 NVME_RW_DSM_FREQ_TYPICAL = 1,
518 NVME_RW_DSM_FREQ_RARE = 2,
519 NVME_RW_DSM_FREQ_READS = 3,
520 NVME_RW_DSM_FREQ_WRITES = 4,
521 NVME_RW_DSM_FREQ_RW = 5,
522 NVME_RW_DSM_FREQ_ONCE = 6,
523 NVME_RW_DSM_FREQ_PREFETCH = 7,
524 NVME_RW_DSM_FREQ_TEMP = 8,
525 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
526 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
527 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
528 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
529 NVME_RW_DSM_SEQ_REQ = 1 << 6,
530 NVME_RW_DSM_COMPRESSED = 1 << 7,
531 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
532 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
533 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
534 NVME_RW_PRINFO_PRACT = 1 << 13,
535 };
536
537 struct nvme_dsm_cmd {
538 __u8 opcode;
539 __u8 flags;
540 __u16 command_id;
541 __le32 nsid;
542 __u64 rsvd2[2];
543 union nvme_data_ptr dptr;
544 __le32 nr;
545 __le32 attributes;
546 __u32 rsvd12[4];
547 };
548
549 enum {
550 NVME_DSMGMT_IDR = 1 << 0,
551 NVME_DSMGMT_IDW = 1 << 1,
552 NVME_DSMGMT_AD = 1 << 2,
553 };
554
555 struct nvme_dsm_range {
556 __le32 cattr;
557 __le32 nlb;
558 __le64 slba;
559 };
560
561 /* Admin commands */
562
563 enum nvme_admin_opcode {
564 nvme_admin_delete_sq = 0x00,
565 nvme_admin_create_sq = 0x01,
566 nvme_admin_get_log_page = 0x02,
567 nvme_admin_delete_cq = 0x04,
568 nvme_admin_create_cq = 0x05,
569 nvme_admin_identify = 0x06,
570 nvme_admin_abort_cmd = 0x08,
571 nvme_admin_set_features = 0x09,
572 nvme_admin_get_features = 0x0a,
573 nvme_admin_async_event = 0x0c,
574 nvme_admin_ns_mgmt = 0x0d,
575 nvme_admin_activate_fw = 0x10,
576 nvme_admin_download_fw = 0x11,
577 nvme_admin_ns_attach = 0x15,
578 nvme_admin_keep_alive = 0x18,
579 nvme_admin_format_nvm = 0x80,
580 nvme_admin_security_send = 0x81,
581 nvme_admin_security_recv = 0x82,
582 };
583
584 enum {
585 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
586 NVME_CQ_IRQ_ENABLED = (1 << 1),
587 NVME_SQ_PRIO_URGENT = (0 << 1),
588 NVME_SQ_PRIO_HIGH = (1 << 1),
589 NVME_SQ_PRIO_MEDIUM = (2 << 1),
590 NVME_SQ_PRIO_LOW = (3 << 1),
591 NVME_FEAT_ARBITRATION = 0x01,
592 NVME_FEAT_POWER_MGMT = 0x02,
593 NVME_FEAT_LBA_RANGE = 0x03,
594 NVME_FEAT_TEMP_THRESH = 0x04,
595 NVME_FEAT_ERR_RECOVERY = 0x05,
596 NVME_FEAT_VOLATILE_WC = 0x06,
597 NVME_FEAT_NUM_QUEUES = 0x07,
598 NVME_FEAT_IRQ_COALESCE = 0x08,
599 NVME_FEAT_IRQ_CONFIG = 0x09,
600 NVME_FEAT_WRITE_ATOMIC = 0x0a,
601 NVME_FEAT_ASYNC_EVENT = 0x0b,
602 NVME_FEAT_AUTO_PST = 0x0c,
603 NVME_FEAT_HOST_MEM_BUF = 0x0d,
604 NVME_FEAT_KATO = 0x0f,
605 NVME_FEAT_SW_PROGRESS = 0x80,
606 NVME_FEAT_HOST_ID = 0x81,
607 NVME_FEAT_RESV_MASK = 0x82,
608 NVME_FEAT_RESV_PERSIST = 0x83,
609 NVME_LOG_ERROR = 0x01,
610 NVME_LOG_SMART = 0x02,
611 NVME_LOG_FW_SLOT = 0x03,
612 NVME_LOG_DISC = 0x70,
613 NVME_LOG_RESERVATION = 0x80,
614 NVME_FWACT_REPL = (0 << 3),
615 NVME_FWACT_REPL_ACTV = (1 << 3),
616 NVME_FWACT_ACTV = (2 << 3),
617 };
618
619 struct nvme_identify {
620 __u8 opcode;
621 __u8 flags;
622 __u16 command_id;
623 __le32 nsid;
624 __u64 rsvd2[2];
625 union nvme_data_ptr dptr;
626 __le32 cns;
627 __u32 rsvd11[5];
628 };
629
630 struct nvme_features {
631 __u8 opcode;
632 __u8 flags;
633 __u16 command_id;
634 __le32 nsid;
635 __u64 rsvd2[2];
636 union nvme_data_ptr dptr;
637 __le32 fid;
638 __le32 dword11;
639 __u32 rsvd12[4];
640 };
641
642 struct nvme_create_cq {
643 __u8 opcode;
644 __u8 flags;
645 __u16 command_id;
646 __u32 rsvd1[5];
647 __le64 prp1;
648 __u64 rsvd8;
649 __le16 cqid;
650 __le16 qsize;
651 __le16 cq_flags;
652 __le16 irq_vector;
653 __u32 rsvd12[4];
654 };
655
656 struct nvme_create_sq {
657 __u8 opcode;
658 __u8 flags;
659 __u16 command_id;
660 __u32 rsvd1[5];
661 __le64 prp1;
662 __u64 rsvd8;
663 __le16 sqid;
664 __le16 qsize;
665 __le16 sq_flags;
666 __le16 cqid;
667 __u32 rsvd12[4];
668 };
669
670 struct nvme_delete_queue {
671 __u8 opcode;
672 __u8 flags;
673 __u16 command_id;
674 __u32 rsvd1[9];
675 __le16 qid;
676 __u16 rsvd10;
677 __u32 rsvd11[5];
678 };
679
680 struct nvme_abort_cmd {
681 __u8 opcode;
682 __u8 flags;
683 __u16 command_id;
684 __u32 rsvd1[9];
685 __le16 sqid;
686 __u16 cid;
687 __u32 rsvd11[5];
688 };
689
690 struct nvme_download_firmware {
691 __u8 opcode;
692 __u8 flags;
693 __u16 command_id;
694 __u32 rsvd1[5];
695 union nvme_data_ptr dptr;
696 __le32 numd;
697 __le32 offset;
698 __u32 rsvd12[4];
699 };
700
701 struct nvme_format_cmd {
702 __u8 opcode;
703 __u8 flags;
704 __u16 command_id;
705 __le32 nsid;
706 __u64 rsvd2[4];
707 __le32 cdw10;
708 __u32 rsvd11[5];
709 };
710
711 struct nvme_get_log_page_command {
712 __u8 opcode;
713 __u8 flags;
714 __u16 command_id;
715 __le32 nsid;
716 __u64 rsvd2[2];
717 union nvme_data_ptr dptr;
718 __u8 lid;
719 __u8 rsvd10;
720 __le16 numdl;
721 __le16 numdu;
722 __u16 rsvd11;
723 __le32 lpol;
724 __le32 lpou;
725 __u32 rsvd14[2];
726 };
727
728 /*
729 * Fabrics subcommands.
730 */
731 enum nvmf_fabrics_opcode {
732 nvme_fabrics_command = 0x7f,
733 };
734
735 enum nvmf_capsule_command {
736 nvme_fabrics_type_property_set = 0x00,
737 nvme_fabrics_type_connect = 0x01,
738 nvme_fabrics_type_property_get = 0x04,
739 };
740
741 struct nvmf_common_command {
742 __u8 opcode;
743 __u8 resv1;
744 __u16 command_id;
745 __u8 fctype;
746 __u8 resv2[35];
747 __u8 ts[24];
748 };
749
750 /*
751 * The legal cntlid range a NVMe Target will provide.
752 * Note that cntlid of value 0 is considered illegal in the fabrics world.
753 * Devices based on earlier specs did not have the subsystem concept;
754 * therefore, those devices had their cntlid value set to 0 as a result.
755 */
756 #define NVME_CNTLID_MIN 1
757 #define NVME_CNTLID_MAX 0xffef
758 #define NVME_CNTLID_DYNAMIC 0xffff
759
760 #define MAX_DISC_LOGS 255
761
762 /* Discovery log page entry */
763 struct nvmf_disc_rsp_page_entry {
764 __u8 trtype;
765 __u8 adrfam;
766 __u8 subtype;
767 __u8 treq;
768 __le16 portid;
769 __le16 cntlid;
770 __le16 asqsz;
771 __u8 resv8[22];
772 char trsvcid[NVMF_TRSVCID_SIZE];
773 __u8 resv64[192];
774 char subnqn[NVMF_NQN_FIELD_LEN];
775 char traddr[NVMF_TRADDR_SIZE];
776 union tsas {
777 char common[NVMF_TSAS_SIZE];
778 struct rdma {
779 __u8 qptype;
780 __u8 prtype;
781 __u8 cms;
782 __u8 resv3[5];
783 __u16 pkey;
784 __u8 resv10[246];
785 } rdma;
786 } tsas;
787 };
788
789 /* Discovery log page header */
790 struct nvmf_disc_rsp_page_hdr {
791 __le64 genctr;
792 __le64 numrec;
793 __le16 recfmt;
794 __u8 resv14[1006];
795 struct nvmf_disc_rsp_page_entry entries[0];
796 };
797
798 struct nvmf_connect_command {
799 __u8 opcode;
800 __u8 resv1;
801 __u16 command_id;
802 __u8 fctype;
803 __u8 resv2[19];
804 union nvme_data_ptr dptr;
805 __le16 recfmt;
806 __le16 qid;
807 __le16 sqsize;
808 __u8 cattr;
809 __u8 resv3;
810 __le32 kato;
811 __u8 resv4[12];
812 };
813
814 struct nvmf_connect_data {
815 __u8 hostid[16];
816 __le16 cntlid;
817 char resv4[238];
818 char subsysnqn[NVMF_NQN_FIELD_LEN];
819 char hostnqn[NVMF_NQN_FIELD_LEN];
820 char resv5[256];
821 };
822
823 struct nvmf_property_set_command {
824 __u8 opcode;
825 __u8 resv1;
826 __u16 command_id;
827 __u8 fctype;
828 __u8 resv2[35];
829 __u8 attrib;
830 __u8 resv3[3];
831 __le32 offset;
832 __le64 value;
833 __u8 resv4[8];
834 };
835
836 struct nvmf_property_get_command {
837 __u8 opcode;
838 __u8 resv1;
839 __u16 command_id;
840 __u8 fctype;
841 __u8 resv2[35];
842 __u8 attrib;
843 __u8 resv3[3];
844 __le32 offset;
845 __u8 resv4[16];
846 };
847
848 struct nvme_command {
849 union {
850 struct nvme_common_command common;
851 struct nvme_rw_command rw;
852 struct nvme_identify identify;
853 struct nvme_features features;
854 struct nvme_create_cq create_cq;
855 struct nvme_create_sq create_sq;
856 struct nvme_delete_queue delete_queue;
857 struct nvme_download_firmware dlfw;
858 struct nvme_format_cmd format;
859 struct nvme_dsm_cmd dsm;
860 struct nvme_abort_cmd abort;
861 struct nvme_get_log_page_command get_log_page;
862 struct nvmf_common_command fabrics;
863 struct nvmf_connect_command connect;
864 struct nvmf_property_set_command prop_set;
865 struct nvmf_property_get_command prop_get;
866 };
867 };
868
869 static inline bool nvme_is_write(struct nvme_command *cmd)
870 {
871 /*
872 * What a mess...
873 *
874 * Why can't we simply have a Fabrics In and Fabrics out command?
875 */
876 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
877 return cmd->fabrics.opcode & 1;
878 return cmd->common.opcode & 1;
879 }
880
881 enum {
882 /*
883 * Generic Command Status:
884 */
885 NVME_SC_SUCCESS = 0x0,
886 NVME_SC_INVALID_OPCODE = 0x1,
887 NVME_SC_INVALID_FIELD = 0x2,
888 NVME_SC_CMDID_CONFLICT = 0x3,
889 NVME_SC_DATA_XFER_ERROR = 0x4,
890 NVME_SC_POWER_LOSS = 0x5,
891 NVME_SC_INTERNAL = 0x6,
892 NVME_SC_ABORT_REQ = 0x7,
893 NVME_SC_ABORT_QUEUE = 0x8,
894 NVME_SC_FUSED_FAIL = 0x9,
895 NVME_SC_FUSED_MISSING = 0xa,
896 NVME_SC_INVALID_NS = 0xb,
897 NVME_SC_CMD_SEQ_ERROR = 0xc,
898 NVME_SC_SGL_INVALID_LAST = 0xd,
899 NVME_SC_SGL_INVALID_COUNT = 0xe,
900 NVME_SC_SGL_INVALID_DATA = 0xf,
901 NVME_SC_SGL_INVALID_METADATA = 0x10,
902 NVME_SC_SGL_INVALID_TYPE = 0x11,
903
904 NVME_SC_SGL_INVALID_OFFSET = 0x16,
905 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
906
907 NVME_SC_LBA_RANGE = 0x80,
908 NVME_SC_CAP_EXCEEDED = 0x81,
909 NVME_SC_NS_NOT_READY = 0x82,
910 NVME_SC_RESERVATION_CONFLICT = 0x83,
911
912 /*
913 * Command Specific Status:
914 */
915 NVME_SC_CQ_INVALID = 0x100,
916 NVME_SC_QID_INVALID = 0x101,
917 NVME_SC_QUEUE_SIZE = 0x102,
918 NVME_SC_ABORT_LIMIT = 0x103,
919 NVME_SC_ABORT_MISSING = 0x104,
920 NVME_SC_ASYNC_LIMIT = 0x105,
921 NVME_SC_FIRMWARE_SLOT = 0x106,
922 NVME_SC_FIRMWARE_IMAGE = 0x107,
923 NVME_SC_INVALID_VECTOR = 0x108,
924 NVME_SC_INVALID_LOG_PAGE = 0x109,
925 NVME_SC_INVALID_FORMAT = 0x10a,
926 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
927 NVME_SC_INVALID_QUEUE = 0x10c,
928 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
929 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
930 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
931 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
932 NVME_SC_FW_NEEDS_RESET = 0x111,
933 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
934 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
935 NVME_SC_OVERLAPPING_RANGE = 0x114,
936 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
937 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
938 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
939 NVME_SC_NS_IS_PRIVATE = 0x119,
940 NVME_SC_NS_NOT_ATTACHED = 0x11a,
941 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
942 NVME_SC_CTRL_LIST_INVALID = 0x11c,
943
944 /*
945 * I/O Command Set Specific - NVM commands:
946 */
947 NVME_SC_BAD_ATTRIBUTES = 0x180,
948 NVME_SC_INVALID_PI = 0x181,
949 NVME_SC_READ_ONLY = 0x182,
950
951 /*
952 * I/O Command Set Specific - Fabrics commands:
953 */
954 NVME_SC_CONNECT_FORMAT = 0x180,
955 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
956 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
957 NVME_SC_CONNECT_RESTART_DISC = 0x183,
958 NVME_SC_CONNECT_INVALID_HOST = 0x184,
959
960 NVME_SC_DISCOVERY_RESTART = 0x190,
961 NVME_SC_AUTH_REQUIRED = 0x191,
962
963 /*
964 * Media and Data Integrity Errors:
965 */
966 NVME_SC_WRITE_FAULT = 0x280,
967 NVME_SC_READ_ERROR = 0x281,
968 NVME_SC_GUARD_CHECK = 0x282,
969 NVME_SC_APPTAG_CHECK = 0x283,
970 NVME_SC_REFTAG_CHECK = 0x284,
971 NVME_SC_COMPARE_FAILED = 0x285,
972 NVME_SC_ACCESS_DENIED = 0x286,
973 NVME_SC_UNWRITTEN_BLOCK = 0x287,
974
975 NVME_SC_DNR = 0x4000,
976 };
977
978 struct nvme_completion {
979 /*
980 * Used by Admin and Fabrics commands to return data:
981 */
982 union {
983 __le16 result16;
984 __le32 result;
985 __le64 result64;
986 };
987 __le16 sq_head; /* how much of this queue may be reclaimed */
988 __le16 sq_id; /* submission queue that generated this entry */
989 __u16 command_id; /* of the command which completed */
990 __le16 status; /* did the command fail, and if so, why? */
991 };
992
993 #define NVME_VS(major, minor, tertiary) \
994 (((major) << 16) | ((minor) << 8) | (tertiary))
995
996 #endif /* _LINUX_NVME_H */
(deprecated) Btrfs devel tree