1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
23 #include "farch_regs.h"
26 #include "workarounds.h"
30 /* Hardware control for SFC4000 (aka Falcon). */
32 /**************************************************************************
36 **************************************************************************
39 #define FALCON_MAC_STATS_SIZE 0x100
41 #define XgRxOctets_offset 0x0
42 #define XgRxOctets_WIDTH 48
43 #define XgRxOctetsOK_offset 0x8
44 #define XgRxOctetsOK_WIDTH 48
45 #define XgRxPkts_offset 0x10
46 #define XgRxPkts_WIDTH 32
47 #define XgRxPktsOK_offset 0x14
48 #define XgRxPktsOK_WIDTH 32
49 #define XgRxBroadcastPkts_offset 0x18
50 #define XgRxBroadcastPkts_WIDTH 32
51 #define XgRxMulticastPkts_offset 0x1C
52 #define XgRxMulticastPkts_WIDTH 32
53 #define XgRxUnicastPkts_offset 0x20
54 #define XgRxUnicastPkts_WIDTH 32
55 #define XgRxUndersizePkts_offset 0x24
56 #define XgRxUndersizePkts_WIDTH 32
57 #define XgRxOversizePkts_offset 0x28
58 #define XgRxOversizePkts_WIDTH 32
59 #define XgRxJabberPkts_offset 0x2C
60 #define XgRxJabberPkts_WIDTH 32
61 #define XgRxUndersizeFCSerrorPkts_offset 0x30
62 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
63 #define XgRxDropEvents_offset 0x34
64 #define XgRxDropEvents_WIDTH 32
65 #define XgRxFCSerrorPkts_offset 0x38
66 #define XgRxFCSerrorPkts_WIDTH 32
67 #define XgRxAlignError_offset 0x3C
68 #define XgRxAlignError_WIDTH 32
69 #define XgRxSymbolError_offset 0x40
70 #define XgRxSymbolError_WIDTH 32
71 #define XgRxInternalMACError_offset 0x44
72 #define XgRxInternalMACError_WIDTH 32
73 #define XgRxControlPkts_offset 0x48
74 #define XgRxControlPkts_WIDTH 32
75 #define XgRxPausePkts_offset 0x4C
76 #define XgRxPausePkts_WIDTH 32
77 #define XgRxPkts64Octets_offset 0x50
78 #define XgRxPkts64Octets_WIDTH 32
79 #define XgRxPkts65to127Octets_offset 0x54
80 #define XgRxPkts65to127Octets_WIDTH 32
81 #define XgRxPkts128to255Octets_offset 0x58
82 #define XgRxPkts128to255Octets_WIDTH 32
83 #define XgRxPkts256to511Octets_offset 0x5C
84 #define XgRxPkts256to511Octets_WIDTH 32
85 #define XgRxPkts512to1023Octets_offset 0x60
86 #define XgRxPkts512to1023Octets_WIDTH 32
87 #define XgRxPkts1024to15xxOctets_offset 0x64
88 #define XgRxPkts1024to15xxOctets_WIDTH 32
89 #define XgRxPkts15xxtoMaxOctets_offset 0x68
90 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
91 #define XgRxLengthError_offset 0x6C
92 #define XgRxLengthError_WIDTH 32
93 #define XgTxPkts_offset 0x80
94 #define XgTxPkts_WIDTH 32
95 #define XgTxOctets_offset 0x88
96 #define XgTxOctets_WIDTH 48
97 #define XgTxMulticastPkts_offset 0x90
98 #define XgTxMulticastPkts_WIDTH 32
99 #define XgTxBroadcastPkts_offset 0x94
100 #define XgTxBroadcastPkts_WIDTH 32
101 #define XgTxUnicastPkts_offset 0x98
102 #define XgTxUnicastPkts_WIDTH 32
103 #define XgTxControlPkts_offset 0x9C
104 #define XgTxControlPkts_WIDTH 32
105 #define XgTxPausePkts_offset 0xA0
106 #define XgTxPausePkts_WIDTH 32
107 #define XgTxPkts64Octets_offset 0xA4
108 #define XgTxPkts64Octets_WIDTH 32
109 #define XgTxPkts65to127Octets_offset 0xA8
110 #define XgTxPkts65to127Octets_WIDTH 32
111 #define XgTxPkts128to255Octets_offset 0xAC
112 #define XgTxPkts128to255Octets_WIDTH 32
113 #define XgTxPkts256to511Octets_offset 0xB0
114 #define XgTxPkts256to511Octets_WIDTH 32
115 #define XgTxPkts512to1023Octets_offset 0xB4
116 #define XgTxPkts512to1023Octets_WIDTH 32
117 #define XgTxPkts1024to15xxOctets_offset 0xB8
118 #define XgTxPkts1024to15xxOctets_WIDTH 32
119 #define XgTxPkts1519toMaxOctets_offset 0xBC
120 #define XgTxPkts1519toMaxOctets_WIDTH 32
121 #define XgTxUndersizePkts_offset 0xC0
122 #define XgTxUndersizePkts_WIDTH 32
123 #define XgTxOversizePkts_offset 0xC4
124 #define XgTxOversizePkts_WIDTH 32
125 #define XgTxNonTcpUdpPkt_offset 0xC8
126 #define XgTxNonTcpUdpPkt_WIDTH 16
127 #define XgTxMacSrcErrPkt_offset 0xCC
128 #define XgTxMacSrcErrPkt_WIDTH 16
129 #define XgTxIpSrcErrPkt_offset 0xD0
130 #define XgTxIpSrcErrPkt_WIDTH 16
131 #define XgDmaDone_offset 0xD4
132 #define XgDmaDone_WIDTH 32
134 #define FALCON_XMAC_STATS_DMA_FLAG(efx) \
135 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
137 #define FALCON_DMA_STAT(ext_name, hw_name) \
138 [FALCON_STAT_ ## ext_name] = \
140 /* 48-bit stats are zero-padded to 64 on DMA */ \
141 hw_name ## _ ## WIDTH == 48 ? 64 : hw_name ## _ ## WIDTH, \
142 hw_name ## _ ## offset }
143 #define FALCON_OTHER_STAT(ext_name) \
144 [FALCON_STAT_ ## ext_name] = { #ext_name, 0, 0 }
146 static const struct efx_hw_stat_desc falcon_stat_desc
[FALCON_STAT_COUNT
] = {
147 FALCON_DMA_STAT(tx_bytes
, XgTxOctets
),
148 FALCON_DMA_STAT(tx_packets
, XgTxPkts
),
149 FALCON_DMA_STAT(tx_pause
, XgTxPausePkts
),
150 FALCON_DMA_STAT(tx_control
, XgTxControlPkts
),
151 FALCON_DMA_STAT(tx_unicast
, XgTxUnicastPkts
),
152 FALCON_DMA_STAT(tx_multicast
, XgTxMulticastPkts
),
153 FALCON_DMA_STAT(tx_broadcast
, XgTxBroadcastPkts
),
154 FALCON_DMA_STAT(tx_lt64
, XgTxUndersizePkts
),
155 FALCON_DMA_STAT(tx_64
, XgTxPkts64Octets
),
156 FALCON_DMA_STAT(tx_65_to_127
, XgTxPkts65to127Octets
),
157 FALCON_DMA_STAT(tx_128_to_255
, XgTxPkts128to255Octets
),
158 FALCON_DMA_STAT(tx_256_to_511
, XgTxPkts256to511Octets
),
159 FALCON_DMA_STAT(tx_512_to_1023
, XgTxPkts512to1023Octets
),
160 FALCON_DMA_STAT(tx_1024_to_15xx
, XgTxPkts1024to15xxOctets
),
161 FALCON_DMA_STAT(tx_15xx_to_jumbo
, XgTxPkts1519toMaxOctets
),
162 FALCON_DMA_STAT(tx_gtjumbo
, XgTxOversizePkts
),
163 FALCON_DMA_STAT(tx_non_tcpudp
, XgTxNonTcpUdpPkt
),
164 FALCON_DMA_STAT(tx_mac_src_error
, XgTxMacSrcErrPkt
),
165 FALCON_DMA_STAT(tx_ip_src_error
, XgTxIpSrcErrPkt
),
166 FALCON_DMA_STAT(rx_bytes
, XgRxOctets
),
167 FALCON_DMA_STAT(rx_good_bytes
, XgRxOctetsOK
),
168 FALCON_OTHER_STAT(rx_bad_bytes
),
169 FALCON_DMA_STAT(rx_packets
, XgRxPkts
),
170 FALCON_DMA_STAT(rx_good
, XgRxPktsOK
),
171 FALCON_DMA_STAT(rx_bad
, XgRxFCSerrorPkts
),
172 FALCON_DMA_STAT(rx_pause
, XgRxPausePkts
),
173 FALCON_DMA_STAT(rx_control
, XgRxControlPkts
),
174 FALCON_DMA_STAT(rx_unicast
, XgRxUnicastPkts
),
175 FALCON_DMA_STAT(rx_multicast
, XgRxMulticastPkts
),
176 FALCON_DMA_STAT(rx_broadcast
, XgRxBroadcastPkts
),
177 FALCON_DMA_STAT(rx_lt64
, XgRxUndersizePkts
),
178 FALCON_DMA_STAT(rx_64
, XgRxPkts64Octets
),
179 FALCON_DMA_STAT(rx_65_to_127
, XgRxPkts65to127Octets
),
180 FALCON_DMA_STAT(rx_128_to_255
, XgRxPkts128to255Octets
),
181 FALCON_DMA_STAT(rx_256_to_511
, XgRxPkts256to511Octets
),
182 FALCON_DMA_STAT(rx_512_to_1023
, XgRxPkts512to1023Octets
),
183 FALCON_DMA_STAT(rx_1024_to_15xx
, XgRxPkts1024to15xxOctets
),
184 FALCON_DMA_STAT(rx_15xx_to_jumbo
, XgRxPkts15xxtoMaxOctets
),
185 FALCON_DMA_STAT(rx_gtjumbo
, XgRxOversizePkts
),
186 FALCON_DMA_STAT(rx_bad_lt64
, XgRxUndersizeFCSerrorPkts
),
187 FALCON_DMA_STAT(rx_bad_gtjumbo
, XgRxJabberPkts
),
188 FALCON_DMA_STAT(rx_overflow
, XgRxDropEvents
),
189 FALCON_DMA_STAT(rx_symbol_error
, XgRxSymbolError
),
190 FALCON_DMA_STAT(rx_align_error
, XgRxAlignError
),
191 FALCON_DMA_STAT(rx_length_error
, XgRxLengthError
),
192 FALCON_DMA_STAT(rx_internal_error
, XgRxInternalMACError
),
193 FALCON_OTHER_STAT(rx_nodesc_drop_cnt
),
195 static const unsigned long falcon_stat_mask
[] = {
196 [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT
) - 1] = ~0UL,
199 /**************************************************************************
201 * Basic SPI command set and bit definitions
203 *************************************************************************/
205 #define SPI_WRSR 0x01 /* Write status register */
206 #define SPI_WRITE 0x02 /* Write data to memory array */
207 #define SPI_READ 0x03 /* Read data from memory array */
208 #define SPI_WRDI 0x04 /* Reset write enable latch */
209 #define SPI_RDSR 0x05 /* Read status register */
210 #define SPI_WREN 0x06 /* Set write enable latch */
211 #define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */
213 #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
214 #define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
215 #define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
216 #define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
217 #define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
218 #define SPI_STATUS_NRDY 0x01 /* Device busy flag */
220 /**************************************************************************
222 * Non-volatile memory layout
224 **************************************************************************
227 /* SFC4000 flash is partitioned into:
228 * 0-0x400 chip and board config (see struct falcon_nvconfig)
229 * 0x400-0x8000 unused (or may contain VPD if EEPROM not present)
230 * 0x8000-end boot code (mapped to PCI expansion ROM)
231 * SFC4000 small EEPROM (size < 0x400) is used for VPD only.
232 * SFC4000 large EEPROM (size >= 0x400) is partitioned into:
233 * 0-0x400 chip and board config
235 * 0x800-0x1800 boot config
236 * Aside from the chip and board config, all of these are optional and may
237 * be absent or truncated depending on the devices used.
239 #define FALCON_NVCONFIG_END 0x400U
240 #define FALCON_FLASH_BOOTCODE_START 0x8000U
241 #define FALCON_EEPROM_BOOTCONFIG_START 0x800U
242 #define FALCON_EEPROM_BOOTCONFIG_END 0x1800U
244 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
245 struct falcon_nvconfig_board_v2
{
251 __le16 asic_sub_revision
;
252 __le16 board_revision
;
255 /* Board configuration v3 extra information */
256 struct falcon_nvconfig_board_v3
{
257 __le32 spi_device_type
[2];
260 /* Bit numbers for spi_device_type */
261 #define SPI_DEV_TYPE_SIZE_LBN 0
262 #define SPI_DEV_TYPE_SIZE_WIDTH 5
263 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
264 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
265 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
266 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
267 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
268 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
269 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
270 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
271 #define SPI_DEV_TYPE_FIELD(type, field) \
272 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
274 #define FALCON_NVCONFIG_OFFSET 0x300
276 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
277 struct falcon_nvconfig
{
278 efx_oword_t ee_vpd_cfg_reg
; /* 0x300 */
279 u8 mac_address
[2][8]; /* 0x310 */
280 efx_oword_t pcie_sd_ctl0123_reg
; /* 0x320 */
281 efx_oword_t pcie_sd_ctl45_reg
; /* 0x330 */
282 efx_oword_t pcie_pcs_ctl_stat_reg
; /* 0x340 */
283 efx_oword_t hw_init_reg
; /* 0x350 */
284 efx_oword_t nic_stat_reg
; /* 0x360 */
285 efx_oword_t glb_ctl_reg
; /* 0x370 */
286 efx_oword_t srm_cfg_reg
; /* 0x380 */
287 efx_oword_t spare_reg
; /* 0x390 */
288 __le16 board_magic_num
; /* 0x3A0 */
289 __le16 board_struct_ver
;
290 __le16 board_checksum
;
291 struct falcon_nvconfig_board_v2 board_v2
;
292 efx_oword_t ee_base_page_reg
; /* 0x3B0 */
293 struct falcon_nvconfig_board_v3 board_v3
; /* 0x3C0 */
296 /*************************************************************************/
298 static int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
);
299 static void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
);
301 static const unsigned int
302 /* "Large" EEPROM device: Atmel AT25640 or similar
303 * 8 KB, 16-bit address, 32 B write block */
304 large_eeprom_type
= ((13 << SPI_DEV_TYPE_SIZE_LBN
)
305 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
306 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
)),
307 /* Default flash device: Atmel AT25F1024
308 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
309 default_flash_type
= ((17 << SPI_DEV_TYPE_SIZE_LBN
)
310 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN
)
311 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN
)
312 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN
)
313 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN
));
315 /**************************************************************************
317 * I2C bus - this is a bit-bashing interface using GPIO pins
318 * Note that it uses the output enables to tristate the outputs
319 * SDA is the data pin and SCL is the clock
321 **************************************************************************
323 static void falcon_setsda(void *data
, int state
)
325 struct efx_nic
*efx
= (struct efx_nic
*)data
;
328 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
329 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO3_OEN
, !state
);
330 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
333 static void falcon_setscl(void *data
, int state
)
335 struct efx_nic
*efx
= (struct efx_nic
*)data
;
338 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
339 EFX_SET_OWORD_FIELD(reg
, FRF_AB_GPIO0_OEN
, !state
);
340 efx_writeo(efx
, ®
, FR_AB_GPIO_CTL
);
343 static int falcon_getsda(void *data
)
345 struct efx_nic
*efx
= (struct efx_nic
*)data
;
348 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
349 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO3_IN
);
352 static int falcon_getscl(void *data
)
354 struct efx_nic
*efx
= (struct efx_nic
*)data
;
357 efx_reado(efx
, ®
, FR_AB_GPIO_CTL
);
358 return EFX_OWORD_FIELD(reg
, FRF_AB_GPIO0_IN
);
361 static const struct i2c_algo_bit_data falcon_i2c_bit_operations
= {
362 .setsda
= falcon_setsda
,
363 .setscl
= falcon_setscl
,
364 .getsda
= falcon_getsda
,
365 .getscl
= falcon_getscl
,
367 /* Wait up to 50 ms for slave to let us pull SCL high */
368 .timeout
= DIV_ROUND_UP(HZ
, 20),
371 static void falcon_push_irq_moderation(struct efx_channel
*channel
)
373 efx_dword_t timer_cmd
;
374 struct efx_nic
*efx
= channel
->efx
;
376 /* Set timer register */
377 if (channel
->irq_moderation
) {
378 EFX_POPULATE_DWORD_2(timer_cmd
,
379 FRF_AB_TC_TIMER_MODE
,
380 FFE_BB_TIMER_MODE_INT_HLDOFF
,
382 channel
->irq_moderation
- 1);
384 EFX_POPULATE_DWORD_2(timer_cmd
,
385 FRF_AB_TC_TIMER_MODE
,
386 FFE_BB_TIMER_MODE_DIS
,
387 FRF_AB_TC_TIMER_VAL
, 0);
389 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER
!= FR_BZ_TIMER_COMMAND_P0
);
390 efx_writed_page_locked(efx
, &timer_cmd
, FR_BZ_TIMER_COMMAND_P0
,
394 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
);
396 static void falcon_prepare_flush(struct efx_nic
*efx
)
398 falcon_deconfigure_mac_wrapper(efx
);
400 /* Wait for the tx and rx fifo's to get to the next packet boundary
401 * (~1ms without back-pressure), then to drain the remainder of the
402 * fifo's at data path speeds (negligible), with a healthy margin. */
406 /* Acknowledge a legacy interrupt from Falcon
408 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
410 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
411 * BIU. Interrupt acknowledge is read sensitive so must write instead
412 * (then read to ensure the BIU collector is flushed)
414 * NB most hardware supports MSI interrupts
416 static inline void falcon_irq_ack_a1(struct efx_nic
*efx
)
420 EFX_POPULATE_DWORD_1(reg
, FRF_AA_INT_ACK_KER_FIELD
, 0xb7eb7e);
421 efx_writed(efx
, ®
, FR_AA_INT_ACK_KER
);
422 efx_readd(efx
, ®
, FR_AA_WORK_AROUND_BROKEN_PCI_READS
);
426 static irqreturn_t
falcon_legacy_interrupt_a1(int irq
, void *dev_id
)
428 struct efx_nic
*efx
= dev_id
;
429 efx_oword_t
*int_ker
= efx
->irq_status
.addr
;
433 /* Check to see if this is our interrupt. If it isn't, we
434 * exit without having touched the hardware.
436 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker
))) {
437 netif_vdbg(efx
, intr
, efx
->net_dev
,
438 "IRQ %d on CPU %d not for me\n", irq
,
439 raw_smp_processor_id());
442 efx
->last_irq_cpu
= raw_smp_processor_id();
443 netif_vdbg(efx
, intr
, efx
->net_dev
,
444 "IRQ %d on CPU %d status " EFX_OWORD_FMT
"\n",
445 irq
, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker
));
447 if (!likely(ACCESS_ONCE(efx
->irq_soft_enabled
)))
450 /* Check to see if we have a serious error condition */
451 syserr
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_FATAL_INT
);
452 if (unlikely(syserr
))
453 return efx_farch_fatal_interrupt(efx
);
455 /* Determine interrupting queues, clear interrupt status
456 * register and acknowledge the device interrupt.
458 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH
> EFX_MAX_CHANNELS
);
459 queues
= EFX_OWORD_FIELD(*int_ker
, FSF_AZ_NET_IVEC_INT_Q
);
460 EFX_ZERO_OWORD(*int_ker
);
461 wmb(); /* Ensure the vector is cleared before interrupt ack */
462 falcon_irq_ack_a1(efx
);
465 efx_schedule_channel_irq(efx_get_channel(efx
, 0));
467 efx_schedule_channel_irq(efx_get_channel(efx
, 1));
470 /**************************************************************************
474 **************************************************************************
477 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
479 static int falcon_spi_poll(struct efx_nic
*efx
)
482 efx_reado(efx
, ®
, FR_AB_EE_SPI_HCMD
);
483 return EFX_OWORD_FIELD(reg
, FRF_AB_EE_SPI_HCMD_CMD_EN
) ? -EBUSY
: 0;
486 /* Wait for SPI command completion */
487 static int falcon_spi_wait(struct efx_nic
*efx
)
489 /* Most commands will finish quickly, so we start polling at
490 * very short intervals. Sometimes the command may have to
491 * wait for VPD or expansion ROM access outside of our
492 * control, so we allow up to 100 ms. */
493 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 10);
496 for (i
= 0; i
< 10; i
++) {
497 if (!falcon_spi_poll(efx
))
503 if (!falcon_spi_poll(efx
))
505 if (time_after_eq(jiffies
, timeout
)) {
506 netif_err(efx
, hw
, efx
->net_dev
,
507 "timed out waiting for SPI\n");
510 schedule_timeout_uninterruptible(1);
515 falcon_spi_cmd(struct efx_nic
*efx
, const struct falcon_spi_device
*spi
,
516 unsigned int command
, int address
,
517 const void *in
, void *out
, size_t len
)
519 bool addressed
= (address
>= 0);
520 bool reading
= (out
!= NULL
);
524 /* Input validation */
525 if (len
> FALCON_SPI_MAX_LEN
)
528 /* Check that previous command is not still running */
529 rc
= falcon_spi_poll(efx
);
533 /* Program address register, if we have an address */
535 EFX_POPULATE_OWORD_1(reg
, FRF_AB_EE_SPI_HADR_ADR
, address
);
536 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HADR
);
539 /* Program data register, if we have data */
541 memcpy(®
, in
, len
);
542 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HDATA
);
545 /* Issue read/write command */
546 EFX_POPULATE_OWORD_7(reg
,
547 FRF_AB_EE_SPI_HCMD_CMD_EN
, 1,
548 FRF_AB_EE_SPI_HCMD_SF_SEL
, spi
->device_id
,
549 FRF_AB_EE_SPI_HCMD_DABCNT
, len
,
550 FRF_AB_EE_SPI_HCMD_READ
, reading
,
551 FRF_AB_EE_SPI_HCMD_DUBCNT
, 0,
552 FRF_AB_EE_SPI_HCMD_ADBCNT
,
553 (addressed
? spi
->addr_len
: 0),
554 FRF_AB_EE_SPI_HCMD_ENC
, command
);
555 efx_writeo(efx
, ®
, FR_AB_EE_SPI_HCMD
);
557 /* Wait for read/write to complete */
558 rc
= falcon_spi_wait(efx
);
564 efx_reado(efx
, ®
, FR_AB_EE_SPI_HDATA
);
565 memcpy(out
, ®
, len
);
572 falcon_spi_munge_command(const struct falcon_spi_device
*spi
,
573 const u8 command
, const unsigned int address
)
575 return command
| (((address
>> 8) & spi
->munge_address
) << 3);
579 falcon_spi_read(struct efx_nic
*efx
, const struct falcon_spi_device
*spi
,
580 loff_t start
, size_t len
, size_t *retlen
, u8
*buffer
)
582 size_t block_len
, pos
= 0;
583 unsigned int command
;
587 block_len
= min(len
- pos
, FALCON_SPI_MAX_LEN
);
589 command
= falcon_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
590 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
, NULL
,
591 buffer
+ pos
, block_len
);
596 /* Avoid locking up the system */
598 if (signal_pending(current
)) {
609 #ifdef CONFIG_SFC_MTD
611 struct falcon_mtd_partition
{
612 struct efx_mtd_partition common
;
613 const struct falcon_spi_device
*spi
;
617 #define to_falcon_mtd_partition(mtd) \
618 container_of(mtd, struct falcon_mtd_partition, common.mtd)
621 falcon_spi_write_limit(const struct falcon_spi_device
*spi
, size_t start
)
623 return min(FALCON_SPI_MAX_LEN
,
624 (spi
->block_size
- (start
& (spi
->block_size
- 1))));
627 /* Wait up to 10 ms for buffered write completion */
629 falcon_spi_wait_write(struct efx_nic
*efx
, const struct falcon_spi_device
*spi
)
631 unsigned long timeout
= jiffies
+ 1 + DIV_ROUND_UP(HZ
, 100);
636 rc
= falcon_spi_cmd(efx
, spi
, SPI_RDSR
, -1, NULL
,
637 &status
, sizeof(status
));
640 if (!(status
& SPI_STATUS_NRDY
))
642 if (time_after_eq(jiffies
, timeout
)) {
643 netif_err(efx
, hw
, efx
->net_dev
,
644 "SPI write timeout on device %d"
645 " last status=0x%02x\n",
646 spi
->device_id
, status
);
649 schedule_timeout_uninterruptible(1);
654 falcon_spi_write(struct efx_nic
*efx
, const struct falcon_spi_device
*spi
,
655 loff_t start
, size_t len
, size_t *retlen
, const u8
*buffer
)
657 u8 verify_buffer
[FALCON_SPI_MAX_LEN
];
658 size_t block_len
, pos
= 0;
659 unsigned int command
;
663 rc
= falcon_spi_cmd(efx
, spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
667 block_len
= min(len
- pos
,
668 falcon_spi_write_limit(spi
, start
+ pos
));
669 command
= falcon_spi_munge_command(spi
, SPI_WRITE
, start
+ pos
);
670 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
671 buffer
+ pos
, NULL
, block_len
);
675 rc
= falcon_spi_wait_write(efx
, spi
);
679 command
= falcon_spi_munge_command(spi
, SPI_READ
, start
+ pos
);
680 rc
= falcon_spi_cmd(efx
, spi
, command
, start
+ pos
,
681 NULL
, verify_buffer
, block_len
);
682 if (memcmp(verify_buffer
, buffer
+ pos
, block_len
)) {
689 /* Avoid locking up the system */
691 if (signal_pending(current
)) {
703 falcon_spi_slow_wait(struct falcon_mtd_partition
*part
, bool uninterruptible
)
705 const struct falcon_spi_device
*spi
= part
->spi
;
706 struct efx_nic
*efx
= part
->common
.mtd
.priv
;
710 /* Wait up to 4s for flash/EEPROM to finish a slow operation. */
711 for (i
= 0; i
< 40; i
++) {
712 __set_current_state(uninterruptible
?
713 TASK_UNINTERRUPTIBLE
: TASK_INTERRUPTIBLE
);
714 schedule_timeout(HZ
/ 10);
715 rc
= falcon_spi_cmd(efx
, spi
, SPI_RDSR
, -1, NULL
,
716 &status
, sizeof(status
));
719 if (!(status
& SPI_STATUS_NRDY
))
721 if (signal_pending(current
))
724 pr_err("%s: timed out waiting for %s\n",
725 part
->common
.name
, part
->common
.dev_type_name
);
730 falcon_spi_unlock(struct efx_nic
*efx
, const struct falcon_spi_device
*spi
)
732 const u8 unlock_mask
= (SPI_STATUS_BP2
| SPI_STATUS_BP1
|
737 rc
= falcon_spi_cmd(efx
, spi
, SPI_RDSR
, -1, NULL
,
738 &status
, sizeof(status
));
742 if (!(status
& unlock_mask
))
743 return 0; /* already unlocked */
745 rc
= falcon_spi_cmd(efx
, spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
748 rc
= falcon_spi_cmd(efx
, spi
, SPI_SST_EWSR
, -1, NULL
, NULL
, 0);
752 status
&= ~unlock_mask
;
753 rc
= falcon_spi_cmd(efx
, spi
, SPI_WRSR
, -1, &status
,
754 NULL
, sizeof(status
));
757 rc
= falcon_spi_wait_write(efx
, spi
);
764 #define FALCON_SPI_VERIFY_BUF_LEN 16
767 falcon_spi_erase(struct falcon_mtd_partition
*part
, loff_t start
, size_t len
)
769 const struct falcon_spi_device
*spi
= part
->spi
;
770 struct efx_nic
*efx
= part
->common
.mtd
.priv
;
771 unsigned pos
, block_len
;
772 u8 empty
[FALCON_SPI_VERIFY_BUF_LEN
];
773 u8 buffer
[FALCON_SPI_VERIFY_BUF_LEN
];
776 if (len
!= spi
->erase_size
)
779 if (spi
->erase_command
== 0)
782 rc
= falcon_spi_unlock(efx
, spi
);
785 rc
= falcon_spi_cmd(efx
, spi
, SPI_WREN
, -1, NULL
, NULL
, 0);
788 rc
= falcon_spi_cmd(efx
, spi
, spi
->erase_command
, start
, NULL
,
792 rc
= falcon_spi_slow_wait(part
, false);
794 /* Verify the entire region has been wiped */
795 memset(empty
, 0xff, sizeof(empty
));
796 for (pos
= 0; pos
< len
; pos
+= block_len
) {
797 block_len
= min(len
- pos
, sizeof(buffer
));
798 rc
= falcon_spi_read(efx
, spi
, start
+ pos
, block_len
,
802 if (memcmp(empty
, buffer
, block_len
))
805 /* Avoid locking up the system */
807 if (signal_pending(current
))
814 static void falcon_mtd_rename(struct efx_mtd_partition
*part
)
816 struct efx_nic
*efx
= part
->mtd
.priv
;
818 snprintf(part
->name
, sizeof(part
->name
), "%s %s",
819 efx
->name
, part
->type_name
);
822 static int falcon_mtd_read(struct mtd_info
*mtd
, loff_t start
,
823 size_t len
, size_t *retlen
, u8
*buffer
)
825 struct falcon_mtd_partition
*part
= to_falcon_mtd_partition(mtd
);
826 struct efx_nic
*efx
= mtd
->priv
;
827 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
830 rc
= mutex_lock_interruptible(&nic_data
->spi_lock
);
833 rc
= falcon_spi_read(efx
, part
->spi
, part
->offset
+ start
,
834 len
, retlen
, buffer
);
835 mutex_unlock(&nic_data
->spi_lock
);
839 static int falcon_mtd_erase(struct mtd_info
*mtd
, loff_t start
, size_t len
)
841 struct falcon_mtd_partition
*part
= to_falcon_mtd_partition(mtd
);
842 struct efx_nic
*efx
= mtd
->priv
;
843 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
846 rc
= mutex_lock_interruptible(&nic_data
->spi_lock
);
849 rc
= falcon_spi_erase(part
, part
->offset
+ start
, len
);
850 mutex_unlock(&nic_data
->spi_lock
);
854 static int falcon_mtd_write(struct mtd_info
*mtd
, loff_t start
,
855 size_t len
, size_t *retlen
, const u8
*buffer
)
857 struct falcon_mtd_partition
*part
= to_falcon_mtd_partition(mtd
);
858 struct efx_nic
*efx
= mtd
->priv
;
859 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
862 rc
= mutex_lock_interruptible(&nic_data
->spi_lock
);
865 rc
= falcon_spi_write(efx
, part
->spi
, part
->offset
+ start
,
866 len
, retlen
, buffer
);
867 mutex_unlock(&nic_data
->spi_lock
);
871 static int falcon_mtd_sync(struct mtd_info
*mtd
)
873 struct falcon_mtd_partition
*part
= to_falcon_mtd_partition(mtd
);
874 struct efx_nic
*efx
= mtd
->priv
;
875 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
878 mutex_lock(&nic_data
->spi_lock
);
879 rc
= falcon_spi_slow_wait(part
, true);
880 mutex_unlock(&nic_data
->spi_lock
);
884 static int falcon_mtd_probe(struct efx_nic
*efx
)
886 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
887 struct falcon_mtd_partition
*parts
;
888 struct falcon_spi_device
*spi
;
894 /* Allocate space for maximum number of partitions */
895 parts
= kcalloc(2, sizeof(*parts
), GFP_KERNEL
);
898 spi
= &nic_data
->spi_flash
;
899 if (falcon_spi_present(spi
) && spi
->size
> FALCON_FLASH_BOOTCODE_START
) {
900 parts
[n_parts
].spi
= spi
;
901 parts
[n_parts
].offset
= FALCON_FLASH_BOOTCODE_START
;
902 parts
[n_parts
].common
.dev_type_name
= "flash";
903 parts
[n_parts
].common
.type_name
= "sfc_flash_bootrom";
904 parts
[n_parts
].common
.mtd
.type
= MTD_NORFLASH
;
905 parts
[n_parts
].common
.mtd
.flags
= MTD_CAP_NORFLASH
;
906 parts
[n_parts
].common
.mtd
.size
= spi
->size
- FALCON_FLASH_BOOTCODE_START
;
907 parts
[n_parts
].common
.mtd
.erasesize
= spi
->erase_size
;
911 spi
= &nic_data
->spi_eeprom
;
912 if (falcon_spi_present(spi
) && spi
->size
> FALCON_EEPROM_BOOTCONFIG_START
) {
913 parts
[n_parts
].spi
= spi
;
914 parts
[n_parts
].offset
= FALCON_EEPROM_BOOTCONFIG_START
;
915 parts
[n_parts
].common
.dev_type_name
= "EEPROM";
916 parts
[n_parts
].common
.type_name
= "sfc_bootconfig";
917 parts
[n_parts
].common
.mtd
.type
= MTD_RAM
;
918 parts
[n_parts
].common
.mtd
.flags
= MTD_CAP_RAM
;
919 parts
[n_parts
].common
.mtd
.size
=
920 min(spi
->size
, FALCON_EEPROM_BOOTCONFIG_END
) -
921 FALCON_EEPROM_BOOTCONFIG_START
;
922 parts
[n_parts
].common
.mtd
.erasesize
= spi
->erase_size
;
926 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
932 #endif /* CONFIG_SFC_MTD */
934 /**************************************************************************
938 **************************************************************************
941 /* Configure the XAUI driver that is an output from Falcon */
942 static void falcon_setup_xaui(struct efx_nic
*efx
)
944 efx_oword_t sdctl
, txdrv
;
946 /* Move the XAUI into low power, unless there is no PHY, in
947 * which case the XAUI will have to drive a cable. */
948 if (efx
->phy_type
== PHY_TYPE_NONE
)
951 efx_reado(efx
, &sdctl
, FR_AB_XX_SD_CTL
);
952 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_HIDRVD
, FFE_AB_XX_SD_CTL_DRV_DEF
);
953 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_LODRVD
, FFE_AB_XX_SD_CTL_DRV_DEF
);
954 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_HIDRVC
, FFE_AB_XX_SD_CTL_DRV_DEF
);
955 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_LODRVC
, FFE_AB_XX_SD_CTL_DRV_DEF
);
956 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_HIDRVB
, FFE_AB_XX_SD_CTL_DRV_DEF
);
957 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_LODRVB
, FFE_AB_XX_SD_CTL_DRV_DEF
);
958 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_HIDRVA
, FFE_AB_XX_SD_CTL_DRV_DEF
);
959 EFX_SET_OWORD_FIELD(sdctl
, FRF_AB_XX_LODRVA
, FFE_AB_XX_SD_CTL_DRV_DEF
);
960 efx_writeo(efx
, &sdctl
, FR_AB_XX_SD_CTL
);
962 EFX_POPULATE_OWORD_8(txdrv
,
963 FRF_AB_XX_DEQD
, FFE_AB_XX_TXDRV_DEQ_DEF
,
964 FRF_AB_XX_DEQC
, FFE_AB_XX_TXDRV_DEQ_DEF
,
965 FRF_AB_XX_DEQB
, FFE_AB_XX_TXDRV_DEQ_DEF
,
966 FRF_AB_XX_DEQA
, FFE_AB_XX_TXDRV_DEQ_DEF
,
967 FRF_AB_XX_DTXD
, FFE_AB_XX_TXDRV_DTX_DEF
,
968 FRF_AB_XX_DTXC
, FFE_AB_XX_TXDRV_DTX_DEF
,
969 FRF_AB_XX_DTXB
, FFE_AB_XX_TXDRV_DTX_DEF
,
970 FRF_AB_XX_DTXA
, FFE_AB_XX_TXDRV_DTX_DEF
);
971 efx_writeo(efx
, &txdrv
, FR_AB_XX_TXDRV_CTL
);
974 int falcon_reset_xaui(struct efx_nic
*efx
)
976 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
980 /* Don't fetch MAC statistics over an XMAC reset */
981 WARN_ON(nic_data
->stats_disable_count
== 0);
983 /* Start reset sequence */
984 EFX_POPULATE_OWORD_1(reg
, FRF_AB_XX_RST_XX_EN
, 1);
985 efx_writeo(efx
, ®
, FR_AB_XX_PWR_RST
);
987 /* Wait up to 10 ms for completion, then reinitialise */
988 for (count
= 0; count
< 1000; count
++) {
989 efx_reado(efx
, ®
, FR_AB_XX_PWR_RST
);
990 if (EFX_OWORD_FIELD(reg
, FRF_AB_XX_RST_XX_EN
) == 0 &&
991 EFX_OWORD_FIELD(reg
, FRF_AB_XX_SD_RST_ACT
) == 0) {
992 falcon_setup_xaui(efx
);
997 netif_err(efx
, hw
, efx
->net_dev
,
998 "timed out waiting for XAUI/XGXS reset\n");
1002 static void falcon_ack_status_intr(struct efx_nic
*efx
)
1004 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1007 if ((efx_nic_rev(efx
) != EFX_REV_FALCON_B0
) || LOOPBACK_INTERNAL(efx
))
1010 /* We expect xgmii faults if the wireside link is down */
1011 if (!efx
->link_state
.up
)
1014 /* We can only use this interrupt to signal the negative edge of
1015 * xaui_align [we have to poll the positive edge]. */
1016 if (nic_data
->xmac_poll_required
)
1019 efx_reado(efx
, ®
, FR_AB_XM_MGT_INT_MSK
);
1022 static bool falcon_xgxs_link_ok(struct efx_nic
*efx
)
1025 bool align_done
, link_ok
= false;
1028 /* Read link status */
1029 efx_reado(efx
, ®
, FR_AB_XX_CORE_STAT
);
1031 align_done
= EFX_OWORD_FIELD(reg
, FRF_AB_XX_ALIGN_DONE
);
1032 sync_status
= EFX_OWORD_FIELD(reg
, FRF_AB_XX_SYNC_STAT
);
1033 if (align_done
&& (sync_status
== FFE_AB_XX_STAT_ALL_LANES
))
1036 /* Clear link status ready for next read */
1037 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_COMMA_DET
, FFE_AB_XX_STAT_ALL_LANES
);
1038 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_CHAR_ERR
, FFE_AB_XX_STAT_ALL_LANES
);
1039 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_DISPERR
, FFE_AB_XX_STAT_ALL_LANES
);
1040 efx_writeo(efx
, ®
, FR_AB_XX_CORE_STAT
);
1045 static bool falcon_xmac_link_ok(struct efx_nic
*efx
)
1048 * Check MAC's XGXS link status except when using XGMII loopback
1049 * which bypasses the XGXS block.
1050 * If possible, check PHY's XGXS link status except when using
1053 return (efx
->loopback_mode
== LOOPBACK_XGMII
||
1054 falcon_xgxs_link_ok(efx
)) &&
1055 (!(efx
->mdio
.mmds
& (1 << MDIO_MMD_PHYXS
)) ||
1056 LOOPBACK_INTERNAL(efx
) ||
1057 efx_mdio_phyxgxs_lane_sync(efx
));
1060 static void falcon_reconfigure_xmac_core(struct efx_nic
*efx
)
1062 unsigned int max_frame_len
;
1064 bool rx_fc
= !!(efx
->link_state
.fc
& EFX_FC_RX
);
1065 bool tx_fc
= !!(efx
->link_state
.fc
& EFX_FC_TX
);
1067 /* Configure MAC - cut-thru mode is hard wired on */
1068 EFX_POPULATE_OWORD_3(reg
,
1069 FRF_AB_XM_RX_JUMBO_MODE
, 1,
1070 FRF_AB_XM_TX_STAT_EN
, 1,
1071 FRF_AB_XM_RX_STAT_EN
, 1);
1072 efx_writeo(efx
, ®
, FR_AB_XM_GLB_CFG
);
1075 EFX_POPULATE_OWORD_6(reg
,
1077 FRF_AB_XM_TX_PRMBL
, 1,
1078 FRF_AB_XM_AUTO_PAD
, 1,
1080 FRF_AB_XM_FCNTL
, tx_fc
,
1081 FRF_AB_XM_IPG
, 0x3);
1082 efx_writeo(efx
, ®
, FR_AB_XM_TX_CFG
);
1085 EFX_POPULATE_OWORD_5(reg
,
1087 FRF_AB_XM_AUTO_DEPAD
, 0,
1088 FRF_AB_XM_ACPT_ALL_MCAST
, 1,
1089 FRF_AB_XM_ACPT_ALL_UCAST
, !efx
->unicast_filter
,
1090 FRF_AB_XM_PASS_CRC_ERR
, 1);
1091 efx_writeo(efx
, ®
, FR_AB_XM_RX_CFG
);
1093 /* Set frame length */
1094 max_frame_len
= EFX_MAX_FRAME_LEN(efx
->net_dev
->mtu
);
1095 EFX_POPULATE_OWORD_1(reg
, FRF_AB_XM_MAX_RX_FRM_SIZE
, max_frame_len
);
1096 efx_writeo(efx
, ®
, FR_AB_XM_RX_PARAM
);
1097 EFX_POPULATE_OWORD_2(reg
,
1098 FRF_AB_XM_MAX_TX_FRM_SIZE
, max_frame_len
,
1099 FRF_AB_XM_TX_JUMBO_MODE
, 1);
1100 efx_writeo(efx
, ®
, FR_AB_XM_TX_PARAM
);
1102 EFX_POPULATE_OWORD_2(reg
,
1103 FRF_AB_XM_PAUSE_TIME
, 0xfffe, /* MAX PAUSE TIME */
1104 FRF_AB_XM_DIS_FCNTL
, !rx_fc
);
1105 efx_writeo(efx
, ®
, FR_AB_XM_FC
);
1107 /* Set MAC address */
1108 memcpy(®
, &efx
->net_dev
->dev_addr
[0], 4);
1109 efx_writeo(efx
, ®
, FR_AB_XM_ADR_LO
);
1110 memcpy(®
, &efx
->net_dev
->dev_addr
[4], 2);
1111 efx_writeo(efx
, ®
, FR_AB_XM_ADR_HI
);
1114 static void falcon_reconfigure_xgxs_core(struct efx_nic
*efx
)
1117 bool xgxs_loopback
= (efx
->loopback_mode
== LOOPBACK_XGXS
);
1118 bool xaui_loopback
= (efx
->loopback_mode
== LOOPBACK_XAUI
);
1119 bool xgmii_loopback
= (efx
->loopback_mode
== LOOPBACK_XGMII
);
1120 bool old_xgmii_loopback
, old_xgxs_loopback
, old_xaui_loopback
;
1122 /* XGXS block is flaky and will need to be reset if moving
1123 * into our out of XGMII, XGXS or XAUI loopbacks. */
1124 efx_reado(efx
, ®
, FR_AB_XX_CORE_STAT
);
1125 old_xgxs_loopback
= EFX_OWORD_FIELD(reg
, FRF_AB_XX_XGXS_LB_EN
);
1126 old_xgmii_loopback
= EFX_OWORD_FIELD(reg
, FRF_AB_XX_XGMII_LB_EN
);
1128 efx_reado(efx
, ®
, FR_AB_XX_SD_CTL
);
1129 old_xaui_loopback
= EFX_OWORD_FIELD(reg
, FRF_AB_XX_LPBKA
);
1131 /* The PHY driver may have turned XAUI off */
1132 if ((xgxs_loopback
!= old_xgxs_loopback
) ||
1133 (xaui_loopback
!= old_xaui_loopback
) ||
1134 (xgmii_loopback
!= old_xgmii_loopback
))
1135 falcon_reset_xaui(efx
);
1137 efx_reado(efx
, ®
, FR_AB_XX_CORE_STAT
);
1138 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_FORCE_SIG
,
1139 (xgxs_loopback
|| xaui_loopback
) ?
1140 FFE_AB_XX_FORCE_SIG_ALL_LANES
: 0);
1141 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_XGXS_LB_EN
, xgxs_loopback
);
1142 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_XGMII_LB_EN
, xgmii_loopback
);
1143 efx_writeo(efx
, ®
, FR_AB_XX_CORE_STAT
);
1145 efx_reado(efx
, ®
, FR_AB_XX_SD_CTL
);
1146 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_LPBKD
, xaui_loopback
);
1147 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_LPBKC
, xaui_loopback
);
1148 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_LPBKB
, xaui_loopback
);
1149 EFX_SET_OWORD_FIELD(reg
, FRF_AB_XX_LPBKA
, xaui_loopback
);
1150 efx_writeo(efx
, ®
, FR_AB_XX_SD_CTL
);
1154 /* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
1155 static bool falcon_xmac_link_ok_retry(struct efx_nic
*efx
, int tries
)
1157 bool mac_up
= falcon_xmac_link_ok(efx
);
1159 if (LOOPBACK_MASK(efx
) & LOOPBACKS_EXTERNAL(efx
) & LOOPBACKS_WS
||
1160 efx_phy_mode_disabled(efx
->phy_mode
))
1161 /* XAUI link is expected to be down */
1164 falcon_stop_nic_stats(efx
);
1166 while (!mac_up
&& tries
) {
1167 netif_dbg(efx
, hw
, efx
->net_dev
, "bashing xaui\n");
1168 falcon_reset_xaui(efx
);
1171 mac_up
= falcon_xmac_link_ok(efx
);
1175 falcon_start_nic_stats(efx
);
1180 static bool falcon_xmac_check_fault(struct efx_nic
*efx
)
1182 return !falcon_xmac_link_ok_retry(efx
, 5);
1185 static int falcon_reconfigure_xmac(struct efx_nic
*efx
)
1187 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1189 efx_farch_filter_sync_rx_mode(efx
);
1191 falcon_reconfigure_xgxs_core(efx
);
1192 falcon_reconfigure_xmac_core(efx
);
1194 falcon_reconfigure_mac_wrapper(efx
);
1196 nic_data
->xmac_poll_required
= !falcon_xmac_link_ok_retry(efx
, 5);
1197 falcon_ack_status_intr(efx
);
1202 static void falcon_poll_xmac(struct efx_nic
*efx
)
1204 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1206 /* We expect xgmii faults if the wireside link is down */
1207 if (!efx
->link_state
.up
|| !nic_data
->xmac_poll_required
)
1210 nic_data
->xmac_poll_required
= !falcon_xmac_link_ok_retry(efx
, 1);
1211 falcon_ack_status_intr(efx
);
1214 /**************************************************************************
1218 **************************************************************************
1221 static void falcon_push_multicast_hash(struct efx_nic
*efx
)
1223 union efx_multicast_hash
*mc_hash
= &efx
->multicast_hash
;
1225 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
1227 efx_writeo(efx
, &mc_hash
->oword
[0], FR_AB_MAC_MC_HASH_REG0
);
1228 efx_writeo(efx
, &mc_hash
->oword
[1], FR_AB_MAC_MC_HASH_REG1
);
1231 static void falcon_reset_macs(struct efx_nic
*efx
)
1233 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1234 efx_oword_t reg
, mac_ctrl
;
1237 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) {
1238 /* It's not safe to use GLB_CTL_REG to reset the
1239 * macs, so instead use the internal MAC resets
1241 EFX_POPULATE_OWORD_1(reg
, FRF_AB_XM_CORE_RST
, 1);
1242 efx_writeo(efx
, ®
, FR_AB_XM_GLB_CFG
);
1244 for (count
= 0; count
< 10000; count
++) {
1245 efx_reado(efx
, ®
, FR_AB_XM_GLB_CFG
);
1246 if (EFX_OWORD_FIELD(reg
, FRF_AB_XM_CORE_RST
) ==
1252 netif_err(efx
, hw
, efx
->net_dev
,
1253 "timed out waiting for XMAC core reset\n");
1256 /* Mac stats will fail whist the TX fifo is draining */
1257 WARN_ON(nic_data
->stats_disable_count
== 0);
1259 efx_reado(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
1260 EFX_SET_OWORD_FIELD(mac_ctrl
, FRF_BB_TXFIFO_DRAIN_EN
, 1);
1261 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
1263 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
1264 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
, 1);
1265 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
, 1);
1266 EFX_SET_OWORD_FIELD(reg
, FRF_AB_RST_EM
, 1);
1267 efx_writeo(efx
, ®
, FR_AB_GLB_CTL
);
1271 efx_reado(efx
, ®
, FR_AB_GLB_CTL
);
1272 if (!EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGTX
) &&
1273 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_XGRX
) &&
1274 !EFX_OWORD_FIELD(reg
, FRF_AB_RST_EM
)) {
1275 netif_dbg(efx
, hw
, efx
->net_dev
,
1276 "Completed MAC reset after %d loops\n",
1281 netif_err(efx
, hw
, efx
->net_dev
, "MAC reset failed\n");
1288 /* Ensure the correct MAC is selected before statistics
1289 * are re-enabled by the caller */
1290 efx_writeo(efx
, &mac_ctrl
, FR_AB_MAC_CTRL
);
1292 falcon_setup_xaui(efx
);
1295 static void falcon_drain_tx_fifo(struct efx_nic
*efx
)
1299 if ((efx_nic_rev(efx
) < EFX_REV_FALCON_B0
) ||
1300 (efx
->loopback_mode
!= LOOPBACK_NONE
))
1303 efx_reado(efx
, ®
, FR_AB_MAC_CTRL
);
1304 /* There is no point in draining more than once */
1305 if (EFX_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
))
1308 falcon_reset_macs(efx
);
1311 static void falcon_deconfigure_mac_wrapper(struct efx_nic
*efx
)
1315 if (efx_nic_rev(efx
) < EFX_REV_FALCON_B0
)
1318 /* Isolate the MAC -> RX */
1319 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
1320 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 0);
1321 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
1323 /* Isolate TX -> MAC */
1324 falcon_drain_tx_fifo(efx
);
1327 static void falcon_reconfigure_mac_wrapper(struct efx_nic
*efx
)
1329 struct efx_link_state
*link_state
= &efx
->link_state
;
1331 int link_speed
, isolate
;
1333 isolate
= !!ACCESS_ONCE(efx
->reset_pending
);
1335 switch (link_state
->speed
) {
1336 case 10000: link_speed
= 3; break;
1337 case 1000: link_speed
= 2; break;
1338 case 100: link_speed
= 1; break;
1339 default: link_speed
= 0; break;
1341 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1342 * as advertised. Disable to ensure packets are not
1343 * indefinitely held and TX queue can be flushed at any point
1344 * while the link is down. */
1345 EFX_POPULATE_OWORD_5(reg
,
1346 FRF_AB_MAC_XOFF_VAL
, 0xffff /* max pause time */,
1347 FRF_AB_MAC_BCAD_ACPT
, 1,
1348 FRF_AB_MAC_UC_PROM
, !efx
->unicast_filter
,
1349 FRF_AB_MAC_LINK_STATUS
, 1, /* always set */
1350 FRF_AB_MAC_SPEED
, link_speed
);
1351 /* On B0, MAC backpressure can be disabled and packets get
1353 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
1354 EFX_SET_OWORD_FIELD(reg
, FRF_BB_TXFIFO_DRAIN_EN
,
1355 !link_state
->up
|| isolate
);
1358 efx_writeo(efx
, ®
, FR_AB_MAC_CTRL
);
1360 /* Restore the multicast hash registers. */
1361 falcon_push_multicast_hash(efx
);
1363 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
1364 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
1365 * initialisation but it may read back as 0) */
1366 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
1367 /* Unisolate the MAC -> RX */
1368 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
1369 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, !isolate
);
1370 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
1373 static void falcon_stats_request(struct efx_nic
*efx
)
1375 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1378 WARN_ON(nic_data
->stats_pending
);
1379 WARN_ON(nic_data
->stats_disable_count
);
1381 FALCON_XMAC_STATS_DMA_FLAG(efx
) = 0;
1382 nic_data
->stats_pending
= true;
1383 wmb(); /* ensure done flag is clear */
1385 /* Initiate DMA transfer of stats */
1386 EFX_POPULATE_OWORD_2(reg
,
1387 FRF_AB_MAC_STAT_DMA_CMD
, 1,
1388 FRF_AB_MAC_STAT_DMA_ADR
,
1389 efx
->stats_buffer
.dma_addr
);
1390 efx_writeo(efx
, ®
, FR_AB_MAC_STAT_DMA
);
1392 mod_timer(&nic_data
->stats_timer
, round_jiffies_up(jiffies
+ HZ
/ 2));
1395 static void falcon_stats_complete(struct efx_nic
*efx
)
1397 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1399 if (!nic_data
->stats_pending
)
1402 nic_data
->stats_pending
= false;
1403 if (FALCON_XMAC_STATS_DMA_FLAG(efx
)) {
1404 rmb(); /* read the done flag before the stats */
1405 efx_nic_update_stats(falcon_stat_desc
, FALCON_STAT_COUNT
,
1406 falcon_stat_mask
, nic_data
->stats
,
1407 efx
->stats_buffer
.addr
, true);
1409 netif_err(efx
, hw
, efx
->net_dev
,
1410 "timed out waiting for statistics\n");
1414 static void falcon_stats_timer_func(unsigned long context
)
1416 struct efx_nic
*efx
= (struct efx_nic
*)context
;
1417 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1419 spin_lock(&efx
->stats_lock
);
1421 falcon_stats_complete(efx
);
1422 if (nic_data
->stats_disable_count
== 0)
1423 falcon_stats_request(efx
);
1425 spin_unlock(&efx
->stats_lock
);
1428 static bool falcon_loopback_link_poll(struct efx_nic
*efx
)
1430 struct efx_link_state old_state
= efx
->link_state
;
1432 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
1433 WARN_ON(!LOOPBACK_INTERNAL(efx
));
1435 efx
->link_state
.fd
= true;
1436 efx
->link_state
.fc
= efx
->wanted_fc
;
1437 efx
->link_state
.up
= true;
1438 efx
->link_state
.speed
= 10000;
1440 return !efx_link_state_equal(&efx
->link_state
, &old_state
);
1443 static int falcon_reconfigure_port(struct efx_nic
*efx
)
1447 WARN_ON(efx_nic_rev(efx
) > EFX_REV_FALCON_B0
);
1449 /* Poll the PHY link state *before* reconfiguring it. This means we
1450 * will pick up the correct speed (in loopback) to select the correct
1453 if (LOOPBACK_INTERNAL(efx
))
1454 falcon_loopback_link_poll(efx
);
1456 efx
->phy_op
->poll(efx
);
1458 falcon_stop_nic_stats(efx
);
1459 falcon_deconfigure_mac_wrapper(efx
);
1461 falcon_reset_macs(efx
);
1463 efx
->phy_op
->reconfigure(efx
);
1464 rc
= falcon_reconfigure_xmac(efx
);
1467 falcon_start_nic_stats(efx
);
1469 /* Synchronise efx->link_state with the kernel */
1470 efx_link_status_changed(efx
);
1475 /* TX flow control may automatically turn itself off if the link
1476 * partner (intermittently) stops responding to pause frames. There
1477 * isn't any indication that this has happened, so the best we do is
1478 * leave it up to the user to spot this and fix it by cycling transmit
1479 * flow control on this end.
1482 static void falcon_a1_prepare_enable_fc_tx(struct efx_nic
*efx
)
1484 /* Schedule a reset to recover */
1485 efx_schedule_reset(efx
, RESET_TYPE_INVISIBLE
);
1488 static void falcon_b0_prepare_enable_fc_tx(struct efx_nic
*efx
)
1490 /* Recover by resetting the EM block */
1491 falcon_stop_nic_stats(efx
);
1492 falcon_drain_tx_fifo(efx
);
1493 falcon_reconfigure_xmac(efx
);
1494 falcon_start_nic_stats(efx
);
1497 /**************************************************************************
1499 * PHY access via GMII
1501 **************************************************************************
1504 /* Wait for GMII access to complete */
1505 static int falcon_gmii_wait(struct efx_nic
*efx
)
1507 efx_oword_t md_stat
;
1510 /* wait up to 50ms - taken max from datasheet */
1511 for (count
= 0; count
< 5000; count
++) {
1512 efx_reado(efx
, &md_stat
, FR_AB_MD_STAT
);
1513 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSY
) == 0) {
1514 if (EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_LNFL
) != 0 ||
1515 EFX_OWORD_FIELD(md_stat
, FRF_AB_MD_BSERR
) != 0) {
1516 netif_err(efx
, hw
, efx
->net_dev
,
1517 "error from GMII access "
1519 EFX_OWORD_VAL(md_stat
));
1526 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for GMII\n");
1530 /* Write an MDIO register of a PHY connected to Falcon. */
1531 static int falcon_mdio_write(struct net_device
*net_dev
,
1532 int prtad
, int devad
, u16 addr
, u16 value
)
1534 struct efx_nic
*efx
= netdev_priv(net_dev
);
1535 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1539 netif_vdbg(efx
, hw
, efx
->net_dev
,
1540 "writing MDIO %d register %d.%d with 0x%04x\n",
1541 prtad
, devad
, addr
, value
);
1543 mutex_lock(&nic_data
->mdio_lock
);
1545 /* Check MDIO not currently being accessed */
1546 rc
= falcon_gmii_wait(efx
);
1550 /* Write the address/ID register */
1551 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
1552 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
1554 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
1555 FRF_AB_MD_DEV_ADR
, devad
);
1556 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
1559 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_TXD
, value
);
1560 efx_writeo(efx
, ®
, FR_AB_MD_TXD
);
1562 EFX_POPULATE_OWORD_2(reg
,
1565 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
1567 /* Wait for data to be written */
1568 rc
= falcon_gmii_wait(efx
);
1570 /* Abort the write operation */
1571 EFX_POPULATE_OWORD_2(reg
,
1574 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
1579 mutex_unlock(&nic_data
->mdio_lock
);
1583 /* Read an MDIO register of a PHY connected to Falcon. */
1584 static int falcon_mdio_read(struct net_device
*net_dev
,
1585 int prtad
, int devad
, u16 addr
)
1587 struct efx_nic
*efx
= netdev_priv(net_dev
);
1588 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1592 mutex_lock(&nic_data
->mdio_lock
);
1594 /* Check MDIO not currently being accessed */
1595 rc
= falcon_gmii_wait(efx
);
1599 EFX_POPULATE_OWORD_1(reg
, FRF_AB_MD_PHY_ADR
, addr
);
1600 efx_writeo(efx
, ®
, FR_AB_MD_PHY_ADR
);
1602 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_PRT_ADR
, prtad
,
1603 FRF_AB_MD_DEV_ADR
, devad
);
1604 efx_writeo(efx
, ®
, FR_AB_MD_ID
);
1606 /* Request data to be read */
1607 EFX_POPULATE_OWORD_2(reg
, FRF_AB_MD_RDC
, 1, FRF_AB_MD_GC
, 0);
1608 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
1610 /* Wait for data to become available */
1611 rc
= falcon_gmii_wait(efx
);
1613 efx_reado(efx
, ®
, FR_AB_MD_RXD
);
1614 rc
= EFX_OWORD_FIELD(reg
, FRF_AB_MD_RXD
);
1615 netif_vdbg(efx
, hw
, efx
->net_dev
,
1616 "read from MDIO %d register %d.%d, got %04x\n",
1617 prtad
, devad
, addr
, rc
);
1619 /* Abort the read operation */
1620 EFX_POPULATE_OWORD_2(reg
,
1623 efx_writeo(efx
, ®
, FR_AB_MD_CS
);
1625 netif_dbg(efx
, hw
, efx
->net_dev
,
1626 "read from MDIO %d register %d.%d, got error %d\n",
1627 prtad
, devad
, addr
, rc
);
1631 mutex_unlock(&nic_data
->mdio_lock
);
1635 /* This call is responsible for hooking in the MAC and PHY operations */
1636 static int falcon_probe_port(struct efx_nic
*efx
)
1638 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1641 switch (efx
->phy_type
) {
1642 case PHY_TYPE_SFX7101
:
1643 efx
->phy_op
= &falcon_sfx7101_phy_ops
;
1645 case PHY_TYPE_QT2022C2
:
1646 case PHY_TYPE_QT2025C
:
1647 efx
->phy_op
= &falcon_qt202x_phy_ops
;
1649 case PHY_TYPE_TXC43128
:
1650 efx
->phy_op
= &falcon_txc_phy_ops
;
1653 netif_err(efx
, probe
, efx
->net_dev
, "Unknown PHY type %d\n",
1658 /* Fill out MDIO structure and loopback modes */
1659 mutex_init(&nic_data
->mdio_lock
);
1660 efx
->mdio
.mdio_read
= falcon_mdio_read
;
1661 efx
->mdio
.mdio_write
= falcon_mdio_write
;
1662 rc
= efx
->phy_op
->probe(efx
);
1666 /* Initial assumption */
1667 efx
->link_state
.speed
= 10000;
1668 efx
->link_state
.fd
= true;
1670 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
1671 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
)
1672 efx
->wanted_fc
= EFX_FC_RX
| EFX_FC_TX
;
1674 efx
->wanted_fc
= EFX_FC_RX
;
1675 if (efx
->mdio
.mmds
& MDIO_DEVS_AN
)
1676 efx
->wanted_fc
|= EFX_FC_AUTO
;
1678 /* Allocate buffer for stats */
1679 rc
= efx_nic_alloc_buffer(efx
, &efx
->stats_buffer
,
1680 FALCON_MAC_STATS_SIZE
, GFP_KERNEL
);
1683 netif_dbg(efx
, probe
, efx
->net_dev
,
1684 "stats buffer at %llx (virt %p phys %llx)\n",
1685 (u64
)efx
->stats_buffer
.dma_addr
,
1686 efx
->stats_buffer
.addr
,
1687 (u64
)virt_to_phys(efx
->stats_buffer
.addr
));
1692 static void falcon_remove_port(struct efx_nic
*efx
)
1694 efx
->phy_op
->remove(efx
);
1695 efx_nic_free_buffer(efx
, &efx
->stats_buffer
);
1698 /* Global events are basically PHY events */
1700 falcon_handle_global_event(struct efx_channel
*channel
, efx_qword_t
*event
)
1702 struct efx_nic
*efx
= channel
->efx
;
1703 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1705 if (EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_G_PHY0_INTR
) ||
1706 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XG_PHY0_INTR
) ||
1707 EFX_QWORD_FIELD(*event
, FSF_AB_GLB_EV_XFP_PHY0_INTR
))
1711 if ((efx_nic_rev(efx
) == EFX_REV_FALCON_B0
) &&
1712 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_XG_MGT_INTR
)) {
1713 nic_data
->xmac_poll_required
= true;
1717 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
?
1718 EFX_QWORD_FIELD(*event
, FSF_AA_GLB_EV_RX_RECOVERY
) :
1719 EFX_QWORD_FIELD(*event
, FSF_BB_GLB_EV_RX_RECOVERY
)) {
1720 netif_err(efx
, rx_err
, efx
->net_dev
,
1721 "channel %d seen global RX_RESET event. Resetting.\n",
1724 atomic_inc(&efx
->rx_reset
);
1725 efx_schedule_reset(efx
, EFX_WORKAROUND_6555(efx
) ?
1726 RESET_TYPE_RX_RECOVERY
: RESET_TYPE_DISABLE
);
1733 /**************************************************************************
1737 **************************************************************************/
1740 falcon_read_nvram(struct efx_nic
*efx
, struct falcon_nvconfig
*nvconfig_out
)
1742 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1743 struct falcon_nvconfig
*nvconfig
;
1744 struct falcon_spi_device
*spi
;
1746 int rc
, magic_num
, struct_ver
;
1747 __le16
*word
, *limit
;
1750 if (falcon_spi_present(&nic_data
->spi_flash
))
1751 spi
= &nic_data
->spi_flash
;
1752 else if (falcon_spi_present(&nic_data
->spi_eeprom
))
1753 spi
= &nic_data
->spi_eeprom
;
1757 region
= kmalloc(FALCON_NVCONFIG_END
, GFP_KERNEL
);
1760 nvconfig
= region
+ FALCON_NVCONFIG_OFFSET
;
1762 mutex_lock(&nic_data
->spi_lock
);
1763 rc
= falcon_spi_read(efx
, spi
, 0, FALCON_NVCONFIG_END
, NULL
, region
);
1764 mutex_unlock(&nic_data
->spi_lock
);
1766 netif_err(efx
, hw
, efx
->net_dev
, "Failed to read %s\n",
1767 falcon_spi_present(&nic_data
->spi_flash
) ?
1768 "flash" : "EEPROM");
1773 magic_num
= le16_to_cpu(nvconfig
->board_magic_num
);
1774 struct_ver
= le16_to_cpu(nvconfig
->board_struct_ver
);
1777 if (magic_num
!= FALCON_NVCONFIG_BOARD_MAGIC_NUM
) {
1778 netif_err(efx
, hw
, efx
->net_dev
,
1779 "NVRAM bad magic 0x%x\n", magic_num
);
1782 if (struct_ver
< 2) {
1783 netif_err(efx
, hw
, efx
->net_dev
,
1784 "NVRAM has ancient version 0x%x\n", struct_ver
);
1786 } else if (struct_ver
< 4) {
1787 word
= &nvconfig
->board_magic_num
;
1788 limit
= (__le16
*) (nvconfig
+ 1);
1791 limit
= region
+ FALCON_NVCONFIG_END
;
1793 for (csum
= 0; word
< limit
; ++word
)
1794 csum
+= le16_to_cpu(*word
);
1796 if (~csum
& 0xffff) {
1797 netif_err(efx
, hw
, efx
->net_dev
,
1798 "NVRAM has incorrect checksum\n");
1804 memcpy(nvconfig_out
, nvconfig
, sizeof(*nvconfig
));
1811 static int falcon_test_nvram(struct efx_nic
*efx
)
1813 return falcon_read_nvram(efx
, NULL
);
1816 static const struct efx_farch_register_test falcon_b0_register_tests
[] = {
1818 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1820 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1822 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1823 { FR_AZ_TX_RESERVED
,
1824 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1826 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1827 { FR_AZ_SRM_TX_DC_CFG
,
1828 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1830 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1831 { FR_AZ_RX_DC_PF_WM
,
1832 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1834 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1836 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1838 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1840 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1842 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1844 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1845 { FR_AB_XM_RX_PARAM
,
1846 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1848 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1850 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1852 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1856 falcon_b0_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
1858 enum reset_type reset_method
= RESET_TYPE_INVISIBLE
;
1861 mutex_lock(&efx
->mac_lock
);
1862 if (efx
->loopback_modes
) {
1863 /* We need the 312 clock from the PHY to test the XMAC
1864 * registers, so move into XGMII loopback if available */
1865 if (efx
->loopback_modes
& (1 << LOOPBACK_XGMII
))
1866 efx
->loopback_mode
= LOOPBACK_XGMII
;
1868 efx
->loopback_mode
= __ffs(efx
->loopback_modes
);
1870 __efx_reconfigure_port(efx
);
1871 mutex_unlock(&efx
->mac_lock
);
1873 efx_reset_down(efx
, reset_method
);
1876 efx_farch_test_registers(efx
, falcon_b0_register_tests
,
1877 ARRAY_SIZE(falcon_b0_register_tests
))
1880 rc
= falcon_reset_hw(efx
, reset_method
);
1881 rc2
= efx_reset_up(efx
, reset_method
, rc
== 0);
1882 return rc
? rc
: rc2
;
1885 /**************************************************************************
1889 **************************************************************************
1892 static enum reset_type
falcon_map_reset_reason(enum reset_type reason
)
1895 case RESET_TYPE_RX_RECOVERY
:
1896 case RESET_TYPE_DMA_ERROR
:
1897 case RESET_TYPE_TX_SKIP
:
1898 /* These can occasionally occur due to hardware bugs.
1899 * We try to reset without disrupting the link.
1901 return RESET_TYPE_INVISIBLE
;
1903 return RESET_TYPE_ALL
;
1907 static int falcon_map_reset_flags(u32
*flags
)
1910 FALCON_RESET_INVISIBLE
= (ETH_RESET_DMA
| ETH_RESET_FILTER
|
1911 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
),
1912 FALCON_RESET_ALL
= FALCON_RESET_INVISIBLE
| ETH_RESET_PHY
,
1913 FALCON_RESET_WORLD
= FALCON_RESET_ALL
| ETH_RESET_IRQ
,
1916 if ((*flags
& FALCON_RESET_WORLD
) == FALCON_RESET_WORLD
) {
1917 *flags
&= ~FALCON_RESET_WORLD
;
1918 return RESET_TYPE_WORLD
;
1921 if ((*flags
& FALCON_RESET_ALL
) == FALCON_RESET_ALL
) {
1922 *flags
&= ~FALCON_RESET_ALL
;
1923 return RESET_TYPE_ALL
;
1926 if ((*flags
& FALCON_RESET_INVISIBLE
) == FALCON_RESET_INVISIBLE
) {
1927 *flags
&= ~FALCON_RESET_INVISIBLE
;
1928 return RESET_TYPE_INVISIBLE
;
1934 /* Resets NIC to known state. This routine must be called in process
1935 * context and is allowed to sleep. */
1936 static int __falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
1938 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
1939 efx_oword_t glb_ctl_reg_ker
;
1942 netif_dbg(efx
, hw
, efx
->net_dev
, "performing %s hardware reset\n",
1943 RESET_TYPE(method
));
1945 /* Initiate device reset */
1946 if (method
== RESET_TYPE_WORLD
) {
1947 rc
= pci_save_state(efx
->pci_dev
);
1949 netif_err(efx
, drv
, efx
->net_dev
,
1950 "failed to backup PCI state of primary "
1951 "function prior to hardware reset\n");
1954 if (efx_nic_is_dual_func(efx
)) {
1955 rc
= pci_save_state(nic_data
->pci_dev2
);
1957 netif_err(efx
, drv
, efx
->net_dev
,
1958 "failed to backup PCI state of "
1959 "secondary function prior to "
1960 "hardware reset\n");
1965 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker
,
1966 FRF_AB_EXT_PHY_RST_DUR
,
1967 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1970 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker
,
1971 /* exclude PHY from "invisible" reset */
1972 FRF_AB_EXT_PHY_RST_CTL
,
1973 method
== RESET_TYPE_INVISIBLE
,
1974 /* exclude EEPROM/flash and PCIe */
1975 FRF_AB_PCIE_CORE_RST_CTL
, 1,
1976 FRF_AB_PCIE_NSTKY_RST_CTL
, 1,
1977 FRF_AB_PCIE_SD_RST_CTL
, 1,
1978 FRF_AB_EE_RST_CTL
, 1,
1979 FRF_AB_EXT_PHY_RST_DUR
,
1980 FFE_AB_EXT_PHY_RST_DUR_10240US
,
1983 efx_writeo(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1985 netif_dbg(efx
, hw
, efx
->net_dev
, "waiting for hardware reset\n");
1986 schedule_timeout_uninterruptible(HZ
/ 20);
1988 /* Restore PCI configuration if needed */
1989 if (method
== RESET_TYPE_WORLD
) {
1990 if (efx_nic_is_dual_func(efx
))
1991 pci_restore_state(nic_data
->pci_dev2
);
1992 pci_restore_state(efx
->pci_dev
);
1993 netif_dbg(efx
, drv
, efx
->net_dev
,
1994 "successfully restored PCI config\n");
1997 /* Assert that reset complete */
1998 efx_reado(efx
, &glb_ctl_reg_ker
, FR_AB_GLB_CTL
);
1999 if (EFX_OWORD_FIELD(glb_ctl_reg_ker
, FRF_AB_SWRST
) != 0) {
2001 netif_err(efx
, hw
, efx
->net_dev
,
2002 "timed out waiting for hardware reset\n");
2005 netif_dbg(efx
, hw
, efx
->net_dev
, "hardware reset complete\n");
2009 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2011 pci_restore_state(efx
->pci_dev
);
2017 static int falcon_reset_hw(struct efx_nic
*efx
, enum reset_type method
)
2019 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2022 mutex_lock(&nic_data
->spi_lock
);
2023 rc
= __falcon_reset_hw(efx
, method
);
2024 mutex_unlock(&nic_data
->spi_lock
);
2029 static void falcon_monitor(struct efx_nic
*efx
)
2034 BUG_ON(!mutex_is_locked(&efx
->mac_lock
));
2036 rc
= falcon_board(efx
)->type
->monitor(efx
);
2038 netif_err(efx
, hw
, efx
->net_dev
,
2039 "Board sensor %s; shutting down PHY\n",
2040 (rc
== -ERANGE
) ? "reported fault" : "failed");
2041 efx
->phy_mode
|= PHY_MODE_LOW_POWER
;
2042 rc
= __efx_reconfigure_port(efx
);
2046 if (LOOPBACK_INTERNAL(efx
))
2047 link_changed
= falcon_loopback_link_poll(efx
);
2049 link_changed
= efx
->phy_op
->poll(efx
);
2052 falcon_stop_nic_stats(efx
);
2053 falcon_deconfigure_mac_wrapper(efx
);
2055 falcon_reset_macs(efx
);
2056 rc
= falcon_reconfigure_xmac(efx
);
2059 falcon_start_nic_stats(efx
);
2061 efx_link_status_changed(efx
);
2064 falcon_poll_xmac(efx
);
2067 /* Zeroes out the SRAM contents. This routine must be called in
2068 * process context and is allowed to sleep.
2070 static int falcon_reset_sram(struct efx_nic
*efx
)
2072 efx_oword_t srm_cfg_reg_ker
, gpio_cfg_reg_ker
;
2075 /* Set the SRAM wake/sleep GPIO appropriately. */
2076 efx_reado(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
2077 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OEN
, 1);
2078 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker
, FRF_AB_GPIO1_OUT
, 1);
2079 efx_writeo(efx
, &gpio_cfg_reg_ker
, FR_AB_GPIO_CTL
);
2081 /* Initiate SRAM reset */
2082 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker
,
2083 FRF_AZ_SRM_INIT_EN
, 1,
2084 FRF_AZ_SRM_NB_SZ
, 0);
2085 efx_writeo(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
2087 /* Wait for SRAM reset to complete */
2090 netif_dbg(efx
, hw
, efx
->net_dev
,
2091 "waiting for SRAM reset (attempt %d)...\n", count
);
2093 /* SRAM reset is slow; expect around 16ms */
2094 schedule_timeout_uninterruptible(HZ
/ 50);
2096 /* Check for reset complete */
2097 efx_reado(efx
, &srm_cfg_reg_ker
, FR_AZ_SRM_CFG
);
2098 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker
, FRF_AZ_SRM_INIT_EN
)) {
2099 netif_dbg(efx
, hw
, efx
->net_dev
,
2100 "SRAM reset complete\n");
2104 } while (++count
< 20); /* wait up to 0.4 sec */
2106 netif_err(efx
, hw
, efx
->net_dev
, "timed out waiting for SRAM reset\n");
2110 static void falcon_spi_device_init(struct efx_nic
*efx
,
2111 struct falcon_spi_device
*spi_device
,
2112 unsigned int device_id
, u32 device_type
)
2114 if (device_type
!= 0) {
2115 spi_device
->device_id
= device_id
;
2117 1 << SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_SIZE
);
2118 spi_device
->addr_len
=
2119 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ADDR_LEN
);
2120 spi_device
->munge_address
= (spi_device
->size
== 1 << 9 &&
2121 spi_device
->addr_len
== 1);
2122 spi_device
->erase_command
=
2123 SPI_DEV_TYPE_FIELD(device_type
, SPI_DEV_TYPE_ERASE_CMD
);
2124 spi_device
->erase_size
=
2125 1 << SPI_DEV_TYPE_FIELD(device_type
,
2126 SPI_DEV_TYPE_ERASE_SIZE
);
2127 spi_device
->block_size
=
2128 1 << SPI_DEV_TYPE_FIELD(device_type
,
2129 SPI_DEV_TYPE_BLOCK_SIZE
);
2131 spi_device
->size
= 0;
2135 /* Extract non-volatile configuration */
2136 static int falcon_probe_nvconfig(struct efx_nic
*efx
)
2138 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2139 struct falcon_nvconfig
*nvconfig
;
2142 nvconfig
= kmalloc(sizeof(*nvconfig
), GFP_KERNEL
);
2146 rc
= falcon_read_nvram(efx
, nvconfig
);
2150 efx
->phy_type
= nvconfig
->board_v2
.port0_phy_type
;
2151 efx
->mdio
.prtad
= nvconfig
->board_v2
.port0_phy_addr
;
2153 if (le16_to_cpu(nvconfig
->board_struct_ver
) >= 3) {
2154 falcon_spi_device_init(
2155 efx
, &nic_data
->spi_flash
, FFE_AB_SPI_DEVICE_FLASH
,
2156 le32_to_cpu(nvconfig
->board_v3
2157 .spi_device_type
[FFE_AB_SPI_DEVICE_FLASH
]));
2158 falcon_spi_device_init(
2159 efx
, &nic_data
->spi_eeprom
, FFE_AB_SPI_DEVICE_EEPROM
,
2160 le32_to_cpu(nvconfig
->board_v3
2161 .spi_device_type
[FFE_AB_SPI_DEVICE_EEPROM
]));
2164 /* Read the MAC addresses */
2165 memcpy(efx
->net_dev
->perm_addr
, nvconfig
->mac_address
[0], ETH_ALEN
);
2167 netif_dbg(efx
, probe
, efx
->net_dev
, "PHY is %d phy_id %d\n",
2168 efx
->phy_type
, efx
->mdio
.prtad
);
2170 rc
= falcon_probe_board(efx
,
2171 le16_to_cpu(nvconfig
->board_v2
.board_revision
));
2177 static void falcon_dimension_resources(struct efx_nic
*efx
)
2179 efx
->rx_dc_base
= 0x20000;
2180 efx
->tx_dc_base
= 0x26000;
2183 /* Probe all SPI devices on the NIC */
2184 static void falcon_probe_spi_devices(struct efx_nic
*efx
)
2186 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2187 efx_oword_t nic_stat
, gpio_ctl
, ee_vpd_cfg
;
2190 efx_reado(efx
, &gpio_ctl
, FR_AB_GPIO_CTL
);
2191 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
2192 efx_reado(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
2194 if (EFX_OWORD_FIELD(gpio_ctl
, FRF_AB_GPIO3_PWRUP_VALUE
)) {
2195 boot_dev
= (EFX_OWORD_FIELD(nic_stat
, FRF_AB_SF_PRST
) ?
2196 FFE_AB_SPI_DEVICE_FLASH
: FFE_AB_SPI_DEVICE_EEPROM
);
2197 netif_dbg(efx
, probe
, efx
->net_dev
, "Booted from %s\n",
2198 boot_dev
== FFE_AB_SPI_DEVICE_FLASH
?
2199 "flash" : "EEPROM");
2201 /* Disable VPD and set clock dividers to safe
2202 * values for initial programming. */
2204 netif_dbg(efx
, probe
, efx
->net_dev
,
2205 "Booted from internal ASIC settings;"
2206 " setting SPI config\n");
2207 EFX_POPULATE_OWORD_3(ee_vpd_cfg
, FRF_AB_EE_VPD_EN
, 0,
2208 /* 125 MHz / 7 ~= 20 MHz */
2209 FRF_AB_EE_SF_CLOCK_DIV
, 7,
2210 /* 125 MHz / 63 ~= 2 MHz */
2211 FRF_AB_EE_EE_CLOCK_DIV
, 63);
2212 efx_writeo(efx
, &ee_vpd_cfg
, FR_AB_EE_VPD_CFG0
);
2215 mutex_init(&nic_data
->spi_lock
);
2217 if (boot_dev
== FFE_AB_SPI_DEVICE_FLASH
)
2218 falcon_spi_device_init(efx
, &nic_data
->spi_flash
,
2219 FFE_AB_SPI_DEVICE_FLASH
,
2220 default_flash_type
);
2221 if (boot_dev
== FFE_AB_SPI_DEVICE_EEPROM
)
2222 falcon_spi_device_init(efx
, &nic_data
->spi_eeprom
,
2223 FFE_AB_SPI_DEVICE_EEPROM
,
2227 static unsigned int falcon_a1_mem_map_size(struct efx_nic
*efx
)
2232 static unsigned int falcon_b0_mem_map_size(struct efx_nic
*efx
)
2234 /* Map everything up to and including the RSS indirection table.
2235 * The PCI core takes care of mapping the MSI-X tables.
2237 return FR_BZ_RX_INDIRECTION_TBL
+
2238 FR_BZ_RX_INDIRECTION_TBL_STEP
* FR_BZ_RX_INDIRECTION_TBL_ROWS
;
2241 static int falcon_probe_nic(struct efx_nic
*efx
)
2243 struct falcon_nic_data
*nic_data
;
2244 struct falcon_board
*board
;
2247 /* Allocate storage for hardware specific data */
2248 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
2251 efx
->nic_data
= nic_data
;
2255 if (efx_farch_fpga_ver(efx
) != 0) {
2256 netif_err(efx
, probe
, efx
->net_dev
,
2257 "Falcon FPGA not supported\n");
2261 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
2262 efx_oword_t nic_stat
;
2263 struct pci_dev
*dev
;
2264 u8 pci_rev
= efx
->pci_dev
->revision
;
2266 if ((pci_rev
== 0xff) || (pci_rev
== 0)) {
2267 netif_err(efx
, probe
, efx
->net_dev
,
2268 "Falcon rev A0 not supported\n");
2271 efx_reado(efx
, &nic_stat
, FR_AB_NIC_STAT
);
2272 if (EFX_OWORD_FIELD(nic_stat
, FRF_AB_STRAP_10G
) == 0) {
2273 netif_err(efx
, probe
, efx
->net_dev
,
2274 "Falcon rev A1 1G not supported\n");
2277 if (EFX_OWORD_FIELD(nic_stat
, FRF_AA_STRAP_PCIE
) == 0) {
2278 netif_err(efx
, probe
, efx
->net_dev
,
2279 "Falcon rev A1 PCI-X not supported\n");
2283 dev
= pci_dev_get(efx
->pci_dev
);
2284 while ((dev
= pci_get_device(PCI_VENDOR_ID_SOLARFLARE
,
2285 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
,
2287 if (dev
->bus
== efx
->pci_dev
->bus
&&
2288 dev
->devfn
== efx
->pci_dev
->devfn
+ 1) {
2289 nic_data
->pci_dev2
= dev
;
2293 if (!nic_data
->pci_dev2
) {
2294 netif_err(efx
, probe
, efx
->net_dev
,
2295 "failed to find secondary function\n");
2301 /* Now we can reset the NIC */
2302 rc
= __falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2304 netif_err(efx
, probe
, efx
->net_dev
, "failed to reset NIC\n");
2308 /* Allocate memory for INT_KER */
2309 rc
= efx_nic_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
),
2313 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
2315 netif_dbg(efx
, probe
, efx
->net_dev
,
2316 "INT_KER at %llx (virt %p phys %llx)\n",
2317 (u64
)efx
->irq_status
.dma_addr
,
2318 efx
->irq_status
.addr
,
2319 (u64
)virt_to_phys(efx
->irq_status
.addr
));
2321 falcon_probe_spi_devices(efx
);
2323 /* Read in the non-volatile configuration */
2324 rc
= falcon_probe_nvconfig(efx
);
2327 netif_err(efx
, probe
, efx
->net_dev
, "NVRAM is invalid\n");
2331 efx
->max_channels
= (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
? 4 :
2333 efx
->timer_quantum_ns
= 4968; /* 621 cycles */
2335 /* Initialise I2C adapter */
2336 board
= falcon_board(efx
);
2337 board
->i2c_adap
.owner
= THIS_MODULE
;
2338 board
->i2c_data
= falcon_i2c_bit_operations
;
2339 board
->i2c_data
.data
= efx
;
2340 board
->i2c_adap
.algo_data
= &board
->i2c_data
;
2341 board
->i2c_adap
.dev
.parent
= &efx
->pci_dev
->dev
;
2342 strlcpy(board
->i2c_adap
.name
, "SFC4000 GPIO",
2343 sizeof(board
->i2c_adap
.name
));
2344 rc
= i2c_bit_add_bus(&board
->i2c_adap
);
2348 rc
= falcon_board(efx
)->type
->init(efx
);
2350 netif_err(efx
, probe
, efx
->net_dev
,
2351 "failed to initialise board\n");
2355 nic_data
->stats_disable_count
= 1;
2356 setup_timer(&nic_data
->stats_timer
, &falcon_stats_timer_func
,
2357 (unsigned long)efx
);
2362 i2c_del_adapter(&board
->i2c_adap
);
2363 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
2365 efx_nic_free_buffer(efx
, &efx
->irq_status
);
2368 if (nic_data
->pci_dev2
) {
2369 pci_dev_put(nic_data
->pci_dev2
);
2370 nic_data
->pci_dev2
= NULL
;
2374 kfree(efx
->nic_data
);
2378 static void falcon_init_rx_cfg(struct efx_nic
*efx
)
2380 /* RX control FIFO thresholds (32 entries) */
2381 const unsigned ctrl_xon_thr
= 20;
2382 const unsigned ctrl_xoff_thr
= 25;
2385 efx_reado(efx
, ®
, FR_AZ_RX_CFG
);
2386 if (efx_nic_rev(efx
) <= EFX_REV_FALCON_A1
) {
2387 /* Data FIFO size is 5.5K. The RX DMA engine only
2388 * supports scattering for user-mode queues, but will
2389 * split DMA writes at intervals of RX_USR_BUF_SIZE
2390 * (32-byte units) even for kernel-mode queues. We
2391 * set it to be so large that that never happens.
2393 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_DESC_PUSH_EN
, 0);
2394 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_USR_BUF_SIZE
,
2396 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_MAC_TH
, 512 >> 8);
2397 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_MAC_TH
, 2048 >> 8);
2398 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XON_TX_TH
, ctrl_xon_thr
);
2399 EFX_SET_OWORD_FIELD(reg
, FRF_AA_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
2401 /* Data FIFO size is 80K; register fields moved */
2402 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_DESC_PUSH_EN
, 0);
2403 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_USR_BUF_SIZE
,
2404 EFX_RX_USR_BUF_SIZE
>> 5);
2405 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
2406 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_MAC_TH
, 27648 >> 8);
2407 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_MAC_TH
, 54272 >> 8);
2408 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XON_TX_TH
, ctrl_xon_thr
);
2409 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_XOFF_TX_TH
, ctrl_xoff_thr
);
2410 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_INGR_EN
, 1);
2412 /* Enable hash insertion. This is broken for the
2413 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
2415 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_INSRT_HDR
, 1);
2416 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_HASH_ALG
, 1);
2417 EFX_SET_OWORD_FIELD(reg
, FRF_BZ_RX_IP_HASH
, 1);
2419 /* Always enable XOFF signal from RX FIFO. We enable
2420 * or disable transmission of pause frames at the MAC. */
2421 EFX_SET_OWORD_FIELD(reg
, FRF_AZ_RX_XOFF_MAC_EN
, 1);
2422 efx_writeo(efx
, ®
, FR_AZ_RX_CFG
);
2425 /* This call performs hardware-specific global initialisation, such as
2426 * defining the descriptor cache sizes and number of RSS channels.
2427 * It does not set up any buffers, descriptor rings or event queues.
2429 static int falcon_init_nic(struct efx_nic
*efx
)
2434 /* Use on-chip SRAM */
2435 efx_reado(efx
, &temp
, FR_AB_NIC_STAT
);
2436 EFX_SET_OWORD_FIELD(temp
, FRF_AB_ONCHIP_SRAM
, 1);
2437 efx_writeo(efx
, &temp
, FR_AB_NIC_STAT
);
2439 rc
= falcon_reset_sram(efx
);
2443 /* Clear the parity enables on the TX data fifos as
2444 * they produce false parity errors because of timing issues
2446 if (EFX_WORKAROUND_5129(efx
)) {
2447 efx_reado(efx
, &temp
, FR_AZ_CSR_SPARE
);
2448 EFX_SET_OWORD_FIELD(temp
, FRF_AB_MEM_PERR_EN_TX_DATA
, 0);
2449 efx_writeo(efx
, &temp
, FR_AZ_CSR_SPARE
);
2452 if (EFX_WORKAROUND_7244(efx
)) {
2453 efx_reado(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
2454 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_FULL_SRCH_LIMIT
, 8);
2455 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_UDP_WILD_SRCH_LIMIT
, 8);
2456 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_FULL_SRCH_LIMIT
, 8);
2457 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TCP_WILD_SRCH_LIMIT
, 8);
2458 efx_writeo(efx
, &temp
, FR_BZ_RX_FILTER_CTL
);
2461 /* XXX This is documented only for Falcon A0/A1 */
2462 /* Setup RX. Wait for descriptor is broken and must
2463 * be disabled. RXDP recovery shouldn't be needed, but is.
2465 efx_reado(efx
, &temp
, FR_AA_RX_SELF_RST
);
2466 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_NODESC_WAIT_DIS
, 1);
2467 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_SELF_RST_EN
, 1);
2468 if (EFX_WORKAROUND_5583(efx
))
2469 EFX_SET_OWORD_FIELD(temp
, FRF_AA_RX_ISCSI_DIS
, 1);
2470 efx_writeo(efx
, &temp
, FR_AA_RX_SELF_RST
);
2472 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2473 * descriptors (which is bad).
2475 efx_reado(efx
, &temp
, FR_AZ_TX_CFG
);
2476 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_NO_EOP_DISC_EN
, 0);
2477 efx_writeo(efx
, &temp
, FR_AZ_TX_CFG
);
2479 falcon_init_rx_cfg(efx
);
2481 if (efx_nic_rev(efx
) >= EFX_REV_FALCON_B0
) {
2482 /* Set hash key for IPv4 */
2483 memcpy(&temp
, efx
->rx_hash_key
, sizeof(temp
));
2484 efx_writeo(efx
, &temp
, FR_BZ_RX_RSS_TKEY
);
2486 /* Set destination of both TX and RX Flush events */
2487 EFX_POPULATE_OWORD_1(temp
, FRF_BZ_FLS_EVQ_ID
, 0);
2488 efx_writeo(efx
, &temp
, FR_BZ_DP_CTRL
);
2491 efx_farch_init_common(efx
);
2496 static void falcon_remove_nic(struct efx_nic
*efx
)
2498 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2499 struct falcon_board
*board
= falcon_board(efx
);
2501 board
->type
->fini(efx
);
2503 /* Remove I2C adapter and clear it in preparation for a retry */
2504 i2c_del_adapter(&board
->i2c_adap
);
2505 memset(&board
->i2c_adap
, 0, sizeof(board
->i2c_adap
));
2507 efx_nic_free_buffer(efx
, &efx
->irq_status
);
2509 __falcon_reset_hw(efx
, RESET_TYPE_ALL
);
2511 /* Release the second function after the reset */
2512 if (nic_data
->pci_dev2
) {
2513 pci_dev_put(nic_data
->pci_dev2
);
2514 nic_data
->pci_dev2
= NULL
;
2517 /* Tear down the private nic state */
2518 kfree(efx
->nic_data
);
2519 efx
->nic_data
= NULL
;
2522 static size_t falcon_describe_nic_stats(struct efx_nic
*efx
, u8
*names
)
2524 return efx_nic_describe_stats(falcon_stat_desc
, FALCON_STAT_COUNT
,
2525 falcon_stat_mask
, names
);
2528 static size_t falcon_update_nic_stats(struct efx_nic
*efx
, u64
*full_stats
,
2529 struct rtnl_link_stats64
*core_stats
)
2531 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2532 u64
*stats
= nic_data
->stats
;
2535 if (!nic_data
->stats_disable_count
) {
2536 efx_reado(efx
, &cnt
, FR_AZ_RX_NODESC_DROP
);
2537 stats
[FALCON_STAT_rx_nodesc_drop_cnt
] +=
2538 EFX_OWORD_FIELD(cnt
, FRF_AB_RX_NODESC_DROP_CNT
);
2540 if (nic_data
->stats_pending
&&
2541 FALCON_XMAC_STATS_DMA_FLAG(efx
)) {
2542 nic_data
->stats_pending
= false;
2543 rmb(); /* read the done flag before the stats */
2544 efx_nic_update_stats(
2545 falcon_stat_desc
, FALCON_STAT_COUNT
,
2547 stats
, efx
->stats_buffer
.addr
, true);
2550 /* Update derived statistic */
2551 efx_update_diff_stat(&stats
[FALCON_STAT_rx_bad_bytes
],
2552 stats
[FALCON_STAT_rx_bytes
] -
2553 stats
[FALCON_STAT_rx_good_bytes
] -
2554 stats
[FALCON_STAT_rx_control
] * 64);
2558 memcpy(full_stats
, stats
, sizeof(u64
) * FALCON_STAT_COUNT
);
2561 core_stats
->rx_packets
= stats
[FALCON_STAT_rx_packets
];
2562 core_stats
->tx_packets
= stats
[FALCON_STAT_tx_packets
];
2563 core_stats
->rx_bytes
= stats
[FALCON_STAT_rx_bytes
];
2564 core_stats
->tx_bytes
= stats
[FALCON_STAT_tx_bytes
];
2565 core_stats
->rx_dropped
= stats
[FALCON_STAT_rx_nodesc_drop_cnt
];
2566 core_stats
->multicast
= stats
[FALCON_STAT_rx_multicast
];
2567 core_stats
->rx_length_errors
=
2568 stats
[FALCON_STAT_rx_gtjumbo
] +
2569 stats
[FALCON_STAT_rx_length_error
];
2570 core_stats
->rx_crc_errors
= stats
[FALCON_STAT_rx_bad
];
2571 core_stats
->rx_frame_errors
= stats
[FALCON_STAT_rx_align_error
];
2572 core_stats
->rx_fifo_errors
= stats
[FALCON_STAT_rx_overflow
];
2574 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
2575 core_stats
->rx_crc_errors
+
2576 core_stats
->rx_frame_errors
+
2577 stats
[FALCON_STAT_rx_symbol_error
]);
2580 return FALCON_STAT_COUNT
;
2583 void falcon_start_nic_stats(struct efx_nic
*efx
)
2585 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2587 spin_lock_bh(&efx
->stats_lock
);
2588 if (--nic_data
->stats_disable_count
== 0)
2589 falcon_stats_request(efx
);
2590 spin_unlock_bh(&efx
->stats_lock
);
2593 void falcon_stop_nic_stats(struct efx_nic
*efx
)
2595 struct falcon_nic_data
*nic_data
= efx
->nic_data
;
2600 spin_lock_bh(&efx
->stats_lock
);
2601 ++nic_data
->stats_disable_count
;
2602 spin_unlock_bh(&efx
->stats_lock
);
2604 del_timer_sync(&nic_data
->stats_timer
);
2606 /* Wait enough time for the most recent transfer to
2608 for (i
= 0; i
< 4 && nic_data
->stats_pending
; i
++) {
2609 if (FALCON_XMAC_STATS_DMA_FLAG(efx
))
2614 spin_lock_bh(&efx
->stats_lock
);
2615 falcon_stats_complete(efx
);
2616 spin_unlock_bh(&efx
->stats_lock
);
2619 static void falcon_set_id_led(struct efx_nic
*efx
, enum efx_led_mode mode
)
2621 falcon_board(efx
)->type
->set_id_led(efx
, mode
);
2624 /**************************************************************************
2628 **************************************************************************
2631 static void falcon_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
2635 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
2638 static int falcon_set_wol(struct efx_nic
*efx
, u32 type
)
2645 /**************************************************************************
2647 * Revision-dependent attributes used by efx.c and nic.c
2649 **************************************************************************
2652 const struct efx_nic_type falcon_a1_nic_type
= {
2653 .mem_map_size
= falcon_a1_mem_map_size
,
2654 .probe
= falcon_probe_nic
,
2655 .remove
= falcon_remove_nic
,
2656 .init
= falcon_init_nic
,
2657 .dimension_resources
= falcon_dimension_resources
,
2658 .fini
= falcon_irq_ack_a1
,
2659 .monitor
= falcon_monitor
,
2660 .map_reset_reason
= falcon_map_reset_reason
,
2661 .map_reset_flags
= falcon_map_reset_flags
,
2662 .reset
= falcon_reset_hw
,
2663 .probe_port
= falcon_probe_port
,
2664 .remove_port
= falcon_remove_port
,
2665 .handle_global_event
= falcon_handle_global_event
,
2666 .fini_dmaq
= efx_farch_fini_dmaq
,
2667 .prepare_flush
= falcon_prepare_flush
,
2668 .finish_flush
= efx_port_dummy_op_void
,
2669 .describe_stats
= falcon_describe_nic_stats
,
2670 .update_stats
= falcon_update_nic_stats
,
2671 .start_stats
= falcon_start_nic_stats
,
2672 .stop_stats
= falcon_stop_nic_stats
,
2673 .set_id_led
= falcon_set_id_led
,
2674 .push_irq_moderation
= falcon_push_irq_moderation
,
2675 .reconfigure_port
= falcon_reconfigure_port
,
2676 .prepare_enable_fc_tx
= falcon_a1_prepare_enable_fc_tx
,
2677 .reconfigure_mac
= falcon_reconfigure_xmac
,
2678 .check_mac_fault
= falcon_xmac_check_fault
,
2679 .get_wol
= falcon_get_wol
,
2680 .set_wol
= falcon_set_wol
,
2681 .resume_wol
= efx_port_dummy_op_void
,
2682 .test_nvram
= falcon_test_nvram
,
2683 .irq_enable_master
= efx_farch_irq_enable_master
,
2684 .irq_test_generate
= efx_farch_irq_test_generate
,
2685 .irq_disable_non_ev
= efx_farch_irq_disable_master
,
2686 .irq_handle_msi
= efx_farch_msi_interrupt
,
2687 .irq_handle_legacy
= falcon_legacy_interrupt_a1
,
2688 .tx_probe
= efx_farch_tx_probe
,
2689 .tx_init
= efx_farch_tx_init
,
2690 .tx_remove
= efx_farch_tx_remove
,
2691 .tx_write
= efx_farch_tx_write
,
2692 .rx_push_indir_table
= efx_farch_rx_push_indir_table
,
2693 .rx_probe
= efx_farch_rx_probe
,
2694 .rx_init
= efx_farch_rx_init
,
2695 .rx_remove
= efx_farch_rx_remove
,
2696 .rx_write
= efx_farch_rx_write
,
2697 .rx_defer_refill
= efx_farch_rx_defer_refill
,
2698 .ev_probe
= efx_farch_ev_probe
,
2699 .ev_init
= efx_farch_ev_init
,
2700 .ev_fini
= efx_farch_ev_fini
,
2701 .ev_remove
= efx_farch_ev_remove
,
2702 .ev_process
= efx_farch_ev_process
,
2703 .ev_read_ack
= efx_farch_ev_read_ack
,
2704 .ev_test_generate
= efx_farch_ev_test_generate
,
2706 /* We don't expose the filter table on Falcon A1 as it is not
2707 * mapped into function 0, but these implementations still
2708 * work with a degenerate case of all tables set to size 0.
2710 .filter_table_probe
= efx_farch_filter_table_probe
,
2711 .filter_table_restore
= efx_farch_filter_table_restore
,
2712 .filter_table_remove
= efx_farch_filter_table_remove
,
2713 .filter_insert
= efx_farch_filter_insert
,
2714 .filter_remove_safe
= efx_farch_filter_remove_safe
,
2715 .filter_get_safe
= efx_farch_filter_get_safe
,
2716 .filter_clear_rx
= efx_farch_filter_clear_rx
,
2717 .filter_count_rx_used
= efx_farch_filter_count_rx_used
,
2718 .filter_get_rx_id_limit
= efx_farch_filter_get_rx_id_limit
,
2719 .filter_get_rx_ids
= efx_farch_filter_get_rx_ids
,
2721 #ifdef CONFIG_SFC_MTD
2722 .mtd_probe
= falcon_mtd_probe
,
2723 .mtd_rename
= falcon_mtd_rename
,
2724 .mtd_read
= falcon_mtd_read
,
2725 .mtd_erase
= falcon_mtd_erase
,
2726 .mtd_write
= falcon_mtd_write
,
2727 .mtd_sync
= falcon_mtd_sync
,
2730 .revision
= EFX_REV_FALCON_A1
,
2731 .txd_ptr_tbl_base
= FR_AA_TX_DESC_PTR_TBL_KER
,
2732 .rxd_ptr_tbl_base
= FR_AA_RX_DESC_PTR_TBL_KER
,
2733 .buf_tbl_base
= FR_AA_BUF_FULL_TBL_KER
,
2734 .evq_ptr_tbl_base
= FR_AA_EVQ_PTR_TBL_KER
,
2735 .evq_rptr_tbl_base
= FR_AA_EVQ_RPTR_KER
,
2736 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
2737 .rx_buffer_padding
= 0x24,
2738 .can_rx_scatter
= false,
2739 .max_interrupt_mode
= EFX_INT_MODE_MSI
,
2740 .timer_period_max
= 1 << FRF_AB_TC_TIMER_VAL_WIDTH
,
2741 .offload_features
= NETIF_F_IP_CSUM
,
2745 const struct efx_nic_type falcon_b0_nic_type
= {
2746 .mem_map_size
= falcon_b0_mem_map_size
,
2747 .probe
= falcon_probe_nic
,
2748 .remove
= falcon_remove_nic
,
2749 .init
= falcon_init_nic
,
2750 .dimension_resources
= falcon_dimension_resources
,
2751 .fini
= efx_port_dummy_op_void
,
2752 .monitor
= falcon_monitor
,
2753 .map_reset_reason
= falcon_map_reset_reason
,
2754 .map_reset_flags
= falcon_map_reset_flags
,
2755 .reset
= falcon_reset_hw
,
2756 .probe_port
= falcon_probe_port
,
2757 .remove_port
= falcon_remove_port
,
2758 .handle_global_event
= falcon_handle_global_event
,
2759 .fini_dmaq
= efx_farch_fini_dmaq
,
2760 .prepare_flush
= falcon_prepare_flush
,
2761 .finish_flush
= efx_port_dummy_op_void
,
2762 .describe_stats
= falcon_describe_nic_stats
,
2763 .update_stats
= falcon_update_nic_stats
,
2764 .start_stats
= falcon_start_nic_stats
,
2765 .stop_stats
= falcon_stop_nic_stats
,
2766 .set_id_led
= falcon_set_id_led
,
2767 .push_irq_moderation
= falcon_push_irq_moderation
,
2768 .reconfigure_port
= falcon_reconfigure_port
,
2769 .prepare_enable_fc_tx
= falcon_b0_prepare_enable_fc_tx
,
2770 .reconfigure_mac
= falcon_reconfigure_xmac
,
2771 .check_mac_fault
= falcon_xmac_check_fault
,
2772 .get_wol
= falcon_get_wol
,
2773 .set_wol
= falcon_set_wol
,
2774 .resume_wol
= efx_port_dummy_op_void
,
2775 .test_chip
= falcon_b0_test_chip
,
2776 .test_nvram
= falcon_test_nvram
,
2777 .irq_enable_master
= efx_farch_irq_enable_master
,
2778 .irq_test_generate
= efx_farch_irq_test_generate
,
2779 .irq_disable_non_ev
= efx_farch_irq_disable_master
,
2780 .irq_handle_msi
= efx_farch_msi_interrupt
,
2781 .irq_handle_legacy
= efx_farch_legacy_interrupt
,
2782 .tx_probe
= efx_farch_tx_probe
,
2783 .tx_init
= efx_farch_tx_init
,
2784 .tx_remove
= efx_farch_tx_remove
,
2785 .tx_write
= efx_farch_tx_write
,
2786 .rx_push_indir_table
= efx_farch_rx_push_indir_table
,
2787 .rx_probe
= efx_farch_rx_probe
,
2788 .rx_init
= efx_farch_rx_init
,
2789 .rx_remove
= efx_farch_rx_remove
,
2790 .rx_write
= efx_farch_rx_write
,
2791 .rx_defer_refill
= efx_farch_rx_defer_refill
,
2792 .ev_probe
= efx_farch_ev_probe
,
2793 .ev_init
= efx_farch_ev_init
,
2794 .ev_fini
= efx_farch_ev_fini
,
2795 .ev_remove
= efx_farch_ev_remove
,
2796 .ev_process
= efx_farch_ev_process
,
2797 .ev_read_ack
= efx_farch_ev_read_ack
,
2798 .ev_test_generate
= efx_farch_ev_test_generate
,
2799 .filter_table_probe
= efx_farch_filter_table_probe
,
2800 .filter_table_restore
= efx_farch_filter_table_restore
,
2801 .filter_table_remove
= efx_farch_filter_table_remove
,
2802 .filter_update_rx_scatter
= efx_farch_filter_update_rx_scatter
,
2803 .filter_insert
= efx_farch_filter_insert
,
2804 .filter_remove_safe
= efx_farch_filter_remove_safe
,
2805 .filter_get_safe
= efx_farch_filter_get_safe
,
2806 .filter_clear_rx
= efx_farch_filter_clear_rx
,
2807 .filter_count_rx_used
= efx_farch_filter_count_rx_used
,
2808 .filter_get_rx_id_limit
= efx_farch_filter_get_rx_id_limit
,
2809 .filter_get_rx_ids
= efx_farch_filter_get_rx_ids
,
2810 #ifdef CONFIG_RFS_ACCEL
2811 .filter_rfs_insert
= efx_farch_filter_rfs_insert
,
2812 .filter_rfs_expire_one
= efx_farch_filter_rfs_expire_one
,
2814 #ifdef CONFIG_SFC_MTD
2815 .mtd_probe
= falcon_mtd_probe
,
2816 .mtd_rename
= falcon_mtd_rename
,
2817 .mtd_read
= falcon_mtd_read
,
2818 .mtd_erase
= falcon_mtd_erase
,
2819 .mtd_write
= falcon_mtd_write
,
2820 .mtd_sync
= falcon_mtd_sync
,
2823 .revision
= EFX_REV_FALCON_B0
,
2824 .txd_ptr_tbl_base
= FR_BZ_TX_DESC_PTR_TBL
,
2825 .rxd_ptr_tbl_base
= FR_BZ_RX_DESC_PTR_TBL
,
2826 .buf_tbl_base
= FR_BZ_BUF_FULL_TBL
,
2827 .evq_ptr_tbl_base
= FR_BZ_EVQ_PTR_TBL
,
2828 .evq_rptr_tbl_base
= FR_BZ_EVQ_RPTR
,
2829 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
2830 .rx_buffer_hash_size
= 0x10,
2831 .rx_buffer_padding
= 0,
2832 .can_rx_scatter
= true,
2833 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
2834 .timer_period_max
= 1 << FRF_AB_TC_TIMER_VAL_WIDTH
,
2835 .offload_features
= NETIF_F_IP_CSUM
| NETIF_F_RXHASH
| NETIF_F_NTUPLE
,
2837 .max_rx_ip_filters
= FR_BZ_RX_FILTER_TBL0_ROWS
,