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iwlwifi: restore PAN support
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / iwlwifi / iwl-trans-pcie-tx.c
blob2b1df0092aee412266d5a0f66dac10981de71c4d
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 #include "iwl-debug.h"
34 #include "iwl-csr.h"
35 #include "iwl-prph.h"
36 #include "iwl-io.h"
37 #include "iwl-agn-hw.h"
38 #include "iwl-op-mode.h"
39 #include "iwl-trans-pcie-int.h"
40
41 #define IWL_TX_CRC_SIZE 4
42 #define IWL_TX_DELIMITER_SIZE 4
43
44 /*
45 * mac80211 queues, ACs, hardware queues, FIFOs.
46 *
47 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
48 *
49 * Mac80211 uses the following numbers, which we get as from it
50 * by way of skb_get_queue_mapping(skb):
51 *
52 * VO 0
53 * VI 1
54 * BE 2
55 * BK 3
56 *
57 *
58 * Regular (not A-MPDU) frames are put into hardware queues corresponding
59 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
60 * own queue per aggregation session (RA/TID combination), such queues are
61 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
62 * order to map frames to the right queue, we also need an AC->hw queue
63 * mapping. This is implemented here.
64 *
65 * Due to the way hw queues are set up (by the hw specific code), the AC->hw
66 * queue mapping is the identity mapping.
67 */
68
69 static const u8 tid_to_ac[] = {
70 IEEE80211_AC_BE,
71 IEEE80211_AC_BK,
72 IEEE80211_AC_BK,
73 IEEE80211_AC_BE,
74 IEEE80211_AC_VI,
75 IEEE80211_AC_VI,
76 IEEE80211_AC_VO,
77 IEEE80211_AC_VO
78 };
79
80
81 /**
82 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
83 */
84 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
85 struct iwl_tx_queue *txq,
86 u16 byte_cnt)
87 {
88 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
89 struct iwl_trans_pcie *trans_pcie =
90 IWL_TRANS_GET_PCIE_TRANS(trans);
91 int write_ptr = txq->q.write_ptr;
92 int txq_id = txq->q.id;
93 u8 sec_ctl = 0;
94 u8 sta_id = 0;
95 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
96 __le16 bc_ent;
97 struct iwl_tx_cmd *tx_cmd =
98 (struct iwl_tx_cmd *) txq->cmd[txq->q.write_ptr]->payload;
99
100 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
101
102 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
103
104 sta_id = tx_cmd->sta_id;
105 sec_ctl = tx_cmd->sec_ctl;
106
107 switch (sec_ctl & TX_CMD_SEC_MSK) {
108 case TX_CMD_SEC_CCM:
109 len += CCMP_MIC_LEN;
110 break;
111 case TX_CMD_SEC_TKIP:
112 len += TKIP_ICV_LEN;
113 break;
114 case TX_CMD_SEC_WEP:
115 len += WEP_IV_LEN + WEP_ICV_LEN;
116 break;
117 }
118
119 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
120
121 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
122
123 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
124 scd_bc_tbl[txq_id].
125 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
126 }
127
128 /**
129 * iwl_txq_update_write_ptr - Send new write index to hardware
130 */
131 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
132 {
133 u32 reg = 0;
134 int txq_id = txq->q.id;
135
136 if (txq->need_update == 0)
137 return;
138
139 if (cfg(trans)->base_params->shadow_reg_enable) {
140 /* shadow register enabled */
141 iwl_write32(trans, HBUS_TARG_WRPTR,
142 txq->q.write_ptr | (txq_id << 8));
143 } else {
144 /* if we're trying to save power */
145 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
146 /* wake up nic if it's powered down ...
147 * uCode will wake up, and interrupt us again, so next
148 * time we'll skip this part. */
149 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
150
151 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
152 IWL_DEBUG_INFO(trans,
153 "Tx queue %d requesting wakeup,"
154 " GP1 = 0x%x\n", txq_id, reg);
155 iwl_set_bit(trans, CSR_GP_CNTRL,
156 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
157 return;
158 }
159
160 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
161 txq->q.write_ptr | (txq_id << 8));
162
163 /*
164 * else not in power-save mode,
165 * uCode will never sleep when we're
166 * trying to tx (during RFKILL, we're not trying to tx).
167 */
168 } else
169 iwl_write32(trans, HBUS_TARG_WRPTR,
170 txq->q.write_ptr | (txq_id << 8));
171 }
172 txq->need_update = 0;
173 }
174
175 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
176 {
177 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
178
179 dma_addr_t addr = get_unaligned_le32(&tb->lo);
180 if (sizeof(dma_addr_t) > sizeof(u32))
181 addr |=
182 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
183
184 return addr;
185 }
186
187 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
188 {
189 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
190
191 return le16_to_cpu(tb->hi_n_len) >> 4;
192 }
193
194 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
195 dma_addr_t addr, u16 len)
196 {
197 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
198 u16 hi_n_len = len << 4;
199
200 put_unaligned_le32(addr, &tb->lo);
201 if (sizeof(dma_addr_t) > sizeof(u32))
202 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
203
204 tb->hi_n_len = cpu_to_le16(hi_n_len);
205
206 tfd->num_tbs = idx + 1;
207 }
208
209 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
210 {
211 return tfd->num_tbs & 0x1f;
212 }
213
214 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
215 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
216 {
217 int i;
218 int num_tbs;
219
220 /* Sanity check on number of chunks */
221 num_tbs = iwl_tfd_get_num_tbs(tfd);
222
223 if (num_tbs >= IWL_NUM_OF_TBS) {
224 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
225 /* @todo issue fatal error, it is quite serious situation */
226 return;
227 }
228
229 /* Unmap tx_cmd */
230 if (num_tbs)
231 dma_unmap_single(trans->dev,
232 dma_unmap_addr(meta, mapping),
233 dma_unmap_len(meta, len),
234 DMA_BIDIRECTIONAL);
235
236 /* Unmap chunks, if any. */
237 for (i = 1; i < num_tbs; i++)
238 dma_unmap_single(trans->dev, iwl_tfd_tb_get_addr(tfd, i),
239 iwl_tfd_tb_get_len(tfd, i), dma_dir);
240 }
241
242 /**
243 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
244 * @trans - transport private data
245 * @txq - tx queue
246 * @index - the index of the TFD to be freed
247 *@dma_dir - the direction of the DMA mapping
248 *
249 * Does NOT advance any TFD circular buffer read/write indexes
250 * Does NOT free the TFD itself (which is within circular buffer)
251 */
252 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
253 int index, enum dma_data_direction dma_dir)
254 {
255 struct iwl_tfd *tfd_tmp = txq->tfds;
256
257 lockdep_assert_held(&txq->lock);
258
259 iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index], dma_dir);
260
261 /* free SKB */
262 if (txq->skbs) {
263 struct sk_buff *skb;
264
265 skb = txq->skbs[index];
266
267 /* Can be called from irqs-disabled context
268 * If skb is not NULL, it means that the whole queue is being
269 * freed and that the queue is not empty - free the skb
270 */
271 if (skb) {
272 iwl_op_mode_free_skb(trans->op_mode, skb);
273 txq->skbs[index] = NULL;
274 }
275 }
276 }
277
278 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
279 struct iwl_tx_queue *txq,
280 dma_addr_t addr, u16 len,
281 u8 reset)
282 {
283 struct iwl_queue *q;
284 struct iwl_tfd *tfd, *tfd_tmp;
285 u32 num_tbs;
286
287 q = &txq->q;
288 tfd_tmp = txq->tfds;
289 tfd = &tfd_tmp[q->write_ptr];
290
291 if (reset)
292 memset(tfd, 0, sizeof(*tfd));
293
294 num_tbs = iwl_tfd_get_num_tbs(tfd);
295
296 /* Each TFD can point to a maximum 20 Tx buffers */
297 if (num_tbs >= IWL_NUM_OF_TBS) {
298 IWL_ERR(trans, "Error can not send more than %d chunks\n",
299 IWL_NUM_OF_TBS);
300 return -EINVAL;
301 }
302
303 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
304 return -EINVAL;
305
306 if (unlikely(addr & ~IWL_TX_DMA_MASK))
307 IWL_ERR(trans, "Unaligned address = %llx\n",
308 (unsigned long long)addr);
309
310 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
311
312 return 0;
313 }
314
315 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
316 * DMA services
317 *
318 * Theory of operation
319 *
320 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
321 * of buffer descriptors, each of which points to one or more data buffers for
322 * the device to read from or fill. Driver and device exchange status of each
323 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
324 * entries in each circular buffer, to protect against confusing empty and full
325 * queue states.
326 *
327 * The device reads or writes the data in the queues via the device's several
328 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
329 *
330 * For Tx queue, there are low mark and high mark limits. If, after queuing
331 * the packet for Tx, free space become < low mark, Tx queue stopped. When
332 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
333 * Tx queue resumed.
334 *
335 ***************************************************/
336
337 int iwl_queue_space(const struct iwl_queue *q)
338 {
339 int s = q->read_ptr - q->write_ptr;
340
341 if (q->read_ptr > q->write_ptr)
342 s -= q->n_bd;
343
344 if (s <= 0)
345 s += q->n_window;
346 /* keep some reserve to not confuse empty and full situations */
347 s -= 2;
348 if (s < 0)
349 s = 0;
350 return s;
351 }
352
353 /**
354 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
355 */
356 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
357 {
358 q->n_bd = count;
359 q->n_window = slots_num;
360 q->id = id;
361
362 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
363 * and iwl_queue_dec_wrap are broken. */
364 if (WARN_ON(!is_power_of_2(count)))
365 return -EINVAL;
366
367 /* slots_num must be power-of-two size, otherwise
368 * get_cmd_index is broken. */
369 if (WARN_ON(!is_power_of_2(slots_num)))
370 return -EINVAL;
371
372 q->low_mark = q->n_window / 4;
373 if (q->low_mark < 4)
374 q->low_mark = 4;
375
376 q->high_mark = q->n_window / 8;
377 if (q->high_mark < 2)
378 q->high_mark = 2;
379
380 q->write_ptr = q->read_ptr = 0;
381
382 return 0;
383 }
384
385 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
386 struct iwl_tx_queue *txq)
387 {
388 struct iwl_trans_pcie *trans_pcie =
389 IWL_TRANS_GET_PCIE_TRANS(trans);
390 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
391 int txq_id = txq->q.id;
392 int read_ptr = txq->q.read_ptr;
393 u8 sta_id = 0;
394 __le16 bc_ent;
395 struct iwl_tx_cmd *tx_cmd =
396 (struct iwl_tx_cmd *) txq->cmd[txq->q.read_ptr]->payload;
397
398 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
399
400 if (txq_id != trans_pcie->cmd_queue)
401 sta_id = tx_cmd->sta_id;
402
403 bc_ent = cpu_to_le16(1 | (sta_id << 12));
404 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
405
406 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
407 scd_bc_tbl[txq_id].
408 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
409 }
410
411 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
412 u16 txq_id)
413 {
414 u32 tbl_dw_addr;
415 u32 tbl_dw;
416 u16 scd_q2ratid;
417
418 struct iwl_trans_pcie *trans_pcie =
419 IWL_TRANS_GET_PCIE_TRANS(trans);
420
421 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
422
423 tbl_dw_addr = trans_pcie->scd_base_addr +
424 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
425
426 tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
427
428 if (txq_id & 0x1)
429 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
430 else
431 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
432
433 iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
434
435 return 0;
436 }
437
438 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
439 {
440 /* Simply stop the queue, but don't change any configuration;
441 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
442 iwl_write_prph(trans,
443 SCD_QUEUE_STATUS_BITS(txq_id),
444 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
445 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
446 }
447
448 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
449 int txq_id, u32 index)
450 {
451 IWL_DEBUG_TX_QUEUES(trans, "Q %d WrPtr: %d", txq_id, index & 0xff);
452 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
453 (index & 0xff) | (txq_id << 8));
454 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), index);
455 }
456
457 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
458 struct iwl_tx_queue *txq,
459 int tx_fifo_id, int scd_retry)
460 {
461 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
462 int txq_id = txq->q.id;
463 int active =
464 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
465
466 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
467 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
468 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
469 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
470 SCD_QUEUE_STTS_REG_MSK);
471
472 txq->sched_retry = scd_retry;
473
474 if (active)
475 IWL_DEBUG_TX_QUEUES(trans, "Activate %s Queue %d on FIFO %d\n",
476 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
477 else
478 IWL_DEBUG_TX_QUEUES(trans, "Deactivate %s Queue %d\n",
479 scd_retry ? "BA" : "AC/CMD", txq_id);
480 }
481
482 static inline int get_ac_from_tid(u16 tid)
483 {
484 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
485 return tid_to_ac[tid];
486
487 /* no support for TIDs 8-15 yet */
488 return -EINVAL;
489 }
490
491 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
492 u8 ctx, u16 tid)
493 {
494 const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
495 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
496 return ac_to_fifo[tid_to_ac[tid]];
497
498 /* no support for TIDs 8-15 yet */
499 return -EINVAL;
500 }
501
502 static inline bool is_agg_txqid_valid(struct iwl_trans *trans, int txq_id)
503 {
504 if (txq_id < IWLAGN_FIRST_AMPDU_QUEUE)
505 return false;
506 return txq_id < (IWLAGN_FIRST_AMPDU_QUEUE +
507 hw_params(trans).num_ampdu_queues);
508 }
509
510 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
511 enum iwl_rxon_context_id ctx, int sta_id,
512 int tid, int frame_limit, u16 ssn)
513 {
514 int tx_fifo, txq_id;
515 u16 ra_tid;
516 unsigned long flags;
517
518 struct iwl_trans_pcie *trans_pcie =
519 IWL_TRANS_GET_PCIE_TRANS(trans);
520
521 if (WARN_ON(sta_id == IWL_INVALID_STATION))
522 return;
523 if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
524 return;
525
526 tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
527 if (WARN_ON(tx_fifo < 0)) {
528 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
529 return;
530 }
531
532 txq_id = trans_pcie->agg_txq[sta_id][tid];
533 if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) {
534 IWL_ERR(trans,
535 "queue number out of range: %d, must be %d to %d\n",
536 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
537 IWLAGN_FIRST_AMPDU_QUEUE +
538 hw_params(trans).num_ampdu_queues - 1);
539 return;
540 }
541
542 ra_tid = BUILD_RAxTID(sta_id, tid);
543
544 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
545
546 /* Stop this Tx queue before configuring it */
547 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
548
549 /* Map receiver-address / traffic-ID to this queue */
550 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
551
552 /* Set this queue as a chain-building queue */
553 iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, (1<<txq_id));
554
555 /* enable aggregations for the queue */
556 iwl_set_bits_prph(trans, SCD_AGGR_SEL, (1<<txq_id));
557
558 /* Place first TFD at index corresponding to start sequence number.
559 * Assumes that ssn_idx is valid (!= 0xFFF) */
560 trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff);
561 trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff);
562 iwl_trans_set_wr_ptrs(trans, txq_id, ssn);
563
564 /* Set up Tx window size and frame limit for this queue */
565 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
566 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
567 sizeof(u32),
568 ((frame_limit <<
569 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
570 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
571 ((frame_limit <<
572 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
573 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
574
575 iwl_set_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
576
577 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
578 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
579 tx_fifo, 1);
580
581 trans_pcie->txq[txq_id].sta_id = sta_id;
582 trans_pcie->txq[txq_id].tid = tid;
583
584 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
585 }
586
587 /*
588 * Find first available (lowest unused) Tx Queue, mark it "active".
589 * Called only when finding queue for aggregation.
590 * Should never return anything < 7, because they should already
591 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
592 */
593 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
594 {
595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
596 int txq_id;
597
598 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
599 if (!test_and_set_bit(txq_id,
600 &trans_pcie->txq_ctx_active_msk))
601 return txq_id;
602 return -1;
603 }
604
605 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
606 int sta_id, int tid)
607 {
608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
609 int txq_id;
610
611 txq_id = iwlagn_txq_ctx_activate_free(trans);
612 if (txq_id == -1) {
613 IWL_ERR(trans, "No free aggregation queue available\n");
614 return -ENXIO;
615 }
616
617 trans_pcie->agg_txq[sta_id][tid] = txq_id;
618 iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
619
620 return 0;
621 }
622
623 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans, int sta_id, int tid)
624 {
625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
626 u8 txq_id = trans_pcie->agg_txq[sta_id][tid];
627
628 if (WARN_ON_ONCE(is_agg_txqid_valid(trans, txq_id) == false)) {
629 IWL_ERR(trans,
630 "queue number out of range: %d, must be %d to %d\n",
631 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
632 IWLAGN_FIRST_AMPDU_QUEUE +
633 hw_params(trans).num_ampdu_queues - 1);
634 return -EINVAL;
635 }
636
637 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
638
639 iwl_clear_bits_prph(trans, SCD_AGGR_SEL, (1 << txq_id));
640
641 trans_pcie->agg_txq[sta_id][tid] = 0;
642 trans_pcie->txq[txq_id].q.read_ptr = 0;
643 trans_pcie->txq[txq_id].q.write_ptr = 0;
644 /* supposes that ssn_idx is valid (!= 0xFFF) */
645 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
646
647 iwl_clear_bits_prph(trans, SCD_INTERRUPT_MASK, (1 << txq_id));
648 iwl_txq_ctx_deactivate(trans_pcie, txq_id);
649 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
650 return 0;
651 }
652
653 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
654
655 /**
656 * iwl_enqueue_hcmd - enqueue a uCode command
657 * @priv: device private data point
658 * @cmd: a point to the ucode command structure
659 *
660 * The function returns < 0 values to indicate the operation is
661 * failed. On success, it turns the index (> 0) of command in the
662 * command queue.
663 */
664 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
665 {
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
667 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
668 struct iwl_queue *q = &txq->q;
669 struct iwl_device_cmd *out_cmd;
670 struct iwl_cmd_meta *out_meta;
671 dma_addr_t phys_addr;
672 u32 idx;
673 u16 copy_size, cmd_size;
674 bool had_nocopy = false;
675 int i;
676 u8 *cmd_dest;
677 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
678 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
679 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
680 int trace_idx;
681 #endif
682
683 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
684 IWL_WARN(trans, "fw recovery, no hcmd send\n");
685 return -EIO;
686 }
687
688 copy_size = sizeof(out_cmd->hdr);
689 cmd_size = sizeof(out_cmd->hdr);
690
691 /* need one for the header if the first is NOCOPY */
692 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
693
694 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
695 if (!cmd->len[i])
696 continue;
697 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
698 had_nocopy = true;
699 } else {
700 /* NOCOPY must not be followed by normal! */
701 if (WARN_ON(had_nocopy))
702 return -EINVAL;
703 copy_size += cmd->len[i];
704 }
705 cmd_size += cmd->len[i];
706 }
707
708 /*
709 * If any of the command structures end up being larger than
710 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
711 * allocated into separate TFDs, then we will need to
712 * increase the size of the buffers.
713 */
714 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
715 return -EINVAL;
716
717 spin_lock_bh(&txq->lock);
718
719 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
720 spin_unlock_bh(&txq->lock);
721
722 IWL_ERR(trans, "No space in command queue\n");
723 iwl_op_mode_cmd_queue_full(trans->op_mode);
724 return -ENOSPC;
725 }
726
727 idx = get_cmd_index(q, q->write_ptr);
728 out_cmd = txq->cmd[idx];
729 out_meta = &txq->meta[idx];
730
731 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
732 if (cmd->flags & CMD_WANT_SKB)
733 out_meta->source = cmd;
734
735 /* set up the header */
736
737 out_cmd->hdr.cmd = cmd->id;
738 out_cmd->hdr.flags = 0;
739 out_cmd->hdr.sequence =
740 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
741 INDEX_TO_SEQ(q->write_ptr));
742
743 /* and copy the data that needs to be copied */
744
745 cmd_dest = out_cmd->payload;
746 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
747 if (!cmd->len[i])
748 continue;
749 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
750 break;
751 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
752 cmd_dest += cmd->len[i];
753 }
754
755 IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
756 "%d bytes at %d[%d]:%d\n",
757 get_cmd_string(out_cmd->hdr.cmd),
758 out_cmd->hdr.cmd,
759 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
760 q->write_ptr, idx, trans_pcie->cmd_queue);
761
762 phys_addr = dma_map_single(trans->dev, &out_cmd->hdr, copy_size,
763 DMA_BIDIRECTIONAL);
764 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
765 idx = -ENOMEM;
766 goto out;
767 }
768
769 dma_unmap_addr_set(out_meta, mapping, phys_addr);
770 dma_unmap_len_set(out_meta, len, copy_size);
771
772 iwlagn_txq_attach_buf_to_tfd(trans, txq,
773 phys_addr, copy_size, 1);
774 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
775 trace_bufs[0] = &out_cmd->hdr;
776 trace_lens[0] = copy_size;
777 trace_idx = 1;
778 #endif
779
780 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
781 if (!cmd->len[i])
782 continue;
783 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
784 continue;
785 phys_addr = dma_map_single(trans->dev,
786 (void *)cmd->data[i],
787 cmd->len[i], DMA_BIDIRECTIONAL);
788 if (dma_mapping_error(trans->dev, phys_addr)) {
789 iwlagn_unmap_tfd(trans, out_meta,
790 &txq->tfds[q->write_ptr],
791 DMA_BIDIRECTIONAL);
792 idx = -ENOMEM;
793 goto out;
794 }
795
796 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
797 cmd->len[i], 0);
798 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
799 trace_bufs[trace_idx] = cmd->data[i];
800 trace_lens[trace_idx] = cmd->len[i];
801 trace_idx++;
802 #endif
803 }
804
805 out_meta->flags = cmd->flags;
806
807 txq->need_update = 1;
808
809 /* check that tracing gets all possible blocks */
810 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
811 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
812 trace_iwlwifi_dev_hcmd(trans->dev, cmd->flags,
813 trace_bufs[0], trace_lens[0],
814 trace_bufs[1], trace_lens[1],
815 trace_bufs[2], trace_lens[2]);
816 #endif
817
818 /* Increment and update queue's write index */
819 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
820 iwl_txq_update_write_ptr(trans, txq);
821
822 out:
823 spin_unlock_bh(&txq->lock);
824 return idx;
825 }
826
827 /**
828 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
829 *
830 * When FW advances 'R' index, all entries between old and new 'R' index
831 * need to be reclaimed. As result, some free space forms. If there is
832 * enough free space (> low mark), wake the stack that feeds us.
833 */
834 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
835 int idx)
836 {
837 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
838 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
839 struct iwl_queue *q = &txq->q;
840 int nfreed = 0;
841
842 lockdep_assert_held(&txq->lock);
843
844 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
845 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
846 "index %d is out of range [0-%d] %d %d.\n", __func__,
847 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
848 return;
849 }
850
851 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
852 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
853
854 if (nfreed++ > 0) {
855 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
856 q->write_ptr, q->read_ptr);
857 iwl_op_mode_nic_error(trans->op_mode);
858 }
859
860 }
861 }
862
863 /**
864 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
865 * @rxb: Rx buffer to reclaim
866 * @handler_status: return value of the handler of the command
867 * (put in setup_rx_handlers)
868 *
869 * If an Rx buffer has an async callback associated with it the callback
870 * will be executed. The attached skb (if present) will only be freed
871 * if the callback returns 1
872 */
873 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_cmd_buffer *rxb,
874 int handler_status)
875 {
876 struct iwl_rx_packet *pkt = rxb_addr(rxb);
877 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
878 int txq_id = SEQ_TO_QUEUE(sequence);
879 int index = SEQ_TO_INDEX(sequence);
880 int cmd_index;
881 struct iwl_device_cmd *cmd;
882 struct iwl_cmd_meta *meta;
883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
884 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
885
886 /* If a Tx command is being handled and it isn't in the actual
887 * command queue then there a command routing bug has been introduced
888 * in the queue management code. */
889 if (WARN(txq_id != trans_pcie->cmd_queue,
890 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
891 txq_id, trans_pcie->cmd_queue, sequence,
892 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
893 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
894 iwl_print_hex_error(trans, pkt, 32);
895 return;
896 }
897
898 spin_lock(&txq->lock);
899
900 cmd_index = get_cmd_index(&txq->q, index);
901 cmd = txq->cmd[cmd_index];
902 meta = &txq->meta[cmd_index];
903
904 txq->time_stamp = jiffies;
905
906 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
907 DMA_BIDIRECTIONAL);
908
909 /* Input error checking is done when commands are added to queue. */
910 if (meta->flags & CMD_WANT_SKB) {
911 struct page *p = rxb_steal_page(rxb);
912
913 meta->source->resp_pkt = pkt;
914 meta->source->_rx_page_addr = (unsigned long)page_address(p);
915 meta->source->_rx_page_order = hw_params(trans).rx_page_order;
916 meta->source->handler_status = handler_status;
917 }
918
919 iwl_hcmd_queue_reclaim(trans, txq_id, index);
920
921 if (!(meta->flags & CMD_ASYNC)) {
922 if (!test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
923 IWL_WARN(trans,
924 "HCMD_ACTIVE already clear for command %s\n",
925 get_cmd_string(cmd->hdr.cmd));
926 }
927 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
928 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
929 get_cmd_string(cmd->hdr.cmd));
930 wake_up(&trans->shrd->wait_command_queue);
931 }
932
933 meta->flags = 0;
934
935 spin_unlock(&txq->lock);
936 }
937
938 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
939
940 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
941 {
942 int ret;
943
944 /* An asynchronous command can not expect an SKB to be set. */
945 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
946 return -EINVAL;
947
948
949 ret = iwl_enqueue_hcmd(trans, cmd);
950 if (ret < 0) {
951 IWL_ERR(trans,
952 "Error sending %s: enqueue_hcmd failed: %d\n",
953 get_cmd_string(cmd->id), ret);
954 return ret;
955 }
956 return 0;
957 }
958
959 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
960 {
961 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
962 int cmd_idx;
963 int ret;
964
965 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
966 get_cmd_string(cmd->id));
967
968 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
969 IWL_ERR(trans, "Command %s failed: FW Error\n",
970 get_cmd_string(cmd->id));
971 return -EIO;
972 }
973
974 if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE,
975 &trans->shrd->status))) {
976 IWL_ERR(trans, "Command %s: a command is already active!\n",
977 get_cmd_string(cmd->id));
978 return -EIO;
979 }
980
981 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
982 get_cmd_string(cmd->id));
983
984 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
985 if (cmd_idx < 0) {
986 ret = cmd_idx;
987 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
988 IWL_ERR(trans,
989 "Error sending %s: enqueue_hcmd failed: %d\n",
990 get_cmd_string(cmd->id), ret);
991 return ret;
992 }
993
994 ret = wait_event_timeout(trans->shrd->wait_command_queue,
995 !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
996 HOST_COMPLETE_TIMEOUT);
997 if (!ret) {
998 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
999 struct iwl_tx_queue *txq =
1000 &trans_pcie->txq[trans_pcie->cmd_queue];
1001 struct iwl_queue *q = &txq->q;
1002
1003 IWL_ERR(trans,
1004 "Error sending %s: time out after %dms.\n",
1005 get_cmd_string(cmd->id),
1006 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1007
1008 IWL_ERR(trans,
1009 "Current CMD queue read_ptr %d write_ptr %d\n",
1010 q->read_ptr, q->write_ptr);
1011
1012 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1013 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1014 "%s\n", get_cmd_string(cmd->id));
1015 ret = -ETIMEDOUT;
1016 goto cancel;
1017 }
1018 }
1019
1020 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1021 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1022 get_cmd_string(cmd->id));
1023 ret = -EIO;
1024 goto cancel;
1025 }
1026
1027 return 0;
1028
1029 cancel:
1030 if (cmd->flags & CMD_WANT_SKB) {
1031 /*
1032 * Cancel the CMD_WANT_SKB flag for the cmd in the
1033 * TX cmd queue. Otherwise in case the cmd comes
1034 * in later, it will possibly set an invalid
1035 * address (cmd->meta.source).
1036 */
1037 trans_pcie->txq[trans_pcie->cmd_queue].meta[cmd_idx].flags &=
1038 ~CMD_WANT_SKB;
1039 }
1040
1041 if (cmd->resp_pkt) {
1042 iwl_free_resp(cmd);
1043 cmd->resp_pkt = NULL;
1044 }
1045
1046 return ret;
1047 }
1048
1049 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1050 {
1051 if (cmd->flags & CMD_ASYNC)
1052 return iwl_send_cmd_async(trans, cmd);
1053
1054 return iwl_send_cmd_sync(trans, cmd);
1055 }
1056
1057 /* Frees buffers until index _not_ inclusive */
1058 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1059 struct sk_buff_head *skbs)
1060 {
1061 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1062 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1063 struct iwl_queue *q = &txq->q;
1064 int last_to_free;
1065 int freed = 0;
1066
1067 /* This function is not meant to release cmd queue*/
1068 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1069 return 0;
1070
1071 lockdep_assert_held(&txq->lock);
1072
1073 /*Since we free until index _not_ inclusive, the one before index is
1074 * the last we will free. This one must be used */
1075 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1076
1077 if ((index >= q->n_bd) ||
1078 (iwl_queue_used(q, last_to_free) == 0)) {
1079 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1080 "last_to_free %d is out of range [0-%d] %d %d.\n",
1081 __func__, txq_id, last_to_free, q->n_bd,
1082 q->write_ptr, q->read_ptr);
1083 return 0;
1084 }
1085
1086 if (WARN_ON(!skb_queue_empty(skbs)))
1087 return 0;
1088
1089 for (;
1090 q->read_ptr != index;
1091 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1092
1093 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1094 continue;
1095
1096 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1097
1098 txq->skbs[txq->q.read_ptr] = NULL;
1099
1100 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1101
1102 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr, DMA_TO_DEVICE);
1103 freed++;
1104 }
1105 return freed;
1106 }
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