drivers/net/wireless/iwlwifi/iwl-csr.h

   1 /******************************************************************************
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   8  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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  17  * General Public License for more details.
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  25  * in the file called LICENSE.GPL.
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #ifndef __iwl_csr_h__
  64 #define __iwl_csr_h__
  65 /*
  66  * CSR (control and status registers)
  67  *
  68  * CSR registers are mapped directly into PCI bus space, and are accessible
  69  * whenever platform supplies power to device, even when device is in
  70  * low power states due to driver-invoked device resets
  71  * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
  72  *
  73  * Use iwl_write32() and iwl_read32() family to access these registers;
  74  * these provide simple PCI bus access, without waking up the MAC.
  75  * Do not use iwl_write_direct32() family for these registers;
  76  * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
  77  * The MAC (uCode processor, etc.) does not need to be powered up for accessing
  78  * the CSR registers.
  79  *
  80  * NOTE:  Device does need to be awake in order to read this memory
  81  *        via CSR_EEPROM and CSR_OTP registers
  82  */
  83 #define CSR_BASE    (0x000)
  84
  85 #define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
  86 #define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
  87 #define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
  88 #define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
  89 #define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
  90 #define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
  91 #define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
  92 #define CSR_GP_CNTRL            (CSR_BASE+0x024)
  93
  94 /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
  95 #define CSR_INT_PERIODIC_REG    (CSR_BASE+0x005)
  96
  97 /*
  98  * Hardware revision info
  99  * Bit fields:
 100  * 31-8:  Reserved
 101  *  7-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
 102  *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 103  *  1-0:  "Dash" (-) value, as in A-1, etc.
 104  *
 105  * NOTE:  Revision step affects calculation of CCK txpower for 4965.
 106  * NOTE:  See also CSR_HW_REV_WA_REG (work-around for bug in 4965).
 107  */
 108 #define CSR_HW_REV              (CSR_BASE+0x028)
 109
 110 /*
 111  * EEPROM and OTP (one-time-programmable) memory reads
 112  *
 113  * NOTE:  Device must be awake, initialized via apm_ops.init(),
 114  *        in order to read.
 115  */
 116 #define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 117 #define CSR_EEPROM_GP           (CSR_BASE+0x030)
 118 #define CSR_OTP_GP_REG          (CSR_BASE+0x034)
 119
 120 #define CSR_GIO_REG             (CSR_BASE+0x03C)
 121 #define CSR_GP_UCODE_REG        (CSR_BASE+0x048)
 122 #define CSR_GP_DRIVER_REG       (CSR_BASE+0x050)
 123
 124 /*
 125  * UCODE-DRIVER GP (general purpose) mailbox registers.
 126  * SET/CLR registers set/clear bit(s) if "1" is written.
 127  */
 128 #define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 129 #define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 130 #define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 131 #define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 132
 133 #define CSR_LED_REG             (CSR_BASE+0x094)
 134 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
 135 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
 136
 137
 138 /* GIO Chicken Bits (PCI Express bus link power management) */
 139 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
 140
 141 /* Analog phase-lock-loop configuration  */
 142 #define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
 143
 144 /*
 145  * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
 146  * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
 147  * See also CSR_HW_REV register.
 148  * Bit fields:
 149  *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 150  *  1-0:  "Dash" (-) value, as in C-1, etc.
 151  */
 152 #define CSR_HW_REV_WA_REG               (CSR_BASE+0x22C)
 153
 154 #define CSR_DBG_HPET_MEM_REG            (CSR_BASE+0x240)
 155 #define CSR_DBG_LINK_PWR_MGMT_REG       (CSR_BASE+0x250)
 156
 157 /* Bits for CSR_HW_IF_CONFIG_REG */
 158 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER      (0x00000C00)
 159 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI         (0x00000100)
 160 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI       (0x00000200)
 161
 162 #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A   (0x00080000)
 163 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
 164 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY      (0x00400000) /* PCI_OWN_SEM */
 165 #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
 166 #define CSR_HW_IF_CONFIG_REG_PREPARE              (0x08000000) /* WAKE_ME */
 167
 168 #define CSR_INT_PERIODIC_DIS                    (0x00) /* disable periodic int*/
 169 #define CSR_INT_PERIODIC_ENA                    (0xFF) /* 255*32 usec ~ 8 msec*/
 170
 171 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 172  * acknowledged (reset) by host writing "1" to flagged bits. */
 173 #define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
 174 #define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
 175 #define CSR_INT_BIT_RX_PERIODIC  (1 << 28) /* Rx periodic */
 176 #define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
 177 #define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
 178 #define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
 179 #define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
 180 #define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
 181 #define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
 182 #define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
 183 #define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
 184
 185 #define CSR_INI_SET_MASK        (CSR_INT_BIT_FH_RX   | \
 186                                  CSR_INT_BIT_HW_ERR  | \
 187                                  CSR_INT_BIT_FH_TX   | \
 188                                  CSR_INT_BIT_SW_ERR  | \
 189                                  CSR_INT_BIT_RF_KILL | \
 190                                  CSR_INT_BIT_SW_RX   | \
 191                                  CSR_INT_BIT_WAKEUP  | \
 192                                  CSR_INT_BIT_ALIVE)
 193
 194 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
 195 #define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
 196 #define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
 197 #define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
 198 #define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
 199 #define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
 200 #define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
 201
 202 #define CSR_FH_INT_RX_MASK      (CSR_FH_INT_BIT_HI_PRIOR | \
 203                                 CSR_FH_INT_BIT_RX_CHNL1 | \
 204                                 CSR_FH_INT_BIT_RX_CHNL0)
 205
 206 #define CSR_FH_INT_TX_MASK      (CSR_FH_INT_BIT_TX_CHNL1 | \
 207                                 CSR_FH_INT_BIT_TX_CHNL0)
 208
 209 /* GPIO */
 210 #define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
 211 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
 212 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
 213
 214 /* RESET */
 215 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
 216 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
 217 #define CSR_RESET_REG_FLAG_SW_RESET                  (0x00000080)
 218 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
 219 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
 220 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
 221
 222 /*
 223  * GP (general purpose) CONTROL REGISTER
 224  * Bit fields:
 225  *    27:  HW_RF_KILL_SW
 226  *         Indicates state of (platform's) hardware RF-Kill switch
 227  * 26-24:  POWER_SAVE_TYPE
 228  *         Indicates current power-saving mode:
 229  *         000 -- No power saving
 230  *         001 -- MAC power-down
 231  *         010 -- PHY (radio) power-down
 232  *         011 -- Error
 233  *   9-6:  SYS_CONFIG
 234  *         Indicates current system configuration, reflecting pins on chip
 235  *         as forced high/low by device circuit board.
 236  *     4:  GOING_TO_SLEEP
 237  *         Indicates MAC is entering a power-saving sleep power-down.
 238  *         Not a good time to access device-internal resources.
 239  *     3:  MAC_ACCESS_REQ
 240  *         Host sets this to request and maintain MAC wakeup, to allow host
 241  *         access to device-internal resources.  Host must wait for
 242  *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
 243  *         device registers.
 244  *     2:  INIT_DONE
 245  *         Host sets this to put device into fully operational D0 power mode.
 246  *         Host resets this after SW_RESET to put device into low power mode.
 247  *     0:  MAC_CLOCK_READY
 248  *         Indicates MAC (ucode processor, etc.) is powered up and can run.
 249  *         Internal resources are accessible.
 250  *         NOTE:  This does not indicate that the processor is actually running.
 251  *         NOTE:  This does not indicate that device has completed
 252  *                init or post-power-down restore of internal SRAM memory.
 253  *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
 254  *                SRAM is restored and uCode is in normal operation mode.
 255  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 256  *                do not need to save/restore it.
 257  *         NOTE:  After device reset, this bit remains "0" until host sets
 258  *                INIT_DONE
 259  */
 260 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY        (0x00000001)
 261 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
 262 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
 263 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
 264
 265 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)
 266
 267 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
 268 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE         (0x04000000)
 269 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
 270
 271
 272 /* HW REV */
 273 #define CSR_HW_REV_TYPE_MSK            (0x00001F0)
 274 #define CSR_HW_REV_TYPE_5300           (0x0000020)
 275 #define CSR_HW_REV_TYPE_5350           (0x0000030)
 276 #define CSR_HW_REV_TYPE_5100           (0x0000050)
 277 #define CSR_HW_REV_TYPE_5150           (0x0000040)
 278 #define CSR_HW_REV_TYPE_1000           (0x0000060)
 279 #define CSR_HW_REV_TYPE_6x00           (0x0000070)
 280 #define CSR_HW_REV_TYPE_6x50           (0x0000080)
 281 #define CSR_HW_REV_TYPE_6150           (0x0000084)
 282 #define CSR_HW_REV_TYPE_6x05           (0x00000B0)
 283 #define CSR_HW_REV_TYPE_6x30           CSR_HW_REV_TYPE_6x05
 284 #define CSR_HW_REV_TYPE_6x35           CSR_HW_REV_TYPE_6x05
 285 #define CSR_HW_REV_TYPE_2x30           (0x00000C0)
 286 #define CSR_HW_REV_TYPE_2x00           (0x0000100)
 287 #define CSR_HW_REV_TYPE_105            (0x0000110)
 288 #define CSR_HW_REV_TYPE_135            (0x0000120)
 289 #define CSR_HW_REV_TYPE_NONE           (0x00001F0)
 290
 291 /* EEPROM REG */
 292 #define CSR_EEPROM_REG_READ_VALID_MSK   (0x00000001)
 293 #define CSR_EEPROM_REG_BIT_CMD          (0x00000002)
 294 #define CSR_EEPROM_REG_MSK_ADDR         (0x0000FFFC)
 295 #define CSR_EEPROM_REG_MSK_DATA         (0xFFFF0000)
 296
 297 /* EEPROM GP */
 298 #define CSR_EEPROM_GP_VALID_MSK         (0x00000007) /* signature */
 299 #define CSR_EEPROM_GP_IF_OWNER_MSK      (0x00000180)
 300 #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP    (0x00000000)
 301 #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP          (0x00000001)
 302 #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K         (0x00000002)
 303 #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K         (0x00000004)
 304
 305 /* One-time-programmable memory general purpose reg */
 306 #define CSR_OTP_GP_REG_DEVICE_SELECT    (0x00010000) /* 0 - EEPROM, 1 - OTP */
 307 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE  (0x00020000) /* 0 - absolute, 1 - relative */
 308 #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
 309 #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
 310
 311 /* GP REG */
 312 #define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
 313 #define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
 314 #define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
 315 #define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
 316 #define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
 317
 318
 319 /* CSR GIO */
 320 #define CSR_GIO_REG_VAL_L0S_ENABLED     (0x00000002)
 321
 322 /*
 323  * UCODE-DRIVER GP (general purpose) mailbox register 1
 324  * Host driver and uCode write and/or read this register to communicate with
 325  * each other.
 326  * Bit fields:
 327  *     4:  UCODE_DISABLE
 328  *         Host sets this to request permanent halt of uCode, same as
 329  *         sending CARD_STATE command with "halt" bit set.
 330  *     3:  CT_KILL_EXIT
 331  *         Host sets this to request exit from CT_KILL state, i.e. host thinks
 332  *         device temperature is low enough to continue normal operation.
 333  *     2:  CMD_BLOCKED
 334  *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
 335  *         to release uCode to clear all Tx and command queues, enter
 336  *         unassociated mode, and power down.
 337  *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
 338  *     1:  SW_BIT_RFKILL
 339  *         Host sets this when issuing CARD_STATE command to request
 340  *         device sleep.
 341  *     0:  MAC_SLEEP
 342  *         uCode sets this when preparing a power-saving power-down.
 343  *         uCode resets this when power-up is complete and SRAM is sane.
 344  *         NOTE:  device saves internal SRAM data to host when powering down,
 345  *                and must restore this data after powering back up.
 346  *                MAC_SLEEP is the best indication that restore is complete.
 347  *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
 348  *                do not need to save/restore it.
 349  */
 350 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
 351 #define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
 352 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
 353 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
 354 #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE       (0x00000020)
 355
 356 /* GP Driver */
 357 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK         (0x00000003)
 358 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB     (0x00000000)
 359 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB     (0x00000001)
 360 #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA     (0x00000002)
 361 #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6        (0x00000004)
 362 #define CSR_GP_DRIVER_REG_BIT_6050_1x2              (0x00000008)
 363
 364 #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER        (0x00000080)
 365
 366 /* GIO Chicken Bits (PCI Express bus link power management) */
 367 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
 368 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
 369
 370 /* LED */
 371 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
 372 #define CSR_LED_REG_TRUN_ON (0x78)
 373 #define CSR_LED_REG_TRUN_OFF (0x38)
 374
 375 /* ANA_PLL */
 376 #define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
 377
 378 /* HPET MEM debug */
 379 #define CSR_DBG_HPET_MEM_REG_VAL        (0xFFFF0000)
 380
 381 /* DRAM INT TABLE */
 382 #define CSR_DRAM_INT_TBL_ENABLE         (1 << 31)
 383 #define CSR_DRAM_INIT_TBL_WRAP_CHECK    (1 << 27)
 384
 385 /*
 386  * HBUS (Host-side Bus)
 387  *
 388  * HBUS registers are mapped directly into PCI bus space, but are used
 389  * to indirectly access device's internal memory or registers that
 390  * may be powered-down.
 391  *
 392  * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
 393  * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
 394  * to make sure the MAC (uCode processor, etc.) is powered up for accessing
 395  * internal resources.
 396  *
 397  * Do not use iwl_write32()/iwl_read32() family to access these registers;
 398  * these provide only simple PCI bus access, without waking up the MAC.
 399  */
 400 #define HBUS_BASE       (0x400)
 401
 402 /*
 403  * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
 404  * structures, error log, event log, verifying uCode load).
 405  * First write to address register, then read from or write to data register
 406  * to complete the job.  Once the address register is set up, accesses to
 407  * data registers auto-increment the address by one dword.
 408  * Bit usage for address registers (read or write):
 409  *  0-31:  memory address within device
 410  */
 411 #define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
 412 #define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
 413 #define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
 414 #define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
 415
 416 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
 417 #define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
 418 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
 419
 420 /*
 421  * Registers for accessing device's internal peripheral registers
 422  * (e.g. SCD, BSM, etc.).  First write to address register,
 423  * then read from or write to data register to complete the job.
 424  * Bit usage for address registers (read or write):
 425  *  0-15:  register address (offset) within device
 426  * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
 427  */
 428 #define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
 429 #define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
 430 #define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
 431 #define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
 432
 433 /*
 434  * Per-Tx-queue write pointer (index, really!)
 435  * Indicates index to next TFD that driver will fill (1 past latest filled).
 436  * Bit usage:
 437  *  0-7:  queue write index
 438  * 11-8:  queue selector
 439  */
 440 #define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
 441
 442 /**********************************************************
 443  * CSR values
 444  **********************************************************/
 445  /*
 446  * host interrupt timeout value
 447  * used with setting interrupt coalescing timer
 448  * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
 449  *
 450  * default interrupt coalescing timer is 64 x 32 = 2048 usecs
 451  * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
 452  */
 453 #define IWL_HOST_INT_TIMEOUT_MAX        (0xFF)
 454 #define IWL_HOST_INT_TIMEOUT_DEF        (0x40)
 455 #define IWL_HOST_INT_TIMEOUT_MIN        (0x0)
 456 #define IWL_HOST_INT_CALIB_TIMEOUT_MAX  (0xFF)
 457 #define IWL_HOST_INT_CALIB_TIMEOUT_DEF  (0x10)
 458 #define IWL_HOST_INT_CALIB_TIMEOUT_MIN  (0x0)
 459
 460 #endif /* !__iwl_csr_h__ */