drivers/media/dvb/frontends/it913x-fe.h

   1 /*
   2  *  Driver for it913x Frontend
   3  *
   4  *
   5  *  This program is free software; you can redistribute it and/or modify
   6  *  it under the terms of the GNU General Public License as published by
   7  *  the Free Software Foundation; either version 2 of the License, or
   8  *  (at your option) any later version.
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  19  */
  20
  21 #ifndef IT913X_FE_H
  22 #define IT913X_FE_H
  23
  24 #include <linux/dvb/frontend.h>
  25 #include "dvb_frontend.h"
  26 #if defined(CONFIG_DVB_IT913X_FE) || (defined(CONFIG_DVB_IT913X_FE_MODULE) && \
  27 defined(MODULE))
  28 extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
  29                         u8 i2c_addr, u8 adf, u8 type);
  30 #else
  31 static inline struct dvb_frontend *it913x_fe_attach(
  32                 struct i2c_adapter *i2c_adap,   u8 i2c_addr, u8 adf, u8 type)
  33 {
  34         printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
  35         return NULL;
  36 }
  37 #endif /* CONFIG_IT913X_FE */
  38 #define I2C_BASE_ADDR           0x10
  39 #define DEV_0                   0x0
  40 #define DEV_1                   0x10
  41 #define PRO_LINK                0x0
  42 #define PRO_DMOD                0x1
  43 #define DEV_0_DMOD              (PRO_DMOD << 0x7)
  44 #define DEV_1_DMOD              (DEV_0_DMOD | DEV_1)
  45 #define CHIP2_I2C_ADDR          0x3a
  46
  47 #define AFE_MEM0                0xfb24
  48
  49 #define MP2_SW_RST              0xf99d
  50 #define MP2IF2_SW_RST           0xf9a4
  51
  52 #define PADODPU                 0xd827
  53 #define THIRDODPU               0xd828
  54 #define AGC_O_D                 0xd829
  55
  56 #define EP0_TX_EN               0xdd11
  57 #define EP0_TX_NAK              0xdd13
  58 #define EP4_TX_LEN_LSB          0xdd88
  59 #define EP4_TX_LEN_MSB          0xdd89
  60 #define EP4_MAX_PKT             0xdd0c
  61 #define EP5_TX_LEN_LSB          0xdd8a
  62 #define EP5_TX_LEN_MSB          0xdd8b
  63 #define EP5_MAX_PKT             0xdd0d
  64
  65 #define IO_MUX_POWER_CLK        0xd800
  66 #define CLK_O_EN                0xd81a
  67 #define I2C_CLK                 0xf103
  68 #define I2C_CLK_100             0x7
  69 #define I2C_CLK_400             0x1a
  70
  71 #define D_TPSD_LOCK             0xf5a9
  72 #define MP2IF2_EN               0xf9a3
  73 #define MP2IF_SERIAL            0xf985
  74 #define TSIS_ENABLE             0xf9cd
  75 #define MP2IF2_HALF_PSB         0xf9a5
  76 #define MP2IF_STOP_EN           0xf9b5
  77 #define MPEG_FULL_SPEED         0xf990
  78 #define TOP_HOSTB_SER_MODE      0xd91c
  79
  80 #define PID_RST                 0xf992
  81 #define PID_EN                  0xf993
  82 #define PID_INX_EN              0xf994
  83 #define PID_INX                 0xf995
  84 #define PID_LSB                 0xf996
  85 #define PID_MSB                 0xf997
  86
  87 #define MP2IF_MPEG_PAR_MODE     0xf986
  88 #define DCA_UPPER_CHIP          0xf731
  89 #define DCA_LOWER_CHIP          0xf732
  90 #define DCA_PLATCH              0xf730
  91 #define DCA_FPGA_LATCH          0xf778
  92 #define DCA_STAND_ALONE         0xf73c
  93 #define DCA_ENABLE              0xf776
  94
  95 #define DVBT_INTEN              0xf41f
  96 #define DVBT_ENABLE             0xf41a
  97 #define HOSTB_DCA_LOWER         0xd91f
  98 #define HOSTB_MPEG_PAR_MODE     0xd91b
  99 #define HOSTB_MPEG_SER_MODE     0xd91c
 100 #define HOSTB_MPEG_SER_DO7      0xd91d
 101 #define HOSTB_DCA_UPPER         0xd91e
 102 #define PADMISCDR2              0xd830
 103 #define PADMISCDR4              0xd831
 104 #define PADMISCDR8              0xd832
 105 #define PADMISCDRSR             0xd833
 106 #define LOCK3_OUT               0xd8fd
 107
 108 #define GPIOH1_O                0xd8af
 109 #define GPIOH1_EN               0xd8b0
 110 #define GPIOH1_ON               0xd8b1
 111 #define GPIOH3_O                0xd8b3
 112 #define GPIOH3_EN               0xd8b4
 113 #define GPIOH3_ON               0xd8b5
 114 #define GPIOH5_O                0xd8bb
 115 #define GPIOH5_EN               0xd8bc
 116 #define GPIOH5_ON               0xd8bd
 117
 118 #define AFE_MEM0                0xfb24
 119
 120 #define REG_TPSD_TX_MODE        0xf900
 121 #define REG_TPSD_GI             0xf901
 122 #define REG_TPSD_HIER           0xf902
 123 #define REG_TPSD_CONST          0xf903
 124 #define REG_BW                  0xf904
 125 #define REG_PRIV                0xf905
 126 #define REG_TPSD_HP_CODE        0xf906
 127 #define REG_TPSD_LP_CODE        0xf907
 128
 129 #define MP2IF_SYNC_LK           0xf999
 130 #define ADC_FREQ                0xf1cd
 131
 132 #define TRIGGER_OFSM            0x0000
 133 /* COEFF Registers start at 0x0001 to 0x0020 */
 134 #define COEFF_1_2048            0x0001
 135 #define XTAL_CLK                0x0025
 136 #define BFS_FCW                 0x0029
 137 #define TPSD_LOCK               0x003c
 138 #define TRAINING_MODE           0x0040
 139 #define ADC_X_2                 0x0045
 140 #define TUNER_ID                0x0046
 141 #define EMPTY_CHANNEL_STATUS    0x0047
 142 #define SIGNAL_LEVEL            0x0048
 143 #define SIGNAL_QUALITY          0x0049
 144 #define EST_SIGNAL_LEVEL        0x004a
 145 #define FREE_BAND               0x004b
 146 #define SUSPEND_FLAG            0x004c
 147 /* Build in tuners */
 148 #define IT9137 0x38
 149
 150 enum {
 151         CMD_DEMOD_READ = 0,
 152         CMD_DEMOD_WRITE,
 153         CMD_TUNER_READ,
 154         CMD_TUNER_WRITE,
 155         CMD_REG_EEPROM_READ,
 156         CMD_REG_EEPROM_WRITE,
 157         CMD_DATA_READ,
 158         CMD_VAR_READ = 8,
 159         CMD_VAR_WRITE,
 160         CMD_PLATFORM_GET,
 161         CMD_PLATFORM_SET,
 162         CMD_IP_CACHE,
 163         CMD_IP_ADD,
 164         CMD_IP_REMOVE,
 165         CMD_PID_ADD,
 166         CMD_PID_REMOVE,
 167         CMD_SIPSI_GET,
 168         CMD_SIPSI_MPE_RESET,
 169         CMD_H_PID_ADD = 0x15,
 170         CMD_H_PID_REMOVE,
 171         CMD_ABORT,
 172         CMD_IR_GET,
 173         CMD_IR_SET,
 174         CMD_FW_DOWNLOAD = 0x21,
 175         CMD_QUERYINFO,
 176         CMD_BOOT,
 177         CMD_FW_DOWNLOAD_BEGIN,
 178         CMD_FW_DOWNLOAD_END,
 179         CMD_RUN_CODE,
 180         CMD_SCATTER_READ = 0x28,
 181         CMD_SCATTER_WRITE,
 182         CMD_GENERIC_READ,
 183         CMD_GENERIC_WRITE
 184 };
 185
 186 enum {
 187         READ_LONG,
 188         WRITE_LONG,
 189         READ_SHORT,
 190         WRITE_SHORT,
 191         READ_DATA,
 192         WRITE_DATA,
 193         WRITE_CMD,
 194 };
 195
 196 #endif /* IT913X_FE_H */