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usb: gadget: r8a66597-udc: use devm_clk_get() to get clock
[linux-2.6/btrfs-unstable.git] / drivers / tty / synclinkmp.c
blob53ba8537de8d2ad5d1ab24c73d809ddef4dcf2e4
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276 #endif
277
278 } SLMP_INFO;
279
280 #define MGSL_MAGIC 0x5401
281
282 /*
283 * define serial signal status change macros
284 */
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290 /* Common Register macros */
291 #define LPR 0x00
292 #define PABR0 0x02
293 #define PABR1 0x03
294 #define WCRL 0x04
295 #define WCRM 0x05
296 #define WCRH 0x06
297 #define DPCR 0x08
298 #define DMER 0x09
299 #define ISR0 0x10
300 #define ISR1 0x11
301 #define ISR2 0x12
302 #define IER0 0x14
303 #define IER1 0x15
304 #define IER2 0x16
305 #define ITCR 0x18
306 #define INTVR 0x1a
307 #define IMVR 0x1c
308
309 /* MSCI Register macros */
310 #define TRB 0x20
311 #define TRBL 0x20
312 #define TRBH 0x21
313 #define SR0 0x22
314 #define SR1 0x23
315 #define SR2 0x24
316 #define SR3 0x25
317 #define FST 0x26
318 #define IE0 0x28
319 #define IE1 0x29
320 #define IE2 0x2a
321 #define FIE 0x2b
322 #define CMD 0x2c
323 #define MD0 0x2e
324 #define MD1 0x2f
325 #define MD2 0x30
326 #define CTL 0x31
327 #define SA0 0x32
328 #define SA1 0x33
329 #define IDL 0x34
330 #define TMC 0x35
331 #define RXS 0x36
332 #define TXS 0x37
333 #define TRC0 0x38
334 #define TRC1 0x39
335 #define RRC 0x3a
336 #define CST0 0x3c
337 #define CST1 0x3d
338
339 /* Timer Register Macros */
340 #define TCNT 0x60
341 #define TCNTL 0x60
342 #define TCNTH 0x61
343 #define TCONR 0x62
344 #define TCONRL 0x62
345 #define TCONRH 0x63
346 #define TMCS 0x64
347 #define TEPR 0x65
348
349 /* DMA Controller Register macros */
350 #define DARL 0x80
351 #define DARH 0x81
352 #define DARB 0x82
353 #define BAR 0x80
354 #define BARL 0x80
355 #define BARH 0x81
356 #define BARB 0x82
357 #define SAR 0x84
358 #define SARL 0x84
359 #define SARH 0x85
360 #define SARB 0x86
361 #define CPB 0x86
362 #define CDA 0x88
363 #define CDAL 0x88
364 #define CDAH 0x89
365 #define EDA 0x8a
366 #define EDAL 0x8a
367 #define EDAH 0x8b
368 #define BFL 0x8c
369 #define BFLL 0x8c
370 #define BFLH 0x8d
371 #define BCR 0x8e
372 #define BCRL 0x8e
373 #define BCRH 0x8f
374 #define DSR 0x90
375 #define DMR 0x91
376 #define FCT 0x93
377 #define DIR 0x94
378 #define DCMD 0x95
379
380 /* combine with timer or DMA register address */
381 #define TIMER0 0x00
382 #define TIMER1 0x08
383 #define TIMER2 0x10
384 #define TIMER3 0x18
385 #define RXDMA 0x00
386 #define TXDMA 0x20
387
388 /* SCA Command Codes */
389 #define NOOP 0x00
390 #define TXRESET 0x01
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
395 #define TXEOM 0x06
396 #define TXABORT 0x07
397 #define MPON 0x08
398 #define TXBUFCLR 0x09
399 #define RXRESET 0x11
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
407 #define CHRESET 0x21
408 #define HUNT 0x31
409
410 /* DMA command codes */
411 #define SWABORT 0x01
412 #define FEICLEAR 0x02
413
414 /* IE0 */
415 #define TXINTE BIT7
416 #define RXINTE BIT6
417 #define TXRDYE BIT1
418 #define RXRDYE BIT0
419
420 /* IE1 & SR1 */
421 #define UDRN BIT7
422 #define IDLE BIT6
423 #define SYNCD BIT4
424 #define FLGD BIT4
425 #define CCTS BIT3
426 #define CDCD BIT2
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
430 #define BRKE BIT0
431 #define IDLD BIT0
432
433 /* IE2 & SR2 */
434 #define EOM BIT7
435 #define PMP BIT6
436 #define SHRT BIT6
437 #define PE BIT5
438 #define ABT BIT5
439 #define FRME BIT4
440 #define RBIT BIT4
441 #define OVRN BIT3
442 #define CRCE BIT2
443
444
445 /*
446 * Global linked list of SyncLink devices
447 */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451
452 /*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457 static bool break_on_load = 0;
458
459 /*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463 static int ttymajor = 0;
464
465 /*
466 * Array of user specified options for ISA adapters.
467 */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488 MODULE_LICENSE("GPL");
489
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495 };
496
497
498 static struct tty_driver *serial_driver;
499
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502
503
504 /* tty callbacks */
505
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534
535 /* ioctl handlers */
536
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
551
552 static void add_device(SLMP_INFO *info);
553 static void device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
620
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627
628
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635
636 static u32 read_ahead_count = 8;
637
638 /* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649 static unsigned char dma_priority = 0x04;
650
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654
655 /*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681 #else
682 if (!info)
683 return 1;
684 #endif
685 return 0;
686 }
687
688 /**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699 {
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709 }
710
711 /* tty callbacks */
712
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739 }
740
741 /* Called when a port is opened. Init and enable port.
742 */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 /* If port is closing, signal caller to try again */
756 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
757 wait_event_interruptible_tty(tty, info->port.close_wait,
758 !(info->port.flags & ASYNC_CLOSING));
759 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
760 -EAGAIN : -ERESTARTSYS);
761 goto cleanup;
762 }
763
764 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
765
766 spin_lock_irqsave(&info->netlock, flags);
767 if (info->netcount) {
768 retval = -EBUSY;
769 spin_unlock_irqrestore(&info->netlock, flags);
770 goto cleanup;
771 }
772 info->port.count++;
773 spin_unlock_irqrestore(&info->netlock, flags);
774
775 if (info->port.count == 1) {
776 /* 1st open on this device, init hardware */
777 retval = startup(info);
778 if (retval < 0)
779 goto cleanup;
780 }
781
782 retval = block_til_ready(tty, filp, info);
783 if (retval) {
784 if (debug_level >= DEBUG_LEVEL_INFO)
785 printk("%s(%d):%s block_til_ready() returned %d\n",
786 __FILE__,__LINE__, info->device_name, retval);
787 goto cleanup;
788 }
789
790 if (debug_level >= DEBUG_LEVEL_INFO)
791 printk("%s(%d):%s open() success\n",
792 __FILE__,__LINE__, info->device_name);
793 retval = 0;
794
795 cleanup:
796 if (retval) {
797 if (tty->count == 1)
798 info->port.tty = NULL; /* tty layer will release tty struct */
799 if(info->port.count)
800 info->port.count--;
801 }
802
803 return retval;
804 }
805
806 /* Called when port is closed. Wait for remaining data to be
807 * sent. Disable port and free resources.
808 */
809 static void close(struct tty_struct *tty, struct file *filp)
810 {
811 SLMP_INFO * info = tty->driver_data;
812
813 if (sanity_check(info, tty->name, "close"))
814 return;
815
816 if (debug_level >= DEBUG_LEVEL_INFO)
817 printk("%s(%d):%s close() entry, count=%d\n",
818 __FILE__,__LINE__, info->device_name, info->port.count);
819
820 if (tty_port_close_start(&info->port, tty, filp) == 0)
821 goto cleanup;
822
823 mutex_lock(&info->port.mutex);
824 if (info->port.flags & ASYNC_INITIALIZED)
825 wait_until_sent(tty, info->timeout);
826
827 flush_buffer(tty);
828 tty_ldisc_flush(tty);
829 shutdown(info);
830 mutex_unlock(&info->port.mutex);
831
832 tty_port_close_end(&info->port, tty);
833 info->port.tty = NULL;
834 cleanup:
835 if (debug_level >= DEBUG_LEVEL_INFO)
836 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
837 tty->driver->name, info->port.count);
838 }
839
840 /* Called by tty_hangup() when a hangup is signaled.
841 * This is the same as closing all open descriptors for the port.
842 */
843 static void hangup(struct tty_struct *tty)
844 {
845 SLMP_INFO *info = tty->driver_data;
846 unsigned long flags;
847
848 if (debug_level >= DEBUG_LEVEL_INFO)
849 printk("%s(%d):%s hangup()\n",
850 __FILE__,__LINE__, info->device_name );
851
852 if (sanity_check(info, tty->name, "hangup"))
853 return;
854
855 mutex_lock(&info->port.mutex);
856 flush_buffer(tty);
857 shutdown(info);
858
859 spin_lock_irqsave(&info->port.lock, flags);
860 info->port.count = 0;
861 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
862 info->port.tty = NULL;
863 spin_unlock_irqrestore(&info->port.lock, flags);
864 mutex_unlock(&info->port.mutex);
865
866 wake_up_interruptible(&info->port.open_wait);
867 }
868
869 /* Set new termios settings
870 */
871 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
872 {
873 SLMP_INFO *info = tty->driver_data;
874 unsigned long flags;
875
876 if (debug_level >= DEBUG_LEVEL_INFO)
877 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
878 tty->driver->name );
879
880 change_params(info);
881
882 /* Handle transition to B0 status */
883 if (old_termios->c_cflag & CBAUD &&
884 !(tty->termios.c_cflag & CBAUD)) {
885 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle transition away from B0 status */
892 if (!(old_termios->c_cflag & CBAUD) &&
893 tty->termios.c_cflag & CBAUD) {
894 info->serial_signals |= SerialSignal_DTR;
895 if (!(tty->termios.c_cflag & CRTSCTS) ||
896 !test_bit(TTY_THROTTLED, &tty->flags)) {
897 info->serial_signals |= SerialSignal_RTS;
898 }
899 spin_lock_irqsave(&info->lock,flags);
900 set_signals(info);
901 spin_unlock_irqrestore(&info->lock,flags);
902 }
903
904 /* Handle turning off CRTSCTS */
905 if (old_termios->c_cflag & CRTSCTS &&
906 !(tty->termios.c_cflag & CRTSCTS)) {
907 tty->hw_stopped = 0;
908 tx_release(tty);
909 }
910 }
911
912 /* Send a block of data
913 *
914 * Arguments:
915 *
916 * tty pointer to tty information structure
917 * buf pointer to buffer containing send data
918 * count size of send data in bytes
919 *
920 * Return Value: number of characters written
921 */
922 static int write(struct tty_struct *tty,
923 const unsigned char *buf, int count)
924 {
925 int c, ret = 0;
926 SLMP_INFO *info = tty->driver_data;
927 unsigned long flags;
928
929 if (debug_level >= DEBUG_LEVEL_INFO)
930 printk("%s(%d):%s write() count=%d\n",
931 __FILE__,__LINE__,info->device_name,count);
932
933 if (sanity_check(info, tty->name, "write"))
934 goto cleanup;
935
936 if (!info->tx_buf)
937 goto cleanup;
938
939 if (info->params.mode == MGSL_MODE_HDLC) {
940 if (count > info->max_frame_size) {
941 ret = -EIO;
942 goto cleanup;
943 }
944 if (info->tx_active)
945 goto cleanup;
946 if (info->tx_count) {
947 /* send accumulated data from send_char() calls */
948 /* as frame and wait before accepting more data. */
949 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
950 goto start;
951 }
952 ret = info->tx_count = count;
953 tx_load_dma_buffer(info, buf, count);
954 goto start;
955 }
956
957 for (;;) {
958 c = min_t(int, count,
959 min(info->max_frame_size - info->tx_count - 1,
960 info->max_frame_size - info->tx_put));
961 if (c <= 0)
962 break;
963
964 memcpy(info->tx_buf + info->tx_put, buf, c);
965
966 spin_lock_irqsave(&info->lock,flags);
967 info->tx_put += c;
968 if (info->tx_put >= info->max_frame_size)
969 info->tx_put -= info->max_frame_size;
970 info->tx_count += c;
971 spin_unlock_irqrestore(&info->lock,flags);
972
973 buf += c;
974 count -= c;
975 ret += c;
976 }
977
978 if (info->params.mode == MGSL_MODE_HDLC) {
979 if (count) {
980 ret = info->tx_count = 0;
981 goto cleanup;
982 }
983 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
984 }
985 start:
986 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
987 spin_lock_irqsave(&info->lock,flags);
988 if (!info->tx_active)
989 tx_start(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991 }
992
993 cleanup:
994 if (debug_level >= DEBUG_LEVEL_INFO)
995 printk( "%s(%d):%s write() returning=%d\n",
996 __FILE__,__LINE__,info->device_name,ret);
997 return ret;
998 }
999
1000 /* Add a character to the transmit buffer.
1001 */
1002 static int put_char(struct tty_struct *tty, unsigned char ch)
1003 {
1004 SLMP_INFO *info = tty->driver_data;
1005 unsigned long flags;
1006 int ret = 0;
1007
1008 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1009 printk( "%s(%d):%s put_char(%d)\n",
1010 __FILE__,__LINE__,info->device_name,ch);
1011 }
1012
1013 if (sanity_check(info, tty->name, "put_char"))
1014 return 0;
1015
1016 if (!info->tx_buf)
1017 return 0;
1018
1019 spin_lock_irqsave(&info->lock,flags);
1020
1021 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1022 !info->tx_active ) {
1023
1024 if (info->tx_count < info->max_frame_size - 1) {
1025 info->tx_buf[info->tx_put++] = ch;
1026 if (info->tx_put >= info->max_frame_size)
1027 info->tx_put -= info->max_frame_size;
1028 info->tx_count++;
1029 ret = 1;
1030 }
1031 }
1032
1033 spin_unlock_irqrestore(&info->lock,flags);
1034 return ret;
1035 }
1036
1037 /* Send a high-priority XON/XOFF character
1038 */
1039 static void send_xchar(struct tty_struct *tty, char ch)
1040 {
1041 SLMP_INFO *info = tty->driver_data;
1042 unsigned long flags;
1043
1044 if (debug_level >= DEBUG_LEVEL_INFO)
1045 printk("%s(%d):%s send_xchar(%d)\n",
1046 __FILE__,__LINE__, info->device_name, ch );
1047
1048 if (sanity_check(info, tty->name, "send_xchar"))
1049 return;
1050
1051 info->x_char = ch;
1052 if (ch) {
1053 /* Make sure transmit interrupts are on */
1054 spin_lock_irqsave(&info->lock,flags);
1055 if (!info->tx_enabled)
1056 tx_start(info);
1057 spin_unlock_irqrestore(&info->lock,flags);
1058 }
1059 }
1060
1061 /* Wait until the transmitter is empty.
1062 */
1063 static void wait_until_sent(struct tty_struct *tty, int timeout)
1064 {
1065 SLMP_INFO * info = tty->driver_data;
1066 unsigned long orig_jiffies, char_time;
1067
1068 if (!info )
1069 return;
1070
1071 if (debug_level >= DEBUG_LEVEL_INFO)
1072 printk("%s(%d):%s wait_until_sent() entry\n",
1073 __FILE__,__LINE__, info->device_name );
1074
1075 if (sanity_check(info, tty->name, "wait_until_sent"))
1076 return;
1077
1078 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1079 goto exit;
1080
1081 orig_jiffies = jiffies;
1082
1083 /* Set check interval to 1/5 of estimated time to
1084 * send a character, and make it at least 1. The check
1085 * interval should also be less than the timeout.
1086 * Note: use tight timings here to satisfy the NIST-PCTS.
1087 */
1088
1089 if ( info->params.data_rate ) {
1090 char_time = info->timeout/(32 * 5);
1091 if (!char_time)
1092 char_time++;
1093 } else
1094 char_time = 1;
1095
1096 if (timeout)
1097 char_time = min_t(unsigned long, char_time, timeout);
1098
1099 if ( info->params.mode == MGSL_MODE_HDLC ) {
1100 while (info->tx_active) {
1101 msleep_interruptible(jiffies_to_msecs(char_time));
1102 if (signal_pending(current))
1103 break;
1104 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1105 break;
1106 }
1107 } else {
1108 /*
1109 * TODO: determine if there is something similar to USC16C32
1110 * TXSTATUS_ALL_SENT status
1111 */
1112 while ( info->tx_active && info->tx_enabled) {
1113 msleep_interruptible(jiffies_to_msecs(char_time));
1114 if (signal_pending(current))
1115 break;
1116 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1117 break;
1118 }
1119 }
1120
1121 exit:
1122 if (debug_level >= DEBUG_LEVEL_INFO)
1123 printk("%s(%d):%s wait_until_sent() exit\n",
1124 __FILE__,__LINE__, info->device_name );
1125 }
1126
1127 /* Return the count of free bytes in transmit buffer
1128 */
1129 static int write_room(struct tty_struct *tty)
1130 {
1131 SLMP_INFO *info = tty->driver_data;
1132 int ret;
1133
1134 if (sanity_check(info, tty->name, "write_room"))
1135 return 0;
1136
1137 if (info->params.mode == MGSL_MODE_HDLC) {
1138 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1139 } else {
1140 ret = info->max_frame_size - info->tx_count - 1;
1141 if (ret < 0)
1142 ret = 0;
1143 }
1144
1145 if (debug_level >= DEBUG_LEVEL_INFO)
1146 printk("%s(%d):%s write_room()=%d\n",
1147 __FILE__, __LINE__, info->device_name, ret);
1148
1149 return ret;
1150 }
1151
1152 /* enable transmitter and send remaining buffered characters
1153 */
1154 static void flush_chars(struct tty_struct *tty)
1155 {
1156 SLMP_INFO *info = tty->driver_data;
1157 unsigned long flags;
1158
1159 if ( debug_level >= DEBUG_LEVEL_INFO )
1160 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1161 __FILE__,__LINE__,info->device_name,info->tx_count);
1162
1163 if (sanity_check(info, tty->name, "flush_chars"))
1164 return;
1165
1166 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1167 !info->tx_buf)
1168 return;
1169
1170 if ( debug_level >= DEBUG_LEVEL_INFO )
1171 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1172 __FILE__,__LINE__,info->device_name );
1173
1174 spin_lock_irqsave(&info->lock,flags);
1175
1176 if (!info->tx_active) {
1177 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1178 info->tx_count ) {
1179 /* operating in synchronous (frame oriented) mode */
1180 /* copy data from circular tx_buf to */
1181 /* transmit DMA buffer. */
1182 tx_load_dma_buffer(info,
1183 info->tx_buf,info->tx_count);
1184 }
1185 tx_start(info);
1186 }
1187
1188 spin_unlock_irqrestore(&info->lock,flags);
1189 }
1190
1191 /* Discard all data in the send buffer
1192 */
1193 static void flush_buffer(struct tty_struct *tty)
1194 {
1195 SLMP_INFO *info = tty->driver_data;
1196 unsigned long flags;
1197
1198 if (debug_level >= DEBUG_LEVEL_INFO)
1199 printk("%s(%d):%s flush_buffer() entry\n",
1200 __FILE__,__LINE__, info->device_name );
1201
1202 if (sanity_check(info, tty->name, "flush_buffer"))
1203 return;
1204
1205 spin_lock_irqsave(&info->lock,flags);
1206 info->tx_count = info->tx_put = info->tx_get = 0;
1207 del_timer(&info->tx_timer);
1208 spin_unlock_irqrestore(&info->lock,flags);
1209
1210 tty_wakeup(tty);
1211 }
1212
1213 /* throttle (stop) transmitter
1214 */
1215 static void tx_hold(struct tty_struct *tty)
1216 {
1217 SLMP_INFO *info = tty->driver_data;
1218 unsigned long flags;
1219
1220 if (sanity_check(info, tty->name, "tx_hold"))
1221 return;
1222
1223 if ( debug_level >= DEBUG_LEVEL_INFO )
1224 printk("%s(%d):%s tx_hold()\n",
1225 __FILE__,__LINE__,info->device_name);
1226
1227 spin_lock_irqsave(&info->lock,flags);
1228 if (info->tx_enabled)
1229 tx_stop(info);
1230 spin_unlock_irqrestore(&info->lock,flags);
1231 }
1232
1233 /* release (start) transmitter
1234 */
1235 static void tx_release(struct tty_struct *tty)
1236 {
1237 SLMP_INFO *info = tty->driver_data;
1238 unsigned long flags;
1239
1240 if (sanity_check(info, tty->name, "tx_release"))
1241 return;
1242
1243 if ( debug_level >= DEBUG_LEVEL_INFO )
1244 printk("%s(%d):%s tx_release()\n",
1245 __FILE__,__LINE__,info->device_name);
1246
1247 spin_lock_irqsave(&info->lock,flags);
1248 if (!info->tx_enabled)
1249 tx_start(info);
1250 spin_unlock_irqrestore(&info->lock,flags);
1251 }
1252
1253 /* Service an IOCTL request
1254 *
1255 * Arguments:
1256 *
1257 * tty pointer to tty instance data
1258 * cmd IOCTL command code
1259 * arg command argument/context
1260 *
1261 * Return Value: 0 if success, otherwise error code
1262 */
1263 static int ioctl(struct tty_struct *tty,
1264 unsigned int cmd, unsigned long arg)
1265 {
1266 SLMP_INFO *info = tty->driver_data;
1267 void __user *argp = (void __user *)arg;
1268
1269 if (debug_level >= DEBUG_LEVEL_INFO)
1270 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1271 info->device_name, cmd );
1272
1273 if (sanity_check(info, tty->name, "ioctl"))
1274 return -ENODEV;
1275
1276 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1277 (cmd != TIOCMIWAIT)) {
1278 if (tty->flags & (1 << TTY_IO_ERROR))
1279 return -EIO;
1280 }
1281
1282 switch (cmd) {
1283 case MGSL_IOCGPARAMS:
1284 return get_params(info, argp);
1285 case MGSL_IOCSPARAMS:
1286 return set_params(info, argp);
1287 case MGSL_IOCGTXIDLE:
1288 return get_txidle(info, argp);
1289 case MGSL_IOCSTXIDLE:
1290 return set_txidle(info, (int)arg);
1291 case MGSL_IOCTXENABLE:
1292 return tx_enable(info, (int)arg);
1293 case MGSL_IOCRXENABLE:
1294 return rx_enable(info, (int)arg);
1295 case MGSL_IOCTXABORT:
1296 return tx_abort(info);
1297 case MGSL_IOCGSTATS:
1298 return get_stats(info, argp);
1299 case MGSL_IOCWAITEVENT:
1300 return wait_mgsl_event(info, argp);
1301 case MGSL_IOCLOOPTXDONE:
1302 return 0; // TODO: Not supported, need to document
1303 /* Wait for modem input (DCD,RI,DSR,CTS) change
1304 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1305 */
1306 case TIOCMIWAIT:
1307 return modem_input_wait(info,(int)arg);
1308
1309 /*
1310 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1311 * Return: write counters to the user passed counter struct
1312 * NB: both 1->0 and 0->1 transitions are counted except for
1313 * RI where only 0->1 is counted.
1314 */
1315 default:
1316 return -ENOIOCTLCMD;
1317 }
1318 return 0;
1319 }
1320
1321 static int get_icount(struct tty_struct *tty,
1322 struct serial_icounter_struct *icount)
1323 {
1324 SLMP_INFO *info = tty->driver_data;
1325 struct mgsl_icount cnow; /* kernel counter temps */
1326 unsigned long flags;
1327
1328 spin_lock_irqsave(&info->lock,flags);
1329 cnow = info->icount;
1330 spin_unlock_irqrestore(&info->lock,flags);
1331
1332 icount->cts = cnow.cts;
1333 icount->dsr = cnow.dsr;
1334 icount->rng = cnow.rng;
1335 icount->dcd = cnow.dcd;
1336 icount->rx = cnow.rx;
1337 icount->tx = cnow.tx;
1338 icount->frame = cnow.frame;
1339 icount->overrun = cnow.overrun;
1340 icount->parity = cnow.parity;
1341 icount->brk = cnow.brk;
1342 icount->buf_overrun = cnow.buf_overrun;
1343
1344 return 0;
1345 }
1346
1347 /*
1348 * /proc fs routines....
1349 */
1350
1351 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1352 {
1353 char stat_buf[30];
1354 unsigned long flags;
1355
1356 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1357 "\tIRQ=%d MaxFrameSize=%u\n",
1358 info->device_name,
1359 info->phys_sca_base,
1360 info->phys_memory_base,
1361 info->phys_statctrl_base,
1362 info->phys_lcr_base,
1363 info->irq_level,
1364 info->max_frame_size );
1365
1366 /* output current serial signal states */
1367 spin_lock_irqsave(&info->lock,flags);
1368 get_signals(info);
1369 spin_unlock_irqrestore(&info->lock,flags);
1370
1371 stat_buf[0] = 0;
1372 stat_buf[1] = 0;
1373 if (info->serial_signals & SerialSignal_RTS)
1374 strcat(stat_buf, "|RTS");
1375 if (info->serial_signals & SerialSignal_CTS)
1376 strcat(stat_buf, "|CTS");
1377 if (info->serial_signals & SerialSignal_DTR)
1378 strcat(stat_buf, "|DTR");
1379 if (info->serial_signals & SerialSignal_DSR)
1380 strcat(stat_buf, "|DSR");
1381 if (info->serial_signals & SerialSignal_DCD)
1382 strcat(stat_buf, "|CD");
1383 if (info->serial_signals & SerialSignal_RI)
1384 strcat(stat_buf, "|RI");
1385
1386 if (info->params.mode == MGSL_MODE_HDLC) {
1387 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1388 info->icount.txok, info->icount.rxok);
1389 if (info->icount.txunder)
1390 seq_printf(m, " txunder:%d", info->icount.txunder);
1391 if (info->icount.txabort)
1392 seq_printf(m, " txabort:%d", info->icount.txabort);
1393 if (info->icount.rxshort)
1394 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1395 if (info->icount.rxlong)
1396 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1397 if (info->icount.rxover)
1398 seq_printf(m, " rxover:%d", info->icount.rxover);
1399 if (info->icount.rxcrc)
1400 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1401 } else {
1402 seq_printf(m, "\tASYNC tx:%d rx:%d",
1403 info->icount.tx, info->icount.rx);
1404 if (info->icount.frame)
1405 seq_printf(m, " fe:%d", info->icount.frame);
1406 if (info->icount.parity)
1407 seq_printf(m, " pe:%d", info->icount.parity);
1408 if (info->icount.brk)
1409 seq_printf(m, " brk:%d", info->icount.brk);
1410 if (info->icount.overrun)
1411 seq_printf(m, " oe:%d", info->icount.overrun);
1412 }
1413
1414 /* Append serial signal status to end */
1415 seq_printf(m, " %s\n", stat_buf+1);
1416
1417 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1418 info->tx_active,info->bh_requested,info->bh_running,
1419 info->pending_bh);
1420 }
1421
1422 /* Called to print information about devices
1423 */
1424 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1425 {
1426 SLMP_INFO *info;
1427
1428 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1429
1430 info = synclinkmp_device_list;
1431 while( info ) {
1432 line_info(m, info);
1433 info = info->next_device;
1434 }
1435 return 0;
1436 }
1437
1438 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1439 {
1440 return single_open(file, synclinkmp_proc_show, NULL);
1441 }
1442
1443 static const struct file_operations synclinkmp_proc_fops = {
1444 .owner = THIS_MODULE,
1445 .open = synclinkmp_proc_open,
1446 .read = seq_read,
1447 .llseek = seq_lseek,
1448 .release = single_release,
1449 };
1450
1451 /* Return the count of bytes in transmit buffer
1452 */
1453 static int chars_in_buffer(struct tty_struct *tty)
1454 {
1455 SLMP_INFO *info = tty->driver_data;
1456
1457 if (sanity_check(info, tty->name, "chars_in_buffer"))
1458 return 0;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s chars_in_buffer()=%d\n",
1462 __FILE__, __LINE__, info->device_name, info->tx_count);
1463
1464 return info->tx_count;
1465 }
1466
1467 /* Signal remote device to throttle send data (our receive data)
1468 */
1469 static void throttle(struct tty_struct * tty)
1470 {
1471 SLMP_INFO *info = tty->driver_data;
1472 unsigned long flags;
1473
1474 if (debug_level >= DEBUG_LEVEL_INFO)
1475 printk("%s(%d):%s throttle() entry\n",
1476 __FILE__,__LINE__, info->device_name );
1477
1478 if (sanity_check(info, tty->name, "throttle"))
1479 return;
1480
1481 if (I_IXOFF(tty))
1482 send_xchar(tty, STOP_CHAR(tty));
1483
1484 if (tty->termios.c_cflag & CRTSCTS) {
1485 spin_lock_irqsave(&info->lock,flags);
1486 info->serial_signals &= ~SerialSignal_RTS;
1487 set_signals(info);
1488 spin_unlock_irqrestore(&info->lock,flags);
1489 }
1490 }
1491
1492 /* Signal remote device to stop throttling send data (our receive data)
1493 */
1494 static void unthrottle(struct tty_struct * tty)
1495 {
1496 SLMP_INFO *info = tty->driver_data;
1497 unsigned long flags;
1498
1499 if (debug_level >= DEBUG_LEVEL_INFO)
1500 printk("%s(%d):%s unthrottle() entry\n",
1501 __FILE__,__LINE__, info->device_name );
1502
1503 if (sanity_check(info, tty->name, "unthrottle"))
1504 return;
1505
1506 if (I_IXOFF(tty)) {
1507 if (info->x_char)
1508 info->x_char = 0;
1509 else
1510 send_xchar(tty, START_CHAR(tty));
1511 }
1512
1513 if (tty->termios.c_cflag & CRTSCTS) {
1514 spin_lock_irqsave(&info->lock,flags);
1515 info->serial_signals |= SerialSignal_RTS;
1516 set_signals(info);
1517 spin_unlock_irqrestore(&info->lock,flags);
1518 }
1519 }
1520
1521 /* set or clear transmit break condition
1522 * break_state -1=set break condition, 0=clear
1523 */
1524 static int set_break(struct tty_struct *tty, int break_state)
1525 {
1526 unsigned char RegValue;
1527 SLMP_INFO * info = tty->driver_data;
1528 unsigned long flags;
1529
1530 if (debug_level >= DEBUG_LEVEL_INFO)
1531 printk("%s(%d):%s set_break(%d)\n",
1532 __FILE__,__LINE__, info->device_name, break_state);
1533
1534 if (sanity_check(info, tty->name, "set_break"))
1535 return -EINVAL;
1536
1537 spin_lock_irqsave(&info->lock,flags);
1538 RegValue = read_reg(info, CTL);
1539 if (break_state == -1)
1540 RegValue |= BIT3;
1541 else
1542 RegValue &= ~BIT3;
1543 write_reg(info, CTL, RegValue);
1544 spin_unlock_irqrestore(&info->lock,flags);
1545 return 0;
1546 }
1547
1548 #if SYNCLINK_GENERIC_HDLC
1549
1550 /**
1551 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1552 * set encoding and frame check sequence (FCS) options
1553 *
1554 * dev pointer to network device structure
1555 * encoding serial encoding setting
1556 * parity FCS setting
1557 *
1558 * returns 0 if success, otherwise error code
1559 */
1560 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1561 unsigned short parity)
1562 {
1563 SLMP_INFO *info = dev_to_port(dev);
1564 unsigned char new_encoding;
1565 unsigned short new_crctype;
1566
1567 /* return error if TTY interface open */
1568 if (info->port.count)
1569 return -EBUSY;
1570
1571 switch (encoding)
1572 {
1573 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1574 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1575 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1576 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1577 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1578 default: return -EINVAL;
1579 }
1580
1581 switch (parity)
1582 {
1583 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1584 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1585 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1586 default: return -EINVAL;
1587 }
1588
1589 info->params.encoding = new_encoding;
1590 info->params.crc_type = new_crctype;
1591
1592 /* if network interface up, reprogram hardware */
1593 if (info->netcount)
1594 program_hw(info);
1595
1596 return 0;
1597 }
1598
1599 /**
1600 * called by generic HDLC layer to send frame
1601 *
1602 * skb socket buffer containing HDLC frame
1603 * dev pointer to network device structure
1604 */
1605 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1606 struct net_device *dev)
1607 {
1608 SLMP_INFO *info = dev_to_port(dev);
1609 unsigned long flags;
1610
1611 if (debug_level >= DEBUG_LEVEL_INFO)
1612 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1613
1614 /* stop sending until this frame completes */
1615 netif_stop_queue(dev);
1616
1617 /* copy data to device buffers */
1618 info->tx_count = skb->len;
1619 tx_load_dma_buffer(info, skb->data, skb->len);
1620
1621 /* update network statistics */
1622 dev->stats.tx_packets++;
1623 dev->stats.tx_bytes += skb->len;
1624
1625 /* done with socket buffer, so free it */
1626 dev_kfree_skb(skb);
1627
1628 /* save start time for transmit timeout detection */
1629 dev->trans_start = jiffies;
1630
1631 /* start hardware transmitter if necessary */
1632 spin_lock_irqsave(&info->lock,flags);
1633 if (!info->tx_active)
1634 tx_start(info);
1635 spin_unlock_irqrestore(&info->lock,flags);
1636
1637 return NETDEV_TX_OK;
1638 }
1639
1640 /**
1641 * called by network layer when interface enabled
1642 * claim resources and initialize hardware
1643 *
1644 * dev pointer to network device structure
1645 *
1646 * returns 0 if success, otherwise error code
1647 */
1648 static int hdlcdev_open(struct net_device *dev)
1649 {
1650 SLMP_INFO *info = dev_to_port(dev);
1651 int rc;
1652 unsigned long flags;
1653
1654 if (debug_level >= DEBUG_LEVEL_INFO)
1655 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1656
1657 /* generic HDLC layer open processing */
1658 if ((rc = hdlc_open(dev)))
1659 return rc;
1660
1661 /* arbitrate between network and tty opens */
1662 spin_lock_irqsave(&info->netlock, flags);
1663 if (info->port.count != 0 || info->netcount != 0) {
1664 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1665 spin_unlock_irqrestore(&info->netlock, flags);
1666 return -EBUSY;
1667 }
1668 info->netcount=1;
1669 spin_unlock_irqrestore(&info->netlock, flags);
1670
1671 /* claim resources and init adapter */
1672 if ((rc = startup(info)) != 0) {
1673 spin_lock_irqsave(&info->netlock, flags);
1674 info->netcount=0;
1675 spin_unlock_irqrestore(&info->netlock, flags);
1676 return rc;
1677 }
1678
1679 /* assert RTS and DTR, apply hardware settings */
1680 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1681 program_hw(info);
1682
1683 /* enable network layer transmit */
1684 dev->trans_start = jiffies;
1685 netif_start_queue(dev);
1686
1687 /* inform generic HDLC layer of current DCD status */
1688 spin_lock_irqsave(&info->lock, flags);
1689 get_signals(info);
1690 spin_unlock_irqrestore(&info->lock, flags);
1691 if (info->serial_signals & SerialSignal_DCD)
1692 netif_carrier_on(dev);
1693 else
1694 netif_carrier_off(dev);
1695 return 0;
1696 }
1697
1698 /**
1699 * called by network layer when interface is disabled
1700 * shutdown hardware and release resources
1701 *
1702 * dev pointer to network device structure
1703 *
1704 * returns 0 if success, otherwise error code
1705 */
1706 static int hdlcdev_close(struct net_device *dev)
1707 {
1708 SLMP_INFO *info = dev_to_port(dev);
1709 unsigned long flags;
1710
1711 if (debug_level >= DEBUG_LEVEL_INFO)
1712 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1713
1714 netif_stop_queue(dev);
1715
1716 /* shutdown adapter and release resources */
1717 shutdown(info);
1718
1719 hdlc_close(dev);
1720
1721 spin_lock_irqsave(&info->netlock, flags);
1722 info->netcount=0;
1723 spin_unlock_irqrestore(&info->netlock, flags);
1724
1725 return 0;
1726 }
1727
1728 /**
1729 * called by network layer to process IOCTL call to network device
1730 *
1731 * dev pointer to network device structure
1732 * ifr pointer to network interface request structure
1733 * cmd IOCTL command code
1734 *
1735 * returns 0 if success, otherwise error code
1736 */
1737 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1738 {
1739 const size_t size = sizeof(sync_serial_settings);
1740 sync_serial_settings new_line;
1741 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1742 SLMP_INFO *info = dev_to_port(dev);
1743 unsigned int flags;
1744
1745 if (debug_level >= DEBUG_LEVEL_INFO)
1746 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1747
1748 /* return error if TTY interface open */
1749 if (info->port.count)
1750 return -EBUSY;
1751
1752 if (cmd != SIOCWANDEV)
1753 return hdlc_ioctl(dev, ifr, cmd);
1754
1755 switch(ifr->ifr_settings.type) {
1756 case IF_GET_IFACE: /* return current sync_serial_settings */
1757
1758 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1759 if (ifr->ifr_settings.size < size) {
1760 ifr->ifr_settings.size = size; /* data size wanted */
1761 return -ENOBUFS;
1762 }
1763
1764 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1765 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1766 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1767 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1768
1769 memset(&new_line, 0, sizeof(new_line));
1770 switch (flags){
1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1775 default: new_line.clock_type = CLOCK_DEFAULT;
1776 }
1777
1778 new_line.clock_rate = info->params.clock_speed;
1779 new_line.loopback = info->params.loopback ? 1:0;
1780
1781 if (copy_to_user(line, &new_line, size))
1782 return -EFAULT;
1783 return 0;
1784
1785 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1786
1787 if(!capable(CAP_NET_ADMIN))
1788 return -EPERM;
1789 if (copy_from_user(&new_line, line, size))
1790 return -EFAULT;
1791
1792 switch (new_line.clock_type)
1793 {
1794 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1795 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1796 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1797 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1798 case CLOCK_DEFAULT: flags = info->params.flags &
1799 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1800 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1801 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1802 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1803 default: return -EINVAL;
1804 }
1805
1806 if (new_line.loopback != 0 && new_line.loopback != 1)
1807 return -EINVAL;
1808
1809 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1810 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1811 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1812 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1813 info->params.flags |= flags;
1814
1815 info->params.loopback = new_line.loopback;
1816
1817 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1818 info->params.clock_speed = new_line.clock_rate;
1819 else
1820 info->params.clock_speed = 0;
1821
1822 /* if network interface up, reprogram hardware */
1823 if (info->netcount)
1824 program_hw(info);
1825 return 0;
1826
1827 default:
1828 return hdlc_ioctl(dev, ifr, cmd);
1829 }
1830 }
1831
1832 /**
1833 * called by network layer when transmit timeout is detected
1834 *
1835 * dev pointer to network device structure
1836 */
1837 static void hdlcdev_tx_timeout(struct net_device *dev)
1838 {
1839 SLMP_INFO *info = dev_to_port(dev);
1840 unsigned long flags;
1841
1842 if (debug_level >= DEBUG_LEVEL_INFO)
1843 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1844
1845 dev->stats.tx_errors++;
1846 dev->stats.tx_aborted_errors++;
1847
1848 spin_lock_irqsave(&info->lock,flags);
1849 tx_stop(info);
1850 spin_unlock_irqrestore(&info->lock,flags);
1851
1852 netif_wake_queue(dev);
1853 }
1854
1855 /**
1856 * called by device driver when transmit completes
1857 * reenable network layer transmit if stopped
1858 *
1859 * info pointer to device instance information
1860 */
1861 static void hdlcdev_tx_done(SLMP_INFO *info)
1862 {
1863 if (netif_queue_stopped(info->netdev))
1864 netif_wake_queue(info->netdev);
1865 }
1866
1867 /**
1868 * called by device driver when frame received
1869 * pass frame to network layer
1870 *
1871 * info pointer to device instance information
1872 * buf pointer to buffer contianing frame data
1873 * size count of data bytes in buf
1874 */
1875 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1876 {
1877 struct sk_buff *skb = dev_alloc_skb(size);
1878 struct net_device *dev = info->netdev;
1879
1880 if (debug_level >= DEBUG_LEVEL_INFO)
1881 printk("hdlcdev_rx(%s)\n",dev->name);
1882
1883 if (skb == NULL) {
1884 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1885 dev->name);
1886 dev->stats.rx_dropped++;
1887 return;
1888 }
1889
1890 memcpy(skb_put(skb, size), buf, size);
1891
1892 skb->protocol = hdlc_type_trans(skb, dev);
1893
1894 dev->stats.rx_packets++;
1895 dev->stats.rx_bytes += size;
1896
1897 netif_rx(skb);
1898 }
1899
1900 static const struct net_device_ops hdlcdev_ops = {
1901 .ndo_open = hdlcdev_open,
1902 .ndo_stop = hdlcdev_close,
1903 .ndo_change_mtu = hdlc_change_mtu,
1904 .ndo_start_xmit = hdlc_start_xmit,
1905 .ndo_do_ioctl = hdlcdev_ioctl,
1906 .ndo_tx_timeout = hdlcdev_tx_timeout,
1907 };
1908
1909 /**
1910 * called by device driver when adding device instance
1911 * do generic HDLC initialization
1912 *
1913 * info pointer to device instance information
1914 *
1915 * returns 0 if success, otherwise error code
1916 */
1917 static int hdlcdev_init(SLMP_INFO *info)
1918 {
1919 int rc;
1920 struct net_device *dev;
1921 hdlc_device *hdlc;
1922
1923 /* allocate and initialize network and HDLC layer objects */
1924
1925 if (!(dev = alloc_hdlcdev(info))) {
1926 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1927 return -ENOMEM;
1928 }
1929
1930 /* for network layer reporting purposes only */
1931 dev->mem_start = info->phys_sca_base;
1932 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1933 dev->irq = info->irq_level;
1934
1935 /* network layer callbacks and settings */
1936 dev->netdev_ops = &hdlcdev_ops;
1937 dev->watchdog_timeo = 10 * HZ;
1938 dev->tx_queue_len = 50;
1939
1940 /* generic HDLC layer callbacks and settings */
1941 hdlc = dev_to_hdlc(dev);
1942 hdlc->attach = hdlcdev_attach;
1943 hdlc->xmit = hdlcdev_xmit;
1944
1945 /* register objects with HDLC layer */
1946 if ((rc = register_hdlc_device(dev))) {
1947 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1948 free_netdev(dev);
1949 return rc;
1950 }
1951
1952 info->netdev = dev;
1953 return 0;
1954 }
1955
1956 /**
1957 * called by device driver when removing device instance
1958 * do generic HDLC cleanup
1959 *
1960 * info pointer to device instance information
1961 */
1962 static void hdlcdev_exit(SLMP_INFO *info)
1963 {
1964 unregister_hdlc_device(info->netdev);
1965 free_netdev(info->netdev);
1966 info->netdev = NULL;
1967 }
1968
1969 #endif /* CONFIG_HDLC */
1970
1971
1972 /* Return next bottom half action to perform.
1973 * Return Value: BH action code or 0 if nothing to do.
1974 */
1975 static int bh_action(SLMP_INFO *info)
1976 {
1977 unsigned long flags;
1978 int rc = 0;
1979
1980 spin_lock_irqsave(&info->lock,flags);
1981
1982 if (info->pending_bh & BH_RECEIVE) {
1983 info->pending_bh &= ~BH_RECEIVE;
1984 rc = BH_RECEIVE;
1985 } else if (info->pending_bh & BH_TRANSMIT) {
1986 info->pending_bh &= ~BH_TRANSMIT;
1987 rc = BH_TRANSMIT;
1988 } else if (info->pending_bh & BH_STATUS) {
1989 info->pending_bh &= ~BH_STATUS;
1990 rc = BH_STATUS;
1991 }
1992
1993 if (!rc) {
1994 /* Mark BH routine as complete */
1995 info->bh_running = false;
1996 info->bh_requested = false;
1997 }
1998
1999 spin_unlock_irqrestore(&info->lock,flags);
2000
2001 return rc;
2002 }
2003
2004 /* Perform bottom half processing of work items queued by ISR.
2005 */
2006 static void bh_handler(struct work_struct *work)
2007 {
2008 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2009 int action;
2010
2011 if ( debug_level >= DEBUG_LEVEL_BH )
2012 printk( "%s(%d):%s bh_handler() entry\n",
2013 __FILE__,__LINE__,info->device_name);
2014
2015 info->bh_running = true;
2016
2017 while((action = bh_action(info)) != 0) {
2018
2019 /* Process work item */
2020 if ( debug_level >= DEBUG_LEVEL_BH )
2021 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2022 __FILE__,__LINE__,info->device_name, action);
2023
2024 switch (action) {
2025
2026 case BH_RECEIVE:
2027 bh_receive(info);
2028 break;
2029 case BH_TRANSMIT:
2030 bh_transmit(info);
2031 break;
2032 case BH_STATUS:
2033 bh_status(info);
2034 break;
2035 default:
2036 /* unknown work item ID */
2037 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2038 __FILE__,__LINE__,info->device_name,action);
2039 break;
2040 }
2041 }
2042
2043 if ( debug_level >= DEBUG_LEVEL_BH )
2044 printk( "%s(%d):%s bh_handler() exit\n",
2045 __FILE__,__LINE__,info->device_name);
2046 }
2047
2048 static void bh_receive(SLMP_INFO *info)
2049 {
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_receive()\n",
2052 __FILE__,__LINE__,info->device_name);
2053
2054 while( rx_get_frame(info) );
2055 }
2056
2057 static void bh_transmit(SLMP_INFO *info)
2058 {
2059 struct tty_struct *tty = info->port.tty;
2060
2061 if ( debug_level >= DEBUG_LEVEL_BH )
2062 printk( "%s(%d):%s bh_transmit() entry\n",
2063 __FILE__,__LINE__,info->device_name);
2064
2065 if (tty)
2066 tty_wakeup(tty);
2067 }
2068
2069 static void bh_status(SLMP_INFO *info)
2070 {
2071 if ( debug_level >= DEBUG_LEVEL_BH )
2072 printk( "%s(%d):%s bh_status() entry\n",
2073 __FILE__,__LINE__,info->device_name);
2074
2075 info->ri_chkcount = 0;
2076 info->dsr_chkcount = 0;
2077 info->dcd_chkcount = 0;
2078 info->cts_chkcount = 0;
2079 }
2080
2081 static void isr_timer(SLMP_INFO * info)
2082 {
2083 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2084
2085 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2086 write_reg(info, IER2, 0);
2087
2088 /* TMCS, Timer Control/Status Register
2089 *
2090 * 07 CMF, Compare match flag (read only) 1=match
2091 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2092 * 05 Reserved, must be 0
2093 * 04 TME, Timer Enable
2094 * 03..00 Reserved, must be 0
2095 *
2096 * 0000 0000
2097 */
2098 write_reg(info, (unsigned char)(timer + TMCS), 0);
2099
2100 info->irq_occurred = true;
2101
2102 if ( debug_level >= DEBUG_LEVEL_ISR )
2103 printk("%s(%d):%s isr_timer()\n",
2104 __FILE__,__LINE__,info->device_name);
2105 }
2106
2107 static void isr_rxint(SLMP_INFO * info)
2108 {
2109 struct tty_struct *tty = info->port.tty;
2110 struct mgsl_icount *icount = &info->icount;
2111 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2112 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2113
2114 /* clear status bits */
2115 if (status)
2116 write_reg(info, SR1, status);
2117
2118 if (status2)
2119 write_reg(info, SR2, status2);
2120
2121 if ( debug_level >= DEBUG_LEVEL_ISR )
2122 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2123 __FILE__,__LINE__,info->device_name,status,status2);
2124
2125 if (info->params.mode == MGSL_MODE_ASYNC) {
2126 if (status & BRKD) {
2127 icount->brk++;
2128
2129 /* process break detection if tty control
2130 * is not set to ignore it
2131 */
2132 if (!(status & info->ignore_status_mask1)) {
2133 if (info->read_status_mask1 & BRKD) {
2134 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2135 if (tty && (info->port.flags & ASYNC_SAK))
2136 do_SAK(tty);
2137 }
2138 }
2139 }
2140 }
2141 else {
2142 if (status & (FLGD|IDLD)) {
2143 if (status & FLGD)
2144 info->icount.exithunt++;
2145 else if (status & IDLD)
2146 info->icount.rxidle++;
2147 wake_up_interruptible(&info->event_wait_q);
2148 }
2149 }
2150
2151 if (status & CDCD) {
2152 /* simulate a common modem status change interrupt
2153 * for our handler
2154 */
2155 get_signals( info );
2156 isr_io_pin(info,
2157 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2158 }
2159 }
2160
2161 /*
2162 * handle async rx data interrupts
2163 */
2164 static void isr_rxrdy(SLMP_INFO * info)
2165 {
2166 u16 status;
2167 unsigned char DataByte;
2168 struct mgsl_icount *icount = &info->icount;
2169
2170 if ( debug_level >= DEBUG_LEVEL_ISR )
2171 printk("%s(%d):%s isr_rxrdy\n",
2172 __FILE__,__LINE__,info->device_name);
2173
2174 while((status = read_reg(info,CST0)) & BIT0)
2175 {
2176 int flag = 0;
2177 bool over = false;
2178 DataByte = read_reg(info,TRB);
2179
2180 icount->rx++;
2181
2182 if ( status & (PE + FRME + OVRN) ) {
2183 printk("%s(%d):%s rxerr=%04X\n",
2184 __FILE__,__LINE__,info->device_name,status);
2185
2186 /* update error statistics */
2187 if (status & PE)
2188 icount->parity++;
2189 else if (status & FRME)
2190 icount->frame++;
2191 else if (status & OVRN)
2192 icount->overrun++;
2193
2194 /* discard char if tty control flags say so */
2195 if (status & info->ignore_status_mask2)
2196 continue;
2197
2198 status &= info->read_status_mask2;
2199
2200 if (status & PE)
2201 flag = TTY_PARITY;
2202 else if (status & FRME)
2203 flag = TTY_FRAME;
2204 if (status & OVRN) {
2205 /* Overrun is special, since it's
2206 * reported immediately, and doesn't
2207 * affect the current character
2208 */
2209 over = true;
2210 }
2211 } /* end of if (error) */
2212
2213 tty_insert_flip_char(&info->port, DataByte, flag);
2214 if (over)
2215 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2216 }
2217
2218 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2219 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2220 __FILE__,__LINE__,info->device_name,
2221 icount->rx,icount->brk,icount->parity,
2222 icount->frame,icount->overrun);
2223 }
2224
2225 tty_flip_buffer_push(&info->port);
2226 }
2227
2228 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2229 {
2230 if ( debug_level >= DEBUG_LEVEL_ISR )
2231 printk("%s(%d):%s isr_txeom status=%02x\n",
2232 __FILE__,__LINE__,info->device_name,status);
2233
2234 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2235 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2236 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2237
2238 if (status & UDRN) {
2239 write_reg(info, CMD, TXRESET);
2240 write_reg(info, CMD, TXENABLE);
2241 } else
2242 write_reg(info, CMD, TXBUFCLR);
2243
2244 /* disable and clear tx interrupts */
2245 info->ie0_value &= ~TXRDYE;
2246 info->ie1_value &= ~(IDLE + UDRN);
2247 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2248 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2249
2250 if ( info->tx_active ) {
2251 if (info->params.mode != MGSL_MODE_ASYNC) {
2252 if (status & UDRN)
2253 info->icount.txunder++;
2254 else if (status & IDLE)
2255 info->icount.txok++;
2256 }
2257
2258 info->tx_active = false;
2259 info->tx_count = info->tx_put = info->tx_get = 0;
2260
2261 del_timer(&info->tx_timer);
2262
2263 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2264 info->serial_signals &= ~SerialSignal_RTS;
2265 info->drop_rts_on_tx_done = false;
2266 set_signals(info);
2267 }
2268
2269 #if SYNCLINK_GENERIC_HDLC
2270 if (info->netcount)
2271 hdlcdev_tx_done(info);
2272 else
2273 #endif
2274 {
2275 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2276 tx_stop(info);
2277 return;
2278 }
2279 info->pending_bh |= BH_TRANSMIT;
2280 }
2281 }
2282 }
2283
2284
2285 /*
2286 * handle tx status interrupts
2287 */
2288 static void isr_txint(SLMP_INFO * info)
2289 {
2290 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2291
2292 /* clear status bits */
2293 write_reg(info, SR1, status);
2294
2295 if ( debug_level >= DEBUG_LEVEL_ISR )
2296 printk("%s(%d):%s isr_txint status=%02x\n",
2297 __FILE__,__LINE__,info->device_name,status);
2298
2299 if (status & (UDRN + IDLE))
2300 isr_txeom(info, status);
2301
2302 if (status & CCTS) {
2303 /* simulate a common modem status change interrupt
2304 * for our handler
2305 */
2306 get_signals( info );
2307 isr_io_pin(info,
2308 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2309
2310 }
2311 }
2312
2313 /*
2314 * handle async tx data interrupts
2315 */
2316 static void isr_txrdy(SLMP_INFO * info)
2317 {
2318 if ( debug_level >= DEBUG_LEVEL_ISR )
2319 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2320 __FILE__,__LINE__,info->device_name,info->tx_count);
2321
2322 if (info->params.mode != MGSL_MODE_ASYNC) {
2323 /* disable TXRDY IRQ, enable IDLE IRQ */
2324 info->ie0_value &= ~TXRDYE;
2325 info->ie1_value |= IDLE;
2326 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2327 return;
2328 }
2329
2330 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2331 tx_stop(info);
2332 return;
2333 }
2334
2335 if ( info->tx_count )
2336 tx_load_fifo( info );
2337 else {
2338 info->tx_active = false;
2339 info->ie0_value &= ~TXRDYE;
2340 write_reg(info, IE0, info->ie0_value);
2341 }
2342
2343 if (info->tx_count < WAKEUP_CHARS)
2344 info->pending_bh |= BH_TRANSMIT;
2345 }
2346
2347 static void isr_rxdmaok(SLMP_INFO * info)
2348 {
2349 /* BIT7 = EOT (end of transfer)
2350 * BIT6 = EOM (end of message/frame)
2351 */
2352 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2353
2354 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2355 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2356
2357 if ( debug_level >= DEBUG_LEVEL_ISR )
2358 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2359 __FILE__,__LINE__,info->device_name,status);
2360
2361 info->pending_bh |= BH_RECEIVE;
2362 }
2363
2364 static void isr_rxdmaerror(SLMP_INFO * info)
2365 {
2366 /* BIT5 = BOF (buffer overflow)
2367 * BIT4 = COF (counter overflow)
2368 */
2369 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2370
2371 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2372 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2373
2374 if ( debug_level >= DEBUG_LEVEL_ISR )
2375 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2376 __FILE__,__LINE__,info->device_name,status);
2377
2378 info->rx_overflow = true;
2379 info->pending_bh |= BH_RECEIVE;
2380 }
2381
2382 static void isr_txdmaok(SLMP_INFO * info)
2383 {
2384 unsigned char status_reg1 = read_reg(info, SR1);
2385
2386 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2387 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2388 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2389
2390 if ( debug_level >= DEBUG_LEVEL_ISR )
2391 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2392 __FILE__,__LINE__,info->device_name,status_reg1);
2393
2394 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2395 write_reg16(info, TRC0, 0);
2396 info->ie0_value |= TXRDYE;
2397 write_reg(info, IE0, info->ie0_value);
2398 }
2399
2400 static void isr_txdmaerror(SLMP_INFO * info)
2401 {
2402 /* BIT5 = BOF (buffer overflow)
2403 * BIT4 = COF (counter overflow)
2404 */
2405 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2406
2407 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2408 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2412 __FILE__,__LINE__,info->device_name,status);
2413 }
2414
2415 /* handle input serial signal changes
2416 */
2417 static void isr_io_pin( SLMP_INFO *info, u16 status )
2418 {
2419 struct mgsl_icount *icount;
2420
2421 if ( debug_level >= DEBUG_LEVEL_ISR )
2422 printk("%s(%d):isr_io_pin status=%04X\n",
2423 __FILE__,__LINE__,status);
2424
2425 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2426 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2427 icount = &info->icount;
2428 /* update input line counters */
2429 if (status & MISCSTATUS_RI_LATCHED) {
2430 icount->rng++;
2431 if ( status & SerialSignal_RI )
2432 info->input_signal_events.ri_up++;
2433 else
2434 info->input_signal_events.ri_down++;
2435 }
2436 if (status & MISCSTATUS_DSR_LATCHED) {
2437 icount->dsr++;
2438 if ( status & SerialSignal_DSR )
2439 info->input_signal_events.dsr_up++;
2440 else
2441 info->input_signal_events.dsr_down++;
2442 }
2443 if (status & MISCSTATUS_DCD_LATCHED) {
2444 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2445 info->ie1_value &= ~CDCD;
2446 write_reg(info, IE1, info->ie1_value);
2447 }
2448 icount->dcd++;
2449 if (status & SerialSignal_DCD) {
2450 info->input_signal_events.dcd_up++;
2451 } else
2452 info->input_signal_events.dcd_down++;
2453 #if SYNCLINK_GENERIC_HDLC
2454 if (info->netcount) {
2455 if (status & SerialSignal_DCD)
2456 netif_carrier_on(info->netdev);
2457 else
2458 netif_carrier_off(info->netdev);
2459 }
2460 #endif
2461 }
2462 if (status & MISCSTATUS_CTS_LATCHED)
2463 {
2464 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2465 info->ie1_value &= ~CCTS;
2466 write_reg(info, IE1, info->ie1_value);
2467 }
2468 icount->cts++;
2469 if ( status & SerialSignal_CTS )
2470 info->input_signal_events.cts_up++;
2471 else
2472 info->input_signal_events.cts_down++;
2473 }
2474 wake_up_interruptible(&info->status_event_wait_q);
2475 wake_up_interruptible(&info->event_wait_q);
2476
2477 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2478 (status & MISCSTATUS_DCD_LATCHED) ) {
2479 if ( debug_level >= DEBUG_LEVEL_ISR )
2480 printk("%s CD now %s...", info->device_name,
2481 (status & SerialSignal_DCD) ? "on" : "off");
2482 if (status & SerialSignal_DCD)
2483 wake_up_interruptible(&info->port.open_wait);
2484 else {
2485 if ( debug_level >= DEBUG_LEVEL_ISR )
2486 printk("doing serial hangup...");
2487 if (info->port.tty)
2488 tty_hangup(info->port.tty);
2489 }
2490 }
2491
2492 if (tty_port_cts_enabled(&info->port) &&
2493 (status & MISCSTATUS_CTS_LATCHED) ) {
2494 if ( info->port.tty ) {
2495 if (info->port.tty->hw_stopped) {
2496 if (status & SerialSignal_CTS) {
2497 if ( debug_level >= DEBUG_LEVEL_ISR )
2498 printk("CTS tx start...");
2499 info->port.tty->hw_stopped = 0;
2500 tx_start(info);
2501 info->pending_bh |= BH_TRANSMIT;
2502 return;
2503 }
2504 } else {
2505 if (!(status & SerialSignal_CTS)) {
2506 if ( debug_level >= DEBUG_LEVEL_ISR )
2507 printk("CTS tx stop...");
2508 info->port.tty->hw_stopped = 1;
2509 tx_stop(info);
2510 }
2511 }
2512 }
2513 }
2514 }
2515
2516 info->pending_bh |= BH_STATUS;
2517 }
2518
2519 /* Interrupt service routine entry point.
2520 *
2521 * Arguments:
2522 * irq interrupt number that caused interrupt
2523 * dev_id device ID supplied during interrupt registration
2524 * regs interrupted processor context
2525 */
2526 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2527 {
2528 SLMP_INFO *info = dev_id;
2529 unsigned char status, status0, status1=0;
2530 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2531 unsigned char timerstatus0, timerstatus1=0;
2532 unsigned char shift;
2533 unsigned int i;
2534 unsigned short tmp;
2535
2536 if ( debug_level >= DEBUG_LEVEL_ISR )
2537 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2538 __FILE__, __LINE__, info->irq_level);
2539
2540 spin_lock(&info->lock);
2541
2542 for(;;) {
2543
2544 /* get status for SCA0 (ports 0-1) */
2545 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2546 status0 = (unsigned char)tmp;
2547 dmastatus0 = (unsigned char)(tmp>>8);
2548 timerstatus0 = read_reg(info, ISR2);
2549
2550 if ( debug_level >= DEBUG_LEVEL_ISR )
2551 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2552 __FILE__, __LINE__, info->device_name,
2553 status0, dmastatus0, timerstatus0);
2554
2555 if (info->port_count == 4) {
2556 /* get status for SCA1 (ports 2-3) */
2557 tmp = read_reg16(info->port_array[2], ISR0);
2558 status1 = (unsigned char)tmp;
2559 dmastatus1 = (unsigned char)(tmp>>8);
2560 timerstatus1 = read_reg(info->port_array[2], ISR2);
2561
2562 if ( debug_level >= DEBUG_LEVEL_ISR )
2563 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2564 __FILE__,__LINE__,info->device_name,
2565 status1,dmastatus1,timerstatus1);
2566 }
2567
2568 if (!status0 && !dmastatus0 && !timerstatus0 &&
2569 !status1 && !dmastatus1 && !timerstatus1)
2570 break;
2571
2572 for(i=0; i < info->port_count ; i++) {
2573 if (info->port_array[i] == NULL)
2574 continue;
2575 if (i < 2) {
2576 status = status0;
2577 dmastatus = dmastatus0;
2578 } else {
2579 status = status1;
2580 dmastatus = dmastatus1;
2581 }
2582
2583 shift = i & 1 ? 4 :0;
2584
2585 if (status & BIT0 << shift)
2586 isr_rxrdy(info->port_array[i]);
2587 if (status & BIT1 << shift)
2588 isr_txrdy(info->port_array[i]);
2589 if (status & BIT2 << shift)
2590 isr_rxint(info->port_array[i]);
2591 if (status & BIT3 << shift)
2592 isr_txint(info->port_array[i]);
2593
2594 if (dmastatus & BIT0 << shift)
2595 isr_rxdmaerror(info->port_array[i]);
2596 if (dmastatus & BIT1 << shift)
2597 isr_rxdmaok(info->port_array[i]);
2598 if (dmastatus & BIT2 << shift)
2599 isr_txdmaerror(info->port_array[i]);
2600 if (dmastatus & BIT3 << shift)
2601 isr_txdmaok(info->port_array[i]);
2602 }
2603
2604 if (timerstatus0 & (BIT5 | BIT4))
2605 isr_timer(info->port_array[0]);
2606 if (timerstatus0 & (BIT7 | BIT6))
2607 isr_timer(info->port_array[1]);
2608 if (timerstatus1 & (BIT5 | BIT4))
2609 isr_timer(info->port_array[2]);
2610 if (timerstatus1 & (BIT7 | BIT6))
2611 isr_timer(info->port_array[3]);
2612 }
2613
2614 for(i=0; i < info->port_count ; i++) {
2615 SLMP_INFO * port = info->port_array[i];
2616
2617 /* Request bottom half processing if there's something
2618 * for it to do and the bh is not already running.
2619 *
2620 * Note: startup adapter diags require interrupts.
2621 * do not request bottom half processing if the
2622 * device is not open in a normal mode.
2623 */
2624 if ( port && (port->port.count || port->netcount) &&
2625 port->pending_bh && !port->bh_running &&
2626 !port->bh_requested ) {
2627 if ( debug_level >= DEBUG_LEVEL_ISR )
2628 printk("%s(%d):%s queueing bh task.\n",
2629 __FILE__,__LINE__,port->device_name);
2630 schedule_work(&port->task);
2631 port->bh_requested = true;
2632 }
2633 }
2634
2635 spin_unlock(&info->lock);
2636
2637 if ( debug_level >= DEBUG_LEVEL_ISR )
2638 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2639 __FILE__, __LINE__, info->irq_level);
2640 return IRQ_HANDLED;
2641 }
2642
2643 /* Initialize and start device.
2644 */
2645 static int startup(SLMP_INFO * info)
2646 {
2647 if ( debug_level >= DEBUG_LEVEL_INFO )
2648 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2649
2650 if (info->port.flags & ASYNC_INITIALIZED)
2651 return 0;
2652
2653 if (!info->tx_buf) {
2654 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2655 if (!info->tx_buf) {
2656 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2657 __FILE__,__LINE__,info->device_name);
2658 return -ENOMEM;
2659 }
2660 }
2661
2662 info->pending_bh = 0;
2663
2664 memset(&info->icount, 0, sizeof(info->icount));
2665
2666 /* program hardware for current parameters */
2667 reset_port(info);
2668
2669 change_params(info);
2670
2671 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2672
2673 if (info->port.tty)
2674 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2675
2676 info->port.flags |= ASYNC_INITIALIZED;
2677
2678 return 0;
2679 }
2680
2681 /* Called by close() and hangup() to shutdown hardware
2682 */
2683 static void shutdown(SLMP_INFO * info)
2684 {
2685 unsigned long flags;
2686
2687 if (!(info->port.flags & ASYNC_INITIALIZED))
2688 return;
2689
2690 if (debug_level >= DEBUG_LEVEL_INFO)
2691 printk("%s(%d):%s synclinkmp_shutdown()\n",
2692 __FILE__,__LINE__, info->device_name );
2693
2694 /* clear status wait queue because status changes */
2695 /* can't happen after shutting down the hardware */
2696 wake_up_interruptible(&info->status_event_wait_q);
2697 wake_up_interruptible(&info->event_wait_q);
2698
2699 del_timer(&info->tx_timer);
2700 del_timer(&info->status_timer);
2701
2702 kfree(info->tx_buf);
2703 info->tx_buf = NULL;
2704
2705 spin_lock_irqsave(&info->lock,flags);
2706
2707 reset_port(info);
2708
2709 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2710 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2711 set_signals(info);
2712 }
2713
2714 spin_unlock_irqrestore(&info->lock,flags);
2715
2716 if (info->port.tty)
2717 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2718
2719 info->port.flags &= ~ASYNC_INITIALIZED;
2720 }
2721
2722 static void program_hw(SLMP_INFO *info)
2723 {
2724 unsigned long flags;
2725
2726 spin_lock_irqsave(&info->lock,flags);
2727
2728 rx_stop(info);
2729 tx_stop(info);
2730
2731 info->tx_count = info->tx_put = info->tx_get = 0;
2732
2733 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2734 hdlc_mode(info);
2735 else
2736 async_mode(info);
2737
2738 set_signals(info);
2739
2740 info->dcd_chkcount = 0;
2741 info->cts_chkcount = 0;
2742 info->ri_chkcount = 0;
2743 info->dsr_chkcount = 0;
2744
2745 info->ie1_value |= (CDCD|CCTS);
2746 write_reg(info, IE1, info->ie1_value);
2747
2748 get_signals(info);
2749
2750 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2751 rx_start(info);
2752
2753 spin_unlock_irqrestore(&info->lock,flags);
2754 }
2755
2756 /* Reconfigure adapter based on new parameters
2757 */
2758 static void change_params(SLMP_INFO *info)
2759 {
2760 unsigned cflag;
2761 int bits_per_char;
2762
2763 if (!info->port.tty)
2764 return;
2765
2766 if (debug_level >= DEBUG_LEVEL_INFO)
2767 printk("%s(%d):%s change_params()\n",
2768 __FILE__,__LINE__, info->device_name );
2769
2770 cflag = info->port.tty->termios.c_cflag;
2771
2772 /* if B0 rate (hangup) specified then negate RTS and DTR */
2773 /* otherwise assert RTS and DTR */
2774 if (cflag & CBAUD)
2775 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2776 else
2777 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2778
2779 /* byte size and parity */
2780
2781 switch (cflag & CSIZE) {
2782 case CS5: info->params.data_bits = 5; break;
2783 case CS6: info->params.data_bits = 6; break;
2784 case CS7: info->params.data_bits = 7; break;
2785 case CS8: info->params.data_bits = 8; break;
2786 /* Never happens, but GCC is too dumb to figure it out */
2787 default: info->params.data_bits = 7; break;
2788 }
2789
2790 if (cflag & CSTOPB)
2791 info->params.stop_bits = 2;
2792 else
2793 info->params.stop_bits = 1;
2794
2795 info->params.parity = ASYNC_PARITY_NONE;
2796 if (cflag & PARENB) {
2797 if (cflag & PARODD)
2798 info->params.parity = ASYNC_PARITY_ODD;
2799 else
2800 info->params.parity = ASYNC_PARITY_EVEN;
2801 #ifdef CMSPAR
2802 if (cflag & CMSPAR)
2803 info->params.parity = ASYNC_PARITY_SPACE;
2804 #endif
2805 }
2806
2807 /* calculate number of jiffies to transmit a full
2808 * FIFO (32 bytes) at specified data rate
2809 */
2810 bits_per_char = info->params.data_bits +
2811 info->params.stop_bits + 1;
2812
2813 /* if port data rate is set to 460800 or less then
2814 * allow tty settings to override, otherwise keep the
2815 * current data rate.
2816 */
2817 if (info->params.data_rate <= 460800) {
2818 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2819 }
2820
2821 if ( info->params.data_rate ) {
2822 info->timeout = (32*HZ*bits_per_char) /
2823 info->params.data_rate;
2824 }
2825 info->timeout += HZ/50; /* Add .02 seconds of slop */
2826
2827 if (cflag & CRTSCTS)
2828 info->port.flags |= ASYNC_CTS_FLOW;
2829 else
2830 info->port.flags &= ~ASYNC_CTS_FLOW;
2831
2832 if (cflag & CLOCAL)
2833 info->port.flags &= ~ASYNC_CHECK_CD;
2834 else
2835 info->port.flags |= ASYNC_CHECK_CD;
2836
2837 /* process tty input control flags */
2838
2839 info->read_status_mask2 = OVRN;
2840 if (I_INPCK(info->port.tty))
2841 info->read_status_mask2 |= PE | FRME;
2842 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2843 info->read_status_mask1 |= BRKD;
2844 if (I_IGNPAR(info->port.tty))
2845 info->ignore_status_mask2 |= PE | FRME;
2846 if (I_IGNBRK(info->port.tty)) {
2847 info->ignore_status_mask1 |= BRKD;
2848 /* If ignoring parity and break indicators, ignore
2849 * overruns too. (For real raw support).
2850 */
2851 if (I_IGNPAR(info->port.tty))
2852 info->ignore_status_mask2 |= OVRN;
2853 }
2854
2855 program_hw(info);
2856 }
2857
2858 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2859 {
2860 int err;
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s get_params()\n",
2864 __FILE__,__LINE__, info->device_name);
2865
2866 if (!user_icount) {
2867 memset(&info->icount, 0, sizeof(info->icount));
2868 } else {
2869 mutex_lock(&info->port.mutex);
2870 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2871 mutex_unlock(&info->port.mutex);
2872 if (err)
2873 return -EFAULT;
2874 }
2875
2876 return 0;
2877 }
2878
2879 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2880 {
2881 int err;
2882 if (debug_level >= DEBUG_LEVEL_INFO)
2883 printk("%s(%d):%s get_params()\n",
2884 __FILE__,__LINE__, info->device_name);
2885
2886 mutex_lock(&info->port.mutex);
2887 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2888 mutex_unlock(&info->port.mutex);
2889 if (err) {
2890 if ( debug_level >= DEBUG_LEVEL_INFO )
2891 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2892 __FILE__,__LINE__,info->device_name);
2893 return -EFAULT;
2894 }
2895
2896 return 0;
2897 }
2898
2899 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2900 {
2901 unsigned long flags;
2902 MGSL_PARAMS tmp_params;
2903 int err;
2904
2905 if (debug_level >= DEBUG_LEVEL_INFO)
2906 printk("%s(%d):%s set_params\n",
2907 __FILE__,__LINE__,info->device_name );
2908 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2909 if (err) {
2910 if ( debug_level >= DEBUG_LEVEL_INFO )
2911 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2912 __FILE__,__LINE__,info->device_name);
2913 return -EFAULT;
2914 }
2915
2916 mutex_lock(&info->port.mutex);
2917 spin_lock_irqsave(&info->lock,flags);
2918 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2919 spin_unlock_irqrestore(&info->lock,flags);
2920
2921 change_params(info);
2922 mutex_unlock(&info->port.mutex);
2923
2924 return 0;
2925 }
2926
2927 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2928 {
2929 int err;
2930
2931 if (debug_level >= DEBUG_LEVEL_INFO)
2932 printk("%s(%d):%s get_txidle()=%d\n",
2933 __FILE__,__LINE__, info->device_name, info->idle_mode);
2934
2935 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2936 if (err) {
2937 if ( debug_level >= DEBUG_LEVEL_INFO )
2938 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2939 __FILE__,__LINE__,info->device_name);
2940 return -EFAULT;
2941 }
2942
2943 return 0;
2944 }
2945
2946 static int set_txidle(SLMP_INFO * info, int idle_mode)
2947 {
2948 unsigned long flags;
2949
2950 if (debug_level >= DEBUG_LEVEL_INFO)
2951 printk("%s(%d):%s set_txidle(%d)\n",
2952 __FILE__,__LINE__,info->device_name, idle_mode );
2953
2954 spin_lock_irqsave(&info->lock,flags);
2955 info->idle_mode = idle_mode;
2956 tx_set_idle( info );
2957 spin_unlock_irqrestore(&info->lock,flags);
2958 return 0;
2959 }
2960
2961 static int tx_enable(SLMP_INFO * info, int enable)
2962 {
2963 unsigned long flags;
2964
2965 if (debug_level >= DEBUG_LEVEL_INFO)
2966 printk("%s(%d):%s tx_enable(%d)\n",
2967 __FILE__,__LINE__,info->device_name, enable);
2968
2969 spin_lock_irqsave(&info->lock,flags);
2970 if ( enable ) {
2971 if ( !info->tx_enabled ) {
2972 tx_start(info);
2973 }
2974 } else {
2975 if ( info->tx_enabled )
2976 tx_stop(info);
2977 }
2978 spin_unlock_irqrestore(&info->lock,flags);
2979 return 0;
2980 }
2981
2982 /* abort send HDLC frame
2983 */
2984 static int tx_abort(SLMP_INFO * info)
2985 {
2986 unsigned long flags;
2987
2988 if (debug_level >= DEBUG_LEVEL_INFO)
2989 printk("%s(%d):%s tx_abort()\n",
2990 __FILE__,__LINE__,info->device_name);
2991
2992 spin_lock_irqsave(&info->lock,flags);
2993 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2994 info->ie1_value &= ~UDRN;
2995 info->ie1_value |= IDLE;
2996 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2997 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2998
2999 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3000 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3001
3002 write_reg(info, CMD, TXABORT);
3003 }
3004 spin_unlock_irqrestore(&info->lock,flags);
3005 return 0;
3006 }
3007
3008 static int rx_enable(SLMP_INFO * info, int enable)
3009 {
3010 unsigned long flags;
3011
3012 if (debug_level >= DEBUG_LEVEL_INFO)
3013 printk("%s(%d):%s rx_enable(%d)\n",
3014 __FILE__,__LINE__,info->device_name,enable);
3015
3016 spin_lock_irqsave(&info->lock,flags);
3017 if ( enable ) {
3018 if ( !info->rx_enabled )
3019 rx_start(info);
3020 } else {
3021 if ( info->rx_enabled )
3022 rx_stop(info);
3023 }
3024 spin_unlock_irqrestore(&info->lock,flags);
3025 return 0;
3026 }
3027
3028 /* wait for specified event to occur
3029 */
3030 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3031 {
3032 unsigned long flags;
3033 int s;
3034 int rc=0;
3035 struct mgsl_icount cprev, cnow;
3036 int events;
3037 int mask;
3038 struct _input_signal_events oldsigs, newsigs;
3039 DECLARE_WAITQUEUE(wait, current);
3040
3041 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3042 if (rc) {
3043 return -EFAULT;
3044 }
3045
3046 if (debug_level >= DEBUG_LEVEL_INFO)
3047 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3048 __FILE__,__LINE__,info->device_name,mask);
3049
3050 spin_lock_irqsave(&info->lock,flags);
3051
3052 /* return immediately if state matches requested events */
3053 get_signals(info);
3054 s = info->serial_signals;
3055
3056 events = mask &
3057 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3058 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3059 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3060 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3061 if (events) {
3062 spin_unlock_irqrestore(&info->lock,flags);
3063 goto exit;
3064 }
3065
3066 /* save current irq counts */
3067 cprev = info->icount;
3068 oldsigs = info->input_signal_events;
3069
3070 /* enable hunt and idle irqs if needed */
3071 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3072 unsigned char oldval = info->ie1_value;
3073 unsigned char newval = oldval +
3074 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3075 (mask & MgslEvent_IdleReceived ? IDLD:0);
3076 if ( oldval != newval ) {
3077 info->ie1_value = newval;
3078 write_reg(info, IE1, info->ie1_value);
3079 }
3080 }
3081
3082 set_current_state(TASK_INTERRUPTIBLE);
3083 add_wait_queue(&info->event_wait_q, &wait);
3084
3085 spin_unlock_irqrestore(&info->lock,flags);
3086
3087 for(;;) {
3088 schedule();
3089 if (signal_pending(current)) {
3090 rc = -ERESTARTSYS;
3091 break;
3092 }
3093
3094 /* get current irq counts */
3095 spin_lock_irqsave(&info->lock,flags);
3096 cnow = info->icount;
3097 newsigs = info->input_signal_events;
3098 set_current_state(TASK_INTERRUPTIBLE);
3099 spin_unlock_irqrestore(&info->lock,flags);
3100
3101 /* if no change, wait aborted for some reason */
3102 if (newsigs.dsr_up == oldsigs.dsr_up &&
3103 newsigs.dsr_down == oldsigs.dsr_down &&
3104 newsigs.dcd_up == oldsigs.dcd_up &&
3105 newsigs.dcd_down == oldsigs.dcd_down &&
3106 newsigs.cts_up == oldsigs.cts_up &&
3107 newsigs.cts_down == oldsigs.cts_down &&
3108 newsigs.ri_up == oldsigs.ri_up &&
3109 newsigs.ri_down == oldsigs.ri_down &&
3110 cnow.exithunt == cprev.exithunt &&
3111 cnow.rxidle == cprev.rxidle) {
3112 rc = -EIO;
3113 break;
3114 }
3115
3116 events = mask &
3117 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3118 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3119 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3120 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3121 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3122 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3123 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3124 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3125 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3126 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3127 if (events)
3128 break;
3129
3130 cprev = cnow;
3131 oldsigs = newsigs;
3132 }
3133
3134 remove_wait_queue(&info->event_wait_q, &wait);
3135 set_current_state(TASK_RUNNING);
3136
3137
3138 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3139 spin_lock_irqsave(&info->lock,flags);
3140 if (!waitqueue_active(&info->event_wait_q)) {
3141 /* disable enable exit hunt mode/idle rcvd IRQs */
3142 info->ie1_value &= ~(FLGD|IDLD);
3143 write_reg(info, IE1, info->ie1_value);
3144 }
3145 spin_unlock_irqrestore(&info->lock,flags);
3146 }
3147 exit:
3148 if ( rc == 0 )
3149 PUT_USER(rc, events, mask_ptr);
3150
3151 return rc;
3152 }
3153
3154 static int modem_input_wait(SLMP_INFO *info,int arg)
3155 {
3156 unsigned long flags;
3157 int rc;
3158 struct mgsl_icount cprev, cnow;
3159 DECLARE_WAITQUEUE(wait, current);
3160
3161 /* save current irq counts */
3162 spin_lock_irqsave(&info->lock,flags);
3163 cprev = info->icount;
3164 add_wait_queue(&info->status_event_wait_q, &wait);
3165 set_current_state(TASK_INTERRUPTIBLE);
3166 spin_unlock_irqrestore(&info->lock,flags);
3167
3168 for(;;) {
3169 schedule();
3170 if (signal_pending(current)) {
3171 rc = -ERESTARTSYS;
3172 break;
3173 }
3174
3175 /* get new irq counts */
3176 spin_lock_irqsave(&info->lock,flags);
3177 cnow = info->icount;
3178 set_current_state(TASK_INTERRUPTIBLE);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180
3181 /* if no change, wait aborted for some reason */
3182 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3183 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3184 rc = -EIO;
3185 break;
3186 }
3187
3188 /* check for change in caller specified modem input */
3189 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3190 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3191 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3192 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3193 rc = 0;
3194 break;
3195 }
3196
3197 cprev = cnow;
3198 }
3199 remove_wait_queue(&info->status_event_wait_q, &wait);
3200 set_current_state(TASK_RUNNING);
3201 return rc;
3202 }
3203
3204 /* return the state of the serial control and status signals
3205 */
3206 static int tiocmget(struct tty_struct *tty)
3207 {
3208 SLMP_INFO *info = tty->driver_data;
3209 unsigned int result;
3210 unsigned long flags;
3211
3212 spin_lock_irqsave(&info->lock,flags);
3213 get_signals(info);
3214 spin_unlock_irqrestore(&info->lock,flags);
3215
3216 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3217 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3218 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3219 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3220 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3221 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3222
3223 if (debug_level >= DEBUG_LEVEL_INFO)
3224 printk("%s(%d):%s tiocmget() value=%08X\n",
3225 __FILE__,__LINE__, info->device_name, result );
3226 return result;
3227 }
3228
3229 /* set modem control signals (DTR/RTS)
3230 */
3231 static int tiocmset(struct tty_struct *tty,
3232 unsigned int set, unsigned int clear)
3233 {
3234 SLMP_INFO *info = tty->driver_data;
3235 unsigned long flags;
3236
3237 if (debug_level >= DEBUG_LEVEL_INFO)
3238 printk("%s(%d):%s tiocmset(%x,%x)\n",
3239 __FILE__,__LINE__,info->device_name, set, clear);
3240
3241 if (set & TIOCM_RTS)
3242 info->serial_signals |= SerialSignal_RTS;
3243 if (set & TIOCM_DTR)
3244 info->serial_signals |= SerialSignal_DTR;
3245 if (clear & TIOCM_RTS)
3246 info->serial_signals &= ~SerialSignal_RTS;
3247 if (clear & TIOCM_DTR)
3248 info->serial_signals &= ~SerialSignal_DTR;
3249
3250 spin_lock_irqsave(&info->lock,flags);
3251 set_signals(info);
3252 spin_unlock_irqrestore(&info->lock,flags);
3253
3254 return 0;
3255 }
3256
3257 static int carrier_raised(struct tty_port *port)
3258 {
3259 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3260 unsigned long flags;
3261
3262 spin_lock_irqsave(&info->lock,flags);
3263 get_signals(info);
3264 spin_unlock_irqrestore(&info->lock,flags);
3265
3266 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3267 }
3268
3269 static void dtr_rts(struct tty_port *port, int on)
3270 {
3271 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3272 unsigned long flags;
3273
3274 spin_lock_irqsave(&info->lock,flags);
3275 if (on)
3276 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3277 else
3278 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3279 set_signals(info);
3280 spin_unlock_irqrestore(&info->lock,flags);
3281 }
3282
3283 /* Block the current process until the specified port is ready to open.
3284 */
3285 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3286 SLMP_INFO *info)
3287 {
3288 DECLARE_WAITQUEUE(wait, current);
3289 int retval;
3290 bool do_clocal = false;
3291 bool extra_count = false;
3292 unsigned long flags;
3293 int cd;
3294 struct tty_port *port = &info->port;
3295
3296 if (debug_level >= DEBUG_LEVEL_INFO)
3297 printk("%s(%d):%s block_til_ready()\n",
3298 __FILE__,__LINE__, tty->driver->name );
3299
3300 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3301 /* nonblock mode is set or port is not enabled */
3302 /* just verify that callout device is not active */
3303 port->flags |= ASYNC_NORMAL_ACTIVE;
3304 return 0;
3305 }
3306
3307 if (tty->termios.c_cflag & CLOCAL)
3308 do_clocal = true;
3309
3310 /* Wait for carrier detect and the line to become
3311 * free (i.e., not in use by the callout). While we are in
3312 * this loop, port->count is dropped by one, so that
3313 * close() knows when to free things. We restore it upon
3314 * exit, either normal or abnormal.
3315 */
3316
3317 retval = 0;
3318 add_wait_queue(&port->open_wait, &wait);
3319
3320 if (debug_level >= DEBUG_LEVEL_INFO)
3321 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3322 __FILE__,__LINE__, tty->driver->name, port->count );
3323
3324 spin_lock_irqsave(&info->lock, flags);
3325 if (!tty_hung_up_p(filp)) {
3326 extra_count = true;
3327 port->count--;
3328 }
3329 spin_unlock_irqrestore(&info->lock, flags);
3330 port->blocked_open++;
3331
3332 while (1) {
3333 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3334 tty_port_raise_dtr_rts(port);
3335
3336 set_current_state(TASK_INTERRUPTIBLE);
3337
3338 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3339 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3340 -EAGAIN : -ERESTARTSYS;
3341 break;
3342 }
3343
3344 cd = tty_port_carrier_raised(port);
3345
3346 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3347 break;
3348
3349 if (signal_pending(current)) {
3350 retval = -ERESTARTSYS;
3351 break;
3352 }
3353
3354 if (debug_level >= DEBUG_LEVEL_INFO)
3355 printk("%s(%d):%s block_til_ready() count=%d\n",
3356 __FILE__,__LINE__, tty->driver->name, port->count );
3357
3358 tty_unlock(tty);
3359 schedule();
3360 tty_lock(tty);
3361 }
3362
3363 set_current_state(TASK_RUNNING);
3364 remove_wait_queue(&port->open_wait, &wait);
3365
3366 if (extra_count)
3367 port->count++;
3368 port->blocked_open--;
3369
3370 if (debug_level >= DEBUG_LEVEL_INFO)
3371 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3372 __FILE__,__LINE__, tty->driver->name, port->count );
3373
3374 if (!retval)
3375 port->flags |= ASYNC_NORMAL_ACTIVE;
3376
3377 return retval;
3378 }
3379
3380 static int alloc_dma_bufs(SLMP_INFO *info)
3381 {
3382 unsigned short BuffersPerFrame;
3383 unsigned short BufferCount;
3384
3385 // Force allocation to start at 64K boundary for each port.
3386 // This is necessary because *all* buffer descriptors for a port
3387 // *must* be in the same 64K block. All descriptors on a port
3388 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3389 // into the CBP register.
3390 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3391
3392 /* Calculate the number of DMA buffers necessary to hold the */
3393 /* largest allowable frame size. Note: If the max frame size is */
3394 /* not an even multiple of the DMA buffer size then we need to */
3395 /* round the buffer count per frame up one. */
3396
3397 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3398 if ( info->max_frame_size % SCABUFSIZE )
3399 BuffersPerFrame++;
3400
3401 /* calculate total number of data buffers (SCABUFSIZE) possible
3402 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3403 * for the descriptor list (BUFFERLISTSIZE).
3404 */
3405 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3406
3407 /* limit number of buffers to maximum amount of descriptors */
3408 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3409 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3410
3411 /* use enough buffers to transmit one max size frame */
3412 info->tx_buf_count = BuffersPerFrame + 1;
3413
3414 /* never use more than half the available buffers for transmit */
3415 if (info->tx_buf_count > (BufferCount/2))
3416 info->tx_buf_count = BufferCount/2;
3417
3418 if (info->tx_buf_count > SCAMAXDESC)
3419 info->tx_buf_count = SCAMAXDESC;
3420
3421 /* use remaining buffers for receive */
3422 info->rx_buf_count = BufferCount - info->tx_buf_count;
3423
3424 if (info->rx_buf_count > SCAMAXDESC)
3425 info->rx_buf_count = SCAMAXDESC;
3426
3427 if ( debug_level >= DEBUG_LEVEL_INFO )
3428 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3429 __FILE__,__LINE__, info->device_name,
3430 info->tx_buf_count,info->rx_buf_count);
3431
3432 if ( alloc_buf_list( info ) < 0 ||
3433 alloc_frame_bufs(info,
3434 info->rx_buf_list,
3435 info->rx_buf_list_ex,
3436 info->rx_buf_count) < 0 ||
3437 alloc_frame_bufs(info,
3438 info->tx_buf_list,
3439 info->tx_buf_list_ex,
3440 info->tx_buf_count) < 0 ||
3441 alloc_tmp_rx_buf(info) < 0 ) {
3442 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3443 __FILE__,__LINE__, info->device_name);
3444 return -ENOMEM;
3445 }
3446
3447 rx_reset_buffers( info );
3448
3449 return 0;
3450 }
3451
3452 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3453 */
3454 static int alloc_buf_list(SLMP_INFO *info)
3455 {
3456 unsigned int i;
3457
3458 /* build list in adapter shared memory */
3459 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3460 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3461 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3462
3463 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3464
3465 /* Save virtual address pointers to the receive and */
3466 /* transmit buffer lists. (Receive 1st). These pointers will */
3467 /* be used by the processor to access the lists. */
3468 info->rx_buf_list = (SCADESC *)info->buffer_list;
3469
3470 info->tx_buf_list = (SCADESC *)info->buffer_list;
3471 info->tx_buf_list += info->rx_buf_count;
3472
3473 /* Build links for circular buffer entry lists (tx and rx)
3474 *
3475 * Note: links are physical addresses read by the SCA device
3476 * to determine the next buffer entry to use.
3477 */
3478
3479 for ( i = 0; i < info->rx_buf_count; i++ ) {
3480 /* calculate and store physical address of this buffer entry */
3481 info->rx_buf_list_ex[i].phys_entry =
3482 info->buffer_list_phys + (i * SCABUFSIZE);
3483
3484 /* calculate and store physical address of */
3485 /* next entry in cirular list of entries */
3486 info->rx_buf_list[i].next = info->buffer_list_phys;
3487 if ( i < info->rx_buf_count - 1 )
3488 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3489
3490 info->rx_buf_list[i].length = SCABUFSIZE;
3491 }
3492
3493 for ( i = 0; i < info->tx_buf_count; i++ ) {
3494 /* calculate and store physical address of this buffer entry */
3495 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3496 ((info->rx_buf_count + i) * sizeof(SCADESC));
3497
3498 /* calculate and store physical address of */
3499 /* next entry in cirular list of entries */
3500
3501 info->tx_buf_list[i].next = info->buffer_list_phys +
3502 info->rx_buf_count * sizeof(SCADESC);
3503
3504 if ( i < info->tx_buf_count - 1 )
3505 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3506 }
3507
3508 return 0;
3509 }
3510
3511 /* Allocate the frame DMA buffers used by the specified buffer list.
3512 */
3513 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3514 {
3515 int i;
3516 unsigned long phys_addr;
3517
3518 for ( i = 0; i < count; i++ ) {
3519 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3520 phys_addr = info->port_array[0]->last_mem_alloc;
3521 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3522
3523 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3524 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3525 }
3526
3527 return 0;
3528 }
3529
3530 static void free_dma_bufs(SLMP_INFO *info)
3531 {
3532 info->buffer_list = NULL;
3533 info->rx_buf_list = NULL;
3534 info->tx_buf_list = NULL;
3535 }
3536
3537 /* allocate buffer large enough to hold max_frame_size.
3538 * This buffer is used to pass an assembled frame to the line discipline.
3539 */
3540 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3541 {
3542 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3543 if (info->tmp_rx_buf == NULL)
3544 return -ENOMEM;
3545 /* unused flag buffer to satisfy receive_buf calling interface */
3546 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3547 if (!info->flag_buf) {
3548 kfree(info->tmp_rx_buf);
3549 info->tmp_rx_buf = NULL;
3550 return -ENOMEM;
3551 }
3552 return 0;
3553 }
3554
3555 static void free_tmp_rx_buf(SLMP_INFO *info)
3556 {
3557 kfree(info->tmp_rx_buf);
3558 info->tmp_rx_buf = NULL;
3559 kfree(info->flag_buf);
3560 info->flag_buf = NULL;
3561 }
3562
3563 static int claim_resources(SLMP_INFO *info)
3564 {
3565 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3566 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3567 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3568 info->init_error = DiagStatus_AddressConflict;
3569 goto errout;
3570 }
3571 else
3572 info->shared_mem_requested = true;
3573
3574 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3575 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3576 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3577 info->init_error = DiagStatus_AddressConflict;
3578 goto errout;
3579 }
3580 else
3581 info->lcr_mem_requested = true;
3582
3583 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3584 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3585 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3586 info->init_error = DiagStatus_AddressConflict;
3587 goto errout;
3588 }
3589 else
3590 info->sca_base_requested = true;
3591
3592 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3593 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3594 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3595 info->init_error = DiagStatus_AddressConflict;
3596 goto errout;
3597 }
3598 else
3599 info->sca_statctrl_requested = true;
3600
3601 info->memory_base = ioremap_nocache(info->phys_memory_base,
3602 SCA_MEM_SIZE);
3603 if (!info->memory_base) {
3604 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3605 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3606 info->init_error = DiagStatus_CantAssignPciResources;
3607 goto errout;
3608 }
3609
3610 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3611 if (!info->lcr_base) {
3612 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3613 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3614 info->init_error = DiagStatus_CantAssignPciResources;
3615 goto errout;
3616 }
3617 info->lcr_base += info->lcr_offset;
3618
3619 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3620 if (!info->sca_base) {
3621 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3622 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3623 info->init_error = DiagStatus_CantAssignPciResources;
3624 goto errout;
3625 }
3626 info->sca_base += info->sca_offset;
3627
3628 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3629 PAGE_SIZE);
3630 if (!info->statctrl_base) {
3631 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3632 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3633 info->init_error = DiagStatus_CantAssignPciResources;
3634 goto errout;
3635 }
3636 info->statctrl_base += info->statctrl_offset;
3637
3638 if ( !memory_test(info) ) {
3639 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3640 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3641 info->init_error = DiagStatus_MemoryError;
3642 goto errout;
3643 }
3644
3645 return 0;
3646
3647 errout:
3648 release_resources( info );
3649 return -ENODEV;
3650 }
3651
3652 static void release_resources(SLMP_INFO *info)
3653 {
3654 if ( debug_level >= DEBUG_LEVEL_INFO )
3655 printk( "%s(%d):%s release_resources() entry\n",
3656 __FILE__,__LINE__,info->device_name );
3657
3658 if ( info->irq_requested ) {
3659 free_irq(info->irq_level, info);
3660 info->irq_requested = false;
3661 }
3662
3663 if ( info->shared_mem_requested ) {
3664 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3665 info->shared_mem_requested = false;
3666 }
3667 if ( info->lcr_mem_requested ) {
3668 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3669 info->lcr_mem_requested = false;
3670 }
3671 if ( info->sca_base_requested ) {
3672 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3673 info->sca_base_requested = false;
3674 }
3675 if ( info->sca_statctrl_requested ) {
3676 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3677 info->sca_statctrl_requested = false;
3678 }
3679
3680 if (info->memory_base){
3681 iounmap(info->memory_base);
3682 info->memory_base = NULL;
3683 }
3684
3685 if (info->sca_base) {
3686 iounmap(info->sca_base - info->sca_offset);
3687 info->sca_base=NULL;
3688 }
3689
3690 if (info->statctrl_base) {
3691 iounmap(info->statctrl_base - info->statctrl_offset);
3692 info->statctrl_base=NULL;
3693 }
3694
3695 if (info->lcr_base){
3696 iounmap(info->lcr_base - info->lcr_offset);
3697 info->lcr_base = NULL;
3698 }
3699
3700 if ( debug_level >= DEBUG_LEVEL_INFO )
3701 printk( "%s(%d):%s release_resources() exit\n",
3702 __FILE__,__LINE__,info->device_name );
3703 }
3704
3705 /* Add the specified device instance data structure to the
3706 * global linked list of devices and increment the device count.
3707 */
3708 static void add_device(SLMP_INFO *info)
3709 {
3710 info->next_device = NULL;
3711 info->line = synclinkmp_device_count;
3712 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3713
3714 if (info->line < MAX_DEVICES) {
3715 if (maxframe[info->line])
3716 info->max_frame_size = maxframe[info->line];
3717 }
3718
3719 synclinkmp_device_count++;
3720
3721 if ( !synclinkmp_device_list )
3722 synclinkmp_device_list = info;
3723 else {
3724 SLMP_INFO *current_dev = synclinkmp_device_list;
3725 while( current_dev->next_device )
3726 current_dev = current_dev->next_device;
3727 current_dev->next_device = info;
3728 }
3729
3730 if ( info->max_frame_size < 4096 )
3731 info->max_frame_size = 4096;
3732 else if ( info->max_frame_size > 65535 )
3733 info->max_frame_size = 65535;
3734
3735 printk( "SyncLink MultiPort %s: "
3736 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3737 info->device_name,
3738 info->phys_sca_base,
3739 info->phys_memory_base,
3740 info->phys_statctrl_base,
3741 info->phys_lcr_base,
3742 info->irq_level,
3743 info->max_frame_size );
3744
3745 #if SYNCLINK_GENERIC_HDLC
3746 hdlcdev_init(info);
3747 #endif
3748 }
3749
3750 static const struct tty_port_operations port_ops = {
3751 .carrier_raised = carrier_raised,
3752 .dtr_rts = dtr_rts,
3753 };
3754
3755 /* Allocate and initialize a device instance structure
3756 *
3757 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3758 */
3759 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3760 {
3761 SLMP_INFO *info;
3762
3763 info = kzalloc(sizeof(SLMP_INFO),
3764 GFP_KERNEL);
3765
3766 if (!info) {
3767 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3768 __FILE__,__LINE__, adapter_num, port_num);
3769 } else {
3770 tty_port_init(&info->port);
3771 info->port.ops = &port_ops;
3772 info->magic = MGSL_MAGIC;
3773 INIT_WORK(&info->task, bh_handler);
3774 info->max_frame_size = 4096;
3775 info->port.close_delay = 5*HZ/10;
3776 info->port.closing_wait = 30*HZ;
3777 init_waitqueue_head(&info->status_event_wait_q);
3778 init_waitqueue_head(&info->event_wait_q);
3779 spin_lock_init(&info->netlock);
3780 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3781 info->idle_mode = HDLC_TXIDLE_FLAGS;
3782 info->adapter_num = adapter_num;
3783 info->port_num = port_num;
3784
3785 /* Copy configuration info to device instance data */
3786 info->irq_level = pdev->irq;
3787 info->phys_lcr_base = pci_resource_start(pdev,0);
3788 info->phys_sca_base = pci_resource_start(pdev,2);
3789 info->phys_memory_base = pci_resource_start(pdev,3);
3790 info->phys_statctrl_base = pci_resource_start(pdev,4);
3791
3792 /* Because veremap only works on page boundaries we must map
3793 * a larger area than is actually implemented for the LCR
3794 * memory range. We map a full page starting at the page boundary.
3795 */
3796 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3797 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3798
3799 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3800 info->phys_sca_base &= ~(PAGE_SIZE-1);
3801
3802 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3803 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3804
3805 info->bus_type = MGSL_BUS_TYPE_PCI;
3806 info->irq_flags = IRQF_SHARED;
3807
3808 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3809 setup_timer(&info->status_timer, status_timeout,
3810 (unsigned long)info);
3811
3812 /* Store the PCI9050 misc control register value because a flaw
3813 * in the PCI9050 prevents LCR registers from being read if
3814 * BIOS assigns an LCR base address with bit 7 set.
3815 *
3816 * Only the misc control register is accessed for which only
3817 * write access is needed, so set an initial value and change
3818 * bits to the device instance data as we write the value
3819 * to the actual misc control register.
3820 */
3821 info->misc_ctrl_value = 0x087e4546;
3822
3823 /* initial port state is unknown - if startup errors
3824 * occur, init_error will be set to indicate the
3825 * problem. Once the port is fully initialized,
3826 * this value will be set to 0 to indicate the
3827 * port is available.
3828 */
3829 info->init_error = -1;
3830 }
3831
3832 return info;
3833 }
3834
3835 static void device_init(int adapter_num, struct pci_dev *pdev)
3836 {
3837 SLMP_INFO *port_array[SCA_MAX_PORTS];
3838 int port;
3839
3840 /* allocate device instances for up to SCA_MAX_PORTS devices */
3841 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3842 port_array[port] = alloc_dev(adapter_num,port,pdev);
3843 if( port_array[port] == NULL ) {
3844 for (--port; port >= 0; --port) {
3845 tty_port_destroy(&port_array[port]->port);
3846 kfree(port_array[port]);
3847 }
3848 return;
3849 }
3850 }
3851
3852 /* give copy of port_array to all ports and add to device list */
3853 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3854 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3855 add_device( port_array[port] );
3856 spin_lock_init(&port_array[port]->lock);
3857 }
3858
3859 /* Allocate and claim adapter resources */
3860 if ( !claim_resources(port_array[0]) ) {
3861
3862 alloc_dma_bufs(port_array[0]);
3863
3864 /* copy resource information from first port to others */
3865 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3866 port_array[port]->lock = port_array[0]->lock;
3867 port_array[port]->irq_level = port_array[0]->irq_level;
3868 port_array[port]->memory_base = port_array[0]->memory_base;
3869 port_array[port]->sca_base = port_array[0]->sca_base;
3870 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3871 port_array[port]->lcr_base = port_array[0]->lcr_base;
3872 alloc_dma_bufs(port_array[port]);
3873 }
3874
3875 if ( request_irq(port_array[0]->irq_level,
3876 synclinkmp_interrupt,
3877 port_array[0]->irq_flags,
3878 port_array[0]->device_name,
3879 port_array[0]) < 0 ) {
3880 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3881 __FILE__,__LINE__,
3882 port_array[0]->device_name,
3883 port_array[0]->irq_level );
3884 }
3885 else {
3886 port_array[0]->irq_requested = true;
3887 adapter_test(port_array[0]);
3888 }
3889 }
3890 }
3891
3892 static const struct tty_operations ops = {
3893 .install = install,
3894 .open = open,
3895 .close = close,
3896 .write = write,
3897 .put_char = put_char,
3898 .flush_chars = flush_chars,
3899 .write_room = write_room,
3900 .chars_in_buffer = chars_in_buffer,
3901 .flush_buffer = flush_buffer,
3902 .ioctl = ioctl,
3903 .throttle = throttle,
3904 .unthrottle = unthrottle,
3905 .send_xchar = send_xchar,
3906 .break_ctl = set_break,
3907 .wait_until_sent = wait_until_sent,
3908 .set_termios = set_termios,
3909 .stop = tx_hold,
3910 .start = tx_release,
3911 .hangup = hangup,
3912 .tiocmget = tiocmget,
3913 .tiocmset = tiocmset,
3914 .get_icount = get_icount,
3915 .proc_fops = &synclinkmp_proc_fops,
3916 };
3917
3918
3919 static void synclinkmp_cleanup(void)
3920 {
3921 int rc;
3922 SLMP_INFO *info;
3923 SLMP_INFO *tmp;
3924
3925 printk("Unloading %s %s\n", driver_name, driver_version);
3926
3927 if (serial_driver) {
3928 if ((rc = tty_unregister_driver(serial_driver)))
3929 printk("%s(%d) failed to unregister tty driver err=%d\n",
3930 __FILE__,__LINE__,rc);
3931 put_tty_driver(serial_driver);
3932 }
3933
3934 /* reset devices */
3935 info = synclinkmp_device_list;
3936 while(info) {
3937 reset_port(info);
3938 info = info->next_device;
3939 }
3940
3941 /* release devices */
3942 info = synclinkmp_device_list;
3943 while(info) {
3944 #if SYNCLINK_GENERIC_HDLC
3945 hdlcdev_exit(info);
3946 #endif
3947 free_dma_bufs(info);
3948 free_tmp_rx_buf(info);
3949 if ( info->port_num == 0 ) {
3950 if (info->sca_base)
3951 write_reg(info, LPR, 1); /* set low power mode */
3952 release_resources(info);
3953 }
3954 tmp = info;
3955 info = info->next_device;
3956 tty_port_destroy(&tmp->port);
3957 kfree(tmp);
3958 }
3959
3960 pci_unregister_driver(&synclinkmp_pci_driver);
3961 }
3962
3963 /* Driver initialization entry point.
3964 */
3965
3966 static int __init synclinkmp_init(void)
3967 {
3968 int rc;
3969
3970 if (break_on_load) {
3971 synclinkmp_get_text_ptr();
3972 BREAKPOINT();
3973 }
3974
3975 printk("%s %s\n", driver_name, driver_version);
3976
3977 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3978 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3979 return rc;
3980 }
3981
3982 serial_driver = alloc_tty_driver(128);
3983 if (!serial_driver) {
3984 rc = -ENOMEM;
3985 goto error;
3986 }
3987
3988 /* Initialize the tty_driver structure */
3989
3990 serial_driver->driver_name = "synclinkmp";
3991 serial_driver->name = "ttySLM";
3992 serial_driver->major = ttymajor;
3993 serial_driver->minor_start = 64;
3994 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3995 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3996 serial_driver->init_termios = tty_std_termios;
3997 serial_driver->init_termios.c_cflag =
3998 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3999 serial_driver->init_termios.c_ispeed = 9600;
4000 serial_driver->init_termios.c_ospeed = 9600;
4001 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4002 tty_set_operations(serial_driver, &ops);
4003 if ((rc = tty_register_driver(serial_driver)) < 0) {
4004 printk("%s(%d):Couldn't register serial driver\n",
4005 __FILE__,__LINE__);
4006 put_tty_driver(serial_driver);
4007 serial_driver = NULL;
4008 goto error;
4009 }
4010
4011 printk("%s %s, tty major#%d\n",
4012 driver_name, driver_version,
4013 serial_driver->major);
4014
4015 return 0;
4016
4017 error:
4018 synclinkmp_cleanup();
4019 return rc;
4020 }
4021
4022 static void __exit synclinkmp_exit(void)
4023 {
4024 synclinkmp_cleanup();
4025 }
4026
4027 module_init(synclinkmp_init);
4028 module_exit(synclinkmp_exit);
4029
4030 /* Set the port for internal loopback mode.
4031 * The TxCLK and RxCLK signals are generated from the BRG and
4032 * the TxD is looped back to the RxD internally.
4033 */
4034 static void enable_loopback(SLMP_INFO *info, int enable)
4035 {
4036 if (enable) {
4037 /* MD2 (Mode Register 2)
4038 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4039 */
4040 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4041
4042 /* degate external TxC clock source */
4043 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4044 write_control_reg(info);
4045
4046 /* RXS/TXS (Rx/Tx clock source)
4047 * 07 Reserved, must be 0
4048 * 06..04 Clock Source, 100=BRG
4049 * 03..00 Clock Divisor, 0000=1
4050 */
4051 write_reg(info, RXS, 0x40);
4052 write_reg(info, TXS, 0x40);
4053
4054 } else {
4055 /* MD2 (Mode Register 2)
4056 * 01..00 CNCT<1..0> Channel connection, 0=normal
4057 */
4058 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4059
4060 /* RXS/TXS (Rx/Tx clock source)
4061 * 07 Reserved, must be 0
4062 * 06..04 Clock Source, 000=RxC/TxC Pin
4063 * 03..00 Clock Divisor, 0000=1
4064 */
4065 write_reg(info, RXS, 0x00);
4066 write_reg(info, TXS, 0x00);
4067 }
4068
4069 /* set LinkSpeed if available, otherwise default to 2Mbps */
4070 if (info->params.clock_speed)
4071 set_rate(info, info->params.clock_speed);
4072 else
4073 set_rate(info, 3686400);
4074 }
4075
4076 /* Set the baud rate register to the desired speed
4077 *
4078 * data_rate data rate of clock in bits per second
4079 * A data rate of 0 disables the AUX clock.
4080 */
4081 static void set_rate( SLMP_INFO *info, u32 data_rate )
4082 {
4083 u32 TMCValue;
4084 unsigned char BRValue;
4085 u32 Divisor=0;
4086
4087 /* fBRG = fCLK/(TMC * 2^BR)
4088 */
4089 if (data_rate != 0) {
4090 Divisor = 14745600/data_rate;
4091 if (!Divisor)
4092 Divisor = 1;
4093
4094 TMCValue = Divisor;
4095
4096 BRValue = 0;
4097 if (TMCValue != 1 && TMCValue != 2) {
4098 /* BRValue of 0 provides 50/50 duty cycle *only* when
4099 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4100 * 50/50 duty cycle.
4101 */
4102 BRValue = 1;
4103 TMCValue >>= 1;
4104 }
4105
4106 /* while TMCValue is too big for TMC register, divide
4107 * by 2 and increment BR exponent.
4108 */
4109 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4110 TMCValue >>= 1;
4111
4112 write_reg(info, TXS,
4113 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4114 write_reg(info, RXS,
4115 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4116 write_reg(info, TMC, (unsigned char)TMCValue);
4117 }
4118 else {
4119 write_reg(info, TXS,0);
4120 write_reg(info, RXS,0);
4121 write_reg(info, TMC, 0);
4122 }
4123 }
4124
4125 /* Disable receiver
4126 */
4127 static void rx_stop(SLMP_INFO *info)
4128 {
4129 if (debug_level >= DEBUG_LEVEL_ISR)
4130 printk("%s(%d):%s rx_stop()\n",
4131 __FILE__,__LINE__, info->device_name );
4132
4133 write_reg(info, CMD, RXRESET);
4134
4135 info->ie0_value &= ~RXRDYE;
4136 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4137
4138 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4139 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4140 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4141
4142 info->rx_enabled = false;
4143 info->rx_overflow = false;
4144 }
4145
4146 /* enable the receiver
4147 */
4148 static void rx_start(SLMP_INFO *info)
4149 {
4150 int i;
4151
4152 if (debug_level >= DEBUG_LEVEL_ISR)
4153 printk("%s(%d):%s rx_start()\n",
4154 __FILE__,__LINE__, info->device_name );
4155
4156 write_reg(info, CMD, RXRESET);
4157
4158 if ( info->params.mode == MGSL_MODE_HDLC ) {
4159 /* HDLC, disabe IRQ on rxdata */
4160 info->ie0_value &= ~RXRDYE;
4161 write_reg(info, IE0, info->ie0_value);
4162
4163 /* Reset all Rx DMA buffers and program rx dma */
4164 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4165 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4166
4167 for (i = 0; i < info->rx_buf_count; i++) {
4168 info->rx_buf_list[i].status = 0xff;
4169
4170 // throttle to 4 shared memory writes at a time to prevent
4171 // hogging local bus (keep latency time for DMA requests low).
4172 if (!(i % 4))
4173 read_status_reg(info);
4174 }
4175 info->current_rx_buf = 0;
4176
4177 /* set current/1st descriptor address */
4178 write_reg16(info, RXDMA + CDA,
4179 info->rx_buf_list_ex[0].phys_entry);
4180
4181 /* set new last rx descriptor address */
4182 write_reg16(info, RXDMA + EDA,
4183 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4184
4185 /* set buffer length (shared by all rx dma data buffers) */
4186 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4187
4188 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4189 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4190 } else {
4191 /* async, enable IRQ on rxdata */
4192 info->ie0_value |= RXRDYE;
4193 write_reg(info, IE0, info->ie0_value);
4194 }
4195
4196 write_reg(info, CMD, RXENABLE);
4197
4198 info->rx_overflow = false;
4199 info->rx_enabled = true;
4200 }
4201
4202 /* Enable the transmitter and send a transmit frame if
4203 * one is loaded in the DMA buffers.
4204 */
4205 static void tx_start(SLMP_INFO *info)
4206 {
4207 if (debug_level >= DEBUG_LEVEL_ISR)
4208 printk("%s(%d):%s tx_start() tx_count=%d\n",
4209 __FILE__,__LINE__, info->device_name,info->tx_count );
4210
4211 if (!info->tx_enabled ) {
4212 write_reg(info, CMD, TXRESET);
4213 write_reg(info, CMD, TXENABLE);
4214 info->tx_enabled = true;
4215 }
4216
4217 if ( info->tx_count ) {
4218
4219 /* If auto RTS enabled and RTS is inactive, then assert */
4220 /* RTS and set a flag indicating that the driver should */
4221 /* negate RTS when the transmission completes. */
4222
4223 info->drop_rts_on_tx_done = false;
4224
4225 if (info->params.mode != MGSL_MODE_ASYNC) {
4226
4227 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4228 get_signals( info );
4229 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4230 info->serial_signals |= SerialSignal_RTS;
4231 set_signals( info );
4232 info->drop_rts_on_tx_done = true;
4233 }
4234 }
4235
4236 write_reg16(info, TRC0,
4237 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4238
4239 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4240 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4241
4242 /* set TX CDA (current descriptor address) */
4243 write_reg16(info, TXDMA + CDA,
4244 info->tx_buf_list_ex[0].phys_entry);
4245
4246 /* set TX EDA (last descriptor address) */
4247 write_reg16(info, TXDMA + EDA,
4248 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4249
4250 /* enable underrun IRQ */
4251 info->ie1_value &= ~IDLE;
4252 info->ie1_value |= UDRN;
4253 write_reg(info, IE1, info->ie1_value);
4254 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4255
4256 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4257 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4258
4259 mod_timer(&info->tx_timer, jiffies +
4260 msecs_to_jiffies(5000));
4261 }
4262 else {
4263 tx_load_fifo(info);
4264 /* async, enable IRQ on txdata */
4265 info->ie0_value |= TXRDYE;
4266 write_reg(info, IE0, info->ie0_value);
4267 }
4268
4269 info->tx_active = true;
4270 }
4271 }
4272
4273 /* stop the transmitter and DMA
4274 */
4275 static void tx_stop( SLMP_INFO *info )
4276 {
4277 if (debug_level >= DEBUG_LEVEL_ISR)
4278 printk("%s(%d):%s tx_stop()\n",
4279 __FILE__,__LINE__, info->device_name );
4280
4281 del_timer(&info->tx_timer);
4282
4283 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4284 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4285
4286 write_reg(info, CMD, TXRESET);
4287
4288 info->ie1_value &= ~(UDRN + IDLE);
4289 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4290 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4291
4292 info->ie0_value &= ~TXRDYE;
4293 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4294
4295 info->tx_enabled = false;
4296 info->tx_active = false;
4297 }
4298
4299 /* Fill the transmit FIFO until the FIFO is full or
4300 * there is no more data to load.
4301 */
4302 static void tx_load_fifo(SLMP_INFO *info)
4303 {
4304 u8 TwoBytes[2];
4305
4306 /* do nothing is now tx data available and no XON/XOFF pending */
4307
4308 if ( !info->tx_count && !info->x_char )
4309 return;
4310
4311 /* load the Transmit FIFO until FIFOs full or all data sent */
4312
4313 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4314
4315 /* there is more space in the transmit FIFO and */
4316 /* there is more data in transmit buffer */
4317
4318 if ( (info->tx_count > 1) && !info->x_char ) {
4319 /* write 16-bits */
4320 TwoBytes[0] = info->tx_buf[info->tx_get++];
4321 if (info->tx_get >= info->max_frame_size)
4322 info->tx_get -= info->max_frame_size;
4323 TwoBytes[1] = info->tx_buf[info->tx_get++];
4324 if (info->tx_get >= info->max_frame_size)
4325 info->tx_get -= info->max_frame_size;
4326
4327 write_reg16(info, TRB, *((u16 *)TwoBytes));
4328
4329 info->tx_count -= 2;
4330 info->icount.tx += 2;
4331 } else {
4332 /* only 1 byte left to transmit or 1 FIFO slot left */
4333
4334 if (info->x_char) {
4335 /* transmit pending high priority char */
4336 write_reg(info, TRB, info->x_char);
4337 info->x_char = 0;
4338 } else {
4339 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4340 if (info->tx_get >= info->max_frame_size)
4341 info->tx_get -= info->max_frame_size;
4342 info->tx_count--;
4343 }
4344 info->icount.tx++;
4345 }
4346 }
4347 }
4348
4349 /* Reset a port to a known state
4350 */
4351 static void reset_port(SLMP_INFO *info)
4352 {
4353 if (info->sca_base) {
4354
4355 tx_stop(info);
4356 rx_stop(info);
4357
4358 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4359 set_signals(info);
4360
4361 /* disable all port interrupts */
4362 info->ie0_value = 0;
4363 info->ie1_value = 0;
4364 info->ie2_value = 0;
4365 write_reg(info, IE0, info->ie0_value);
4366 write_reg(info, IE1, info->ie1_value);
4367 write_reg(info, IE2, info->ie2_value);
4368
4369 write_reg(info, CMD, CHRESET);
4370 }
4371 }
4372
4373 /* Reset all the ports to a known state.
4374 */
4375 static void reset_adapter(SLMP_INFO *info)
4376 {
4377 int i;
4378
4379 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4380 if (info->port_array[i])
4381 reset_port(info->port_array[i]);
4382 }
4383 }
4384
4385 /* Program port for asynchronous communications.
4386 */
4387 static void async_mode(SLMP_INFO *info)
4388 {
4389
4390 unsigned char RegValue;
4391
4392 tx_stop(info);
4393 rx_stop(info);
4394
4395 /* MD0, Mode Register 0
4396 *
4397 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4398 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4399 * 03 Reserved, must be 0
4400 * 02 CRCCC, CRC Calculation, 0=disabled
4401 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4402 *
4403 * 0000 0000
4404 */
4405 RegValue = 0x00;
4406 if (info->params.stop_bits != 1)
4407 RegValue |= BIT1;
4408 write_reg(info, MD0, RegValue);
4409
4410 /* MD1, Mode Register 1
4411 *
4412 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4413 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4414 * 03..02 RXCHR<1..0>, rx char size
4415 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4416 *
4417 * 0100 0000
4418 */
4419 RegValue = 0x40;
4420 switch (info->params.data_bits) {
4421 case 7: RegValue |= BIT4 + BIT2; break;
4422 case 6: RegValue |= BIT5 + BIT3; break;
4423 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4424 }
4425 if (info->params.parity != ASYNC_PARITY_NONE) {
4426 RegValue |= BIT1;
4427 if (info->params.parity == ASYNC_PARITY_ODD)
4428 RegValue |= BIT0;
4429 }
4430 write_reg(info, MD1, RegValue);
4431
4432 /* MD2, Mode Register 2
4433 *
4434 * 07..02 Reserved, must be 0
4435 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4436 *
4437 * 0000 0000
4438 */
4439 RegValue = 0x00;
4440 if (info->params.loopback)
4441 RegValue |= (BIT1 + BIT0);
4442 write_reg(info, MD2, RegValue);
4443
4444 /* RXS, Receive clock source
4445 *
4446 * 07 Reserved, must be 0
4447 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4448 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4449 */
4450 RegValue=BIT6;
4451 write_reg(info, RXS, RegValue);
4452
4453 /* TXS, Transmit clock source
4454 *
4455 * 07 Reserved, must be 0
4456 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4457 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4458 */
4459 RegValue=BIT6;
4460 write_reg(info, TXS, RegValue);
4461
4462 /* Control Register
4463 *
4464 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4465 */
4466 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4467 write_control_reg(info);
4468
4469 tx_set_idle(info);
4470
4471 /* RRC Receive Ready Control 0
4472 *
4473 * 07..05 Reserved, must be 0
4474 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4475 */
4476 write_reg(info, RRC, 0x00);
4477
4478 /* TRC0 Transmit Ready Control 0
4479 *
4480 * 07..05 Reserved, must be 0
4481 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4482 */
4483 write_reg(info, TRC0, 0x10);
4484
4485 /* TRC1 Transmit Ready Control 1
4486 *
4487 * 07..05 Reserved, must be 0
4488 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4489 */
4490 write_reg(info, TRC1, 0x1e);
4491
4492 /* CTL, MSCI control register
4493 *
4494 * 07..06 Reserved, set to 0
4495 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4496 * 04 IDLC, idle control, 0=mark 1=idle register
4497 * 03 BRK, break, 0=off 1 =on (async)
4498 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4499 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4500 * 00 RTS, RTS output control, 0=active 1=inactive
4501 *
4502 * 0001 0001
4503 */
4504 RegValue = 0x10;
4505 if (!(info->serial_signals & SerialSignal_RTS))
4506 RegValue |= 0x01;
4507 write_reg(info, CTL, RegValue);
4508
4509 /* enable status interrupts */
4510 info->ie0_value |= TXINTE + RXINTE;
4511 write_reg(info, IE0, info->ie0_value);
4512
4513 /* enable break detect interrupt */
4514 info->ie1_value = BRKD;
4515 write_reg(info, IE1, info->ie1_value);
4516
4517 /* enable rx overrun interrupt */
4518 info->ie2_value = OVRN;
4519 write_reg(info, IE2, info->ie2_value);
4520
4521 set_rate( info, info->params.data_rate * 16 );
4522 }
4523
4524 /* Program the SCA for HDLC communications.
4525 */
4526 static void hdlc_mode(SLMP_INFO *info)
4527 {
4528 unsigned char RegValue;
4529 u32 DpllDivisor;
4530
4531 // Can't use DPLL because SCA outputs recovered clock on RxC when
4532 // DPLL mode selected. This causes output contention with RxC receiver.
4533 // Use of DPLL would require external hardware to disable RxC receiver
4534 // when DPLL mode selected.
4535 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4536
4537 /* disable DMA interrupts */
4538 write_reg(info, TXDMA + DIR, 0);
4539 write_reg(info, RXDMA + DIR, 0);
4540
4541 /* MD0, Mode Register 0
4542 *
4543 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4544 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4545 * 03 Reserved, must be 0
4546 * 02 CRCCC, CRC Calculation, 1=enabled
4547 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4548 * 00 CRC0, CRC initial value, 1 = all 1s
4549 *
4550 * 1000 0001
4551 */
4552 RegValue = 0x81;
4553 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4554 RegValue |= BIT4;
4555 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4556 RegValue |= BIT4;
4557 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4558 RegValue |= BIT2 + BIT1;
4559 write_reg(info, MD0, RegValue);
4560
4561 /* MD1, Mode Register 1
4562 *
4563 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4564 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4565 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4566 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4567 *
4568 * 0000 0000
4569 */
4570 RegValue = 0x00;
4571 write_reg(info, MD1, RegValue);
4572
4573 /* MD2, Mode Register 2
4574 *
4575 * 07 NRZFM, 0=NRZ, 1=FM
4576 * 06..05 CODE<1..0> Encoding, 00=NRZ
4577 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4578 * 02 Reserved, must be 0
4579 * 01..00 CNCT<1..0> Channel connection, 0=normal
4580 *
4581 * 0000 0000
4582 */
4583 RegValue = 0x00;
4584 switch(info->params.encoding) {
4585 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4586 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4587 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4588 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4589 #if 0
4590 case HDLC_ENCODING_NRZB: /* not supported */
4591 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4592 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4593 #endif
4594 }
4595 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4596 DpllDivisor = 16;
4597 RegValue |= BIT3;
4598 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4599 DpllDivisor = 8;
4600 } else {
4601 DpllDivisor = 32;
4602 RegValue |= BIT4;
4603 }
4604 write_reg(info, MD2, RegValue);
4605
4606
4607 /* RXS, Receive clock source
4608 *
4609 * 07 Reserved, must be 0
4610 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4611 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4612 */
4613 RegValue=0;
4614 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4615 RegValue |= BIT6;
4616 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4617 RegValue |= BIT6 + BIT5;
4618 write_reg(info, RXS, RegValue);
4619
4620 /* TXS, Transmit clock source
4621 *
4622 * 07 Reserved, must be 0
4623 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4624 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4625 */
4626 RegValue=0;
4627 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4628 RegValue |= BIT6;
4629 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4630 RegValue |= BIT6 + BIT5;
4631 write_reg(info, TXS, RegValue);
4632
4633 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4634 set_rate(info, info->params.clock_speed * DpllDivisor);
4635 else
4636 set_rate(info, info->params.clock_speed);
4637
4638 /* GPDATA (General Purpose I/O Data Register)
4639 *
4640 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4641 */
4642 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4643 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4644 else
4645 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4646 write_control_reg(info);
4647
4648 /* RRC Receive Ready Control 0
4649 *
4650 * 07..05 Reserved, must be 0
4651 * 04..00 RRC<4..0> Rx FIFO trigger active
4652 */
4653 write_reg(info, RRC, rx_active_fifo_level);
4654
4655 /* TRC0 Transmit Ready Control 0
4656 *
4657 * 07..05 Reserved, must be 0
4658 * 04..00 TRC<4..0> Tx FIFO trigger active
4659 */
4660 write_reg(info, TRC0, tx_active_fifo_level);
4661
4662 /* TRC1 Transmit Ready Control 1
4663 *
4664 * 07..05 Reserved, must be 0
4665 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4666 */
4667 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4668
4669 /* DMR, DMA Mode Register
4670 *
4671 * 07..05 Reserved, must be 0
4672 * 04 TMOD, Transfer Mode: 1=chained-block
4673 * 03 Reserved, must be 0
4674 * 02 NF, Number of Frames: 1=multi-frame
4675 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4676 * 00 Reserved, must be 0
4677 *
4678 * 0001 0100
4679 */
4680 write_reg(info, TXDMA + DMR, 0x14);
4681 write_reg(info, RXDMA + DMR, 0x14);
4682
4683 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4684 write_reg(info, RXDMA + CPB,
4685 (unsigned char)(info->buffer_list_phys >> 16));
4686
4687 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4688 write_reg(info, TXDMA + CPB,
4689 (unsigned char)(info->buffer_list_phys >> 16));
4690
4691 /* enable status interrupts. other code enables/disables
4692 * the individual sources for these two interrupt classes.
4693 */
4694 info->ie0_value |= TXINTE + RXINTE;
4695 write_reg(info, IE0, info->ie0_value);
4696
4697 /* CTL, MSCI control register
4698 *
4699 * 07..06 Reserved, set to 0
4700 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4701 * 04 IDLC, idle control, 0=mark 1=idle register
4702 * 03 BRK, break, 0=off 1 =on (async)
4703 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4704 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4705 * 00 RTS, RTS output control, 0=active 1=inactive
4706 *
4707 * 0001 0001
4708 */
4709 RegValue = 0x10;
4710 if (!(info->serial_signals & SerialSignal_RTS))
4711 RegValue |= 0x01;
4712 write_reg(info, CTL, RegValue);
4713
4714 /* preamble not supported ! */
4715
4716 tx_set_idle(info);
4717 tx_stop(info);
4718 rx_stop(info);
4719
4720 set_rate(info, info->params.clock_speed);
4721
4722 if (info->params.loopback)
4723 enable_loopback(info,1);
4724 }
4725
4726 /* Set the transmit HDLC idle mode
4727 */
4728 static void tx_set_idle(SLMP_INFO *info)
4729 {
4730 unsigned char RegValue = 0xff;
4731
4732 /* Map API idle mode to SCA register bits */
4733 switch(info->idle_mode) {
4734 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4735 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4736 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4737 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4738 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4739 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4740 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4741 }
4742
4743 write_reg(info, IDL, RegValue);
4744 }
4745
4746 /* Query the adapter for the state of the V24 status (input) signals.
4747 */
4748 static void get_signals(SLMP_INFO *info)
4749 {
4750 u16 status = read_reg(info, SR3);
4751 u16 gpstatus = read_status_reg(info);
4752 u16 testbit;
4753
4754 /* clear all serial signals except RTS and DTR */
4755 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4756
4757 /* set serial signal bits to reflect MISR */
4758
4759 if (!(status & BIT3))
4760 info->serial_signals |= SerialSignal_CTS;
4761
4762 if ( !(status & BIT2))
4763 info->serial_signals |= SerialSignal_DCD;
4764
4765 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4766 if (!(gpstatus & testbit))
4767 info->serial_signals |= SerialSignal_RI;
4768
4769 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4770 if (!(gpstatus & testbit))
4771 info->serial_signals |= SerialSignal_DSR;
4772 }
4773
4774 /* Set the state of RTS and DTR based on contents of
4775 * serial_signals member of device context.
4776 */
4777 static void set_signals(SLMP_INFO *info)
4778 {
4779 unsigned char RegValue;
4780 u16 EnableBit;
4781
4782 RegValue = read_reg(info, CTL);
4783 if (info->serial_signals & SerialSignal_RTS)
4784 RegValue &= ~BIT0;
4785 else
4786 RegValue |= BIT0;
4787 write_reg(info, CTL, RegValue);
4788
4789 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4790 EnableBit = BIT1 << (info->port_num*2);
4791 if (info->serial_signals & SerialSignal_DTR)
4792 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4793 else
4794 info->port_array[0]->ctrlreg_value |= EnableBit;
4795 write_control_reg(info);
4796 }
4797
4798 /*******************/
4799 /* DMA Buffer Code */
4800 /*******************/
4801
4802 /* Set the count for all receive buffers to SCABUFSIZE
4803 * and set the current buffer to the first buffer. This effectively
4804 * makes all buffers free and discards any data in buffers.
4805 */
4806 static void rx_reset_buffers(SLMP_INFO *info)
4807 {
4808 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4809 }
4810
4811 /* Free the buffers used by a received frame
4812 *
4813 * info pointer to device instance data
4814 * first index of 1st receive buffer of frame
4815 * last index of last receive buffer of frame
4816 */
4817 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4818 {
4819 bool done = false;
4820
4821 while(!done) {
4822 /* reset current buffer for reuse */
4823 info->rx_buf_list[first].status = 0xff;
4824
4825 if (first == last) {
4826 done = true;
4827 /* set new last rx descriptor address */
4828 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4829 }
4830
4831 first++;
4832 if (first == info->rx_buf_count)
4833 first = 0;
4834 }
4835
4836 /* set current buffer to next buffer after last buffer of frame */
4837 info->current_rx_buf = first;
4838 }
4839
4840 /* Return a received frame from the receive DMA buffers.
4841 * Only frames received without errors are returned.
4842 *
4843 * Return Value: true if frame returned, otherwise false
4844 */
4845 static bool rx_get_frame(SLMP_INFO *info)
4846 {
4847 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4848 unsigned short status;
4849 unsigned int framesize = 0;
4850 bool ReturnCode = false;
4851 unsigned long flags;
4852 struct tty_struct *tty = info->port.tty;
4853 unsigned char addr_field = 0xff;
4854 SCADESC *desc;
4855 SCADESC_EX *desc_ex;
4856
4857 CheckAgain:
4858 /* assume no frame returned, set zero length */
4859 framesize = 0;
4860 addr_field = 0xff;
4861
4862 /*
4863 * current_rx_buf points to the 1st buffer of the next available
4864 * receive frame. To find the last buffer of the frame look for
4865 * a non-zero status field in the buffer entries. (The status
4866 * field is set by the 16C32 after completing a receive frame.
4867 */
4868 StartIndex = EndIndex = info->current_rx_buf;
4869
4870 for ( ;; ) {
4871 desc = &info->rx_buf_list[EndIndex];
4872 desc_ex = &info->rx_buf_list_ex[EndIndex];
4873
4874 if (desc->status == 0xff)
4875 goto Cleanup; /* current desc still in use, no frames available */
4876
4877 if (framesize == 0 && info->params.addr_filter != 0xff)
4878 addr_field = desc_ex->virt_addr[0];
4879
4880 framesize += desc->length;
4881
4882 /* Status != 0 means last buffer of frame */
4883 if (desc->status)
4884 break;
4885
4886 EndIndex++;
4887 if (EndIndex == info->rx_buf_count)
4888 EndIndex = 0;
4889
4890 if (EndIndex == info->current_rx_buf) {
4891 /* all buffers have been 'used' but none mark */
4892 /* the end of a frame. Reset buffers and receiver. */
4893 if ( info->rx_enabled ){
4894 spin_lock_irqsave(&info->lock,flags);
4895 rx_start(info);
4896 spin_unlock_irqrestore(&info->lock,flags);
4897 }
4898 goto Cleanup;
4899 }
4900
4901 }
4902
4903 /* check status of receive frame */
4904
4905 /* frame status is byte stored after frame data
4906 *
4907 * 7 EOM (end of msg), 1 = last buffer of frame
4908 * 6 Short Frame, 1 = short frame
4909 * 5 Abort, 1 = frame aborted
4910 * 4 Residue, 1 = last byte is partial
4911 * 3 Overrun, 1 = overrun occurred during frame reception
4912 * 2 CRC, 1 = CRC error detected
4913 *
4914 */
4915 status = desc->status;
4916
4917 /* ignore CRC bit if not using CRC (bit is undefined) */
4918 /* Note:CRC is not save to data buffer */
4919 if (info->params.crc_type == HDLC_CRC_NONE)
4920 status &= ~BIT2;
4921
4922 if (framesize == 0 ||
4923 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4924 /* discard 0 byte frames, this seems to occur sometime
4925 * when remote is idling flags.
4926 */
4927 rx_free_frame_buffers(info, StartIndex, EndIndex);
4928 goto CheckAgain;
4929 }
4930
4931 if (framesize < 2)
4932 status |= BIT6;
4933
4934 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4935 /* received frame has errors,
4936 * update counts and mark frame size as 0
4937 */
4938 if (status & BIT6)
4939 info->icount.rxshort++;
4940 else if (status & BIT5)
4941 info->icount.rxabort++;
4942 else if (status & BIT3)
4943 info->icount.rxover++;
4944 else
4945 info->icount.rxcrc++;
4946
4947 framesize = 0;
4948 #if SYNCLINK_GENERIC_HDLC
4949 {
4950 info->netdev->stats.rx_errors++;
4951 info->netdev->stats.rx_frame_errors++;
4952 }
4953 #endif
4954 }
4955
4956 if ( debug_level >= DEBUG_LEVEL_BH )
4957 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4958 __FILE__,__LINE__,info->device_name,status,framesize);
4959
4960 if ( debug_level >= DEBUG_LEVEL_DATA )
4961 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4962 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4963
4964 if (framesize) {
4965 if (framesize > info->max_frame_size)
4966 info->icount.rxlong++;
4967 else {
4968 /* copy dma buffer(s) to contiguous intermediate buffer */
4969 int copy_count = framesize;
4970 int index = StartIndex;
4971 unsigned char *ptmp = info->tmp_rx_buf;
4972 info->tmp_rx_buf_count = framesize;
4973
4974 info->icount.rxok++;
4975
4976 while(copy_count) {
4977 int partial_count = min(copy_count,SCABUFSIZE);
4978 memcpy( ptmp,
4979 info->rx_buf_list_ex[index].virt_addr,
4980 partial_count );
4981 ptmp += partial_count;
4982 copy_count -= partial_count;
4983
4984 if ( ++index == info->rx_buf_count )
4985 index = 0;
4986 }
4987
4988 #if SYNCLINK_GENERIC_HDLC
4989 if (info->netcount)
4990 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4991 else
4992 #endif
4993 ldisc_receive_buf(tty,info->tmp_rx_buf,
4994 info->flag_buf, framesize);
4995 }
4996 }
4997 /* Free the buffers used by this frame. */
4998 rx_free_frame_buffers( info, StartIndex, EndIndex );
4999
5000 ReturnCode = true;
5001
5002 Cleanup:
5003 if ( info->rx_enabled && info->rx_overflow ) {
5004 /* Receiver is enabled, but needs to restarted due to
5005 * rx buffer overflow. If buffers are empty, restart receiver.
5006 */
5007 if (info->rx_buf_list[EndIndex].status == 0xff) {
5008 spin_lock_irqsave(&info->lock,flags);
5009 rx_start(info);
5010 spin_unlock_irqrestore(&info->lock,flags);
5011 }
5012 }
5013
5014 return ReturnCode;
5015 }
5016
5017 /* load the transmit DMA buffer with data
5018 */
5019 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5020 {
5021 unsigned short copy_count;
5022 unsigned int i = 0;
5023 SCADESC *desc;
5024 SCADESC_EX *desc_ex;
5025
5026 if ( debug_level >= DEBUG_LEVEL_DATA )
5027 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5028
5029 /* Copy source buffer to one or more DMA buffers, starting with
5030 * the first transmit dma buffer.
5031 */
5032 for(i=0;;)
5033 {
5034 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5035
5036 desc = &info->tx_buf_list[i];
5037 desc_ex = &info->tx_buf_list_ex[i];
5038
5039 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5040
5041 desc->length = copy_count;
5042 desc->status = 0;
5043
5044 buf += copy_count;
5045 count -= copy_count;
5046
5047 if (!count)
5048 break;
5049
5050 i++;
5051 if (i >= info->tx_buf_count)
5052 i = 0;
5053 }
5054
5055 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5056 info->last_tx_buf = ++i;
5057 }
5058
5059 static bool register_test(SLMP_INFO *info)
5060 {
5061 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5062 static unsigned int count = ARRAY_SIZE(testval);
5063 unsigned int i;
5064 bool rc = true;
5065 unsigned long flags;
5066
5067 spin_lock_irqsave(&info->lock,flags);
5068 reset_port(info);
5069
5070 /* assume failure */
5071 info->init_error = DiagStatus_AddressFailure;
5072
5073 /* Write bit patterns to various registers but do it out of */
5074 /* sync, then read back and verify values. */
5075
5076 for (i = 0 ; i < count ; i++) {
5077 write_reg(info, TMC, testval[i]);
5078 write_reg(info, IDL, testval[(i+1)%count]);
5079 write_reg(info, SA0, testval[(i+2)%count]);
5080 write_reg(info, SA1, testval[(i+3)%count]);
5081
5082 if ( (read_reg(info, TMC) != testval[i]) ||
5083 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5084 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5085 (read_reg(info, SA1) != testval[(i+3)%count]) )
5086 {
5087 rc = false;
5088 break;
5089 }
5090 }
5091
5092 reset_port(info);
5093 spin_unlock_irqrestore(&info->lock,flags);
5094
5095 return rc;
5096 }
5097
5098 static bool irq_test(SLMP_INFO *info)
5099 {
5100 unsigned long timeout;
5101 unsigned long flags;
5102
5103 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5104
5105 spin_lock_irqsave(&info->lock,flags);
5106 reset_port(info);
5107
5108 /* assume failure */
5109 info->init_error = DiagStatus_IrqFailure;
5110 info->irq_occurred = false;
5111
5112 /* setup timer0 on SCA0 to interrupt */
5113
5114 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5115 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5116
5117 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5118 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5119
5120
5121 /* TMCS, Timer Control/Status Register
5122 *
5123 * 07 CMF, Compare match flag (read only) 1=match
5124 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5125 * 05 Reserved, must be 0
5126 * 04 TME, Timer Enable
5127 * 03..00 Reserved, must be 0
5128 *
5129 * 0101 0000
5130 */
5131 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5132
5133 spin_unlock_irqrestore(&info->lock,flags);
5134
5135 timeout=100;
5136 while( timeout-- && !info->irq_occurred ) {
5137 msleep_interruptible(10);
5138 }
5139
5140 spin_lock_irqsave(&info->lock,flags);
5141 reset_port(info);
5142 spin_unlock_irqrestore(&info->lock,flags);
5143
5144 return info->irq_occurred;
5145 }
5146
5147 /* initialize individual SCA device (2 ports)
5148 */
5149 static bool sca_init(SLMP_INFO *info)
5150 {
5151 /* set wait controller to single mem partition (low), no wait states */
5152 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5153 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5154 write_reg(info, WCRL, 0); /* wait controller low range */
5155 write_reg(info, WCRM, 0); /* wait controller mid range */
5156 write_reg(info, WCRH, 0); /* wait controller high range */
5157
5158 /* DPCR, DMA Priority Control
5159 *
5160 * 07..05 Not used, must be 0
5161 * 04 BRC, bus release condition: 0=all transfers complete
5162 * 03 CCC, channel change condition: 0=every cycle
5163 * 02..00 PR<2..0>, priority 100=round robin
5164 *
5165 * 00000100 = 0x04
5166 */
5167 write_reg(info, DPCR, dma_priority);
5168
5169 /* DMA Master Enable, BIT7: 1=enable all channels */
5170 write_reg(info, DMER, 0x80);
5171
5172 /* enable all interrupt classes */
5173 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5174 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5175 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5176
5177 /* ITCR, interrupt control register
5178 * 07 IPC, interrupt priority, 0=MSCI->DMA
5179 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5180 * 04 VOS, Vector Output, 0=unmodified vector
5181 * 03..00 Reserved, must be 0
5182 */
5183 write_reg(info, ITCR, 0);
5184
5185 return true;
5186 }
5187
5188 /* initialize adapter hardware
5189 */
5190 static bool init_adapter(SLMP_INFO *info)
5191 {
5192 int i;
5193
5194 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5195 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5196 u32 readval;
5197
5198 info->misc_ctrl_value |= BIT30;
5199 *MiscCtrl = info->misc_ctrl_value;
5200
5201 /*
5202 * Force at least 170ns delay before clearing
5203 * reset bit. Each read from LCR takes at least
5204 * 30ns so 10 times for 300ns to be safe.
5205 */
5206 for(i=0;i<10;i++)
5207 readval = *MiscCtrl;
5208
5209 info->misc_ctrl_value &= ~BIT30;
5210 *MiscCtrl = info->misc_ctrl_value;
5211
5212 /* init control reg (all DTRs off, all clksel=input) */
5213 info->ctrlreg_value = 0xaa;
5214 write_control_reg(info);
5215
5216 {
5217 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5218 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5219
5220 switch(read_ahead_count)
5221 {
5222 case 16:
5223 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5224 break;
5225 case 8:
5226 lcr1_brdr_value |= BIT5 + BIT4;
5227 break;
5228 case 4:
5229 lcr1_brdr_value |= BIT5 + BIT3;
5230 break;
5231 case 0:
5232 lcr1_brdr_value |= BIT5;
5233 break;
5234 }
5235
5236 *LCR1BRDR = lcr1_brdr_value;
5237 *MiscCtrl = misc_ctrl_value;
5238 }
5239
5240 sca_init(info->port_array[0]);
5241 sca_init(info->port_array[2]);
5242
5243 return true;
5244 }
5245
5246 /* Loopback an HDLC frame to test the hardware
5247 * interrupt and DMA functions.
5248 */
5249 static bool loopback_test(SLMP_INFO *info)
5250 {
5251 #define TESTFRAMESIZE 20
5252
5253 unsigned long timeout;
5254 u16 count = TESTFRAMESIZE;
5255 unsigned char buf[TESTFRAMESIZE];
5256 bool rc = false;
5257 unsigned long flags;
5258
5259 struct tty_struct *oldtty = info->port.tty;
5260 u32 speed = info->params.clock_speed;
5261
5262 info->params.clock_speed = 3686400;
5263 info->port.tty = NULL;
5264
5265 /* assume failure */
5266 info->init_error = DiagStatus_DmaFailure;
5267
5268 /* build and send transmit frame */
5269 for (count = 0; count < TESTFRAMESIZE;++count)
5270 buf[count] = (unsigned char)count;
5271
5272 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5273
5274 /* program hardware for HDLC and enabled receiver */
5275 spin_lock_irqsave(&info->lock,flags);
5276 hdlc_mode(info);
5277 enable_loopback(info,1);
5278 rx_start(info);
5279 info->tx_count = count;
5280 tx_load_dma_buffer(info,buf,count);
5281 tx_start(info);
5282 spin_unlock_irqrestore(&info->lock,flags);
5283
5284 /* wait for receive complete */
5285 /* Set a timeout for waiting for interrupt. */
5286 for ( timeout = 100; timeout; --timeout ) {
5287 msleep_interruptible(10);
5288
5289 if (rx_get_frame(info)) {
5290 rc = true;
5291 break;
5292 }
5293 }
5294
5295 /* verify received frame length and contents */
5296 if (rc &&
5297 ( info->tmp_rx_buf_count != count ||
5298 memcmp(buf, info->tmp_rx_buf,count))) {
5299 rc = false;
5300 }
5301
5302 spin_lock_irqsave(&info->lock,flags);
5303 reset_adapter(info);
5304 spin_unlock_irqrestore(&info->lock,flags);
5305
5306 info->params.clock_speed = speed;
5307 info->port.tty = oldtty;
5308
5309 return rc;
5310 }
5311
5312 /* Perform diagnostics on hardware
5313 */
5314 static int adapter_test( SLMP_INFO *info )
5315 {
5316 unsigned long flags;
5317 if ( debug_level >= DEBUG_LEVEL_INFO )
5318 printk( "%s(%d):Testing device %s\n",
5319 __FILE__,__LINE__,info->device_name );
5320
5321 spin_lock_irqsave(&info->lock,flags);
5322 init_adapter(info);
5323 spin_unlock_irqrestore(&info->lock,flags);
5324
5325 info->port_array[0]->port_count = 0;
5326
5327 if ( register_test(info->port_array[0]) &&
5328 register_test(info->port_array[1])) {
5329
5330 info->port_array[0]->port_count = 2;
5331
5332 if ( register_test(info->port_array[2]) &&
5333 register_test(info->port_array[3]) )
5334 info->port_array[0]->port_count += 2;
5335 }
5336 else {
5337 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5338 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5339 return -ENODEV;
5340 }
5341
5342 if ( !irq_test(info->port_array[0]) ||
5343 !irq_test(info->port_array[1]) ||
5344 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5345 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5346 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5347 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5348 return -ENODEV;
5349 }
5350
5351 if (!loopback_test(info->port_array[0]) ||
5352 !loopback_test(info->port_array[1]) ||
5353 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5354 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5355 printk( "%s(%d):DMA test failure for device %s\n",
5356 __FILE__,__LINE__,info->device_name);
5357 return -ENODEV;
5358 }
5359
5360 if ( debug_level >= DEBUG_LEVEL_INFO )
5361 printk( "%s(%d):device %s passed diagnostics\n",
5362 __FILE__,__LINE__,info->device_name );
5363
5364 info->port_array[0]->init_error = 0;
5365 info->port_array[1]->init_error = 0;
5366 if ( info->port_count > 2 ) {
5367 info->port_array[2]->init_error = 0;
5368 info->port_array[3]->init_error = 0;
5369 }
5370
5371 return 0;
5372 }
5373
5374 /* Test the shared memory on a PCI adapter.
5375 */
5376 static bool memory_test(SLMP_INFO *info)
5377 {
5378 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5379 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5380 unsigned long count = ARRAY_SIZE(testval);
5381 unsigned long i;
5382 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5383 unsigned long * addr = (unsigned long *)info->memory_base;
5384
5385 /* Test data lines with test pattern at one location. */
5386
5387 for ( i = 0 ; i < count ; i++ ) {
5388 *addr = testval[i];
5389 if ( *addr != testval[i] )
5390 return false;
5391 }
5392
5393 /* Test address lines with incrementing pattern over */
5394 /* entire address range. */
5395
5396 for ( i = 0 ; i < limit ; i++ ) {
5397 *addr = i * 4;
5398 addr++;
5399 }
5400
5401 addr = (unsigned long *)info->memory_base;
5402
5403 for ( i = 0 ; i < limit ; i++ ) {
5404 if ( *addr != i * 4 )
5405 return false;
5406 addr++;
5407 }
5408
5409 memset( info->memory_base, 0, SCA_MEM_SIZE );
5410 return true;
5411 }
5412
5413 /* Load data into PCI adapter shared memory.
5414 *
5415 * The PCI9050 releases control of the local bus
5416 * after completing the current read or write operation.
5417 *
5418 * While the PCI9050 write FIFO not empty, the
5419 * PCI9050 treats all of the writes as a single transaction
5420 * and does not release the bus. This causes DMA latency problems
5421 * at high speeds when copying large data blocks to the shared memory.
5422 *
5423 * This function breaks a write into multiple transations by
5424 * interleaving a read which flushes the write FIFO and 'completes'
5425 * the write transation. This allows any pending DMA request to gain control
5426 * of the local bus in a timely fasion.
5427 */
5428 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5429 {
5430 /* A load interval of 16 allows for 4 32-bit writes at */
5431 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5432
5433 unsigned short interval = count / sca_pci_load_interval;
5434 unsigned short i;
5435
5436 for ( i = 0 ; i < interval ; i++ )
5437 {
5438 memcpy(dest, src, sca_pci_load_interval);
5439 read_status_reg(info);
5440 dest += sca_pci_load_interval;
5441 src += sca_pci_load_interval;
5442 }
5443
5444 memcpy(dest, src, count % sca_pci_load_interval);
5445 }
5446
5447 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5448 {
5449 int i;
5450 int linecount;
5451 if (xmit)
5452 printk("%s tx data:\n",info->device_name);
5453 else
5454 printk("%s rx data:\n",info->device_name);
5455
5456 while(count) {
5457 if (count > 16)
5458 linecount = 16;
5459 else
5460 linecount = count;
5461
5462 for(i=0;i<linecount;i++)
5463 printk("%02X ",(unsigned char)data[i]);
5464 for(;i<17;i++)
5465 printk(" ");
5466 for(i=0;i<linecount;i++) {
5467 if (data[i]>=040 && data[i]<=0176)
5468 printk("%c",data[i]);
5469 else
5470 printk(".");
5471 }
5472 printk("\n");
5473
5474 data += linecount;
5475 count -= linecount;
5476 }
5477 } /* end of trace_block() */
5478
5479 /* called when HDLC frame times out
5480 * update stats and do tx completion processing
5481 */
5482 static void tx_timeout(unsigned long context)
5483 {
5484 SLMP_INFO *info = (SLMP_INFO*)context;
5485 unsigned long flags;
5486
5487 if ( debug_level >= DEBUG_LEVEL_INFO )
5488 printk( "%s(%d):%s tx_timeout()\n",
5489 __FILE__,__LINE__,info->device_name);
5490 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5491 info->icount.txtimeout++;
5492 }
5493 spin_lock_irqsave(&info->lock,flags);
5494 info->tx_active = false;
5495 info->tx_count = info->tx_put = info->tx_get = 0;
5496
5497 spin_unlock_irqrestore(&info->lock,flags);
5498
5499 #if SYNCLINK_GENERIC_HDLC
5500 if (info->netcount)
5501 hdlcdev_tx_done(info);
5502 else
5503 #endif
5504 bh_transmit(info);
5505 }
5506
5507 /* called to periodically check the DSR/RI modem signal input status
5508 */
5509 static void status_timeout(unsigned long context)
5510 {
5511 u16 status = 0;
5512 SLMP_INFO *info = (SLMP_INFO*)context;
5513 unsigned long flags;
5514 unsigned char delta;
5515
5516
5517 spin_lock_irqsave(&info->lock,flags);
5518 get_signals(info);
5519 spin_unlock_irqrestore(&info->lock,flags);
5520
5521 /* check for DSR/RI state change */
5522
5523 delta = info->old_signals ^ info->serial_signals;
5524 info->old_signals = info->serial_signals;
5525
5526 if (delta & SerialSignal_DSR)
5527 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5528
5529 if (delta & SerialSignal_RI)
5530 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5531
5532 if (delta & SerialSignal_DCD)
5533 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5534
5535 if (delta & SerialSignal_CTS)
5536 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5537
5538 if (status)
5539 isr_io_pin(info,status);
5540
5541 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5542 }
5543
5544
5545 /* Register Access Routines -
5546 * All registers are memory mapped
5547 */
5548 #define CALC_REGADDR() \
5549 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5550 if (info->port_num > 1) \
5551 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5552 if ( info->port_num & 1) { \
5553 if (Addr > 0x7f) \
5554 RegAddr += 0x40; /* DMA access */ \
5555 else if (Addr > 0x1f && Addr < 0x60) \
5556 RegAddr += 0x20; /* MSCI access */ \
5557 }
5558
5559
5560 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5561 {
5562 CALC_REGADDR();
5563 return *RegAddr;
5564 }
5565 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5566 {
5567 CALC_REGADDR();
5568 *RegAddr = Value;
5569 }
5570
5571 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5572 {
5573 CALC_REGADDR();
5574 return *((u16 *)RegAddr);
5575 }
5576
5577 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5578 {
5579 CALC_REGADDR();
5580 *((u16 *)RegAddr) = Value;
5581 }
5582
5583 static unsigned char read_status_reg(SLMP_INFO * info)
5584 {
5585 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5586 return *RegAddr;
5587 }
5588
5589 static void write_control_reg(SLMP_INFO * info)
5590 {
5591 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5592 *RegAddr = info->port_array[0]->ctrlreg_value;
5593 }
5594
5595
5596 static int synclinkmp_init_one (struct pci_dev *dev,
5597 const struct pci_device_id *ent)
5598 {
5599 if (pci_enable_device(dev)) {
5600 printk("error enabling pci device %p\n", dev);
5601 return -EIO;
5602 }
5603 device_init( ++synclinkmp_adapter_count, dev );
5604 return 0;
5605 }
5606
5607 static void synclinkmp_remove_one (struct pci_dev *dev)
5608 {
5609 }
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