drivers/pinctrl/intel/pinctrl-intel.h

   1 /*
   2  * Core pinctrl/GPIO driver for Intel GPIO controllers
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef PINCTRL_INTEL_H
  14 #define PINCTRL_INTEL_H
  15
  16 struct pinctrl_pin_desc;
  17 struct platform_device;
  18 struct device;
  19
  20 /**
  21  * struct intel_pingroup - Description about group of pins
  22  * @name: Name of the groups
  23  * @pins: All pins in this group
  24  * @npins: Number of pins in this groups
  25  * @mode: Native mode in which the group is muxed out @pins
  26  */
  27 struct intel_pingroup {
  28         const char *name;
  29         const unsigned *pins;
  30         size_t npins;
  31         unsigned short mode;
  32 };
  33
  34 /**
  35  * struct intel_function - Description about a function
  36  * @name: Name of the function
  37  * @groups: An array of groups for this function
  38  * @ngroups: Number of groups in @groups
  39  */
  40 struct intel_function {
  41         const char *name;
  42         const char * const *groups;
  43         size_t ngroups;
  44 };
  45
  46 /**
  47  * struct intel_community - Intel pin community description
  48  * @barno: MMIO BAR number where registers for this community reside
  49  * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
  50  *                 then there is no support for owner.
  51  * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
  52  *                     locking is not supported.
  53  * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
  54  *                  is assumed that the host owns the pin (rather than
  55  *                  ACPI).
  56  * @ie_offset: Register offset of GPI_IE from @regs.
  57  * @pin_base: Starting pin of pins in this community
  58  * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
  59  *            HOSTSW_OWN,  GPI_IS, GPI_IE, etc.
  60  * @npins: Number of pins in this community
  61  * @features: Additional features supported by the hardware
  62  * @regs: Community specific common registers (reserved for core driver)
  63  * @pad_regs: Community specific pad registers (reserved for core driver)
  64  * @ngpps: Number of groups (hw groups) in this community (reserved for
  65  *         core driver)
  66  */
  67 struct intel_community {
  68         unsigned barno;
  69         unsigned padown_offset;
  70         unsigned padcfglock_offset;
  71         unsigned hostown_offset;
  72         unsigned ie_offset;
  73         unsigned pin_base;
  74         unsigned gpp_size;
  75         size_t npins;
  76         unsigned features;
  77         void __iomem *regs;
  78         void __iomem *pad_regs;
  79         size_t ngpps;
  80 };
  81
  82 /* Additional features supported by the hardware */
  83 #define PINCTRL_FEATURE_DEBOUNCE        BIT(0)
  84 #define PINCTRL_FEATURE_1K_PD           BIT(1)
  85
  86 #define PIN_GROUP(n, p, m)                      \
  87         {                                       \
  88                 .name = (n),                    \
  89                 .pins = (p),                    \
  90                 .npins = ARRAY_SIZE((p)),       \
  91                 .mode = (m),                    \
  92         }
  93
  94 #define FUNCTION(n, g)                          \
  95         {                                       \
  96                 .name = (n),                    \
  97                 .groups = (g),                  \
  98                 .ngroups = ARRAY_SIZE((g)),     \
  99         }
 100
 101 /**
 102  * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
 103  * @uid: ACPI _UID for the probe driver use if needed
 104  * @pins: Array if pins this pinctrl controls
 105  * @npins: Number of pins in the array
 106  * @groups: Array of pin groups
 107  * @ngroups: Number of groups in the array
 108  * @functions: Array of functions
 109  * @nfunctions: Number of functions in the array
 110  * @communities: Array of communities this pinctrl handles
 111  * @ncommunities: Number of communities in the array
 112  *
 113  * The @communities is used as a template by the core driver. It will make
 114  * copy of all communities and fill in rest of the information.
 115  */
 116 struct intel_pinctrl_soc_data {
 117         const char *uid;
 118         const struct pinctrl_pin_desc *pins;
 119         size_t npins;
 120         const struct intel_pingroup *groups;
 121         size_t ngroups;
 122         const struct intel_function *functions;
 123         size_t nfunctions;
 124         const struct intel_community *communities;
 125         size_t ncommunities;
 126 };
 127
 128 int intel_pinctrl_probe(struct platform_device *pdev,
 129                         const struct intel_pinctrl_soc_data *soc_data);
 130 #ifdef CONFIG_PM_SLEEP
 131 int intel_pinctrl_suspend(struct device *dev);
 132 int intel_pinctrl_resume(struct device *dev);
 133 #endif
 134
 135 #endif /* PINCTRL_INTEL_H */