2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/platform_data/sh_ipmmu.h>
37 #include <mach/dma-register.h>
38 #include <mach/hardware.h>
39 #include <mach/irqs.h>
40 #include <mach/sh7372.h>
41 #include <mach/common.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/time.h>
47 static struct map_desc sh7372_io_desc
[] __initdata
= {
48 /* create a 1:1 entity map for 0xe6xxxxxx
49 * used by CPGA, INTC and PFC.
52 .virtual = 0xe6000000,
53 .pfn
= __phys_to_pfn(0xe6000000),
55 .type
= MT_DEVICE_NONSHARED
59 void __init
sh7372_map_io(void)
61 iotable_init(sh7372_io_desc
, ARRAY_SIZE(sh7372_io_desc
));
65 static struct plat_sci_port scif0_platform_data
= {
66 .mapbase
= 0xe6c40000,
67 .flags
= UPF_BOOT_AUTOCONF
,
68 .scscr
= SCSCR_RE
| SCSCR_TE
,
69 .scbrr_algo_id
= SCBRR_ALGO_4
,
71 .irqs
= { evt2irq(0x0c00), evt2irq(0x0c00),
72 evt2irq(0x0c00), evt2irq(0x0c00) },
75 static struct platform_device scif0_device
= {
79 .platform_data
= &scif0_platform_data
,
84 static struct plat_sci_port scif1_platform_data
= {
85 .mapbase
= 0xe6c50000,
86 .flags
= UPF_BOOT_AUTOCONF
,
87 .scscr
= SCSCR_RE
| SCSCR_TE
,
88 .scbrr_algo_id
= SCBRR_ALGO_4
,
90 .irqs
= { evt2irq(0x0c20), evt2irq(0x0c20),
91 evt2irq(0x0c20), evt2irq(0x0c20) },
94 static struct platform_device scif1_device
= {
98 .platform_data
= &scif1_platform_data
,
103 static struct plat_sci_port scif2_platform_data
= {
104 .mapbase
= 0xe6c60000,
105 .flags
= UPF_BOOT_AUTOCONF
,
106 .scscr
= SCSCR_RE
| SCSCR_TE
,
107 .scbrr_algo_id
= SCBRR_ALGO_4
,
109 .irqs
= { evt2irq(0x0c40), evt2irq(0x0c40),
110 evt2irq(0x0c40), evt2irq(0x0c40) },
113 static struct platform_device scif2_device
= {
117 .platform_data
= &scif2_platform_data
,
122 static struct plat_sci_port scif3_platform_data
= {
123 .mapbase
= 0xe6c70000,
124 .flags
= UPF_BOOT_AUTOCONF
,
125 .scscr
= SCSCR_RE
| SCSCR_TE
,
126 .scbrr_algo_id
= SCBRR_ALGO_4
,
128 .irqs
= { evt2irq(0x0c60), evt2irq(0x0c60),
129 evt2irq(0x0c60), evt2irq(0x0c60) },
132 static struct platform_device scif3_device
= {
136 .platform_data
= &scif3_platform_data
,
141 static struct plat_sci_port scif4_platform_data
= {
142 .mapbase
= 0xe6c80000,
143 .flags
= UPF_BOOT_AUTOCONF
,
144 .scscr
= SCSCR_RE
| SCSCR_TE
,
145 .scbrr_algo_id
= SCBRR_ALGO_4
,
147 .irqs
= { evt2irq(0x0d20), evt2irq(0x0d20),
148 evt2irq(0x0d20), evt2irq(0x0d20) },
151 static struct platform_device scif4_device
= {
155 .platform_data
= &scif4_platform_data
,
160 static struct plat_sci_port scif5_platform_data
= {
161 .mapbase
= 0xe6cb0000,
162 .flags
= UPF_BOOT_AUTOCONF
,
163 .scscr
= SCSCR_RE
| SCSCR_TE
,
164 .scbrr_algo_id
= SCBRR_ALGO_4
,
166 .irqs
= { evt2irq(0x0d40), evt2irq(0x0d40),
167 evt2irq(0x0d40), evt2irq(0x0d40) },
170 static struct platform_device scif5_device
= {
174 .platform_data
= &scif5_platform_data
,
179 static struct plat_sci_port scif6_platform_data
= {
180 .mapbase
= 0xe6c30000,
181 .flags
= UPF_BOOT_AUTOCONF
,
182 .scscr
= SCSCR_RE
| SCSCR_TE
,
183 .scbrr_algo_id
= SCBRR_ALGO_4
,
185 .irqs
= { evt2irq(0x0d60), evt2irq(0x0d60),
186 evt2irq(0x0d60), evt2irq(0x0d60) },
189 static struct platform_device scif6_device
= {
193 .platform_data
= &scif6_platform_data
,
198 static struct sh_timer_config cmt2_platform_data
= {
200 .channel_offset
= 0x40,
202 .clockevent_rating
= 125,
203 .clocksource_rating
= 125,
206 static struct resource cmt2_resources
[] = {
211 .flags
= IORESOURCE_MEM
,
214 .start
= evt2irq(0x0b80), /* CMT2 */
215 .flags
= IORESOURCE_IRQ
,
219 static struct platform_device cmt2_device
= {
223 .platform_data
= &cmt2_platform_data
,
225 .resource
= cmt2_resources
,
226 .num_resources
= ARRAY_SIZE(cmt2_resources
),
230 static struct sh_timer_config tmu00_platform_data
= {
232 .channel_offset
= 0x4,
234 .clockevent_rating
= 200,
237 static struct resource tmu00_resources
[] = {
242 .flags
= IORESOURCE_MEM
,
245 .start
= intcs_evt2irq(0xe80), /* TMU_TUNI0 */
246 .flags
= IORESOURCE_IRQ
,
250 static struct platform_device tmu00_device
= {
254 .platform_data
= &tmu00_platform_data
,
256 .resource
= tmu00_resources
,
257 .num_resources
= ARRAY_SIZE(tmu00_resources
),
260 static struct sh_timer_config tmu01_platform_data
= {
262 .channel_offset
= 0x10,
264 .clocksource_rating
= 200,
267 static struct resource tmu01_resources
[] = {
272 .flags
= IORESOURCE_MEM
,
275 .start
= intcs_evt2irq(0xea0), /* TMU_TUNI1 */
276 .flags
= IORESOURCE_IRQ
,
280 static struct platform_device tmu01_device
= {
284 .platform_data
= &tmu01_platform_data
,
286 .resource
= tmu01_resources
,
287 .num_resources
= ARRAY_SIZE(tmu01_resources
),
291 static struct resource iic0_resources
[] = {
295 .end
= 0xFFF20425 - 1,
296 .flags
= IORESOURCE_MEM
,
299 .start
= intcs_evt2irq(0xe00), /* IIC0_ALI0 */
300 .end
= intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
301 .flags
= IORESOURCE_IRQ
,
305 static struct platform_device iic0_device
= {
306 .name
= "i2c-sh_mobile",
307 .id
= 0, /* "i2c0" clock */
308 .num_resources
= ARRAY_SIZE(iic0_resources
),
309 .resource
= iic0_resources
,
312 static struct resource iic1_resources
[] = {
316 .end
= 0xE6C20425 - 1,
317 .flags
= IORESOURCE_MEM
,
320 .start
= evt2irq(0x780), /* IIC1_ALI1 */
321 .end
= evt2irq(0x7e0), /* IIC1_DTEI1 */
322 .flags
= IORESOURCE_IRQ
,
326 static struct platform_device iic1_device
= {
327 .name
= "i2c-sh_mobile",
328 .id
= 1, /* "i2c1" clock */
329 .num_resources
= ARRAY_SIZE(iic1_resources
),
330 .resource
= iic1_resources
,
334 static const struct sh_dmae_slave_config sh7372_dmae_slaves
[] = {
336 .slave_id
= SHDMA_SLAVE_SCIF0_TX
,
338 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
341 .slave_id
= SHDMA_SLAVE_SCIF0_RX
,
343 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
346 .slave_id
= SHDMA_SLAVE_SCIF1_TX
,
348 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
351 .slave_id
= SHDMA_SLAVE_SCIF1_RX
,
353 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
356 .slave_id
= SHDMA_SLAVE_SCIF2_TX
,
358 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
361 .slave_id
= SHDMA_SLAVE_SCIF2_RX
,
363 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
366 .slave_id
= SHDMA_SLAVE_SCIF3_TX
,
368 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
371 .slave_id
= SHDMA_SLAVE_SCIF3_RX
,
373 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
376 .slave_id
= SHDMA_SLAVE_SCIF4_TX
,
378 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
381 .slave_id
= SHDMA_SLAVE_SCIF4_RX
,
383 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
386 .slave_id
= SHDMA_SLAVE_SCIF5_TX
,
388 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
391 .slave_id
= SHDMA_SLAVE_SCIF5_RX
,
393 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
396 .slave_id
= SHDMA_SLAVE_SCIF6_TX
,
398 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
401 .slave_id
= SHDMA_SLAVE_SCIF6_RX
,
403 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
406 .slave_id
= SHDMA_SLAVE_FLCTL0_TX
,
408 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
411 .slave_id
= SHDMA_SLAVE_FLCTL0_RX
,
413 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
416 .slave_id
= SHDMA_SLAVE_FLCTL1_TX
,
418 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
421 .slave_id
= SHDMA_SLAVE_FLCTL1_RX
,
423 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
426 .slave_id
= SHDMA_SLAVE_SDHI0_TX
,
428 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
431 .slave_id
= SHDMA_SLAVE_SDHI0_RX
,
433 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
436 .slave_id
= SHDMA_SLAVE_SDHI1_TX
,
438 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
441 .slave_id
= SHDMA_SLAVE_SDHI1_RX
,
443 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
446 .slave_id
= SHDMA_SLAVE_SDHI2_TX
,
448 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
451 .slave_id
= SHDMA_SLAVE_SDHI2_RX
,
453 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
456 .slave_id
= SHDMA_SLAVE_FSIA_TX
,
458 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
461 .slave_id
= SHDMA_SLAVE_FSIA_RX
,
463 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
466 .slave_id
= SHDMA_SLAVE_MMCIF_TX
,
468 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
471 .slave_id
= SHDMA_SLAVE_MMCIF_RX
,
473 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
478 #define SH7372_CHCLR (0x220 - 0x20)
480 static const struct sh_dmae_channel sh7372_dmae_channels
[] = {
485 .chclr_offset
= SH7372_CHCLR
+ 0,
490 .chclr_offset
= SH7372_CHCLR
+ 0x10,
495 .chclr_offset
= SH7372_CHCLR
+ 0x20,
500 .chclr_offset
= SH7372_CHCLR
+ 0x30,
505 .chclr_offset
= SH7372_CHCLR
+ 0x50,
510 .chclr_offset
= SH7372_CHCLR
+ 0x60,
514 static struct sh_dmae_pdata dma_platform_data
= {
515 .slave
= sh7372_dmae_slaves
,
516 .slave_num
= ARRAY_SIZE(sh7372_dmae_slaves
),
517 .channel
= sh7372_dmae_channels
,
518 .channel_num
= ARRAY_SIZE(sh7372_dmae_channels
),
519 .ts_low_shift
= TS_LOW_SHIFT
,
520 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
521 .ts_high_shift
= TS_HI_SHIFT
,
522 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
523 .ts_shift
= dma_ts_shift
,
524 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
525 .dmaor_init
= DMAOR_DME
,
529 /* Resource order important! */
530 static struct resource sh7372_dmae0_resources
[] = {
532 /* Channel registers and DMAOR */
535 .flags
= IORESOURCE_MEM
,
541 .flags
= IORESOURCE_MEM
,
545 .start
= evt2irq(0x20c0),
546 .end
= evt2irq(0x20c0),
547 .flags
= IORESOURCE_IRQ
,
550 /* IRQ for channels 0-5 */
551 .start
= evt2irq(0x2000),
552 .end
= evt2irq(0x20a0),
553 .flags
= IORESOURCE_IRQ
,
557 /* Resource order important! */
558 static struct resource sh7372_dmae1_resources
[] = {
560 /* Channel registers and DMAOR */
563 .flags
= IORESOURCE_MEM
,
569 .flags
= IORESOURCE_MEM
,
573 .start
= evt2irq(0x21c0),
574 .end
= evt2irq(0x21c0),
575 .flags
= IORESOURCE_IRQ
,
578 /* IRQ for channels 0-5 */
579 .start
= evt2irq(0x2100),
580 .end
= evt2irq(0x21a0),
581 .flags
= IORESOURCE_IRQ
,
585 /* Resource order important! */
586 static struct resource sh7372_dmae2_resources
[] = {
588 /* Channel registers and DMAOR */
591 .flags
= IORESOURCE_MEM
,
597 .flags
= IORESOURCE_MEM
,
601 .start
= evt2irq(0x22c0),
602 .end
= evt2irq(0x22c0),
603 .flags
= IORESOURCE_IRQ
,
606 /* IRQ for channels 0-5 */
607 .start
= evt2irq(0x2200),
608 .end
= evt2irq(0x22a0),
609 .flags
= IORESOURCE_IRQ
,
613 static struct platform_device dma0_device
= {
614 .name
= "sh-dma-engine",
616 .resource
= sh7372_dmae0_resources
,
617 .num_resources
= ARRAY_SIZE(sh7372_dmae0_resources
),
619 .platform_data
= &dma_platform_data
,
623 static struct platform_device dma1_device
= {
624 .name
= "sh-dma-engine",
626 .resource
= sh7372_dmae1_resources
,
627 .num_resources
= ARRAY_SIZE(sh7372_dmae1_resources
),
629 .platform_data
= &dma_platform_data
,
633 static struct platform_device dma2_device
= {
634 .name
= "sh-dma-engine",
636 .resource
= sh7372_dmae2_resources
,
637 .num_resources
= ARRAY_SIZE(sh7372_dmae2_resources
),
639 .platform_data
= &dma_platform_data
,
646 static const struct sh_dmae_channel sh7372_usb_dmae_channels
[] = {
655 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves
[] = {
657 .slave_id
= SHDMA_SLAVE_USB0_TX
,
658 .chcr
= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE
),
660 .slave_id
= SHDMA_SLAVE_USB0_RX
,
661 .chcr
= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE
),
665 static struct sh_dmae_pdata usb_dma0_platform_data
= {
666 .slave
= sh7372_usb_dmae0_slaves
,
667 .slave_num
= ARRAY_SIZE(sh7372_usb_dmae0_slaves
),
668 .channel
= sh7372_usb_dmae_channels
,
669 .channel_num
= ARRAY_SIZE(sh7372_usb_dmae_channels
),
670 .ts_low_shift
= USBTS_LOW_SHIFT
,
671 .ts_low_mask
= USBTS_LOW_BIT
<< USBTS_LOW_SHIFT
,
672 .ts_high_shift
= USBTS_HI_SHIFT
,
673 .ts_high_mask
= USBTS_HI_BIT
<< USBTS_HI_SHIFT
,
674 .ts_shift
= dma_usbts_shift
,
675 .ts_shift_num
= ARRAY_SIZE(dma_usbts_shift
),
676 .dmaor_init
= DMAOR_DME
,
678 .chcr_ie_bit
= 1 << 5,
685 static struct resource sh7372_usb_dmae0_resources
[] = {
687 /* Channel registers and DMAOR */
689 .end
= 0xe68a0064 - 1,
690 .flags
= IORESOURCE_MEM
,
695 .end
= 0xe68a0014 - 1,
696 .flags
= IORESOURCE_MEM
,
699 /* IRQ for channels */
700 .start
= evt2irq(0x0a00),
701 .end
= evt2irq(0x0a00),
702 .flags
= IORESOURCE_IRQ
,
706 static struct platform_device usb_dma0_device
= {
707 .name
= "sh-dma-engine",
709 .resource
= sh7372_usb_dmae0_resources
,
710 .num_resources
= ARRAY_SIZE(sh7372_usb_dmae0_resources
),
712 .platform_data
= &usb_dma0_platform_data
,
717 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves
[] = {
719 .slave_id
= SHDMA_SLAVE_USB1_TX
,
720 .chcr
= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE
),
722 .slave_id
= SHDMA_SLAVE_USB1_RX
,
723 .chcr
= USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE
),
727 static struct sh_dmae_pdata usb_dma1_platform_data
= {
728 .slave
= sh7372_usb_dmae1_slaves
,
729 .slave_num
= ARRAY_SIZE(sh7372_usb_dmae1_slaves
),
730 .channel
= sh7372_usb_dmae_channels
,
731 .channel_num
= ARRAY_SIZE(sh7372_usb_dmae_channels
),
732 .ts_low_shift
= USBTS_LOW_SHIFT
,
733 .ts_low_mask
= USBTS_LOW_BIT
<< USBTS_LOW_SHIFT
,
734 .ts_high_shift
= USBTS_HI_SHIFT
,
735 .ts_high_mask
= USBTS_HI_BIT
<< USBTS_HI_SHIFT
,
736 .ts_shift
= dma_usbts_shift
,
737 .ts_shift_num
= ARRAY_SIZE(dma_usbts_shift
),
738 .dmaor_init
= DMAOR_DME
,
740 .chcr_ie_bit
= 1 << 5,
747 static struct resource sh7372_usb_dmae1_resources
[] = {
749 /* Channel registers and DMAOR */
751 .end
= 0xe68c0064 - 1,
752 .flags
= IORESOURCE_MEM
,
757 .end
= 0xe68c0014 - 1,
758 .flags
= IORESOURCE_MEM
,
761 /* IRQ for channels */
762 .start
= evt2irq(0x1d00),
763 .end
= evt2irq(0x1d00),
764 .flags
= IORESOURCE_IRQ
,
768 static struct platform_device usb_dma1_device
= {
769 .name
= "sh-dma-engine",
771 .resource
= sh7372_usb_dmae1_resources
,
772 .num_resources
= ARRAY_SIZE(sh7372_usb_dmae1_resources
),
774 .platform_data
= &usb_dma1_platform_data
,
779 static struct uio_info vpu_platform_data
= {
782 .irq
= intcs_evt2irq(0x980),
785 static struct resource vpu_resources
[] = {
790 .flags
= IORESOURCE_MEM
,
794 static struct platform_device vpu_device
= {
795 .name
= "uio_pdrv_genirq",
798 .platform_data
= &vpu_platform_data
,
800 .resource
= vpu_resources
,
801 .num_resources
= ARRAY_SIZE(vpu_resources
),
805 static struct uio_info veu0_platform_data
= {
808 .irq
= intcs_evt2irq(0x700),
811 static struct resource veu0_resources
[] = {
816 .flags
= IORESOURCE_MEM
,
820 static struct platform_device veu0_device
= {
821 .name
= "uio_pdrv_genirq",
824 .platform_data
= &veu0_platform_data
,
826 .resource
= veu0_resources
,
827 .num_resources
= ARRAY_SIZE(veu0_resources
),
831 static struct uio_info veu1_platform_data
= {
834 .irq
= intcs_evt2irq(0x720),
837 static struct resource veu1_resources
[] = {
842 .flags
= IORESOURCE_MEM
,
846 static struct platform_device veu1_device
= {
847 .name
= "uio_pdrv_genirq",
850 .platform_data
= &veu1_platform_data
,
852 .resource
= veu1_resources
,
853 .num_resources
= ARRAY_SIZE(veu1_resources
),
857 static struct uio_info veu2_platform_data
= {
860 .irq
= intcs_evt2irq(0x740),
863 static struct resource veu2_resources
[] = {
868 .flags
= IORESOURCE_MEM
,
872 static struct platform_device veu2_device
= {
873 .name
= "uio_pdrv_genirq",
876 .platform_data
= &veu2_platform_data
,
878 .resource
= veu2_resources
,
879 .num_resources
= ARRAY_SIZE(veu2_resources
),
883 static struct uio_info veu3_platform_data
= {
886 .irq
= intcs_evt2irq(0x760),
889 static struct resource veu3_resources
[] = {
894 .flags
= IORESOURCE_MEM
,
898 static struct platform_device veu3_device
= {
899 .name
= "uio_pdrv_genirq",
902 .platform_data
= &veu3_platform_data
,
904 .resource
= veu3_resources
,
905 .num_resources
= ARRAY_SIZE(veu3_resources
),
909 static struct uio_info jpu_platform_data
= {
912 .irq
= intcs_evt2irq(0x560),
915 static struct resource jpu_resources
[] = {
920 .flags
= IORESOURCE_MEM
,
924 static struct platform_device jpu_device
= {
925 .name
= "uio_pdrv_genirq",
928 .platform_data
= &jpu_platform_data
,
930 .resource
= jpu_resources
,
931 .num_resources
= ARRAY_SIZE(jpu_resources
),
935 static struct uio_info spu0_platform_data
= {
938 .irq
= evt2irq(0x1800),
941 static struct resource spu0_resources
[] = {
946 .flags
= IORESOURCE_MEM
,
950 static struct platform_device spu0_device
= {
951 .name
= "uio_pdrv_genirq",
954 .platform_data
= &spu0_platform_data
,
956 .resource
= spu0_resources
,
957 .num_resources
= ARRAY_SIZE(spu0_resources
),
961 static struct uio_info spu1_platform_data
= {
964 .irq
= evt2irq(0x1820),
967 static struct resource spu1_resources
[] = {
972 .flags
= IORESOURCE_MEM
,
976 static struct platform_device spu1_device
= {
977 .name
= "uio_pdrv_genirq",
980 .platform_data
= &spu1_platform_data
,
982 .resource
= spu1_resources
,
983 .num_resources
= ARRAY_SIZE(spu1_resources
),
986 /* IPMMUI (an IPMMU module for ICB/LMB) */
987 static struct resource ipmmu_resources
[] = {
992 .flags
= IORESOURCE_MEM
,
996 static const char * const ipmmu_dev_names
[] = {
997 "sh_mobile_lcdc_fb.0",
998 "sh_mobile_lcdc_fb.1",
1000 "uio_pdrv_genirq.0",
1001 "uio_pdrv_genirq.1",
1002 "uio_pdrv_genirq.2",
1003 "uio_pdrv_genirq.3",
1004 "uio_pdrv_genirq.4",
1005 "uio_pdrv_genirq.5",
1008 static struct shmobile_ipmmu_platform_data ipmmu_platform_data
= {
1009 .dev_names
= ipmmu_dev_names
,
1010 .num_dev_names
= ARRAY_SIZE(ipmmu_dev_names
),
1013 static struct platform_device ipmmu_device
= {
1017 .platform_data
= &ipmmu_platform_data
,
1019 .resource
= ipmmu_resources
,
1020 .num_resources
= ARRAY_SIZE(ipmmu_resources
),
1023 static struct platform_device
*sh7372_early_devices
[] __initdata
= {
1037 static struct platform_device
*sh7372_late_devices
[] __initdata
= {
1055 void __init
sh7372_add_standard_devices(void)
1057 struct pm_domain_device domain_devices
[] = {
1058 { "A3RV", &vpu_device
, },
1059 { "A4MP", &spu0_device
, },
1060 { "A4MP", &spu1_device
, },
1061 { "A3SP", &scif0_device
, },
1062 { "A3SP", &scif1_device
, },
1063 { "A3SP", &scif2_device
, },
1064 { "A3SP", &scif3_device
, },
1065 { "A3SP", &scif4_device
, },
1066 { "A3SP", &scif5_device
, },
1067 { "A3SP", &scif6_device
, },
1068 { "A3SP", &iic1_device
, },
1069 { "A3SP", &dma0_device
, },
1070 { "A3SP", &dma1_device
, },
1071 { "A3SP", &dma2_device
, },
1072 { "A3SP", &usb_dma0_device
, },
1073 { "A3SP", &usb_dma1_device
, },
1074 { "A4R", &iic0_device
, },
1075 { "A4R", &veu0_device
, },
1076 { "A4R", &veu1_device
, },
1077 { "A4R", &veu2_device
, },
1078 { "A4R", &veu3_device
, },
1079 { "A4R", &jpu_device
, },
1080 { "A4R", &tmu00_device
, },
1081 { "A4R", &tmu01_device
, },
1084 sh7372_init_pm_domains();
1086 platform_add_devices(sh7372_early_devices
,
1087 ARRAY_SIZE(sh7372_early_devices
));
1089 platform_add_devices(sh7372_late_devices
,
1090 ARRAY_SIZE(sh7372_late_devices
));
1092 rmobile_add_devices_to_domains(domain_devices
,
1093 ARRAY_SIZE(domain_devices
));
1096 static void __init
sh7372_earlytimer_init(void)
1098 sh7372_clock_init();
1099 shmobile_earlytimer_init();
1102 void __init
sh7372_add_early_devices(void)
1104 early_platform_add_devices(sh7372_early_devices
,
1105 ARRAY_SIZE(sh7372_early_devices
));
1107 /* setup early console here as well */
1108 shmobile_setup_console();
1110 /* override timer setup with soc-specific code */
1111 shmobile_timer
.init
= sh7372_earlytimer_init
;
1114 #ifdef CONFIG_USE_OF
1116 void __init
sh7372_add_early_devices_dt(void)
1118 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1120 early_platform_add_devices(sh7372_early_devices
,
1121 ARRAY_SIZE(sh7372_early_devices
));
1123 /* setup early console here as well */
1124 shmobile_setup_console();
1127 static const struct of_dev_auxdata sh7372_auxdata_lookup
[] __initconst
= {
1131 void __init
sh7372_add_standard_devices_dt(void)
1133 /* clocks are setup late during boot in the case of DT */
1134 sh7372_clock_init();
1136 platform_add_devices(sh7372_early_devices
,
1137 ARRAY_SIZE(sh7372_early_devices
));
1139 of_platform_populate(NULL
, of_default_bus_match_table
,
1140 sh7372_auxdata_lookup
, NULL
);
1143 static const char *sh7372_boards_compat_dt
[] __initdata
= {
1148 DT_MACHINE_START(SH7372_DT
, "Generic SH7372 (Flattened Device Tree)")
1149 .map_io
= sh7372_map_io
,
1150 .init_early
= sh7372_add_early_devices_dt
,
1151 .nr_irqs
= NR_IRQS_LEGACY
,
1152 .init_irq
= sh7372_init_irq
,
1153 .handle_irq
= shmobile_handle_irq_intc
,
1154 .init_machine
= sh7372_add_standard_devices_dt
,
1155 .timer
= &shmobile_timer
,
1156 .dt_compat
= sh7372_boards_compat_dt
,
1159 #endif /* CONFIG_USE_OF */