5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 Support for Broadcom's BCMRing platform.
331 bool "Cirrus Logic CLPS711x/EP721x-based"
333 select ARCH_USES_GETTIMEOFFSET
335 Support for Cirrus Logic 711x/721x based boards.
338 bool "Cavium Networks CNS3XXX family"
340 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select PCI_DOMAINS if PCI
344 select NO_MACH_MEMORY_H
346 Support for Cavium Networks CNS3XXX platform.
349 bool "Cortina Systems Gemini"
351 select ARCH_REQUIRE_GPIOLIB
352 select ARCH_USES_GETTIMEOFFSET
353 select NO_MACH_MEMORY_H
355 Support for the Cortina Systems Gemini family SoCs
358 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
362 select GENERIC_CLOCKEVENTS
364 select GENERIC_IRQ_CHIP
368 Support for CSR SiRFSoC ARM Cortex A9 Platform
375 select ARCH_USES_GETTIMEOFFSET
377 This is an evaluation board for the StrongARM processor available
378 from Digital. It has limited hardware on-board, including an
379 Ethernet interface, two PCMCIA sockets, two serial ports and a
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_HAS_HOLES_MEMORYMODEL
390 select ARCH_USES_GETTIMEOFFSET
392 This enables support for the Cirrus EP93xx series of CPUs.
394 config ARCH_FOOTBRIDGE
398 select GENERIC_CLOCKEVENTS
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Freescale MXC/iMX-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
409 select GENERIC_IRQ_CHIP
410 select HAVE_SCHED_CLOCK
412 Support for Freescale MXC/iMX-based family of processors
415 bool "Freescale MXS-based"
416 select GENERIC_CLOCKEVENTS
417 select ARCH_REQUIRE_GPIOLIB
420 select NO_MACH_MEMORY_H
422 Support for Freescale MXS-based family of processors
425 bool "Hilscher NetX based"
429 select GENERIC_CLOCKEVENTS
430 select NO_MACH_MEMORY_H
432 This enables support for systems based on the Hilscher NetX Soc
435 bool "Hynix HMS720x-based"
438 select ARCH_USES_GETTIMEOFFSET
439 select NO_MACH_MEMORY_H
441 This enables support for systems based on the Hynix HMS720x
449 select ARCH_SUPPORTS_MSI
452 Support for Intel's IOP13XX (XScale) family of processors.
460 select ARCH_REQUIRE_GPIOLIB
461 select NO_MACH_MEMORY_H
463 Support for Intel's 80219 and IOP32X (XScale) family of
472 select ARCH_REQUIRE_GPIOLIB
473 select NO_MACH_MEMORY_H
475 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_USES_GETTIMEOFFSET
484 Support for Intel's IXP23xx (XScale) family of processors.
487 bool "IXP2400/2800-based"
491 select ARCH_USES_GETTIMEOFFSET
493 Support for Intel's IXP2400/2800 (XScale) family of processors.
501 select GENERIC_CLOCKEVENTS
502 select HAVE_SCHED_CLOCK
503 select MIGHT_HAVE_PCI
504 select DMABOUNCE if PCI
505 select NO_MACH_MEMORY_H
507 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
516 select NO_MACH_MEMORY_H
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
527 select NO_MACH_MEMORY_H
529 Support for the following Marvell Kirkwood series SoCs:
530 88F6180, 88F6192 and 88F6281.
536 select ARCH_REQUIRE_GPIOLIB
539 select USB_ARCH_HAS_OHCI
542 select GENERIC_CLOCKEVENTS
543 select NO_MACH_MEMORY_H
545 Support for the NXP LPC32XX family of processors
548 bool "Marvell MV78xx0"
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
554 select NO_MACH_MEMORY_H
556 Support for the following Marvell MV78xx0 series SoCs:
564 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
567 select NO_MACH_MEMORY_H
569 Support for the following Marvell Orion 5x series SoCs:
570 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
571 Orion-2 (5281), Orion-1-90 (6183).
574 bool "Marvell PXA168/910/MMP2"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select HAVE_SCHED_CLOCK
583 select NO_MACH_MEMORY_H
585 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
588 bool "Micrel/Kendin KS8695"
590 select ARCH_REQUIRE_GPIOLIB
591 select ARCH_USES_GETTIMEOFFSET
593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
594 System-on-Chip devices.
597 bool "Nuvoton W90X900 CPU"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NO_MACH_MEMORY_H
605 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
606 At present, the w90x900 has been renamed nuc900, regarding
607 the ARM series product line, you can login the following
608 link address to know more.
610 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
611 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
614 bool "Nuvoton NUC93X CPU"
617 select NO_MACH_MEMORY_H
619 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
620 low-power and high performance MPEG-4/JPEG multimedia controller chip.
627 select GENERIC_CLOCKEVENTS
630 select HAVE_SCHED_CLOCK
631 select ARCH_HAS_CPUFREQ
632 select NO_MACH_MEMORY_H
634 This enables support for NVIDIA Tegra based systems (Tegra APX,
635 Tegra 6xx and Tegra 2 series).
638 bool "Philips Nexperia PNX4008 Mobile"
641 select ARCH_USES_GETTIMEOFFSET
642 select NO_MACH_MEMORY_H
644 This enables support for Philips PNX4008 mobile platform.
647 bool "PXA2xx/PXA3xx-based"
650 select ARCH_HAS_CPUFREQ
653 select ARCH_REQUIRE_GPIOLIB
654 select GENERIC_CLOCKEVENTS
655 select HAVE_SCHED_CLOCK
660 select MULTI_IRQ_HANDLER
662 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
667 select GENERIC_CLOCKEVENTS
668 select ARCH_REQUIRE_GPIOLIB
670 select NO_MACH_MEMORY_H
672 Support for Qualcomm MSM/QSD based systems. This runs on the
673 apps processor of the MSM/QSD and depends on a shared memory
674 interface to the modem processor which runs the baseband
675 stack and controls some vital subsystems
676 (clock and power control, etc).
679 bool "Renesas SH-Mobile / R-Mobile"
682 select HAVE_MACH_CLKDEV
683 select GENERIC_CLOCKEVENTS
686 select MULTI_IRQ_HANDLER
687 select PM_GENERIC_DOMAINS if PM
689 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
696 select ARCH_MAY_HAVE_PC_FDC
697 select HAVE_PATA_PLATFORM
700 select ARCH_SPARSEMEM_ENABLE
701 select ARCH_USES_GETTIMEOFFSET
703 On the Acorn Risc-PC, Linux can support the internal IDE disk and
704 CD-ROM interface, serial and parallel port, and the floppy drive.
711 select ARCH_SPARSEMEM_ENABLE
713 select ARCH_HAS_CPUFREQ
715 select GENERIC_CLOCKEVENTS
717 select HAVE_SCHED_CLOCK
719 select ARCH_REQUIRE_GPIOLIB
721 Support for StrongARM 11x0 based boards.
724 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
726 select ARCH_HAS_CPUFREQ
729 select ARCH_USES_GETTIMEOFFSET
730 select HAVE_S3C2410_I2C if I2C
731 select NO_MACH_MEMORY_H
733 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
734 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
735 the Samsung SMDK2410 development board (and derivatives).
737 Note, the S3C2416 and the S3C2450 are so close that they even share
738 the same SoC ID code. This means that there is no separate machine
739 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
742 bool "Samsung S3C64XX"
749 select ARCH_USES_GETTIMEOFFSET
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
752 select SAMSUNG_CLKSRC
753 select SAMSUNG_IRQ_VIC_TIMER
754 select SAMSUNG_IRQ_UART
755 select S3C_GPIO_TRACK
756 select S3C_GPIO_PULL_UPDOWN
757 select S3C_GPIO_CFG_S3C24XX
758 select S3C_GPIO_CFG_S3C64XX
760 select USB_ARCH_HAS_OHCI
761 select SAMSUNG_GPIOLIB_4BIT
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 Samsung S3C64XX series based systems
768 bool "Samsung S5P6440 S5P6450"
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select GENERIC_CLOCKEVENTS
776 select HAVE_SCHED_CLOCK
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C_RTC if RTC_CLASS
780 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
784 bool "Samsung S5PC100"
789 select ARM_L1_CACHE_SHIFT_6
790 select ARCH_USES_GETTIMEOFFSET
791 select HAVE_S3C2410_I2C if I2C
792 select HAVE_S3C_RTC if RTC_CLASS
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select NO_MACH_MEMORY_H
796 Samsung S5PC100 series based systems
799 bool "Samsung S5PV210/S5PC110"
801 select ARCH_SPARSEMEM_ENABLE
802 select ARCH_HAS_HOLES_MEMORYMODEL
807 select ARM_L1_CACHE_SHIFT_6
808 select ARCH_HAS_CPUFREQ
809 select GENERIC_CLOCKEVENTS
810 select HAVE_SCHED_CLOCK
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C_RTC if RTC_CLASS
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 Samsung S5PV210/S5PC110 series based systems
818 bool "Samsung EXYNOS4"
820 select ARCH_SPARSEMEM_ENABLE
821 select ARCH_HAS_HOLES_MEMORYMODEL
825 select ARCH_HAS_CPUFREQ
826 select GENERIC_CLOCKEVENTS
827 select HAVE_S3C_RTC if RTC_CLASS
828 select HAVE_S3C2410_I2C if I2C
829 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 Samsung EXYNOS4 series based systems
840 select ARCH_USES_GETTIMEOFFSET
842 Support for the StrongARM based Digital DNARD machine, also known
843 as "Shark" (<http://www.shark-linux.de/shark.html>).
846 bool "Telechips TCC ARM926-based systems"
851 select GENERIC_CLOCKEVENTS
852 select NO_MACH_MEMORY_H
854 Support for Telechips TCC ARM926-based systems.
857 bool "ST-Ericsson U300 Series"
861 select HAVE_SCHED_CLOCK
865 select GENERIC_CLOCKEVENTS
867 select HAVE_MACH_CLKDEV
870 Support for ST-Ericsson U300 series mobile platforms.
873 bool "ST-Ericsson U8500 Series"
876 select GENERIC_CLOCKEVENTS
878 select ARCH_REQUIRE_GPIOLIB
879 select ARCH_HAS_CPUFREQ
880 select NO_MACH_MEMORY_H
882 Support for ST-Ericsson's Ux500 architecture
885 bool "STMicroelectronics Nomadik"
890 select GENERIC_CLOCKEVENTS
891 select ARCH_REQUIRE_GPIOLIB
892 select NO_MACH_MEMORY_H
894 Support for the Nomadik platform by ST-Ericsson
898 select GENERIC_CLOCKEVENTS
899 select ARCH_REQUIRE_GPIOLIB
903 select GENERIC_ALLOCATOR
904 select GENERIC_IRQ_CHIP
905 select ARCH_HAS_HOLES_MEMORYMODEL
907 Support for TI's DaVinci platform.
912 select ARCH_REQUIRE_GPIOLIB
913 select ARCH_HAS_CPUFREQ
915 select GENERIC_CLOCKEVENTS
916 select HAVE_SCHED_CLOCK
917 select ARCH_HAS_HOLES_MEMORYMODEL
919 Support for TI's OMAP platform (OMAP1/2/3/4).
924 select ARCH_REQUIRE_GPIOLIB
927 select GENERIC_CLOCKEVENTS
929 select NO_MACH_MEMORY_H
931 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
934 bool "VIA/WonderMedia 85xx"
937 select ARCH_HAS_CPUFREQ
938 select GENERIC_CLOCKEVENTS
939 select ARCH_REQUIRE_GPIOLIB
941 select NO_MACH_MEMORY_H
943 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
946 bool "Xilinx Zynq ARM Cortex A9 Platform"
949 select GENERIC_CLOCKEVENTS
956 Support for Xilinx Zynq ARM Cortex A9 Platform
960 # This is sorted alphabetically by mach-* pathname. However, plat-*
961 # Kconfigs may be included either alphabetically (according to the
962 # plat- suffix) or along side the corresponding mach-* source.
964 source "arch/arm/mach-at91/Kconfig"
966 source "arch/arm/mach-bcmring/Kconfig"
968 source "arch/arm/mach-clps711x/Kconfig"
970 source "arch/arm/mach-cns3xxx/Kconfig"
972 source "arch/arm/mach-davinci/Kconfig"
974 source "arch/arm/mach-dove/Kconfig"
976 source "arch/arm/mach-ep93xx/Kconfig"
978 source "arch/arm/mach-footbridge/Kconfig"
980 source "arch/arm/mach-gemini/Kconfig"
982 source "arch/arm/mach-h720x/Kconfig"
984 source "arch/arm/mach-integrator/Kconfig"
986 source "arch/arm/mach-iop32x/Kconfig"
988 source "arch/arm/mach-iop33x/Kconfig"
990 source "arch/arm/mach-iop13xx/Kconfig"
992 source "arch/arm/mach-ixp4xx/Kconfig"
994 source "arch/arm/mach-ixp2000/Kconfig"
996 source "arch/arm/mach-ixp23xx/Kconfig"
998 source "arch/arm/mach-kirkwood/Kconfig"
1000 source "arch/arm/mach-ks8695/Kconfig"
1002 source "arch/arm/mach-lpc32xx/Kconfig"
1004 source "arch/arm/mach-msm/Kconfig"
1006 source "arch/arm/mach-mv78xx0/Kconfig"
1008 source "arch/arm/plat-mxc/Kconfig"
1010 source "arch/arm/mach-mxs/Kconfig"
1012 source "arch/arm/mach-netx/Kconfig"
1014 source "arch/arm/mach-nomadik/Kconfig"
1015 source "arch/arm/plat-nomadik/Kconfig"
1017 source "arch/arm/mach-nuc93x/Kconfig"
1019 source "arch/arm/plat-omap/Kconfig"
1021 source "arch/arm/mach-omap1/Kconfig"
1023 source "arch/arm/mach-omap2/Kconfig"
1025 source "arch/arm/mach-orion5x/Kconfig"
1027 source "arch/arm/mach-pxa/Kconfig"
1028 source "arch/arm/plat-pxa/Kconfig"
1030 source "arch/arm/mach-mmp/Kconfig"
1032 source "arch/arm/mach-realview/Kconfig"
1034 source "arch/arm/mach-sa1100/Kconfig"
1036 source "arch/arm/plat-samsung/Kconfig"
1037 source "arch/arm/plat-s3c24xx/Kconfig"
1038 source "arch/arm/plat-s5p/Kconfig"
1040 source "arch/arm/plat-spear/Kconfig"
1042 source "arch/arm/plat-tcc/Kconfig"
1045 source "arch/arm/mach-s3c2410/Kconfig"
1046 source "arch/arm/mach-s3c2412/Kconfig"
1047 source "arch/arm/mach-s3c2416/Kconfig"
1048 source "arch/arm/mach-s3c2440/Kconfig"
1049 source "arch/arm/mach-s3c2443/Kconfig"
1053 source "arch/arm/mach-s3c64xx/Kconfig"
1056 source "arch/arm/mach-s5p64x0/Kconfig"
1058 source "arch/arm/mach-s5pc100/Kconfig"
1060 source "arch/arm/mach-s5pv210/Kconfig"
1062 source "arch/arm/mach-exynos4/Kconfig"
1064 source "arch/arm/mach-shmobile/Kconfig"
1066 source "arch/arm/mach-tegra/Kconfig"
1068 source "arch/arm/mach-u300/Kconfig"
1070 source "arch/arm/mach-ux500/Kconfig"
1072 source "arch/arm/mach-versatile/Kconfig"
1074 source "arch/arm/mach-vexpress/Kconfig"
1075 source "arch/arm/plat-versatile/Kconfig"
1077 source "arch/arm/mach-vt8500/Kconfig"
1079 source "arch/arm/mach-w90x900/Kconfig"
1081 # Definitions to make life easier
1087 select GENERIC_CLOCKEVENTS
1088 select HAVE_SCHED_CLOCK
1093 select GENERIC_IRQ_CHIP
1094 select HAVE_SCHED_CLOCK
1099 config PLAT_VERSATILE
1102 config ARM_TIMER_SP804
1106 source arch/arm/mm/Kconfig
1109 bool "Enable iWMMXt support"
1110 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1111 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1113 Enable support for iWMMXt context switching at run time if
1114 running on a CPU that supports it.
1116 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1119 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1123 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1124 (!ARCH_OMAP3 || OMAP3_EMU)
1128 config MULTI_IRQ_HANDLER
1131 Allow each machine to specify it's own IRQ handler at run time.
1134 source "arch/arm/Kconfig-nommu"
1137 config ARM_ERRATA_411920
1138 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1139 depends on CPU_V6 || CPU_V6K
1141 Invalidation of the Instruction Cache operation can
1142 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1143 It does not affect the MPCore. This option enables the ARM Ltd.
1144 recommended workaround.
1146 config ARM_ERRATA_430973
1147 bool "ARM errata: Stale prediction on replaced interworking branch"
1150 This option enables the workaround for the 430973 Cortex-A8
1151 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1152 interworking branch is replaced with another code sequence at the
1153 same virtual address, whether due to self-modifying code or virtual
1154 to physical address re-mapping, Cortex-A8 does not recover from the
1155 stale interworking branch prediction. This results in Cortex-A8
1156 executing the new code sequence in the incorrect ARM or Thumb state.
1157 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1158 and also flushes the branch target cache at every context switch.
1159 Note that setting specific bits in the ACTLR register may not be
1160 available in non-secure mode.
1162 config ARM_ERRATA_458693
1163 bool "ARM errata: Processor deadlock when a false hazard is created"
1166 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1167 erratum. For very specific sequences of memory operations, it is
1168 possible for a hazard condition intended for a cache line to instead
1169 be incorrectly associated with a different cache line. This false
1170 hazard might then cause a processor deadlock. The workaround enables
1171 the L1 caching of the NEON accesses and disables the PLD instruction
1172 in the ACTLR register. Note that setting specific bits in the ACTLR
1173 register may not be available in non-secure mode.
1175 config ARM_ERRATA_460075
1176 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1179 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1180 erratum. Any asynchronous access to the L2 cache may encounter a
1181 situation in which recent store transactions to the L2 cache are lost
1182 and overwritten with stale memory contents from external memory. The
1183 workaround disables the write-allocate mode for the L2 cache via the
1184 ACTLR register. Note that setting specific bits in the ACTLR register
1185 may not be available in non-secure mode.
1187 config ARM_ERRATA_742230
1188 bool "ARM errata: DMB operation may be faulty"
1189 depends on CPU_V7 && SMP
1191 This option enables the workaround for the 742230 Cortex-A9
1192 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1193 between two write operations may not ensure the correct visibility
1194 ordering of the two writes. This workaround sets a specific bit in
1195 the diagnostic register of the Cortex-A9 which causes the DMB
1196 instruction to behave as a DSB, ensuring the correct behaviour of
1199 config ARM_ERRATA_742231
1200 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1201 depends on CPU_V7 && SMP
1203 This option enables the workaround for the 742231 Cortex-A9
1204 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1205 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1206 accessing some data located in the same cache line, may get corrupted
1207 data due to bad handling of the address hazard when the line gets
1208 replaced from one of the CPUs at the same time as another CPU is
1209 accessing it. This workaround sets specific bits in the diagnostic
1210 register of the Cortex-A9 which reduces the linefill issuing
1211 capabilities of the processor.
1213 config PL310_ERRATA_588369
1214 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1215 depends on CACHE_L2X0
1217 The PL310 L2 cache controller implements three types of Clean &
1218 Invalidate maintenance operations: by Physical Address
1219 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1220 They are architecturally defined to behave as the execution of a
1221 clean operation followed immediately by an invalidate operation,
1222 both performing to the same memory location. This functionality
1223 is not correctly implemented in PL310 as clean lines are not
1224 invalidated as a result of these operations.
1226 config ARM_ERRATA_720789
1227 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1228 depends on CPU_V7 && SMP
1230 This option enables the workaround for the 720789 Cortex-A9 (prior to
1231 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1232 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1233 As a consequence of this erratum, some TLB entries which should be
1234 invalidated are not, resulting in an incoherency in the system page
1235 tables. The workaround changes the TLB flushing routines to invalidate
1236 entries regardless of the ASID.
1238 config PL310_ERRATA_727915
1239 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1240 depends on CACHE_L2X0
1242 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1243 operation (offset 0x7FC). This operation runs in background so that
1244 PL310 can handle normal accesses while it is in progress. Under very
1245 rare circumstances, due to this erratum, write data can be lost when
1246 PL310 treats a cacheable write transaction during a Clean &
1247 Invalidate by Way operation.
1249 config ARM_ERRATA_743622
1250 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1253 This option enables the workaround for the 743622 Cortex-A9
1254 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1255 optimisation in the Cortex-A9 Store Buffer may lead to data
1256 corruption. This workaround sets a specific bit in the diagnostic
1257 register of the Cortex-A9 which disables the Store Buffer
1258 optimisation, preventing the defect from occurring. This has no
1259 visible impact on the overall performance or power consumption of the
1262 config ARM_ERRATA_751472
1263 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1264 depends on CPU_V7 && SMP
1266 This option enables the workaround for the 751472 Cortex-A9 (prior
1267 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1268 completion of a following broadcasted operation if the second
1269 operation is received by a CPU before the ICIALLUIS has completed,
1270 potentially leading to corrupted entries in the cache or TLB.
1272 config ARM_ERRATA_753970
1273 bool "ARM errata: cache sync operation may be faulty"
1274 depends on CACHE_PL310
1276 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1278 Under some condition the effect of cache sync operation on
1279 the store buffer still remains when the operation completes.
1280 This means that the store buffer is always asked to drain and
1281 this prevents it from merging any further writes. The workaround
1282 is to replace the normal offset of cache sync operation (0x730)
1283 by another offset targeting an unmapped PL310 register 0x740.
1284 This has the same effect as the cache sync operation: store buffer
1285 drain and waiting for all buffers empty.
1287 config ARM_ERRATA_754322
1288 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1291 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1292 r3p*) erratum. A speculative memory access may cause a page table walk
1293 which starts prior to an ASID switch but completes afterwards. This
1294 can populate the micro-TLB with a stale entry which may be hit with
1295 the new ASID. This workaround places two dsb instructions in the mm
1296 switching code so that no page table walks can cross the ASID switch.
1298 config ARM_ERRATA_754327
1299 bool "ARM errata: no automatic Store Buffer drain"
1300 depends on CPU_V7 && SMP
1302 This option enables the workaround for the 754327 Cortex-A9 (prior to
1303 r2p0) erratum. The Store Buffer does not have any automatic draining
1304 mechanism and therefore a livelock may occur if an external agent
1305 continuously polls a memory location waiting to observe an update.
1306 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1307 written polling loops from denying visibility of updates to memory.
1311 source "arch/arm/common/Kconfig"
1321 Find out whether you have ISA slots on your motherboard. ISA is the
1322 name of a bus system, i.e. the way the CPU talks to the other stuff
1323 inside your box. Other bus systems are PCI, EISA, MicroChannel
1324 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1325 newer boards don't support it. If you have ISA, say Y, otherwise N.
1327 # Select ISA DMA controller support
1332 # Select ISA DMA interface
1337 bool "PCI support" if MIGHT_HAVE_PCI
1339 Find out whether you have a PCI motherboard. PCI is the name of a
1340 bus system, i.e. the way the CPU talks to the other stuff inside
1341 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1342 VESA. If you have PCI, say Y, otherwise N.
1348 config PCI_NANOENGINE
1349 bool "BSE nanoEngine PCI support"
1350 depends on SA1100_NANOENGINE
1352 Enable PCI on the BSE nanoEngine board.
1357 # Select the host bridge type
1358 config PCI_HOST_VIA82C505
1360 depends on PCI && ARCH_SHARK
1363 config PCI_HOST_ITE8152
1365 depends on PCI && MACH_ARMCORE
1369 source "drivers/pci/Kconfig"
1371 source "drivers/pcmcia/Kconfig"
1375 menu "Kernel Features"
1377 source "kernel/time/Kconfig"
1380 bool "Symmetric Multi-Processing"
1381 depends on CPU_V6K || CPU_V7
1382 depends on GENERIC_CLOCKEVENTS
1383 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1384 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1385 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1386 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1387 select USE_GENERIC_SMP_HELPERS
1388 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1390 This enables support for systems with more than one CPU. If you have
1391 a system with only one CPU, like most personal computers, say N. If
1392 you have a system with more than one CPU, say Y.
1394 If you say N here, the kernel will run on single and multiprocessor
1395 machines, but will use only one CPU of a multiprocessor machine. If
1396 you say Y here, the kernel will run on many, but not all, single
1397 processor machines. On a single processor machine, the kernel will
1398 run faster if you say N here.
1400 See also <file:Documentation/i386/IO-APIC.txt>,
1401 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1402 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1404 If you don't know what to do here, say N.
1407 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1408 depends on EXPERIMENTAL
1409 depends on SMP && !XIP_KERNEL
1412 SMP kernels contain instructions which fail on non-SMP processors.
1413 Enabling this option allows the kernel to modify itself to make
1414 these instructions safe. Disabling it allows about 1K of space
1417 If you don't know what to do here, say Y.
1422 This option enables support for the ARM system coherency unit
1429 This options enables support for the ARM timer and watchdog unit
1432 prompt "Memory split"
1435 Select the desired split between kernel and user memory.
1437 If you are not absolutely sure what you are doing, leave this
1441 bool "3G/1G user/kernel split"
1443 bool "2G/2G user/kernel split"
1445 bool "1G/3G user/kernel split"
1450 default 0x40000000 if VMSPLIT_1G
1451 default 0x80000000 if VMSPLIT_2G
1455 int "Maximum number of CPUs (2-32)"
1461 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1462 depends on SMP && HOTPLUG && EXPERIMENTAL
1464 Say Y here to experiment with turning CPUs off and on. CPUs
1465 can be controlled through /sys/devices/system/cpu.
1468 bool "Use local timer interrupts"
1471 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1473 Enable support for local timers on SMP platforms, rather then the
1474 legacy IPI broadcast method. Local timers allows the system
1475 accounting to be spread across the timer interval, preventing a
1476 "thundering herd" at every timer tick.
1478 source kernel/Kconfig.preempt
1482 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1483 ARCH_S5PV210 || ARCH_EXYNOS4
1484 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1485 default AT91_TIMER_HZ if ARCH_AT91
1486 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1489 config THUMB2_KERNEL
1490 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1491 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1493 select ARM_ASM_UNIFIED
1495 By enabling this option, the kernel will be compiled in
1496 Thumb-2 mode. A compiler/assembler that understand the unified
1497 ARM-Thumb syntax is needed.
1501 config THUMB2_AVOID_R_ARM_THM_JUMP11
1502 bool "Work around buggy Thumb-2 short branch relocations in gas"
1503 depends on THUMB2_KERNEL && MODULES
1506 Various binutils versions can resolve Thumb-2 branches to
1507 locally-defined, preemptible global symbols as short-range "b.n"
1508 branch instructions.
1510 This is a problem, because there's no guarantee the final
1511 destination of the symbol, or any candidate locations for a
1512 trampoline, are within range of the branch. For this reason, the
1513 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1514 relocation in modules at all, and it makes little sense to add
1517 The symptom is that the kernel fails with an "unsupported
1518 relocation" error when loading some modules.
1520 Until fixed tools are available, passing
1521 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1522 code which hits this problem, at the cost of a bit of extra runtime
1523 stack usage in some cases.
1525 The problem is described in more detail at:
1526 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1528 Only Thumb-2 kernels are affected.
1530 Unless you are sure your tools don't have this problem, say Y.
1532 config ARM_ASM_UNIFIED
1536 bool "Use the ARM EABI to compile the kernel"
1538 This option allows for the kernel to be compiled using the latest
1539 ARM ABI (aka EABI). This is only useful if you are using a user
1540 space environment that is also compiled with EABI.
1542 Since there are major incompatibilities between the legacy ABI and
1543 EABI, especially with regard to structure member alignment, this
1544 option also changes the kernel syscall calling convention to
1545 disambiguate both ABIs and allow for backward compatibility support
1546 (selected with CONFIG_OABI_COMPAT).
1548 To use this you need GCC version 4.0.0 or later.
1551 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1552 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1555 This option preserves the old syscall interface along with the
1556 new (ARM EABI) one. It also provides a compatibility layer to
1557 intercept syscalls that have structure arguments which layout
1558 in memory differs between the legacy ABI and the new ARM EABI
1559 (only for non "thumb" binaries). This option adds a tiny
1560 overhead to all syscalls and produces a slightly larger kernel.
1561 If you know you'll be using only pure EABI user space then you
1562 can say N here. If this option is not selected and you attempt
1563 to execute a legacy ABI binary then the result will be
1564 UNPREDICTABLE (in fact it can be predicted that it won't work
1565 at all). If in doubt say Y.
1567 config ARCH_HAS_HOLES_MEMORYMODEL
1570 config ARCH_SPARSEMEM_ENABLE
1573 config ARCH_SPARSEMEM_DEFAULT
1574 def_bool ARCH_SPARSEMEM_ENABLE
1576 config ARCH_SELECT_MEMORY_MODEL
1577 def_bool ARCH_SPARSEMEM_ENABLE
1579 config HAVE_ARCH_PFN_VALID
1580 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1583 bool "High Memory Support"
1586 The address space of ARM processors is only 4 Gigabytes large
1587 and it has to accommodate user address space, kernel address
1588 space as well as some memory mapped IO. That means that, if you
1589 have a large amount of physical memory and/or IO, not all of the
1590 memory can be "permanently mapped" by the kernel. The physical
1591 memory that is not permanently mapped is called "high memory".
1593 Depending on the selected kernel/user memory split, minimum
1594 vmalloc space and actual amount of RAM, you may not need this
1595 option which should result in a slightly faster kernel.
1600 bool "Allocate 2nd-level pagetables from highmem"
1603 config HW_PERF_EVENTS
1604 bool "Enable hardware performance counter support for perf events"
1605 depends on PERF_EVENTS && CPU_HAS_PMU
1608 Enable hardware performance counter support for perf events. If
1609 disabled, perf events will use software events only.
1613 config FORCE_MAX_ZONEORDER
1614 int "Maximum zone order" if ARCH_SHMOBILE
1615 range 11 64 if ARCH_SHMOBILE
1616 default "9" if SA1111
1619 The kernel memory allocator divides physically contiguous memory
1620 blocks into "zones", where each zone is a power of two number of
1621 pages. This option selects the largest power of two that the kernel
1622 keeps in the memory allocator. If you need to allocate very large
1623 blocks of physically contiguous memory, then you may need to
1624 increase this value.
1626 This config option is actually maximum order plus one. For example,
1627 a value of 11 means that the largest free memory block is 2^10 pages.
1630 bool "Timer and CPU usage LEDs"
1631 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1632 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1633 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1634 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1635 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1636 ARCH_AT91 || ARCH_DAVINCI || \
1637 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1639 If you say Y here, the LEDs on your machine will be used
1640 to provide useful information about your current system status.
1642 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1643 be able to select which LEDs are active using the options below. If
1644 you are compiling a kernel for the EBSA-110 or the LART however, the
1645 red LED will simply flash regularly to indicate that the system is
1646 still functional. It is safe to say Y here if you have a CATS
1647 system, but the driver will do nothing.
1650 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1651 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1652 || MACH_OMAP_PERSEUS2
1654 depends on !GENERIC_CLOCKEVENTS
1655 default y if ARCH_EBSA110
1657 If you say Y here, one of the system LEDs (the green one on the
1658 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1659 will flash regularly to indicate that the system is still
1660 operational. This is mainly useful to kernel hackers who are
1661 debugging unstable kernels.
1663 The LART uses the same LED for both Timer LED and CPU usage LED
1664 functions. You may choose to use both, but the Timer LED function
1665 will overrule the CPU usage LED.
1668 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1670 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1671 || MACH_OMAP_PERSEUS2
1674 If you say Y here, the red LED will be used to give a good real
1675 time indication of CPU usage, by lighting whenever the idle task
1676 is not currently executing.
1678 The LART uses the same LED for both Timer LED and CPU usage LED
1679 functions. You may choose to use both, but the Timer LED function
1680 will overrule the CPU usage LED.
1682 config ALIGNMENT_TRAP
1684 depends on CPU_CP15_MMU
1685 default y if !ARCH_EBSA110
1686 select HAVE_PROC_CPU if PROC_FS
1688 ARM processors cannot fetch/store information which is not
1689 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1690 address divisible by 4. On 32-bit ARM processors, these non-aligned
1691 fetch/store instructions will be emulated in software if you say
1692 here, which has a severe performance impact. This is necessary for
1693 correct operation of some network protocols. With an IP-only
1694 configuration it is safe to say N, otherwise say Y.
1696 config UACCESS_WITH_MEMCPY
1697 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1698 depends on MMU && EXPERIMENTAL
1699 default y if CPU_FEROCEON
1701 Implement faster copy_to_user and clear_user methods for CPU
1702 cores where a 8-word STM instruction give significantly higher
1703 memory write throughput than a sequence of individual 32bit stores.
1705 A possible side effect is a slight increase in scheduling latency
1706 between threads sharing the same address space if they invoke
1707 such copy operations with large buffers.
1709 However, if the CPU data cache is using a write-allocate mode,
1710 this option is unlikely to provide any performance gain.
1714 prompt "Enable seccomp to safely compute untrusted bytecode"
1716 This kernel feature is useful for number crunching applications
1717 that may need to compute untrusted bytecode during their
1718 execution. By using pipes or other transports made available to
1719 the process as file descriptors supporting the read/write
1720 syscalls, it's possible to isolate those applications in
1721 their own address space using seccomp. Once seccomp is
1722 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1723 and the task is only allowed to execute a few safe syscalls
1724 defined by each seccomp mode.
1726 config CC_STACKPROTECTOR
1727 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1728 depends on EXPERIMENTAL
1730 This option turns on the -fstack-protector GCC feature. This
1731 feature puts, at the beginning of functions, a canary value on
1732 the stack just before the return address, and validates
1733 the value just before actually returning. Stack based buffer
1734 overflows (that need to overwrite this return address) now also
1735 overwrite the canary, which gets detected and the attack is then
1736 neutralized via a kernel panic.
1737 This feature requires gcc version 4.2 or above.
1739 config DEPRECATED_PARAM_STRUCT
1740 bool "Provide old way to pass kernel parameters"
1742 This was deprecated in 2001 and announced to live on for 5 years.
1743 Some old boot loaders still use this way.
1750 bool "Flattened Device Tree support"
1752 select OF_EARLY_FLATTREE
1755 Include support for flattened device tree machine descriptions.
1757 # Compressed boot loader in ROM. Yes, we really want to ask about
1758 # TEXT and BSS so we preserve their values in the config files.
1759 config ZBOOT_ROM_TEXT
1760 hex "Compressed ROM boot loader base address"
1763 The physical address at which the ROM-able zImage is to be
1764 placed in the target. Platforms which normally make use of
1765 ROM-able zImage formats normally set this to a suitable
1766 value in their defconfig file.
1768 If ZBOOT_ROM is not enabled, this has no effect.
1770 config ZBOOT_ROM_BSS
1771 hex "Compressed ROM boot loader BSS address"
1774 The base address of an area of read/write memory in the target
1775 for the ROM-able zImage which must be available while the
1776 decompressor is running. It must be large enough to hold the
1777 entire decompressed kernel plus an additional 128 KiB.
1778 Platforms which normally make use of ROM-able zImage formats
1779 normally set this to a suitable value in their defconfig file.
1781 If ZBOOT_ROM is not enabled, this has no effect.
1784 bool "Compressed boot loader in ROM/flash"
1785 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1787 Say Y here if you intend to execute your compressed kernel image
1788 (zImage) directly from ROM or flash. If unsure, say N.
1791 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1792 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1793 default ZBOOT_ROM_NONE
1795 Include experimental SD/MMC loading code in the ROM-able zImage.
1796 With this enabled it is possible to write the the ROM-able zImage
1797 kernel image to an MMC or SD card and boot the kernel straight
1798 from the reset vector. At reset the processor Mask ROM will load
1799 the first part of the the ROM-able zImage which in turn loads the
1800 rest the kernel image to RAM.
1802 config ZBOOT_ROM_NONE
1803 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1805 Do not load image from SD or MMC
1807 config ZBOOT_ROM_MMCIF
1808 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1810 Load image from MMCIF hardware block.
1812 config ZBOOT_ROM_SH_MOBILE_SDHI
1813 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1815 Load image from SDHI hardware block
1820 string "Default kernel command string"
1823 On some architectures (EBSA110 and CATS), there is currently no way
1824 for the boot loader to pass arguments to the kernel. For these
1825 architectures, you should supply some command-line options at build
1826 time by entering them here. As a minimum, you should specify the
1827 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1830 prompt "Kernel command line type" if CMDLINE != ""
1831 default CMDLINE_FROM_BOOTLOADER
1833 config CMDLINE_FROM_BOOTLOADER
1834 bool "Use bootloader kernel arguments if available"
1836 Uses the command-line options passed by the boot loader. If
1837 the boot loader doesn't provide any, the default kernel command
1838 string provided in CMDLINE will be used.
1840 config CMDLINE_EXTEND
1841 bool "Extend bootloader kernel arguments"
1843 The command-line arguments provided by the boot loader will be
1844 appended to the default kernel command string.
1846 config CMDLINE_FORCE
1847 bool "Always use the default kernel command string"
1849 Always use the default kernel command string, even if the boot
1850 loader passes other arguments to the kernel.
1851 This is useful if you cannot or don't want to change the
1852 command-line options your boot loader passes to the kernel.
1856 bool "Kernel Execute-In-Place from ROM"
1857 depends on !ZBOOT_ROM
1859 Execute-In-Place allows the kernel to run from non-volatile storage
1860 directly addressable by the CPU, such as NOR flash. This saves RAM
1861 space since the text section of the kernel is not loaded from flash
1862 to RAM. Read-write sections, such as the data section and stack,
1863 are still copied to RAM. The XIP kernel is not compressed since
1864 it has to run directly from flash, so it will take more space to
1865 store it. The flash address used to link the kernel object files,
1866 and for storing it, is configuration dependent. Therefore, if you
1867 say Y here, you must know the proper physical address where to
1868 store the kernel image depending on your own flash memory usage.
1870 Also note that the make target becomes "make xipImage" rather than
1871 "make zImage" or "make Image". The final kernel binary to put in
1872 ROM memory will be arch/arm/boot/xipImage.
1876 config XIP_PHYS_ADDR
1877 hex "XIP Kernel Physical Location"
1878 depends on XIP_KERNEL
1879 default "0x00080000"
1881 This is the physical address in your flash memory the kernel will
1882 be linked for and stored to. This address is dependent on your
1886 bool "Kexec system call (EXPERIMENTAL)"
1887 depends on EXPERIMENTAL
1889 kexec is a system call that implements the ability to shutdown your
1890 current kernel, and to start another kernel. It is like a reboot
1891 but it is independent of the system firmware. And like a reboot
1892 you can start any kernel with it, not just Linux.
1894 It is an ongoing process to be certain the hardware in a machine
1895 is properly shutdown, so do not be surprised if this code does not
1896 initially work for you. It may help to enable device hotplugging
1900 bool "Export atags in procfs"
1904 Should the atags used to boot the kernel be exported in an "atags"
1905 file in procfs. Useful with kexec.
1908 bool "Build kdump crash kernel (EXPERIMENTAL)"
1909 depends on EXPERIMENTAL
1911 Generate crash dump after being started by kexec. This should
1912 be normally only set in special crash dump kernels which are
1913 loaded in the main kernel with kexec-tools into a specially
1914 reserved region and then later executed after a crash by
1915 kdump/kexec. The crash dump kernel must be compiled to a
1916 memory address not used by the main kernel
1918 For more details see Documentation/kdump/kdump.txt
1920 config AUTO_ZRELADDR
1921 bool "Auto calculation of the decompressed kernel image address"
1922 depends on !ZBOOT_ROM && !ARCH_U300
1924 ZRELADDR is the physical address where the decompressed kernel
1925 image will be placed. If AUTO_ZRELADDR is selected, the address
1926 will be determined at run-time by masking the current IP with
1927 0xf8000000. This assumes the zImage being placed in the first 128MB
1928 from start of memory.
1932 menu "CPU Power Management"
1936 source "drivers/cpufreq/Kconfig"
1939 tristate "CPUfreq driver for i.MX CPUs"
1940 depends on ARCH_MXC && CPU_FREQ
1942 This enables the CPUfreq driver for i.MX CPUs.
1944 config CPU_FREQ_SA1100
1947 config CPU_FREQ_SA1110
1950 config CPU_FREQ_INTEGRATOR
1951 tristate "CPUfreq driver for ARM Integrator CPUs"
1952 depends on ARCH_INTEGRATOR && CPU_FREQ
1955 This enables the CPUfreq driver for ARM Integrator CPUs.
1957 For details, take a look at <file:Documentation/cpu-freq>.
1963 depends on CPU_FREQ && ARCH_PXA && PXA25x
1965 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1970 Internal configuration node for common cpufreq on Samsung SoC
1972 config CPU_FREQ_S3C24XX
1973 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1974 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1977 This enables the CPUfreq driver for the Samsung S3C24XX family
1980 For details, take a look at <file:Documentation/cpu-freq>.
1984 config CPU_FREQ_S3C24XX_PLL
1985 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1986 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1988 Compile in support for changing the PLL frequency from the
1989 S3C24XX series CPUfreq driver. The PLL takes time to settle
1990 after a frequency change, so by default it is not enabled.
1992 This also means that the PLL tables for the selected CPU(s) will
1993 be built which may increase the size of the kernel image.
1995 config CPU_FREQ_S3C24XX_DEBUG
1996 bool "Debug CPUfreq Samsung driver core"
1997 depends on CPU_FREQ_S3C24XX
1999 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2001 config CPU_FREQ_S3C24XX_IODEBUG
2002 bool "Debug CPUfreq Samsung driver IO timing"
2003 depends on CPU_FREQ_S3C24XX
2005 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2007 config CPU_FREQ_S3C24XX_DEBUGFS
2008 bool "Export debugfs for CPUFreq"
2009 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2011 Export status information via debugfs.
2015 source "drivers/cpuidle/Kconfig"
2019 menu "Floating point emulation"
2021 comment "At least one emulation must be selected"
2024 bool "NWFPE math emulation"
2025 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2027 Say Y to include the NWFPE floating point emulator in the kernel.
2028 This is necessary to run most binaries. Linux does not currently
2029 support floating point hardware so you need to say Y here even if
2030 your machine has an FPA or floating point co-processor podule.
2032 You may say N here if you are going to load the Acorn FPEmulator
2033 early in the bootup.
2036 bool "Support extended precision"
2037 depends on FPE_NWFPE
2039 Say Y to include 80-bit support in the kernel floating-point
2040 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2041 Note that gcc does not generate 80-bit operations by default,
2042 so in most cases this option only enlarges the size of the
2043 floating point emulator without any good reason.
2045 You almost surely want to say N here.
2048 bool "FastFPE math emulation (EXPERIMENTAL)"
2049 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2051 Say Y here to include the FAST floating point emulator in the kernel.
2052 This is an experimental much faster emulator which now also has full
2053 precision for the mantissa. It does not support any exceptions.
2054 It is very simple, and approximately 3-6 times faster than NWFPE.
2056 It should be sufficient for most programs. It may be not suitable
2057 for scientific calculations, but you have to check this for yourself.
2058 If you do not feel you need a faster FP emulation you should better
2062 bool "VFP-format floating point maths"
2063 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2065 Say Y to include VFP support code in the kernel. This is needed
2066 if your hardware includes a VFP unit.
2068 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2069 release notes and additional status information.
2071 Say N if your target does not have VFP hardware.
2079 bool "Advanced SIMD (NEON) Extension support"
2080 depends on VFPv3 && CPU_V7
2082 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2087 menu "Userspace binary formats"
2089 source "fs/Kconfig.binfmt"
2092 tristate "RISC OS personality"
2095 Say Y here to include the kernel code necessary if you want to run
2096 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2097 experimental; if this sounds frightening, say N and sleep in peace.
2098 You can also say M here to compile this support as a module (which
2099 will be called arthur).
2103 menu "Power management options"
2105 source "kernel/power/Kconfig"
2107 config ARCH_SUSPEND_POSSIBLE
2108 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2109 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2110 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2115 source "net/Kconfig"
2117 source "drivers/Kconfig"
2121 source "arch/arm/Kconfig.debug"
2123 source "security/Kconfig"
2125 source "crypto/Kconfig"
2127 source "lib/Kconfig"