2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
44 static int wm8994_drc_base
[] = {
50 static int wm8994_retune_mobile_base
[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1
,
52 WM8994_AIF1_DAC2_EQ_GAINS_1
,
53 WM8994_AIF2_EQ_GAINS_1
,
56 static int wm8994_readable(struct snd_soc_codec
*codec
, unsigned int reg
)
58 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
59 struct wm8994
*control
= wm8994
->control_data
;
73 case WM8994_INTERRUPT_STATUS_1
:
74 case WM8994_INTERRUPT_STATUS_2
:
75 case WM8994_INTERRUPT_RAW_STATUS_2
:
78 case WM8958_DSP2_PROGRAM
:
79 case WM8958_DSP2_CONFIG
:
80 case WM8958_DSP2_EXECCONTROL
:
81 if (control
->type
== WM8958
)
90 if (reg
>= WM8994_CACHE_SIZE
)
92 return wm8994_access_masks
[reg
].readable
!= 0;
95 static int wm8994_volatile(struct snd_soc_codec
*codec
, unsigned int reg
)
97 if (reg
>= WM8994_CACHE_SIZE
)
101 case WM8994_SOFTWARE_RESET
:
102 case WM8994_CHIP_REVISION
:
103 case WM8994_DC_SERVO_1
:
104 case WM8994_DC_SERVO_READBACK
:
105 case WM8994_RATE_STATUS
:
108 case WM8958_DSP2_EXECCONTROL
:
109 case WM8958_MIC_DETECT_3
:
116 static int wm8994_write(struct snd_soc_codec
*codec
, unsigned int reg
,
121 BUG_ON(reg
> WM8994_MAX_REGISTER
);
123 if (!wm8994_volatile(codec
, reg
)) {
124 ret
= snd_soc_cache_write(codec
, reg
, value
);
126 dev_err(codec
->dev
, "Cache write to %x failed: %d\n",
130 return wm8994_reg_write(codec
->control_data
, reg
, value
);
133 static unsigned int wm8994_read(struct snd_soc_codec
*codec
,
139 BUG_ON(reg
> WM8994_MAX_REGISTER
);
141 if (!wm8994_volatile(codec
, reg
) && wm8994_readable(codec
, reg
) &&
142 reg
< codec
->driver
->reg_cache_size
) {
143 ret
= snd_soc_cache_read(codec
, reg
, &val
);
147 dev_err(codec
->dev
, "Cache read from %x failed: %d\n",
151 return wm8994_reg_read(codec
->control_data
, reg
);
154 static int configure_aif_clock(struct snd_soc_codec
*codec
, int aif
)
156 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
166 switch (wm8994
->sysclk
[aif
]) {
167 case WM8994_SYSCLK_MCLK1
:
168 rate
= wm8994
->mclk
[0];
171 case WM8994_SYSCLK_MCLK2
:
173 rate
= wm8994
->mclk
[1];
176 case WM8994_SYSCLK_FLL1
:
178 rate
= wm8994
->fll
[0].out
;
181 case WM8994_SYSCLK_FLL2
:
183 rate
= wm8994
->fll
[1].out
;
190 if (rate
>= 13500000) {
192 reg1
|= WM8994_AIF1CLK_DIV
;
194 dev_dbg(codec
->dev
, "Dividing AIF%d clock to %dHz\n",
198 if (rate
&& rate
< 3000000)
199 dev_warn(codec
->dev
, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
202 wm8994
->aifclk
[aif
] = rate
;
204 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
+ offset
,
205 WM8994_AIF1CLK_SRC_MASK
| WM8994_AIF1CLK_DIV
,
211 static int configure_clock(struct snd_soc_codec
*codec
)
213 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
216 /* Bring up the AIF clocks first */
217 configure_aif_clock(codec
, 0);
218 configure_aif_clock(codec
, 1);
220 /* Then switch CLK_SYS over to the higher of them; a change
221 * can only happen as a result of a clocking change which can
222 * only be made outside of DAPM so we can safely redo the
226 /* If they're equal it doesn't matter which is used */
227 if (wm8994
->aifclk
[0] == wm8994
->aifclk
[1])
230 if (wm8994
->aifclk
[0] < wm8994
->aifclk
[1])
231 new = WM8994_SYSCLK_SRC
;
235 old
= snd_soc_read(codec
, WM8994_CLOCKING_1
) & WM8994_SYSCLK_SRC
;
237 /* If there's no change then we're done. */
241 snd_soc_update_bits(codec
, WM8994_CLOCKING_1
, WM8994_SYSCLK_SRC
, new);
243 snd_soc_dapm_sync(&codec
->dapm
);
248 static int check_clk_sys(struct snd_soc_dapm_widget
*source
,
249 struct snd_soc_dapm_widget
*sink
)
251 int reg
= snd_soc_read(source
->codec
, WM8994_CLOCKING_1
);
254 /* Check what we're currently using for CLK_SYS */
255 if (reg
& WM8994_SYSCLK_SRC
)
260 return strcmp(source
->name
, clk
) == 0;
263 static const char *sidetone_hpf_text
[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
267 static const struct soc_enum sidetone_hpf
=
268 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 7, 7, sidetone_hpf_text
);
270 static const char *adc_hpf_text
[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
274 static const struct soc_enum aif1adc1_hpf
=
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS
, 13, 4, adc_hpf_text
);
277 static const struct soc_enum aif1adc2_hpf
=
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS
, 13, 4, adc_hpf_text
);
280 static const struct soc_enum aif2adc_hpf
=
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS
, 13, 4, adc_hpf_text
);
283 static const DECLARE_TLV_DB_SCALE(aif_tlv
, 0, 600, 0);
284 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
285 static const DECLARE_TLV_DB_SCALE(st_tlv
, -3600, 300, 0);
286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv
, -1600, 183, 0);
287 static const DECLARE_TLV_DB_SCALE(eq_tlv
, -1200, 100, 0);
289 #define WM8994_DRC_SWITCH(xname, reg, shift) \
290 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
291 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
292 .put = wm8994_put_drc_sw, \
293 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
295 static int wm8994_put_drc_sw(struct snd_kcontrol
*kcontrol
,
296 struct snd_ctl_elem_value
*ucontrol
)
298 struct soc_mixer_control
*mc
=
299 (struct soc_mixer_control
*)kcontrol
->private_value
;
300 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
303 /* Can't enable both ADC and DAC paths simultaneously */
304 if (mc
->shift
== WM8994_AIF1DAC1_DRC_ENA_SHIFT
)
305 mask
= WM8994_AIF1ADC1L_DRC_ENA_MASK
|
306 WM8994_AIF1ADC1R_DRC_ENA_MASK
;
308 mask
= WM8994_AIF1DAC1_DRC_ENA_MASK
;
310 ret
= snd_soc_read(codec
, mc
->reg
);
316 return snd_soc_put_volsw(kcontrol
, ucontrol
);
319 static void wm8994_set_drc(struct snd_soc_codec
*codec
, int drc
)
321 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
322 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
323 int base
= wm8994_drc_base
[drc
];
324 int cfg
= wm8994
->drc_cfg
[drc
];
327 /* Save any enables; the configuration should clear them. */
328 save
= snd_soc_read(codec
, base
);
329 save
&= WM8994_AIF1DAC1_DRC_ENA
| WM8994_AIF1ADC1L_DRC_ENA
|
330 WM8994_AIF1ADC1R_DRC_ENA
;
332 for (i
= 0; i
< WM8994_DRC_REGS
; i
++)
333 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
334 pdata
->drc_cfgs
[cfg
].regs
[i
]);
336 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_DRC_ENA
|
337 WM8994_AIF1ADC1L_DRC_ENA
|
338 WM8994_AIF1ADC1R_DRC_ENA
, save
);
341 /* Icky as hell but saves code duplication */
342 static int wm8994_get_drc(const char *name
)
344 if (strcmp(name
, "AIF1DRC1 Mode") == 0)
346 if (strcmp(name
, "AIF1DRC2 Mode") == 0)
348 if (strcmp(name
, "AIF2DRC Mode") == 0)
353 static int wm8994_put_drc_enum(struct snd_kcontrol
*kcontrol
,
354 struct snd_ctl_elem_value
*ucontrol
)
356 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
357 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
358 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
359 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
360 int value
= ucontrol
->value
.integer
.value
[0];
365 if (value
>= pdata
->num_drc_cfgs
)
368 wm8994
->drc_cfg
[drc
] = value
;
370 wm8994_set_drc(codec
, drc
);
375 static int wm8994_get_drc_enum(struct snd_kcontrol
*kcontrol
,
376 struct snd_ctl_elem_value
*ucontrol
)
378 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
379 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
380 int drc
= wm8994_get_drc(kcontrol
->id
.name
);
382 ucontrol
->value
.enumerated
.item
[0] = wm8994
->drc_cfg
[drc
];
387 static void wm8994_set_retune_mobile(struct snd_soc_codec
*codec
, int block
)
389 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
390 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
391 int base
= wm8994_retune_mobile_base
[block
];
392 int iface
, best
, best_val
, save
, i
, cfg
;
394 if (!pdata
|| !wm8994
->num_retune_mobile_texts
)
409 /* Find the version of the currently selected configuration
410 * with the nearest sample rate. */
411 cfg
= wm8994
->retune_mobile_cfg
[block
];
414 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
415 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
416 wm8994
->retune_mobile_texts
[cfg
]) == 0 &&
417 abs(pdata
->retune_mobile_cfgs
[i
].rate
418 - wm8994
->dac_rates
[iface
]) < best_val
) {
420 best_val
= abs(pdata
->retune_mobile_cfgs
[i
].rate
421 - wm8994
->dac_rates
[iface
]);
425 dev_dbg(codec
->dev
, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
427 pdata
->retune_mobile_cfgs
[best
].name
,
428 pdata
->retune_mobile_cfgs
[best
].rate
,
429 wm8994
->dac_rates
[iface
]);
431 /* The EQ will be disabled while reconfiguring it, remember the
432 * current configuration.
434 save
= snd_soc_read(codec
, base
);
435 save
&= WM8994_AIF1DAC1_EQ_ENA
;
437 for (i
= 0; i
< WM8994_EQ_REGS
; i
++)
438 snd_soc_update_bits(codec
, base
+ i
, 0xffff,
439 pdata
->retune_mobile_cfgs
[best
].regs
[i
]);
441 snd_soc_update_bits(codec
, base
, WM8994_AIF1DAC1_EQ_ENA
, save
);
444 /* Icky as hell but saves code duplication */
445 static int wm8994_get_retune_mobile_block(const char *name
)
447 if (strcmp(name
, "AIF1.1 EQ Mode") == 0)
449 if (strcmp(name
, "AIF1.2 EQ Mode") == 0)
451 if (strcmp(name
, "AIF2 EQ Mode") == 0)
456 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
457 struct snd_ctl_elem_value
*ucontrol
)
459 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
460 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
461 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
462 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
463 int value
= ucontrol
->value
.integer
.value
[0];
468 if (value
>= pdata
->num_retune_mobile_cfgs
)
471 wm8994
->retune_mobile_cfg
[block
] = value
;
473 wm8994_set_retune_mobile(codec
, block
);
478 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol
*kcontrol
,
479 struct snd_ctl_elem_value
*ucontrol
)
481 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
482 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
483 int block
= wm8994_get_retune_mobile_block(kcontrol
->id
.name
);
485 ucontrol
->value
.enumerated
.item
[0] = wm8994
->retune_mobile_cfg
[block
];
490 static const char *aif_chan_src_text
[] = {
494 static const struct soc_enum aif1adcl_src
=
495 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 15, 2, aif_chan_src_text
);
497 static const struct soc_enum aif1adcr_src
=
498 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1
, 14, 2, aif_chan_src_text
);
500 static const struct soc_enum aif2adcl_src
=
501 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 15, 2, aif_chan_src_text
);
503 static const struct soc_enum aif2adcr_src
=
504 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1
, 14, 2, aif_chan_src_text
);
506 static const struct soc_enum aif1dacl_src
=
507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 15, 2, aif_chan_src_text
);
509 static const struct soc_enum aif1dacr_src
=
510 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2
, 14, 2, aif_chan_src_text
);
512 static const struct soc_enum aif2dacl_src
=
513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 15, 2, aif_chan_src_text
);
515 static const struct soc_enum aif2dacr_src
=
516 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2
, 14, 2, aif_chan_src_text
);
518 static const char *osr_text
[] = {
519 "Low Power", "High Performance",
522 static const struct soc_enum dac_osr
=
523 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 0, 2, osr_text
);
525 static const struct soc_enum adc_osr
=
526 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING
, 1, 2, osr_text
);
528 static const struct snd_kcontrol_new wm8994_snd_controls
[] = {
529 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME
,
530 WM8994_AIF1_ADC1_RIGHT_VOLUME
,
531 1, 119, 0, digital_tlv
),
532 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME
,
533 WM8994_AIF1_ADC2_RIGHT_VOLUME
,
534 1, 119, 0, digital_tlv
),
535 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME
,
536 WM8994_AIF2_ADC_RIGHT_VOLUME
,
537 1, 119, 0, digital_tlv
),
539 SOC_ENUM("AIF1ADCL Source", aif1adcl_src
),
540 SOC_ENUM("AIF1ADCR Source", aif1adcr_src
),
541 SOC_ENUM("AIF2ADCL Source", aif2adcl_src
),
542 SOC_ENUM("AIF2ADCR Source", aif2adcr_src
),
544 SOC_ENUM("AIF1DACL Source", aif1dacl_src
),
545 SOC_ENUM("AIF1DACR Source", aif1dacr_src
),
546 SOC_ENUM("AIF2DACL Source", aif2dacl_src
),
547 SOC_ENUM("AIF2DACR Source", aif2dacr_src
),
549 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME
,
550 WM8994_AIF1_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
551 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME
,
552 WM8994_AIF1_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
553 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME
,
554 WM8994_AIF2_DAC_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
556 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2
, 10, 3, 0, aif_tlv
),
557 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2
, 10, 3, 0, aif_tlv
),
559 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1
, 0, 1, 0),
560 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1
, 0, 1, 0),
561 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1
, 0, 1, 0),
563 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1
, 2),
564 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1
, 1),
565 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1
, 0),
567 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1
, 2),
568 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1
, 1),
569 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1
, 0),
571 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1
, 2),
572 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1
, 1),
573 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1
, 0),
575 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
577 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES
,
579 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
581 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES
,
583 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf
),
584 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE
, 6, 1, 0),
586 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf
),
587 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS
, 12, 11, 1, 0),
589 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf
),
590 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS
, 12, 11, 1, 0),
592 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf
),
593 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS
, 12, 11, 1, 0),
595 SOC_ENUM("ADC OSR", adc_osr
),
596 SOC_ENUM("DAC OSR", dac_osr
),
598 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME
,
599 WM8994_DAC1_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
600 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME
,
601 WM8994_DAC1_RIGHT_VOLUME
, 9, 1, 1),
603 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME
,
604 WM8994_DAC2_RIGHT_VOLUME
, 1, 96, 0, digital_tlv
),
605 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME
,
606 WM8994_DAC2_RIGHT_VOLUME
, 9, 1, 1),
608 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION
,
609 6, 1, 1, wm_hubs_spkmix_tlv
),
610 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION
,
611 2, 1, 1, wm_hubs_spkmix_tlv
),
613 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION
,
614 6, 1, 1, wm_hubs_spkmix_tlv
),
615 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION
,
616 2, 1, 1, wm_hubs_spkmix_tlv
),
618 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2
,
619 10, 15, 0, wm8994_3d_tlv
),
620 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2
,
622 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2
,
623 10, 15, 0, wm8994_3d_tlv
),
624 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2
,
626 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2
,
627 10, 15, 0, wm8994_3d_tlv
),
628 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2
,
632 static const struct snd_kcontrol_new wm8994_eq_controls
[] = {
633 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 11, 31, 0,
635 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 6, 31, 0,
637 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1
, 1, 31, 0,
639 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 11, 31, 0,
641 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2
, 6, 31, 0,
644 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 11, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 6, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1
, 1, 31, 0,
650 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 11, 31, 0,
652 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2
, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1
, 11, 31, 0,
657 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1
, 6, 31, 0,
659 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1
, 1, 31, 0,
661 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2
, 11, 31, 0,
663 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2
, 6, 31, 0,
667 static const struct snd_kcontrol_new wm8958_snd_controls
[] = {
668 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2
, 10, 3, 0, aif_tlv
),
671 static int clk_sys_event(struct snd_soc_dapm_widget
*w
,
672 struct snd_kcontrol
*kcontrol
, int event
)
674 struct snd_soc_codec
*codec
= w
->codec
;
677 case SND_SOC_DAPM_PRE_PMU
:
678 return configure_clock(codec
);
680 case SND_SOC_DAPM_POST_PMD
:
681 configure_clock(codec
);
688 static void wm8994_update_class_w(struct snd_soc_codec
*codec
)
690 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
692 int source
= 0; /* GCC flow analysis can't track enable */
695 /* Only support direct DAC->headphone paths */
696 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_1
);
697 if (!(reg
& WM8994_DAC1L_TO_HPOUT1L
)) {
698 dev_vdbg(codec
->dev
, "HPL connected to output mixer\n");
702 reg
= snd_soc_read(codec
, WM8994_OUTPUT_MIXER_2
);
703 if (!(reg
& WM8994_DAC1R_TO_HPOUT1R
)) {
704 dev_vdbg(codec
->dev
, "HPR connected to output mixer\n");
708 /* We also need the same setting for L/R and only one path */
709 reg
= snd_soc_read(codec
, WM8994_DAC1_LEFT_MIXER_ROUTING
);
711 case WM8994_AIF2DACL_TO_DAC1L
:
712 dev_vdbg(codec
->dev
, "Class W source AIF2DAC\n");
713 source
= 2 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
715 case WM8994_AIF1DAC2L_TO_DAC1L
:
716 dev_vdbg(codec
->dev
, "Class W source AIF1DAC2\n");
717 source
= 1 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
719 case WM8994_AIF1DAC1L_TO_DAC1L
:
720 dev_vdbg(codec
->dev
, "Class W source AIF1DAC1\n");
721 source
= 0 << WM8994_CP_DYN_SRC_SEL_SHIFT
;
724 dev_vdbg(codec
->dev
, "DAC mixer setting: %x\n", reg
);
729 reg_r
= snd_soc_read(codec
, WM8994_DAC1_RIGHT_MIXER_ROUTING
);
731 dev_vdbg(codec
->dev
, "Left and right DAC mixers different\n");
736 dev_dbg(codec
->dev
, "Class W enabled\n");
737 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
739 WM8994_CP_DYN_SRC_SEL_MASK
,
740 source
| WM8994_CP_DYN_PWR
);
741 wm8994
->hubs
.class_w
= true;
744 dev_dbg(codec
->dev
, "Class W disabled\n");
745 snd_soc_update_bits(codec
, WM8994_CLASS_W_1
,
746 WM8994_CP_DYN_PWR
, 0);
747 wm8994
->hubs
.class_w
= false;
751 static int late_enable_ev(struct snd_soc_dapm_widget
*w
,
752 struct snd_kcontrol
*kcontrol
, int event
)
754 struct snd_soc_codec
*codec
= w
->codec
;
755 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
758 case SND_SOC_DAPM_PRE_PMU
:
759 if (wm8994
->aif1clk_enable
) {
760 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
761 WM8994_AIF1CLK_ENA_MASK
,
763 wm8994
->aif1clk_enable
= 0;
765 if (wm8994
->aif2clk_enable
) {
766 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
767 WM8994_AIF2CLK_ENA_MASK
,
769 wm8994
->aif2clk_enable
= 0;
774 /* We may also have postponed startup of DSP, handle that. */
775 wm8958_aif_ev(w
, kcontrol
, event
);
780 static int late_disable_ev(struct snd_soc_dapm_widget
*w
,
781 struct snd_kcontrol
*kcontrol
, int event
)
783 struct snd_soc_codec
*codec
= w
->codec
;
784 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
787 case SND_SOC_DAPM_POST_PMD
:
788 if (wm8994
->aif1clk_disable
) {
789 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
790 WM8994_AIF1CLK_ENA_MASK
, 0);
791 wm8994
->aif1clk_disable
= 0;
793 if (wm8994
->aif2clk_disable
) {
794 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
795 WM8994_AIF2CLK_ENA_MASK
, 0);
796 wm8994
->aif2clk_disable
= 0;
804 static int aif1clk_ev(struct snd_soc_dapm_widget
*w
,
805 struct snd_kcontrol
*kcontrol
, int event
)
807 struct snd_soc_codec
*codec
= w
->codec
;
808 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
811 case SND_SOC_DAPM_PRE_PMU
:
812 wm8994
->aif1clk_enable
= 1;
814 case SND_SOC_DAPM_POST_PMD
:
815 wm8994
->aif1clk_disable
= 1;
822 static int aif2clk_ev(struct snd_soc_dapm_widget
*w
,
823 struct snd_kcontrol
*kcontrol
, int event
)
825 struct snd_soc_codec
*codec
= w
->codec
;
826 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
829 case SND_SOC_DAPM_PRE_PMU
:
830 wm8994
->aif2clk_enable
= 1;
832 case SND_SOC_DAPM_POST_PMD
:
833 wm8994
->aif2clk_disable
= 1;
840 static int adc_mux_ev(struct snd_soc_dapm_widget
*w
,
841 struct snd_kcontrol
*kcontrol
, int event
)
843 late_enable_ev(w
, kcontrol
, event
);
847 static int micbias_ev(struct snd_soc_dapm_widget
*w
,
848 struct snd_kcontrol
*kcontrol
, int event
)
850 late_enable_ev(w
, kcontrol
, event
);
854 static int dac_ev(struct snd_soc_dapm_widget
*w
,
855 struct snd_kcontrol
*kcontrol
, int event
)
857 struct snd_soc_codec
*codec
= w
->codec
;
858 unsigned int mask
= 1 << w
->shift
;
860 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
865 static const char *hp_mux_text
[] = {
870 #define WM8994_HP_ENUM(xname, xenum) \
871 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
872 .info = snd_soc_info_enum_double, \
873 .get = snd_soc_dapm_get_enum_double, \
874 .put = wm8994_put_hp_enum, \
875 .private_value = (unsigned long)&xenum }
877 static int wm8994_put_hp_enum(struct snd_kcontrol
*kcontrol
,
878 struct snd_ctl_elem_value
*ucontrol
)
880 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
881 struct snd_soc_codec
*codec
= w
->codec
;
884 ret
= snd_soc_dapm_put_enum_double(kcontrol
, ucontrol
);
886 wm8994_update_class_w(codec
);
891 static const struct soc_enum hpl_enum
=
892 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1
, 8, 2, hp_mux_text
);
894 static const struct snd_kcontrol_new hpl_mux
=
895 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum
);
897 static const struct soc_enum hpr_enum
=
898 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2
, 8, 2, hp_mux_text
);
900 static const struct snd_kcontrol_new hpr_mux
=
901 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum
);
903 static const char *adc_mux_text
[] = {
908 static const struct soc_enum adc_enum
=
909 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text
);
911 static const struct snd_kcontrol_new adcl_mux
=
912 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum
);
914 static const struct snd_kcontrol_new adcr_mux
=
915 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum
);
917 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
918 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 9, 1, 0),
919 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 7, 1, 0),
920 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER
, 5, 1, 0),
921 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 3, 1, 0),
922 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 1, 1, 0),
925 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
926 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER
, 8, 1, 0),
927 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER
, 6, 1, 0),
928 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER
, 4, 1, 0),
929 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER
, 2, 1, 0),
930 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER
, 0, 1, 0),
933 /* Debugging; dump chip status after DAPM transitions */
934 static int post_ev(struct snd_soc_dapm_widget
*w
,
935 struct snd_kcontrol
*kcontrol
, int event
)
937 struct snd_soc_codec
*codec
= w
->codec
;
938 dev_dbg(codec
->dev
, "SRC status: %x\n",
940 WM8994_RATE_STATUS
));
944 static const struct snd_kcontrol_new aif1adc1l_mix
[] = {
945 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
947 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING
,
951 static const struct snd_kcontrol_new aif1adc1r_mix
[] = {
952 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
954 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING
,
958 static const struct snd_kcontrol_new aif1adc2l_mix
[] = {
959 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
961 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING
,
965 static const struct snd_kcontrol_new aif1adc2r_mix
[] = {
966 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
968 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING
,
972 static const struct snd_kcontrol_new aif2dac2l_mix
[] = {
973 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
975 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
977 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
979 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
981 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING
,
985 static const struct snd_kcontrol_new aif2dac2r_mix
[] = {
986 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
988 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
990 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
992 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
994 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING
,
998 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
999 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1000 .info = snd_soc_info_volsw, \
1001 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1002 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1004 static int wm8994_put_class_w(struct snd_kcontrol
*kcontrol
,
1005 struct snd_ctl_elem_value
*ucontrol
)
1007 struct snd_soc_dapm_widget
*w
= snd_kcontrol_chip(kcontrol
);
1008 struct snd_soc_codec
*codec
= w
->codec
;
1011 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
1013 wm8994_update_class_w(codec
);
1018 static const struct snd_kcontrol_new dac1l_mix
[] = {
1019 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1021 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1023 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1025 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1027 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING
,
1031 static const struct snd_kcontrol_new dac1r_mix
[] = {
1032 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1034 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1036 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1038 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1040 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING
,
1044 static const char *sidetone_text
[] = {
1045 "ADC/DMIC1", "DMIC2",
1048 static const struct soc_enum sidetone1_enum
=
1049 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 0, 2, sidetone_text
);
1051 static const struct snd_kcontrol_new sidetone1_mux
=
1052 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum
);
1054 static const struct soc_enum sidetone2_enum
=
1055 SOC_ENUM_SINGLE(WM8994_SIDETONE
, 1, 2, sidetone_text
);
1057 static const struct snd_kcontrol_new sidetone2_mux
=
1058 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum
);
1060 static const char *aif1dac_text
[] = {
1061 "AIF1DACDAT", "AIF3DACDAT",
1064 static const struct soc_enum aif1dac_enum
=
1065 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 0, 2, aif1dac_text
);
1067 static const struct snd_kcontrol_new aif1dac_mux
=
1068 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum
);
1070 static const char *aif2dac_text
[] = {
1071 "AIF2DACDAT", "AIF3DACDAT",
1074 static const struct soc_enum aif2dac_enum
=
1075 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 1, 2, aif2dac_text
);
1077 static const struct snd_kcontrol_new aif2dac_mux
=
1078 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum
);
1080 static const char *aif2adc_text
[] = {
1081 "AIF2ADCDAT", "AIF3DACDAT",
1084 static const struct soc_enum aif2adc_enum
=
1085 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 2, 2, aif2adc_text
);
1087 static const struct snd_kcontrol_new aif2adc_mux
=
1088 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum
);
1090 static const char *aif3adc_text
[] = {
1091 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1094 static const struct soc_enum wm8994_aif3adc_enum
=
1095 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 3, aif3adc_text
);
1097 static const struct snd_kcontrol_new wm8994_aif3adc_mux
=
1098 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum
);
1100 static const struct soc_enum wm8958_aif3adc_enum
=
1101 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 3, 4, aif3adc_text
);
1103 static const struct snd_kcontrol_new wm8958_aif3adc_mux
=
1104 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum
);
1106 static const char *mono_pcm_out_text
[] = {
1107 "None", "AIF2ADCL", "AIF2ADCR",
1110 static const struct soc_enum mono_pcm_out_enum
=
1111 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 9, 3, mono_pcm_out_text
);
1113 static const struct snd_kcontrol_new mono_pcm_out_mux
=
1114 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum
);
1116 static const char *aif2dac_src_text
[] = {
1120 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1121 static const struct soc_enum aif2dacl_src_enum
=
1122 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 7, 2, aif2dac_src_text
);
1124 static const struct snd_kcontrol_new aif2dacl_src_mux
=
1125 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum
);
1127 static const struct soc_enum aif2dacr_src_enum
=
1128 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6
, 8, 2, aif2dac_src_text
);
1130 static const struct snd_kcontrol_new aif2dacr_src_mux
=
1131 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum
);
1133 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets
[] = {
1134 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM
, 0, 0, aif1clk_ev
,
1135 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1136 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM
, 0, 0, aif2clk_ev
,
1137 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
1139 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1140 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1141 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1142 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1143 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1144 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1145 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0,
1146 late_enable_ev
, SND_SOC_DAPM_PRE_PMU
),
1148 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev
)
1151 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets
[] = {
1152 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1
, 0, 0, NULL
, 0),
1153 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1
, 0, 0, NULL
, 0)
1156 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets
[] = {
1157 SND_SOC_DAPM_DAC_E("DAC2L", NULL
, SND_SOC_NOPM
, 3, 0,
1158 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1159 SND_SOC_DAPM_DAC_E("DAC2R", NULL
, SND_SOC_NOPM
, 2, 0,
1160 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1161 SND_SOC_DAPM_DAC_E("DAC1L", NULL
, SND_SOC_NOPM
, 1, 0,
1162 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1163 SND_SOC_DAPM_DAC_E("DAC1R", NULL
, SND_SOC_NOPM
, 0, 0,
1164 dac_ev
, SND_SOC_DAPM_PRE_PMU
),
1167 static const struct snd_soc_dapm_widget wm8994_dac_widgets
[] = {
1168 SND_SOC_DAPM_DAC("DAC2L", NULL
, WM8994_POWER_MANAGEMENT_5
, 3, 0),
1169 SND_SOC_DAPM_DAC("DAC2R", NULL
, WM8994_POWER_MANAGEMENT_5
, 2, 0),
1170 SND_SOC_DAPM_DAC("DAC1L", NULL
, WM8994_POWER_MANAGEMENT_5
, 1, 0),
1171 SND_SOC_DAPM_DAC("DAC1R", NULL
, WM8994_POWER_MANAGEMENT_5
, 0, 0),
1174 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets
[] = {
1175 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
,
1176 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1177 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
,
1178 adc_mux_ev
, SND_SOC_DAPM_PRE_PMU
),
1181 static const struct snd_soc_dapm_widget wm8994_adc_widgets
[] = {
1182 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4
, 1, 0, &adcl_mux
),
1183 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4
, 0, 0, &adcr_mux
),
1186 static const struct snd_soc_dapm_widget wm8994_dapm_widgets
[] = {
1187 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1188 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1189 SND_SOC_DAPM_INPUT("Clock"),
1191 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS
, 2, 0),
1192 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM
, 0, 0, micbias_ev
,
1193 SND_SOC_DAPM_PRE_PMU
),
1195 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM
, 0, 0, clk_sys_event
,
1196 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1198 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1
, 3, 0, NULL
, 0),
1199 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1
, 2, 0, NULL
, 0),
1200 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1
, 1, 0, NULL
, 0),
1202 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL
,
1203 0, WM8994_POWER_MANAGEMENT_4
, 9, 0),
1204 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL
,
1205 0, WM8994_POWER_MANAGEMENT_4
, 8, 0),
1206 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL
, 0,
1207 WM8994_POWER_MANAGEMENT_5
, 9, 0, wm8958_aif_ev
,
1208 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1209 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL
, 0,
1210 WM8994_POWER_MANAGEMENT_5
, 8, 0, wm8958_aif_ev
,
1211 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1213 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL
,
1214 0, WM8994_POWER_MANAGEMENT_4
, 11, 0),
1215 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL
,
1216 0, WM8994_POWER_MANAGEMENT_4
, 10, 0),
1217 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL
, 0,
1218 WM8994_POWER_MANAGEMENT_5
, 11, 0, wm8958_aif_ev
,
1219 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1220 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL
, 0,
1221 WM8994_POWER_MANAGEMENT_5
, 10, 0, wm8958_aif_ev
,
1222 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1224 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM
, 0, 0,
1225 aif1adc1l_mix
, ARRAY_SIZE(aif1adc1l_mix
)),
1226 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM
, 0, 0,
1227 aif1adc1r_mix
, ARRAY_SIZE(aif1adc1r_mix
)),
1229 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM
, 0, 0,
1230 aif1adc2l_mix
, ARRAY_SIZE(aif1adc2l_mix
)),
1231 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM
, 0, 0,
1232 aif1adc2r_mix
, ARRAY_SIZE(aif1adc2r_mix
)),
1234 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM
, 0, 0,
1235 aif2dac2l_mix
, ARRAY_SIZE(aif2dac2l_mix
)),
1236 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM
, 0, 0,
1237 aif2dac2r_mix
, ARRAY_SIZE(aif2dac2r_mix
)),
1239 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone1_mux
),
1240 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM
, 0, 0, &sidetone2_mux
),
1242 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM
, 0, 0,
1243 dac1l_mix
, ARRAY_SIZE(dac1l_mix
)),
1244 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM
, 0, 0,
1245 dac1r_mix
, ARRAY_SIZE(dac1r_mix
)),
1247 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL
, 0,
1248 WM8994_POWER_MANAGEMENT_4
, 13, 0),
1249 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL
, 0,
1250 WM8994_POWER_MANAGEMENT_4
, 12, 0),
1251 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL
, 0,
1252 WM8994_POWER_MANAGEMENT_5
, 13, 0, wm8958_aif_ev
,
1253 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1254 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL
, 0,
1255 WM8994_POWER_MANAGEMENT_5
, 12, 0, wm8958_aif_ev
,
1256 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
1258 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM
, 0, 0),
1259 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM
, 0, 0),
1260 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM
, 0, 0),
1261 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM
, 0, 0),
1263 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM
, 0, 0, &aif1dac_mux
),
1264 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM
, 0, 0, &aif2dac_mux
),
1265 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM
, 0, 0, &aif2adc_mux
),
1267 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM
, 0, 0),
1268 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM
, 0, 0),
1270 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1
, 4, 0, NULL
, 0),
1272 SND_SOC_DAPM_ADC("DMIC2L", NULL
, WM8994_POWER_MANAGEMENT_4
, 5, 0),
1273 SND_SOC_DAPM_ADC("DMIC2R", NULL
, WM8994_POWER_MANAGEMENT_4
, 4, 0),
1274 SND_SOC_DAPM_ADC("DMIC1L", NULL
, WM8994_POWER_MANAGEMENT_4
, 3, 0),
1275 SND_SOC_DAPM_ADC("DMIC1R", NULL
, WM8994_POWER_MANAGEMENT_4
, 2, 0),
1277 /* Power is done with the muxes since the ADC power also controls the
1278 * downsampling chain, the chip will automatically manage the analogue
1279 * specific portions.
1281 SND_SOC_DAPM_ADC("ADCL", NULL
, SND_SOC_NOPM
, 1, 0),
1282 SND_SOC_DAPM_ADC("ADCR", NULL
, SND_SOC_NOPM
, 0, 0),
1284 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpl_mux
),
1285 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM
, 0, 0, &hpr_mux
),
1287 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3
, 8, 0,
1288 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
1289 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3
, 9, 0,
1290 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
1292 SND_SOC_DAPM_POST("Debug log", post_ev
),
1295 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets
[] = {
1296 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8994_aif3adc_mux
),
1299 static const struct snd_soc_dapm_widget wm8958_dapm_widgets
[] = {
1300 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM
, 0, 0, &mono_pcm_out_mux
),
1301 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM
, 0, 0, &aif2dacl_src_mux
),
1302 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM
, 0, 0, &aif2dacr_src_mux
),
1303 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM
, 0, 0, &wm8958_aif3adc_mux
),
1306 static const struct snd_soc_dapm_route intercon
[] = {
1307 { "CLK_SYS", NULL
, "AIF1CLK", check_clk_sys
},
1308 { "CLK_SYS", NULL
, "AIF2CLK", check_clk_sys
},
1310 { "DSP1CLK", NULL
, "CLK_SYS" },
1311 { "DSP2CLK", NULL
, "CLK_SYS" },
1312 { "DSPINTCLK", NULL
, "CLK_SYS" },
1314 { "AIF1ADC1L", NULL
, "AIF1CLK" },
1315 { "AIF1ADC1L", NULL
, "DSP1CLK" },
1316 { "AIF1ADC1R", NULL
, "AIF1CLK" },
1317 { "AIF1ADC1R", NULL
, "DSP1CLK" },
1318 { "AIF1ADC1R", NULL
, "DSPINTCLK" },
1320 { "AIF1DAC1L", NULL
, "AIF1CLK" },
1321 { "AIF1DAC1L", NULL
, "DSP1CLK" },
1322 { "AIF1DAC1R", NULL
, "AIF1CLK" },
1323 { "AIF1DAC1R", NULL
, "DSP1CLK" },
1324 { "AIF1DAC1R", NULL
, "DSPINTCLK" },
1326 { "AIF1ADC2L", NULL
, "AIF1CLK" },
1327 { "AIF1ADC2L", NULL
, "DSP1CLK" },
1328 { "AIF1ADC2R", NULL
, "AIF1CLK" },
1329 { "AIF1ADC2R", NULL
, "DSP1CLK" },
1330 { "AIF1ADC2R", NULL
, "DSPINTCLK" },
1332 { "AIF1DAC2L", NULL
, "AIF1CLK" },
1333 { "AIF1DAC2L", NULL
, "DSP1CLK" },
1334 { "AIF1DAC2R", NULL
, "AIF1CLK" },
1335 { "AIF1DAC2R", NULL
, "DSP1CLK" },
1336 { "AIF1DAC2R", NULL
, "DSPINTCLK" },
1338 { "AIF2ADCL", NULL
, "AIF2CLK" },
1339 { "AIF2ADCL", NULL
, "DSP2CLK" },
1340 { "AIF2ADCR", NULL
, "AIF2CLK" },
1341 { "AIF2ADCR", NULL
, "DSP2CLK" },
1342 { "AIF2ADCR", NULL
, "DSPINTCLK" },
1344 { "AIF2DACL", NULL
, "AIF2CLK" },
1345 { "AIF2DACL", NULL
, "DSP2CLK" },
1346 { "AIF2DACR", NULL
, "AIF2CLK" },
1347 { "AIF2DACR", NULL
, "DSP2CLK" },
1348 { "AIF2DACR", NULL
, "DSPINTCLK" },
1350 { "DMIC1L", NULL
, "DMIC1DAT" },
1351 { "DMIC1L", NULL
, "CLK_SYS" },
1352 { "DMIC1R", NULL
, "DMIC1DAT" },
1353 { "DMIC1R", NULL
, "CLK_SYS" },
1354 { "DMIC2L", NULL
, "DMIC2DAT" },
1355 { "DMIC2L", NULL
, "CLK_SYS" },
1356 { "DMIC2R", NULL
, "DMIC2DAT" },
1357 { "DMIC2R", NULL
, "CLK_SYS" },
1359 { "ADCL", NULL
, "AIF1CLK" },
1360 { "ADCL", NULL
, "DSP1CLK" },
1361 { "ADCL", NULL
, "DSPINTCLK" },
1363 { "ADCR", NULL
, "AIF1CLK" },
1364 { "ADCR", NULL
, "DSP1CLK" },
1365 { "ADCR", NULL
, "DSPINTCLK" },
1367 { "ADCL Mux", "ADC", "ADCL" },
1368 { "ADCL Mux", "DMIC", "DMIC1L" },
1369 { "ADCR Mux", "ADC", "ADCR" },
1370 { "ADCR Mux", "DMIC", "DMIC1R" },
1372 { "DAC1L", NULL
, "AIF1CLK" },
1373 { "DAC1L", NULL
, "DSP1CLK" },
1374 { "DAC1L", NULL
, "DSPINTCLK" },
1376 { "DAC1R", NULL
, "AIF1CLK" },
1377 { "DAC1R", NULL
, "DSP1CLK" },
1378 { "DAC1R", NULL
, "DSPINTCLK" },
1380 { "DAC2L", NULL
, "AIF2CLK" },
1381 { "DAC2L", NULL
, "DSP2CLK" },
1382 { "DAC2L", NULL
, "DSPINTCLK" },
1384 { "DAC2R", NULL
, "AIF2DACR" },
1385 { "DAC2R", NULL
, "AIF2CLK" },
1386 { "DAC2R", NULL
, "DSP2CLK" },
1387 { "DAC2R", NULL
, "DSPINTCLK" },
1389 { "TOCLK", NULL
, "CLK_SYS" },
1392 { "AIF1ADC1L", NULL
, "AIF1ADC1L Mixer" },
1393 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1394 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1396 { "AIF1ADC1R", NULL
, "AIF1ADC1R Mixer" },
1397 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1398 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1400 { "AIF1ADC2L", NULL
, "AIF1ADC2L Mixer" },
1401 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1402 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1404 { "AIF1ADC2R", NULL
, "AIF1ADC2R Mixer" },
1405 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1406 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1408 /* Pin level routing for AIF3 */
1409 { "AIF1DAC1L", NULL
, "AIF1DAC Mux" },
1410 { "AIF1DAC1R", NULL
, "AIF1DAC Mux" },
1411 { "AIF1DAC2L", NULL
, "AIF1DAC Mux" },
1412 { "AIF1DAC2R", NULL
, "AIF1DAC Mux" },
1414 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1415 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1416 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1417 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1418 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1419 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1420 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1423 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1424 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1425 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1426 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1427 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1429 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1430 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1431 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1432 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1433 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1435 /* DAC2/AIF2 outputs */
1436 { "AIF2ADCL", NULL
, "AIF2DAC2L Mixer" },
1437 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1438 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1439 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1440 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1441 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1443 { "AIF2ADCR", NULL
, "AIF2DAC2R Mixer" },
1444 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1445 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1446 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1447 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1448 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1450 { "AIF1ADCDAT", NULL
, "AIF1ADC1L" },
1451 { "AIF1ADCDAT", NULL
, "AIF1ADC1R" },
1452 { "AIF1ADCDAT", NULL
, "AIF1ADC2L" },
1453 { "AIF1ADCDAT", NULL
, "AIF1ADC2R" },
1455 { "AIF2ADCDAT", NULL
, "AIF2ADC Mux" },
1458 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1459 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1460 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1461 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1462 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1463 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1464 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1465 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1468 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1469 { "Left Sidetone", "DMIC2", "DMIC2L" },
1470 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1471 { "Right Sidetone", "DMIC2", "DMIC2R" },
1474 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1475 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1477 { "SPKL", "DAC1 Switch", "DAC1L" },
1478 { "SPKL", "DAC2 Switch", "DAC2L" },
1480 { "SPKR", "DAC1 Switch", "DAC1R" },
1481 { "SPKR", "DAC2 Switch", "DAC2R" },
1483 { "Left Headphone Mux", "DAC", "DAC1L" },
1484 { "Right Headphone Mux", "DAC", "DAC1R" },
1487 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon
[] = {
1488 { "DAC1L", NULL
, "Late DAC1L Enable PGA" },
1489 { "Late DAC1L Enable PGA", NULL
, "DAC1L Mixer" },
1490 { "DAC1R", NULL
, "Late DAC1R Enable PGA" },
1491 { "Late DAC1R Enable PGA", NULL
, "DAC1R Mixer" },
1492 { "DAC2L", NULL
, "Late DAC2L Enable PGA" },
1493 { "Late DAC2L Enable PGA", NULL
, "AIF2DAC2L Mixer" },
1494 { "DAC2R", NULL
, "Late DAC2R Enable PGA" },
1495 { "Late DAC2R Enable PGA", NULL
, "AIF2DAC2R Mixer" }
1498 static const struct snd_soc_dapm_route wm8994_lateclk_intercon
[] = {
1499 { "DAC1L", NULL
, "DAC1L Mixer" },
1500 { "DAC1R", NULL
, "DAC1R Mixer" },
1501 { "DAC2L", NULL
, "AIF2DAC2L Mixer" },
1502 { "DAC2R", NULL
, "AIF2DAC2R Mixer" },
1505 static const struct snd_soc_dapm_route wm8994_revd_intercon
[] = {
1506 { "AIF1DACDAT", NULL
, "AIF2DACDAT" },
1507 { "AIF2DACDAT", NULL
, "AIF1DACDAT" },
1508 { "AIF1ADCDAT", NULL
, "AIF2ADCDAT" },
1509 { "AIF2ADCDAT", NULL
, "AIF1ADCDAT" },
1510 { "MICBIAS", NULL
, "CLK_SYS" },
1511 { "MICBIAS", NULL
, "MICBIAS Supply" },
1514 static const struct snd_soc_dapm_route wm8994_intercon
[] = {
1515 { "AIF2DACL", NULL
, "AIF2DAC Mux" },
1516 { "AIF2DACR", NULL
, "AIF2DAC Mux" },
1519 static const struct snd_soc_dapm_route wm8958_intercon
[] = {
1520 { "AIF2DACL", NULL
, "AIF2DACL Mux" },
1521 { "AIF2DACR", NULL
, "AIF2DACR Mux" },
1523 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1524 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1525 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1526 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1528 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1529 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1531 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1534 /* The size in bits of the FLL divide multiplied by 10
1535 * to allow rounding later */
1536 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1546 static int wm8994_get_fll_config(struct fll_div
*fll
,
1547 int freq_in
, int freq_out
)
1550 unsigned int K
, Ndiv
, Nmod
;
1552 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in
, freq_out
);
1554 /* Scale the input frequency down to <= 13.5MHz */
1555 fll
->clk_ref_div
= 0;
1556 while (freq_in
> 13500000) {
1560 if (fll
->clk_ref_div
> 3)
1563 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll
->clk_ref_div
, freq_in
);
1565 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1567 while (freq_out
* (fll
->outdiv
+ 1) < 90000000) {
1569 if (fll
->outdiv
> 63)
1572 freq_out
*= fll
->outdiv
+ 1;
1573 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll
->outdiv
, freq_out
);
1575 if (freq_in
> 1000000) {
1576 fll
->fll_fratio
= 0;
1577 } else if (freq_in
> 256000) {
1578 fll
->fll_fratio
= 1;
1580 } else if (freq_in
> 128000) {
1581 fll
->fll_fratio
= 2;
1583 } else if (freq_in
> 64000) {
1584 fll
->fll_fratio
= 3;
1587 fll
->fll_fratio
= 4;
1590 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll
->fll_fratio
, freq_in
);
1592 /* Now, calculate N.K */
1593 Ndiv
= freq_out
/ freq_in
;
1596 Nmod
= freq_out
% freq_in
;
1597 pr_debug("Nmod=%d\n", Nmod
);
1599 /* Calculate fractional part - scale up so we can round. */
1600 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
1602 do_div(Kpart
, freq_in
);
1604 K
= Kpart
& 0xFFFFFFFF;
1609 /* Move down to proper range now rounding is done */
1612 pr_debug("N=%x K=%x\n", fll
->n
, fll
->k
);
1617 static int _wm8994_set_fll(struct snd_soc_codec
*codec
, int id
, int src
,
1618 unsigned int freq_in
, unsigned int freq_out
)
1620 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1621 int reg_offset
, ret
;
1623 u16 reg
, aif1
, aif2
;
1625 aif1
= snd_soc_read(codec
, WM8994_AIF1_CLOCKING_1
)
1626 & WM8994_AIF1CLK_ENA
;
1628 aif2
= snd_soc_read(codec
, WM8994_AIF2_CLOCKING_1
)
1629 & WM8994_AIF2CLK_ENA
;
1646 /* Allow no source specification when stopping */
1649 src
= wm8994
->fll
[id
].src
;
1651 case WM8994_FLL_SRC_MCLK1
:
1652 case WM8994_FLL_SRC_MCLK2
:
1653 case WM8994_FLL_SRC_LRCLK
:
1654 case WM8994_FLL_SRC_BCLK
:
1660 /* Are we changing anything? */
1661 if (wm8994
->fll
[id
].src
== src
&&
1662 wm8994
->fll
[id
].in
== freq_in
&& wm8994
->fll
[id
].out
== freq_out
)
1665 /* If we're stopping the FLL redo the old config - no
1666 * registers will actually be written but we avoid GCC flow
1667 * analysis bugs spewing warnings.
1670 ret
= wm8994_get_fll_config(&fll
, freq_in
, freq_out
);
1672 ret
= wm8994_get_fll_config(&fll
, wm8994
->fll
[id
].in
,
1673 wm8994
->fll
[id
].out
);
1677 /* Gate the AIF clocks while we reclock */
1678 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1679 WM8994_AIF1CLK_ENA
, 0);
1680 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1681 WM8994_AIF2CLK_ENA
, 0);
1683 /* We always need to disable the FLL while reconfiguring */
1684 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1685 WM8994_FLL1_ENA
, 0);
1687 reg
= (fll
.outdiv
<< WM8994_FLL1_OUTDIV_SHIFT
) |
1688 (fll
.fll_fratio
<< WM8994_FLL1_FRATIO_SHIFT
);
1689 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_2
+ reg_offset
,
1690 WM8994_FLL1_OUTDIV_MASK
|
1691 WM8994_FLL1_FRATIO_MASK
, reg
);
1693 snd_soc_write(codec
, WM8994_FLL1_CONTROL_3
+ reg_offset
, fll
.k
);
1695 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_4
+ reg_offset
,
1697 fll
.n
<< WM8994_FLL1_N_SHIFT
);
1699 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_5
+ reg_offset
,
1700 WM8994_FLL1_REFCLK_DIV_MASK
|
1701 WM8994_FLL1_REFCLK_SRC_MASK
,
1702 (fll
.clk_ref_div
<< WM8994_FLL1_REFCLK_DIV_SHIFT
) |
1705 /* Enable (with fractional mode if required) */
1708 reg
= WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
;
1710 reg
= WM8994_FLL1_ENA
;
1711 snd_soc_update_bits(codec
, WM8994_FLL1_CONTROL_1
+ reg_offset
,
1712 WM8994_FLL1_ENA
| WM8994_FLL1_FRAC
,
1716 wm8994
->fll
[id
].in
= freq_in
;
1717 wm8994
->fll
[id
].out
= freq_out
;
1718 wm8994
->fll
[id
].src
= src
;
1720 /* Enable any gated AIF clocks */
1721 snd_soc_update_bits(codec
, WM8994_AIF1_CLOCKING_1
,
1722 WM8994_AIF1CLK_ENA
, aif1
);
1723 snd_soc_update_bits(codec
, WM8994_AIF2_CLOCKING_1
,
1724 WM8994_AIF2CLK_ENA
, aif2
);
1726 configure_clock(codec
);
1732 static int opclk_divs
[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1734 static int wm8994_set_fll(struct snd_soc_dai
*dai
, int id
, int src
,
1735 unsigned int freq_in
, unsigned int freq_out
)
1737 return _wm8994_set_fll(dai
->codec
, id
, src
, freq_in
, freq_out
);
1740 static int wm8994_set_dai_sysclk(struct snd_soc_dai
*dai
,
1741 int clk_id
, unsigned int freq
, int dir
)
1743 struct snd_soc_codec
*codec
= dai
->codec
;
1744 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1753 /* AIF3 shares clocking with AIF1/2 */
1758 case WM8994_SYSCLK_MCLK1
:
1759 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK1
;
1760 wm8994
->mclk
[0] = freq
;
1761 dev_dbg(dai
->dev
, "AIF%d using MCLK1 at %uHz\n",
1765 case WM8994_SYSCLK_MCLK2
:
1766 /* TODO: Set GPIO AF */
1767 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_MCLK2
;
1768 wm8994
->mclk
[1] = freq
;
1769 dev_dbg(dai
->dev
, "AIF%d using MCLK2 at %uHz\n",
1773 case WM8994_SYSCLK_FLL1
:
1774 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL1
;
1775 dev_dbg(dai
->dev
, "AIF%d using FLL1\n", dai
->id
);
1778 case WM8994_SYSCLK_FLL2
:
1779 wm8994
->sysclk
[dai
->id
- 1] = WM8994_SYSCLK_FLL2
;
1780 dev_dbg(dai
->dev
, "AIF%d using FLL2\n", dai
->id
);
1783 case WM8994_SYSCLK_OPCLK
:
1784 /* Special case - a division (times 10) is given and
1785 * no effect on main clocking.
1788 for (i
= 0; i
< ARRAY_SIZE(opclk_divs
); i
++)
1789 if (opclk_divs
[i
] == freq
)
1791 if (i
== ARRAY_SIZE(opclk_divs
))
1793 snd_soc_update_bits(codec
, WM8994_CLOCKING_2
,
1794 WM8994_OPCLK_DIV_MASK
, i
);
1795 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1796 WM8994_OPCLK_ENA
, WM8994_OPCLK_ENA
);
1798 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_2
,
1799 WM8994_OPCLK_ENA
, 0);
1806 configure_clock(codec
);
1811 static int wm8994_set_bias_level(struct snd_soc_codec
*codec
,
1812 enum snd_soc_bias_level level
)
1814 struct wm8994
*control
= codec
->control_data
;
1815 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
1818 case SND_SOC_BIAS_ON
:
1821 case SND_SOC_BIAS_PREPARE
:
1823 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1824 WM8994_VMID_SEL_MASK
, 0x2);
1827 case SND_SOC_BIAS_STANDBY
:
1828 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1829 pm_runtime_get_sync(codec
->dev
);
1831 switch (control
->type
) {
1833 if (wm8994
->revision
< 4) {
1834 /* Tweak DC servo and DSP
1835 * configuration for improved
1837 snd_soc_write(codec
, 0x102, 0x3);
1838 snd_soc_write(codec
, 0x56, 0x3);
1839 snd_soc_write(codec
, 0x817, 0);
1840 snd_soc_write(codec
, 0x102, 0);
1845 if (wm8994
->revision
== 0) {
1846 /* Optimise performance for rev A */
1847 snd_soc_write(codec
, 0x102, 0x3);
1848 snd_soc_write(codec
, 0xcb, 0x81);
1849 snd_soc_write(codec
, 0x817, 0);
1850 snd_soc_write(codec
, 0x102, 0);
1852 snd_soc_update_bits(codec
,
1853 WM8958_CHARGE_PUMP_2
,
1860 /* Discharge LINEOUT1 & 2 */
1861 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1862 WM8994_LINEOUT1_DISCH
|
1863 WM8994_LINEOUT2_DISCH
,
1864 WM8994_LINEOUT1_DISCH
|
1865 WM8994_LINEOUT2_DISCH
);
1867 /* Startup bias, VMID ramp & buffer */
1868 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1869 WM8994_STARTUP_BIAS_ENA
|
1870 WM8994_VMID_BUF_ENA
|
1871 WM8994_VMID_RAMP_MASK
,
1872 WM8994_STARTUP_BIAS_ENA
|
1873 WM8994_VMID_BUF_ENA
|
1874 (0x11 << WM8994_VMID_RAMP_SHIFT
));
1876 /* Main bias enable, VMID=2x40k */
1877 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1879 WM8994_VMID_SEL_MASK
,
1880 WM8994_BIAS_ENA
| 0x2);
1886 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1887 WM8994_VMID_SEL_MASK
, 0x4);
1891 case SND_SOC_BIAS_OFF
:
1892 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_STANDBY
) {
1893 /* Switch over to startup biases */
1894 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1896 WM8994_STARTUP_BIAS_ENA
|
1897 WM8994_VMID_BUF_ENA
|
1898 WM8994_VMID_RAMP_MASK
,
1900 WM8994_STARTUP_BIAS_ENA
|
1901 WM8994_VMID_BUF_ENA
|
1902 (1 << WM8994_VMID_RAMP_SHIFT
));
1904 /* Disable main biases */
1905 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_1
,
1907 WM8994_VMID_SEL_MASK
, 0);
1909 /* Discharge line */
1910 snd_soc_update_bits(codec
, WM8994_ANTIPOP_1
,
1911 WM8994_LINEOUT1_DISCH
|
1912 WM8994_LINEOUT2_DISCH
,
1913 WM8994_LINEOUT1_DISCH
|
1914 WM8994_LINEOUT2_DISCH
);
1918 /* Switch off startup biases */
1919 snd_soc_update_bits(codec
, WM8994_ANTIPOP_2
,
1921 WM8994_STARTUP_BIAS_ENA
|
1922 WM8994_VMID_BUF_ENA
|
1923 WM8994_VMID_RAMP_MASK
, 0);
1925 wm8994
->cur_fw
= NULL
;
1927 pm_runtime_put(codec
->dev
);
1931 codec
->dapm
.bias_level
= level
;
1935 static int wm8994_set_dai_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1937 struct snd_soc_codec
*codec
= dai
->codec
;
1938 struct wm8994
*control
= codec
->control_data
;
1946 ms_reg
= WM8994_AIF1_MASTER_SLAVE
;
1947 aif1_reg
= WM8994_AIF1_CONTROL_1
;
1950 ms_reg
= WM8994_AIF2_MASTER_SLAVE
;
1951 aif1_reg
= WM8994_AIF2_CONTROL_1
;
1957 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1958 case SND_SOC_DAIFMT_CBS_CFS
:
1960 case SND_SOC_DAIFMT_CBM_CFM
:
1961 ms
= WM8994_AIF1_MSTR
;
1967 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1968 case SND_SOC_DAIFMT_DSP_B
:
1969 aif1
|= WM8994_AIF1_LRCLK_INV
;
1970 case SND_SOC_DAIFMT_DSP_A
:
1973 case SND_SOC_DAIFMT_I2S
:
1976 case SND_SOC_DAIFMT_RIGHT_J
:
1978 case SND_SOC_DAIFMT_LEFT_J
:
1985 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1986 case SND_SOC_DAIFMT_DSP_A
:
1987 case SND_SOC_DAIFMT_DSP_B
:
1988 /* frame inversion not valid for DSP modes */
1989 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1990 case SND_SOC_DAIFMT_NB_NF
:
1992 case SND_SOC_DAIFMT_IB_NF
:
1993 aif1
|= WM8994_AIF1_BCLK_INV
;
2000 case SND_SOC_DAIFMT_I2S
:
2001 case SND_SOC_DAIFMT_RIGHT_J
:
2002 case SND_SOC_DAIFMT_LEFT_J
:
2003 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
2004 case SND_SOC_DAIFMT_NB_NF
:
2006 case SND_SOC_DAIFMT_IB_IF
:
2007 aif1
|= WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
;
2009 case SND_SOC_DAIFMT_IB_NF
:
2010 aif1
|= WM8994_AIF1_BCLK_INV
;
2012 case SND_SOC_DAIFMT_NB_IF
:
2013 aif1
|= WM8994_AIF1_LRCLK_INV
;
2023 /* The AIF2 format configuration needs to be mirrored to AIF3
2024 * on WM8958 if it's in use so just do it all the time. */
2025 if (control
->type
== WM8958
&& dai
->id
== 2)
2026 snd_soc_update_bits(codec
, WM8958_AIF3_CONTROL_1
,
2027 WM8994_AIF1_LRCLK_INV
|
2028 WM8958_AIF3_FMT_MASK
, aif1
);
2030 snd_soc_update_bits(codec
, aif1_reg
,
2031 WM8994_AIF1_BCLK_INV
| WM8994_AIF1_LRCLK_INV
|
2032 WM8994_AIF1_FMT_MASK
,
2034 snd_soc_update_bits(codec
, ms_reg
, WM8994_AIF1_MSTR
,
2056 static int fs_ratios
[] = {
2057 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2060 static int bclk_divs
[] = {
2061 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2062 640, 880, 960, 1280, 1760, 1920
2065 static int wm8994_hw_params(struct snd_pcm_substream
*substream
,
2066 struct snd_pcm_hw_params
*params
,
2067 struct snd_soc_dai
*dai
)
2069 struct snd_soc_codec
*codec
= dai
->codec
;
2070 struct wm8994
*control
= codec
->control_data
;
2071 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2082 int id
= dai
->id
- 1;
2084 int i
, cur_val
, best_val
, bclk_rate
, best
;
2088 aif1_reg
= WM8994_AIF1_CONTROL_1
;
2089 aif2_reg
= WM8994_AIF1_CONTROL_2
;
2090 bclk_reg
= WM8994_AIF1_BCLK
;
2091 rate_reg
= WM8994_AIF1_RATE
;
2092 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2093 wm8994
->lrclk_shared
[0]) {
2094 lrclk_reg
= WM8994_AIF1DAC_LRCLK
;
2096 lrclk_reg
= WM8994_AIF1ADC_LRCLK
;
2097 dev_dbg(codec
->dev
, "AIF1 using split LRCLK\n");
2101 aif1_reg
= WM8994_AIF2_CONTROL_1
;
2102 aif2_reg
= WM8994_AIF2_CONTROL_2
;
2103 bclk_reg
= WM8994_AIF2_BCLK
;
2104 rate_reg
= WM8994_AIF2_RATE
;
2105 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
||
2106 wm8994
->lrclk_shared
[1]) {
2107 lrclk_reg
= WM8994_AIF2DAC_LRCLK
;
2109 lrclk_reg
= WM8994_AIF2ADC_LRCLK
;
2110 dev_dbg(codec
->dev
, "AIF2 using split LRCLK\n");
2114 switch (control
->type
) {
2116 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2125 bclk_rate
= params_rate(params
) * 2;
2126 switch (params_format(params
)) {
2127 case SNDRV_PCM_FORMAT_S16_LE
:
2130 case SNDRV_PCM_FORMAT_S20_3LE
:
2134 case SNDRV_PCM_FORMAT_S24_LE
:
2138 case SNDRV_PCM_FORMAT_S32_LE
:
2146 /* Try to find an appropriate sample rate; look for an exact match. */
2147 for (i
= 0; i
< ARRAY_SIZE(srs
); i
++)
2148 if (srs
[i
].rate
== params_rate(params
))
2150 if (i
== ARRAY_SIZE(srs
))
2152 rate_val
|= srs
[i
].val
<< WM8994_AIF1_SR_SHIFT
;
2154 dev_dbg(dai
->dev
, "Sample rate is %dHz\n", srs
[i
].rate
);
2155 dev_dbg(dai
->dev
, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2156 dai
->id
, wm8994
->aifclk
[id
], bclk_rate
);
2158 if (params_channels(params
) == 1 &&
2159 (snd_soc_read(codec
, aif1_reg
) & 0x18) == 0x18)
2160 aif2
|= WM8994_AIF1_MONO
;
2162 if (wm8994
->aifclk
[id
] == 0) {
2163 dev_err(dai
->dev
, "AIF%dCLK not configured\n", dai
->id
);
2167 /* AIFCLK/fs ratio; look for a close match in either direction */
2169 best_val
= abs((fs_ratios
[0] * params_rate(params
))
2170 - wm8994
->aifclk
[id
]);
2171 for (i
= 1; i
< ARRAY_SIZE(fs_ratios
); i
++) {
2172 cur_val
= abs((fs_ratios
[i
] * params_rate(params
))
2173 - wm8994
->aifclk
[id
]);
2174 if (cur_val
>= best_val
)
2179 dev_dbg(dai
->dev
, "Selected AIF%dCLK/fs = %d\n",
2180 dai
->id
, fs_ratios
[best
]);
2183 /* We may not get quite the right frequency if using
2184 * approximate clocks so look for the closest match that is
2185 * higher than the target (we need to ensure that there enough
2186 * BCLKs to clock out the samples).
2189 for (i
= 0; i
< ARRAY_SIZE(bclk_divs
); i
++) {
2190 cur_val
= (wm8994
->aifclk
[id
] * 10 / bclk_divs
[i
]) - bclk_rate
;
2191 if (cur_val
< 0) /* BCLK table is sorted */
2195 bclk_rate
= wm8994
->aifclk
[id
] * 10 / bclk_divs
[best
];
2196 dev_dbg(dai
->dev
, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2197 bclk_divs
[best
], bclk_rate
);
2198 bclk
|= best
<< WM8994_AIF1_BCLK_DIV_SHIFT
;
2200 lrclk
= bclk_rate
/ params_rate(params
);
2201 dev_dbg(dai
->dev
, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2202 lrclk
, bclk_rate
/ lrclk
);
2204 snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2205 snd_soc_update_bits(codec
, aif2_reg
, WM8994_AIF1_MONO
, aif2
);
2206 snd_soc_update_bits(codec
, bclk_reg
, WM8994_AIF1_BCLK_DIV_MASK
, bclk
);
2207 snd_soc_update_bits(codec
, lrclk_reg
, WM8994_AIF1DAC_RATE_MASK
,
2209 snd_soc_update_bits(codec
, rate_reg
, WM8994_AIF1_SR_MASK
|
2210 WM8994_AIF1CLK_RATE_MASK
, rate_val
);
2212 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
2215 wm8994
->dac_rates
[0] = params_rate(params
);
2216 wm8994_set_retune_mobile(codec
, 0);
2217 wm8994_set_retune_mobile(codec
, 1);
2220 wm8994
->dac_rates
[1] = params_rate(params
);
2221 wm8994_set_retune_mobile(codec
, 2);
2229 static int wm8994_aif3_hw_params(struct snd_pcm_substream
*substream
,
2230 struct snd_pcm_hw_params
*params
,
2231 struct snd_soc_dai
*dai
)
2233 struct snd_soc_codec
*codec
= dai
->codec
;
2234 struct wm8994
*control
= codec
->control_data
;
2240 switch (control
->type
) {
2242 aif1_reg
= WM8958_AIF3_CONTROL_1
;
2251 switch (params_format(params
)) {
2252 case SNDRV_PCM_FORMAT_S16_LE
:
2254 case SNDRV_PCM_FORMAT_S20_3LE
:
2257 case SNDRV_PCM_FORMAT_S24_LE
:
2260 case SNDRV_PCM_FORMAT_S32_LE
:
2267 return snd_soc_update_bits(codec
, aif1_reg
, WM8994_AIF1_WL_MASK
, aif1
);
2270 static int wm8994_aif_mute(struct snd_soc_dai
*codec_dai
, int mute
)
2272 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2276 switch (codec_dai
->id
) {
2278 mute_reg
= WM8994_AIF1_DAC1_FILTERS_1
;
2281 mute_reg
= WM8994_AIF2_DAC_FILTERS_1
;
2288 reg
= WM8994_AIF1DAC1_MUTE
;
2292 snd_soc_update_bits(codec
, mute_reg
, WM8994_AIF1DAC1_MUTE
, reg
);
2297 static int wm8994_set_tristate(struct snd_soc_dai
*codec_dai
, int tristate
)
2299 struct snd_soc_codec
*codec
= codec_dai
->codec
;
2302 switch (codec_dai
->id
) {
2304 reg
= WM8994_AIF1_MASTER_SLAVE
;
2305 mask
= WM8994_AIF1_TRI
;
2308 reg
= WM8994_AIF2_MASTER_SLAVE
;
2309 mask
= WM8994_AIF2_TRI
;
2312 reg
= WM8994_POWER_MANAGEMENT_6
;
2313 mask
= WM8994_AIF3_TRI
;
2324 return snd_soc_update_bits(codec
, reg
, mask
, val
);
2327 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2329 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2330 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2332 static struct snd_soc_dai_ops wm8994_aif1_dai_ops
= {
2333 .set_sysclk
= wm8994_set_dai_sysclk
,
2334 .set_fmt
= wm8994_set_dai_fmt
,
2335 .hw_params
= wm8994_hw_params
,
2336 .digital_mute
= wm8994_aif_mute
,
2337 .set_pll
= wm8994_set_fll
,
2338 .set_tristate
= wm8994_set_tristate
,
2341 static struct snd_soc_dai_ops wm8994_aif2_dai_ops
= {
2342 .set_sysclk
= wm8994_set_dai_sysclk
,
2343 .set_fmt
= wm8994_set_dai_fmt
,
2344 .hw_params
= wm8994_hw_params
,
2345 .digital_mute
= wm8994_aif_mute
,
2346 .set_pll
= wm8994_set_fll
,
2347 .set_tristate
= wm8994_set_tristate
,
2350 static struct snd_soc_dai_ops wm8994_aif3_dai_ops
= {
2351 .hw_params
= wm8994_aif3_hw_params
,
2352 .set_tristate
= wm8994_set_tristate
,
2355 static struct snd_soc_dai_driver wm8994_dai
[] = {
2357 .name
= "wm8994-aif1",
2360 .stream_name
= "AIF1 Playback",
2363 .rates
= WM8994_RATES
,
2364 .formats
= WM8994_FORMATS
,
2367 .stream_name
= "AIF1 Capture",
2370 .rates
= WM8994_RATES
,
2371 .formats
= WM8994_FORMATS
,
2373 .ops
= &wm8994_aif1_dai_ops
,
2376 .name
= "wm8994-aif2",
2379 .stream_name
= "AIF2 Playback",
2382 .rates
= WM8994_RATES
,
2383 .formats
= WM8994_FORMATS
,
2386 .stream_name
= "AIF2 Capture",
2389 .rates
= WM8994_RATES
,
2390 .formats
= WM8994_FORMATS
,
2392 .ops
= &wm8994_aif2_dai_ops
,
2395 .name
= "wm8994-aif3",
2398 .stream_name
= "AIF3 Playback",
2401 .rates
= WM8994_RATES
,
2402 .formats
= WM8994_FORMATS
,
2405 .stream_name
= "AIF3 Capture",
2408 .rates
= WM8994_RATES
,
2409 .formats
= WM8994_FORMATS
,
2411 .ops
= &wm8994_aif3_dai_ops
,
2416 static int wm8994_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
2418 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2421 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2422 memcpy(&wm8994
->fll_suspend
[i
], &wm8994
->fll
[i
],
2423 sizeof(struct wm8994_fll_config
));
2424 ret
= _wm8994_set_fll(codec
, i
+ 1, 0, 0, 0);
2426 dev_warn(codec
->dev
, "Failed to stop FLL%d: %d\n",
2430 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
2435 static int wm8994_resume(struct snd_soc_codec
*codec
)
2437 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2439 unsigned int val
, mask
;
2441 if (wm8994
->revision
< 4) {
2442 /* force a HW read */
2443 val
= wm8994_reg_read(codec
->control_data
,
2444 WM8994_POWER_MANAGEMENT_5
);
2446 /* modify the cache only */
2447 codec
->cache_only
= 1;
2448 mask
= WM8994_DAC1R_ENA
| WM8994_DAC1L_ENA
|
2449 WM8994_DAC2R_ENA
| WM8994_DAC2L_ENA
;
2451 snd_soc_update_bits(codec
, WM8994_POWER_MANAGEMENT_5
,
2453 codec
->cache_only
= 0;
2456 /* Restore the registers */
2457 ret
= snd_soc_cache_sync(codec
);
2459 dev_err(codec
->dev
, "Failed to sync cache: %d\n", ret
);
2461 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2463 for (i
= 0; i
< ARRAY_SIZE(wm8994
->fll
); i
++) {
2464 if (!wm8994
->fll_suspend
[i
].out
)
2467 ret
= _wm8994_set_fll(codec
, i
+ 1,
2468 wm8994
->fll_suspend
[i
].src
,
2469 wm8994
->fll_suspend
[i
].in
,
2470 wm8994
->fll_suspend
[i
].out
);
2472 dev_warn(codec
->dev
, "Failed to restore FLL%d: %d\n",
2479 #define wm8994_suspend NULL
2480 #define wm8994_resume NULL
2483 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv
*wm8994
)
2485 struct snd_soc_codec
*codec
= wm8994
->codec
;
2486 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2487 struct snd_kcontrol_new controls
[] = {
2488 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2489 wm8994
->retune_mobile_enum
,
2490 wm8994_get_retune_mobile_enum
,
2491 wm8994_put_retune_mobile_enum
),
2492 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2493 wm8994
->retune_mobile_enum
,
2494 wm8994_get_retune_mobile_enum
,
2495 wm8994_put_retune_mobile_enum
),
2496 SOC_ENUM_EXT("AIF2 EQ Mode",
2497 wm8994
->retune_mobile_enum
,
2498 wm8994_get_retune_mobile_enum
,
2499 wm8994_put_retune_mobile_enum
),
2504 /* We need an array of texts for the enum API but the number
2505 * of texts is likely to be less than the number of
2506 * configurations due to the sample rate dependency of the
2507 * configurations. */
2508 wm8994
->num_retune_mobile_texts
= 0;
2509 wm8994
->retune_mobile_texts
= NULL
;
2510 for (i
= 0; i
< pdata
->num_retune_mobile_cfgs
; i
++) {
2511 for (j
= 0; j
< wm8994
->num_retune_mobile_texts
; j
++) {
2512 if (strcmp(pdata
->retune_mobile_cfgs
[i
].name
,
2513 wm8994
->retune_mobile_texts
[j
]) == 0)
2517 if (j
!= wm8994
->num_retune_mobile_texts
)
2520 /* Expand the array... */
2521 t
= krealloc(wm8994
->retune_mobile_texts
,
2523 (wm8994
->num_retune_mobile_texts
+ 1),
2528 /* ...store the new entry... */
2529 t
[wm8994
->num_retune_mobile_texts
] =
2530 pdata
->retune_mobile_cfgs
[i
].name
;
2532 /* ...and remember the new version. */
2533 wm8994
->num_retune_mobile_texts
++;
2534 wm8994
->retune_mobile_texts
= t
;
2537 dev_dbg(codec
->dev
, "Allocated %d unique ReTune Mobile names\n",
2538 wm8994
->num_retune_mobile_texts
);
2540 wm8994
->retune_mobile_enum
.max
= wm8994
->num_retune_mobile_texts
;
2541 wm8994
->retune_mobile_enum
.texts
= wm8994
->retune_mobile_texts
;
2543 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2544 ARRAY_SIZE(controls
));
2546 dev_err(wm8994
->codec
->dev
,
2547 "Failed to add ReTune Mobile controls: %d\n", ret
);
2550 static void wm8994_handle_pdata(struct wm8994_priv
*wm8994
)
2552 struct snd_soc_codec
*codec
= wm8994
->codec
;
2553 struct wm8994_pdata
*pdata
= wm8994
->pdata
;
2559 wm_hubs_handle_analogue_pdata(codec
, pdata
->lineout1_diff
,
2560 pdata
->lineout2_diff
,
2565 pdata
->micbias1_lvl
,
2566 pdata
->micbias2_lvl
);
2568 dev_dbg(codec
->dev
, "%d DRC configurations\n", pdata
->num_drc_cfgs
);
2570 if (pdata
->num_drc_cfgs
) {
2571 struct snd_kcontrol_new controls
[] = {
2572 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994
->drc_enum
,
2573 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2574 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994
->drc_enum
,
2575 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2576 SOC_ENUM_EXT("AIF2DRC Mode", wm8994
->drc_enum
,
2577 wm8994_get_drc_enum
, wm8994_put_drc_enum
),
2580 /* We need an array of texts for the enum API */
2581 wm8994
->drc_texts
= kmalloc(sizeof(char *)
2582 * pdata
->num_drc_cfgs
, GFP_KERNEL
);
2583 if (!wm8994
->drc_texts
) {
2584 dev_err(wm8994
->codec
->dev
,
2585 "Failed to allocate %d DRC config texts\n",
2586 pdata
->num_drc_cfgs
);
2590 for (i
= 0; i
< pdata
->num_drc_cfgs
; i
++)
2591 wm8994
->drc_texts
[i
] = pdata
->drc_cfgs
[i
].name
;
2593 wm8994
->drc_enum
.max
= pdata
->num_drc_cfgs
;
2594 wm8994
->drc_enum
.texts
= wm8994
->drc_texts
;
2596 ret
= snd_soc_add_controls(wm8994
->codec
, controls
,
2597 ARRAY_SIZE(controls
));
2599 dev_err(wm8994
->codec
->dev
,
2600 "Failed to add DRC mode controls: %d\n", ret
);
2602 for (i
= 0; i
< WM8994_NUM_DRC
; i
++)
2603 wm8994_set_drc(codec
, i
);
2606 dev_dbg(codec
->dev
, "%d ReTune Mobile configurations\n",
2607 pdata
->num_retune_mobile_cfgs
);
2609 if (pdata
->num_retune_mobile_cfgs
)
2610 wm8994_handle_retune_mobile_pdata(wm8994
);
2612 snd_soc_add_controls(wm8994
->codec
, wm8994_eq_controls
,
2613 ARRAY_SIZE(wm8994_eq_controls
));
2615 for (i
= 0; i
< ARRAY_SIZE(pdata
->micbias
); i
++) {
2616 if (pdata
->micbias
[i
]) {
2617 snd_soc_write(codec
, WM8958_MICBIAS1
+ i
,
2618 pdata
->micbias
[i
] & 0xffff);
2624 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2626 * @codec: WM8994 codec
2627 * @jack: jack to report detection events on
2628 * @micbias: microphone bias to detect on
2629 * @det: value to report for presence detection
2630 * @shrt: value to report for short detection
2632 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2633 * being used to bring out signals to the processor then only platform
2634 * data configuration is needed for WM8994 and processor GPIOs should
2635 * be configured using snd_soc_jack_add_gpios() instead.
2637 * Configuration of detection levels is available via the micbias1_lvl
2638 * and micbias2_lvl platform data members.
2640 int wm8994_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2641 int micbias
, int det
, int shrt
)
2643 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2644 struct wm8994_micdet
*micdet
;
2645 struct wm8994
*control
= codec
->control_data
;
2648 if (control
->type
!= WM8994
)
2653 micdet
= &wm8994
->micdet
[0];
2656 micdet
= &wm8994
->micdet
[1];
2662 dev_dbg(codec
->dev
, "Configuring microphone detection on %d: %x %x\n",
2663 micbias
, det
, shrt
);
2665 /* Store the configuration */
2666 micdet
->jack
= jack
;
2668 micdet
->shrt
= shrt
;
2670 /* If either of the jacks is set up then enable detection */
2671 if (wm8994
->micdet
[0].jack
|| wm8994
->micdet
[1].jack
)
2672 reg
= WM8994_MICD_ENA
;
2676 snd_soc_update_bits(codec
, WM8994_MICBIAS
, WM8994_MICD_ENA
, reg
);
2680 EXPORT_SYMBOL_GPL(wm8994_mic_detect
);
2682 static irqreturn_t
wm8994_mic_irq(int irq
, void *data
)
2684 struct wm8994_priv
*priv
= data
;
2685 struct snd_soc_codec
*codec
= priv
->codec
;
2689 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2690 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
2693 reg
= snd_soc_read(codec
, WM8994_INTERRUPT_RAW_STATUS_2
);
2695 dev_err(codec
->dev
, "Failed to read microphone status: %d\n",
2700 dev_dbg(codec
->dev
, "Microphone status: %x\n", reg
);
2703 if (reg
& WM8994_MIC1_DET_STS
)
2704 report
|= priv
->micdet
[0].det
;
2705 if (reg
& WM8994_MIC1_SHRT_STS
)
2706 report
|= priv
->micdet
[0].shrt
;
2707 snd_soc_jack_report(priv
->micdet
[0].jack
, report
,
2708 priv
->micdet
[0].det
| priv
->micdet
[0].shrt
);
2711 if (reg
& WM8994_MIC2_DET_STS
)
2712 report
|= priv
->micdet
[1].det
;
2713 if (reg
& WM8994_MIC2_SHRT_STS
)
2714 report
|= priv
->micdet
[1].shrt
;
2715 snd_soc_jack_report(priv
->micdet
[1].jack
, report
,
2716 priv
->micdet
[1].det
| priv
->micdet
[1].shrt
);
2721 /* Default microphone detection handler for WM8958 - the user can
2722 * override this if they wish.
2724 static void wm8958_default_micdet(u16 status
, void *data
)
2726 struct snd_soc_codec
*codec
= data
;
2727 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2730 /* If nothing present then clear our statuses */
2731 if (!(status
& WM8958_MICD_STS
))
2734 report
= SND_JACK_MICROPHONE
;
2736 /* Everything else is buttons; just assign slots */
2738 report
|= SND_JACK_BTN_0
;
2741 snd_soc_jack_report(wm8994
->micdet
[0].jack
, report
,
2742 SND_JACK_BTN_0
| SND_JACK_MICROPHONE
);
2746 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2748 * @codec: WM8958 codec
2749 * @jack: jack to report detection events on
2751 * Enable microphone detection functionality for the WM8958. By
2752 * default simple detection which supports the detection of up to 6
2753 * buttons plus video and microphone functionality is supported.
2755 * The WM8958 has an advanced jack detection facility which is able to
2756 * support complex accessory detection, especially when used in
2757 * conjunction with external circuitry. In order to provide maximum
2758 * flexiblity a callback is provided which allows a completely custom
2759 * detection algorithm.
2761 int wm8958_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
2762 wm8958_micdet_cb cb
, void *cb_data
)
2764 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
2765 struct wm8994
*control
= codec
->control_data
;
2767 if (control
->type
!= WM8958
)
2772 dev_dbg(codec
->dev
, "Using default micdet callback\n");
2773 cb
= wm8958_default_micdet
;
2777 wm8994
->micdet
[0].jack
= jack
;
2778 wm8994
->jack_cb
= cb
;
2779 wm8994
->jack_cb_data
= cb_data
;
2781 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2782 WM8958_MICD_ENA
, WM8958_MICD_ENA
);
2784 snd_soc_update_bits(codec
, WM8958_MIC_DETECT_1
,
2785 WM8958_MICD_ENA
, 0);
2790 EXPORT_SYMBOL_GPL(wm8958_mic_detect
);
2792 static irqreturn_t
wm8958_mic_irq(int irq
, void *data
)
2794 struct wm8994_priv
*wm8994
= data
;
2795 struct snd_soc_codec
*codec
= wm8994
->codec
;
2798 reg
= snd_soc_read(codec
, WM8958_MIC_DETECT_3
);
2800 dev_err(codec
->dev
, "Failed to read mic detect status: %d\n",
2805 if (!(reg
& WM8958_MICD_VALID
)) {
2806 dev_dbg(codec
->dev
, "Mic detect data not valid\n");
2810 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2811 trace_snd_soc_jack_irq(dev_name(codec
->dev
));
2814 if (wm8994
->jack_cb
)
2815 wm8994
->jack_cb(reg
, wm8994
->jack_cb_data
);
2817 dev_warn(codec
->dev
, "Accessory detection with no callback\n");
2823 static int wm8994_codec_probe(struct snd_soc_codec
*codec
)
2825 struct wm8994
*control
;
2826 struct wm8994_priv
*wm8994
;
2827 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
2830 codec
->control_data
= dev_get_drvdata(codec
->dev
->parent
);
2831 control
= codec
->control_data
;
2833 wm8994
= kzalloc(sizeof(struct wm8994_priv
), GFP_KERNEL
);
2836 snd_soc_codec_set_drvdata(codec
, wm8994
);
2838 wm8994
->pdata
= dev_get_platdata(codec
->dev
->parent
);
2839 wm8994
->codec
= codec
;
2841 if (wm8994
->pdata
&& wm8994
->pdata
->micdet_irq
)
2842 wm8994
->micdet_irq
= wm8994
->pdata
->micdet_irq
;
2843 else if (wm8994
->pdata
&& wm8994
->pdata
->irq_base
)
2844 wm8994
->micdet_irq
= wm8994
->pdata
->irq_base
+
2845 WM8994_IRQ_MIC1_DET
;
2847 pm_runtime_enable(codec
->dev
);
2848 pm_runtime_resume(codec
->dev
);
2850 /* Read our current status back from the chip - we don't want to
2851 * reset as this may interfere with the GPIO or LDO operation. */
2852 for (i
= 0; i
< WM8994_CACHE_SIZE
; i
++) {
2853 if (!wm8994_readable(codec
, i
) || wm8994_volatile(codec
, i
))
2856 ret
= wm8994_reg_read(codec
->control_data
, i
);
2860 ret
= snd_soc_cache_write(codec
, i
, ret
);
2863 "Failed to initialise cache for 0x%x: %d\n",
2869 /* Set revision-specific configuration */
2870 wm8994
->revision
= snd_soc_read(codec
, WM8994_CHIP_REVISION
);
2871 switch (control
->type
) {
2873 switch (wm8994
->revision
) {
2876 wm8994
->hubs
.dcs_codes
= -5;
2877 wm8994
->hubs
.hp_startup_mode
= 1;
2878 wm8994
->hubs
.dcs_readback_mode
= 1;
2881 wm8994
->hubs
.dcs_readback_mode
= 1;
2886 wm8994
->hubs
.dcs_readback_mode
= 1;
2893 switch (control
->type
) {
2895 if (wm8994
->micdet_irq
) {
2896 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
2898 IRQF_TRIGGER_RISING
,
2902 dev_warn(codec
->dev
,
2903 "Failed to request Mic1 detect IRQ: %d\n",
2907 ret
= wm8994_request_irq(codec
->control_data
,
2908 WM8994_IRQ_MIC1_SHRT
,
2909 wm8994_mic_irq
, "Mic 1 short",
2912 dev_warn(codec
->dev
,
2913 "Failed to request Mic1 short IRQ: %d\n",
2916 ret
= wm8994_request_irq(codec
->control_data
,
2917 WM8994_IRQ_MIC2_DET
,
2918 wm8994_mic_irq
, "Mic 2 detect",
2921 dev_warn(codec
->dev
,
2922 "Failed to request Mic2 detect IRQ: %d\n",
2925 ret
= wm8994_request_irq(codec
->control_data
,
2926 WM8994_IRQ_MIC2_SHRT
,
2927 wm8994_mic_irq
, "Mic 2 short",
2930 dev_warn(codec
->dev
,
2931 "Failed to request Mic2 short IRQ: %d\n",
2936 if (wm8994
->micdet_irq
) {
2937 ret
= request_threaded_irq(wm8994
->micdet_irq
, NULL
,
2939 IRQF_TRIGGER_RISING
,
2943 dev_warn(codec
->dev
,
2944 "Failed to request Mic detect IRQ: %d\n",
2949 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2950 * configured on init - if a system wants to do this dynamically
2951 * at runtime we can deal with that then.
2953 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_1
);
2955 dev_err(codec
->dev
, "Failed to read GPIO1 state: %d\n", ret
);
2958 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
2959 wm8994
->lrclk_shared
[0] = 1;
2960 wm8994_dai
[0].symmetric_rates
= 1;
2962 wm8994
->lrclk_shared
[0] = 0;
2965 ret
= wm8994_reg_read(codec
->control_data
, WM8994_GPIO_6
);
2967 dev_err(codec
->dev
, "Failed to read GPIO6 state: %d\n", ret
);
2970 if ((ret
& WM8994_GPN_FN_MASK
) != WM8994_GP_FN_PIN_SPECIFIC
) {
2971 wm8994
->lrclk_shared
[1] = 1;
2972 wm8994_dai
[1].symmetric_rates
= 1;
2974 wm8994
->lrclk_shared
[1] = 0;
2977 wm8994_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
2979 /* Latch volume updates (right only; we always do left then right). */
2980 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_LEFT_VOLUME
,
2981 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
2982 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_RIGHT_VOLUME
,
2983 WM8994_AIF1DAC1_VU
, WM8994_AIF1DAC1_VU
);
2984 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_LEFT_VOLUME
,
2985 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
2986 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_RIGHT_VOLUME
,
2987 WM8994_AIF1DAC2_VU
, WM8994_AIF1DAC2_VU
);
2988 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_LEFT_VOLUME
,
2989 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
2990 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_RIGHT_VOLUME
,
2991 WM8994_AIF2DAC_VU
, WM8994_AIF2DAC_VU
);
2992 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_LEFT_VOLUME
,
2993 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
2994 snd_soc_update_bits(codec
, WM8994_AIF1_ADC1_RIGHT_VOLUME
,
2995 WM8994_AIF1ADC1_VU
, WM8994_AIF1ADC1_VU
);
2996 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_LEFT_VOLUME
,
2997 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
2998 snd_soc_update_bits(codec
, WM8994_AIF1_ADC2_RIGHT_VOLUME
,
2999 WM8994_AIF1ADC2_VU
, WM8994_AIF1ADC2_VU
);
3000 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_LEFT_VOLUME
,
3001 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3002 snd_soc_update_bits(codec
, WM8994_AIF2_ADC_RIGHT_VOLUME
,
3003 WM8994_AIF2ADC_VU
, WM8994_AIF1ADC2_VU
);
3004 snd_soc_update_bits(codec
, WM8994_DAC1_LEFT_VOLUME
,
3005 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3006 snd_soc_update_bits(codec
, WM8994_DAC1_RIGHT_VOLUME
,
3007 WM8994_DAC1_VU
, WM8994_DAC1_VU
);
3008 snd_soc_update_bits(codec
, WM8994_DAC2_LEFT_VOLUME
,
3009 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3010 snd_soc_update_bits(codec
, WM8994_DAC2_RIGHT_VOLUME
,
3011 WM8994_DAC2_VU
, WM8994_DAC2_VU
);
3013 /* Set the low bit of the 3D stereo depth so TLV matches */
3014 snd_soc_update_bits(codec
, WM8994_AIF1_DAC1_FILTERS_2
,
3015 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
,
3016 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT
);
3017 snd_soc_update_bits(codec
, WM8994_AIF1_DAC2_FILTERS_2
,
3018 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
,
3019 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT
);
3020 snd_soc_update_bits(codec
, WM8994_AIF2_DAC_FILTERS_2
,
3021 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
,
3022 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT
);
3024 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3025 * behaviour on idle TDM clock cycles. */
3026 snd_soc_update_bits(codec
, WM8994_AIF1_CONTROL_1
,
3027 WM8994_AIF1ADC_TDM
, WM8994_AIF1ADC_TDM
);
3029 wm8994_update_class_w(codec
);
3031 wm8994_handle_pdata(wm8994
);
3033 wm_hubs_add_analogue_controls(codec
);
3034 snd_soc_add_controls(codec
, wm8994_snd_controls
,
3035 ARRAY_SIZE(wm8994_snd_controls
));
3036 snd_soc_dapm_new_controls(dapm
, wm8994_dapm_widgets
,
3037 ARRAY_SIZE(wm8994_dapm_widgets
));
3039 switch (control
->type
) {
3041 snd_soc_dapm_new_controls(dapm
, wm8994_specific_dapm_widgets
,
3042 ARRAY_SIZE(wm8994_specific_dapm_widgets
));
3043 if (wm8994
->revision
< 4) {
3044 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3045 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3046 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3047 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3048 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3049 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3051 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3052 ARRAY_SIZE(wm8994_lateclk_widgets
));
3053 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3054 ARRAY_SIZE(wm8994_adc_widgets
));
3055 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3056 ARRAY_SIZE(wm8994_dac_widgets
));
3060 snd_soc_add_controls(codec
, wm8958_snd_controls
,
3061 ARRAY_SIZE(wm8958_snd_controls
));
3062 snd_soc_dapm_new_controls(dapm
, wm8958_dapm_widgets
,
3063 ARRAY_SIZE(wm8958_dapm_widgets
));
3064 if (wm8994
->revision
< 1) {
3065 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_revd_widgets
,
3066 ARRAY_SIZE(wm8994_lateclk_revd_widgets
));
3067 snd_soc_dapm_new_controls(dapm
, wm8994_adc_revd_widgets
,
3068 ARRAY_SIZE(wm8994_adc_revd_widgets
));
3069 snd_soc_dapm_new_controls(dapm
, wm8994_dac_revd_widgets
,
3070 ARRAY_SIZE(wm8994_dac_revd_widgets
));
3072 snd_soc_dapm_new_controls(dapm
, wm8994_lateclk_widgets
,
3073 ARRAY_SIZE(wm8994_lateclk_widgets
));
3074 snd_soc_dapm_new_controls(dapm
, wm8994_adc_widgets
,
3075 ARRAY_SIZE(wm8994_adc_widgets
));
3076 snd_soc_dapm_new_controls(dapm
, wm8994_dac_widgets
,
3077 ARRAY_SIZE(wm8994_dac_widgets
));
3083 wm_hubs_add_analogue_routes(codec
, 0, 0);
3084 snd_soc_dapm_add_routes(dapm
, intercon
, ARRAY_SIZE(intercon
));
3086 switch (control
->type
) {
3088 snd_soc_dapm_add_routes(dapm
, wm8994_intercon
,
3089 ARRAY_SIZE(wm8994_intercon
));
3091 if (wm8994
->revision
< 4) {
3092 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3093 ARRAY_SIZE(wm8994_revd_intercon
));
3094 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3095 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3097 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3098 ARRAY_SIZE(wm8994_lateclk_intercon
));
3102 if (wm8994
->revision
< 1) {
3103 snd_soc_dapm_add_routes(dapm
, wm8994_revd_intercon
,
3104 ARRAY_SIZE(wm8994_revd_intercon
));
3105 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_revd_intercon
,
3106 ARRAY_SIZE(wm8994_lateclk_revd_intercon
));
3108 snd_soc_dapm_add_routes(dapm
, wm8994_lateclk_intercon
,
3109 ARRAY_SIZE(wm8994_lateclk_intercon
));
3110 snd_soc_dapm_add_routes(dapm
, wm8958_intercon
,
3111 ARRAY_SIZE(wm8958_intercon
));
3114 wm8958_dsp2_init(codec
);
3121 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_SHRT
, wm8994
);
3122 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
, wm8994
);
3123 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
, wm8994
);
3124 if (wm8994
->micdet_irq
)
3125 free_irq(wm8994
->micdet_irq
, wm8994
);
3131 static int wm8994_codec_remove(struct snd_soc_codec
*codec
)
3133 struct wm8994_priv
*wm8994
= snd_soc_codec_get_drvdata(codec
);
3134 struct wm8994
*control
= codec
->control_data
;
3136 wm8994_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
3138 pm_runtime_disable(codec
->dev
);
3140 switch (control
->type
) {
3142 if (wm8994
->micdet_irq
)
3143 free_irq(wm8994
->micdet_irq
, wm8994
);
3144 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC2_DET
,
3146 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_SHRT
,
3148 wm8994_free_irq(codec
->control_data
, WM8994_IRQ_MIC1_DET
,
3153 if (wm8994
->micdet_irq
)
3154 free_irq(wm8994
->micdet_irq
, wm8994
);
3158 release_firmware(wm8994
->mbc
);
3159 if (wm8994
->mbc_vss
)
3160 release_firmware(wm8994
->mbc_vss
);
3162 release_firmware(wm8994
->enh_eq
);
3163 kfree(wm8994
->retune_mobile_texts
);
3164 kfree(wm8994
->drc_texts
);
3170 static struct snd_soc_codec_driver soc_codec_dev_wm8994
= {
3171 .probe
= wm8994_codec_probe
,
3172 .remove
= wm8994_codec_remove
,
3173 .suspend
= wm8994_suspend
,
3174 .resume
= wm8994_resume
,
3175 .read
= wm8994_read
,
3176 .write
= wm8994_write
,
3177 .readable_register
= wm8994_readable
,
3178 .volatile_register
= wm8994_volatile
,
3179 .set_bias_level
= wm8994_set_bias_level
,
3181 .reg_cache_size
= WM8994_CACHE_SIZE
,
3182 .reg_cache_default
= wm8994_reg_defaults
,
3184 .compress_type
= SND_SOC_RBTREE_COMPRESSION
,
3187 static int __devinit
wm8994_probe(struct platform_device
*pdev
)
3189 return snd_soc_register_codec(&pdev
->dev
, &soc_codec_dev_wm8994
,
3190 wm8994_dai
, ARRAY_SIZE(wm8994_dai
));
3193 static int __devexit
wm8994_remove(struct platform_device
*pdev
)
3195 snd_soc_unregister_codec(&pdev
->dev
);
3199 static struct platform_driver wm8994_codec_driver
= {
3201 .name
= "wm8994-codec",
3202 .owner
= THIS_MODULE
,
3204 .probe
= wm8994_probe
,
3205 .remove
= __devexit_p(wm8994_remove
),
3208 static __init
int wm8994_init(void)
3210 return platform_driver_register(&wm8994_codec_driver
);
3212 module_init(wm8994_init
);
3214 static __exit
void wm8994_exit(void)
3216 platform_driver_unregister(&wm8994_codec_driver
);
3218 module_exit(wm8994_exit
);
3221 MODULE_DESCRIPTION("ASoC WM8994 driver");
3222 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3223 MODULE_LICENSE("GPL");
3224 MODULE_ALIAS("platform:wm8994-codec");