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[POWERPC] pasemi: Implement MSI support
[linux-2.6/btrfs-unstable.git] / arch / powerpc / sysdev / mpic.c
blobf74fe26b787e1c81b423e8359e1bdc0e8d0e6e8d
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38
39 #include "mpic.h"
40
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
54 #else
55 #define distribute_irqs (0)
56 #endif
57 #endif
58
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
62 MPIC_GREG_BASE,
63 MPIC_GREG_FEATURE_0,
64 MPIC_GREG_GLOBAL_CONF_0,
65 MPIC_GREG_VENDOR_ID,
66 MPIC_GREG_IPI_VECTOR_PRI_0,
67 MPIC_GREG_IPI_STRIDE,
68 MPIC_GREG_SPURIOUS,
69 MPIC_GREG_TIMER_FREQ,
70
71 MPIC_TIMER_BASE,
72 MPIC_TIMER_STRIDE,
73 MPIC_TIMER_CURRENT_CNT,
74 MPIC_TIMER_BASE_CNT,
75 MPIC_TIMER_VECTOR_PRI,
76 MPIC_TIMER_DESTINATION,
77
78 MPIC_CPU_BASE,
79 MPIC_CPU_STRIDE,
80 MPIC_CPU_IPI_DISPATCH_0,
81 MPIC_CPU_IPI_DISPATCH_STRIDE,
82 MPIC_CPU_CURRENT_TASK_PRI,
83 MPIC_CPU_WHOAMI,
84 MPIC_CPU_INTACK,
85 MPIC_CPU_EOI,
86
87 MPIC_IRQ_BASE,
88 MPIC_IRQ_STRIDE,
89 MPIC_IRQ_VECTOR_PRI,
90 MPIC_VECPRI_VECTOR_MASK,
91 MPIC_VECPRI_POLARITY_POSITIVE,
92 MPIC_VECPRI_POLARITY_NEGATIVE,
93 MPIC_VECPRI_SENSE_LEVEL,
94 MPIC_VECPRI_SENSE_EDGE,
95 MPIC_VECPRI_POLARITY_MASK,
96 MPIC_VECPRI_SENSE_MASK,
97 MPIC_IRQ_DESTINATION
98 },
99 [1] = { /* Tsi108/109 PIC */
100 TSI108_GREG_BASE,
101 TSI108_GREG_FEATURE_0,
102 TSI108_GREG_GLOBAL_CONF_0,
103 TSI108_GREG_VENDOR_ID,
104 TSI108_GREG_IPI_VECTOR_PRI_0,
105 TSI108_GREG_IPI_STRIDE,
106 TSI108_GREG_SPURIOUS,
107 TSI108_GREG_TIMER_FREQ,
108
109 TSI108_TIMER_BASE,
110 TSI108_TIMER_STRIDE,
111 TSI108_TIMER_CURRENT_CNT,
112 TSI108_TIMER_BASE_CNT,
113 TSI108_TIMER_VECTOR_PRI,
114 TSI108_TIMER_DESTINATION,
115
116 TSI108_CPU_BASE,
117 TSI108_CPU_STRIDE,
118 TSI108_CPU_IPI_DISPATCH_0,
119 TSI108_CPU_IPI_DISPATCH_STRIDE,
120 TSI108_CPU_CURRENT_TASK_PRI,
121 TSI108_CPU_WHOAMI,
122 TSI108_CPU_INTACK,
123 TSI108_CPU_EOI,
124
125 TSI108_IRQ_BASE,
126 TSI108_IRQ_STRIDE,
127 TSI108_IRQ_VECTOR_PRI,
128 TSI108_VECPRI_VECTOR_MASK,
129 TSI108_VECPRI_POLARITY_POSITIVE,
130 TSI108_VECPRI_POLARITY_NEGATIVE,
131 TSI108_VECPRI_SENSE_LEVEL,
132 TSI108_VECPRI_SENSE_EDGE,
133 TSI108_VECPRI_POLARITY_MASK,
134 TSI108_VECPRI_SENSE_MASK,
135 TSI108_IRQ_DESTINATION
136 },
137 };
138
139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
140
141 #else /* CONFIG_MPIC_WEIRD */
142
143 #define MPIC_INFO(name) MPIC_##name
144
145 #endif /* CONFIG_MPIC_WEIRD */
146
147 /*
148 * Register accessor functions
149 */
150
151
152 static inline u32 _mpic_read(enum mpic_reg_type type,
153 struct mpic_reg_bank *rb,
154 unsigned int reg)
155 {
156 switch(type) {
157 #ifdef CONFIG_PPC_DCR
158 case mpic_access_dcr:
159 return dcr_read(rb->dhost, reg);
160 #endif
161 case mpic_access_mmio_be:
162 return in_be32(rb->base + (reg >> 2));
163 case mpic_access_mmio_le:
164 default:
165 return in_le32(rb->base + (reg >> 2));
166 }
167 }
168
169 static inline void _mpic_write(enum mpic_reg_type type,
170 struct mpic_reg_bank *rb,
171 unsigned int reg, u32 value)
172 {
173 switch(type) {
174 #ifdef CONFIG_PPC_DCR
175 case mpic_access_dcr:
176 return dcr_write(rb->dhost, reg, value);
177 #endif
178 case mpic_access_mmio_be:
179 return out_be32(rb->base + (reg >> 2), value);
180 case mpic_access_mmio_le:
181 default:
182 return out_le32(rb->base + (reg >> 2), value);
183 }
184 }
185
186 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
187 {
188 enum mpic_reg_type type = mpic->reg_type;
189 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
190 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
191
192 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
193 type = mpic_access_mmio_be;
194 return _mpic_read(type, &mpic->gregs, offset);
195 }
196
197 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
198 {
199 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
200 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
201
202 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
203 }
204
205 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
206 {
207 unsigned int cpu = 0;
208
209 if (mpic->flags & MPIC_PRIMARY)
210 cpu = hard_smp_processor_id();
211 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
212 }
213
214 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
215 {
216 unsigned int cpu = 0;
217
218 if (mpic->flags & MPIC_PRIMARY)
219 cpu = hard_smp_processor_id();
220
221 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
222 }
223
224 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
225 {
226 unsigned int isu = src_no >> mpic->isu_shift;
227 unsigned int idx = src_no & mpic->isu_mask;
228
229 #ifdef CONFIG_MPIC_BROKEN_REGREAD
230 if (reg == 0)
231 return mpic->isu_reg0_shadow[idx];
232 else
233 #endif
234 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
235 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
236 }
237
238 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
239 unsigned int reg, u32 value)
240 {
241 unsigned int isu = src_no >> mpic->isu_shift;
242 unsigned int idx = src_no & mpic->isu_mask;
243
244 _mpic_write(mpic->reg_type, &mpic->isus[isu],
245 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
246
247 #ifdef CONFIG_MPIC_BROKEN_REGREAD
248 if (reg == 0)
249 mpic->isu_reg0_shadow[idx] = value;
250 #endif
251 }
252
253 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
254 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
255 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
256 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
257 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
258 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
259 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
260 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
261
262
263 /*
264 * Low level utility functions
265 */
266
267
268 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
269 struct mpic_reg_bank *rb, unsigned int offset,
270 unsigned int size)
271 {
272 rb->base = ioremap(phys_addr + offset, size);
273 BUG_ON(rb->base == NULL);
274 }
275
276 #ifdef CONFIG_PPC_DCR
277 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
278 unsigned int offset, unsigned int size)
279 {
280 const u32 *dbasep;
281
282 dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
283
284 rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
285 BUG_ON(!DCR_MAP_OK(rb->dhost));
286 }
287
288 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
289 struct mpic_reg_bank *rb, unsigned int offset,
290 unsigned int size)
291 {
292 if (mpic->flags & MPIC_USES_DCR)
293 _mpic_map_dcr(mpic, rb, offset, size);
294 else
295 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
296 }
297 #else /* CONFIG_PPC_DCR */
298 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
299 #endif /* !CONFIG_PPC_DCR */
300
301
302
303 /* Check if we have one of those nice broken MPICs with a flipped endian on
304 * reads from IPI registers
305 */
306 static void __init mpic_test_broken_ipi(struct mpic *mpic)
307 {
308 u32 r;
309
310 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
311 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
312
313 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
314 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
315 mpic->flags |= MPIC_BROKEN_IPI;
316 }
317 }
318
319 #ifdef CONFIG_MPIC_U3_HT_IRQS
320
321 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
322 * to force the edge setting on the MPIC and do the ack workaround.
323 */
324 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
325 {
326 if (source >= 128 || !mpic->fixups)
327 return 0;
328 return mpic->fixups[source].base != NULL;
329 }
330
331
332 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
333 {
334 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
335
336 if (fixup->applebase) {
337 unsigned int soff = (fixup->index >> 3) & ~3;
338 unsigned int mask = 1U << (fixup->index & 0x1f);
339 writel(mask, fixup->applebase + soff);
340 } else {
341 spin_lock(&mpic->fixup_lock);
342 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
343 writel(fixup->data, fixup->base + 4);
344 spin_unlock(&mpic->fixup_lock);
345 }
346 }
347
348 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
349 unsigned int irqflags)
350 {
351 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
352 unsigned long flags;
353 u32 tmp;
354
355 if (fixup->base == NULL)
356 return;
357
358 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
359 source, irqflags, fixup->index);
360 spin_lock_irqsave(&mpic->fixup_lock, flags);
361 /* Enable and configure */
362 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
363 tmp = readl(fixup->base + 4);
364 tmp &= ~(0x23U);
365 if (irqflags & IRQ_LEVEL)
366 tmp |= 0x22;
367 writel(tmp, fixup->base + 4);
368 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
369
370 #ifdef CONFIG_PM
371 /* use the lowest bit inverted to the actual HW,
372 * set if this fixup was enabled, clear otherwise */
373 mpic->save_data[source].fixup_data = tmp | 1;
374 #endif
375 }
376
377 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
378 unsigned int irqflags)
379 {
380 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
381 unsigned long flags;
382 u32 tmp;
383
384 if (fixup->base == NULL)
385 return;
386
387 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
388
389 /* Disable */
390 spin_lock_irqsave(&mpic->fixup_lock, flags);
391 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
392 tmp = readl(fixup->base + 4);
393 tmp |= 1;
394 writel(tmp, fixup->base + 4);
395 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
396
397 #ifdef CONFIG_PM
398 /* use the lowest bit inverted to the actual HW,
399 * set if this fixup was enabled, clear otherwise */
400 mpic->save_data[source].fixup_data = tmp & ~1;
401 #endif
402 }
403
404 #ifdef CONFIG_PCI_MSI
405 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
406 unsigned int devfn)
407 {
408 u8 __iomem *base;
409 u8 pos, flags;
410 u64 addr = 0;
411
412 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
413 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
414 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
415 if (id == PCI_CAP_ID_HT) {
416 id = readb(devbase + pos + 3);
417 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
418 break;
419 }
420 }
421
422 if (pos == 0)
423 return;
424
425 base = devbase + pos;
426
427 flags = readb(base + HT_MSI_FLAGS);
428 if (!(flags & HT_MSI_FLAGS_FIXED)) {
429 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
430 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
431 }
432
433 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
434 PCI_SLOT(devfn), PCI_FUNC(devfn),
435 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
436
437 if (!(flags & HT_MSI_FLAGS_ENABLE))
438 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
439 }
440 #else
441 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
442 unsigned int devfn)
443 {
444 return;
445 }
446 #endif
447
448 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
449 unsigned int devfn, u32 vdid)
450 {
451 int i, irq, n;
452 u8 __iomem *base;
453 u32 tmp;
454 u8 pos;
455
456 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
457 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
458 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
459 if (id == PCI_CAP_ID_HT) {
460 id = readb(devbase + pos + 3);
461 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
462 break;
463 }
464 }
465 if (pos == 0)
466 return;
467
468 base = devbase + pos;
469 writeb(0x01, base + 2);
470 n = (readl(base + 4) >> 16) & 0xff;
471
472 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
473 " has %d irqs\n",
474 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
475
476 for (i = 0; i <= n; i++) {
477 writeb(0x10 + 2 * i, base + 2);
478 tmp = readl(base + 4);
479 irq = (tmp >> 16) & 0xff;
480 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
481 /* mask it , will be unmasked later */
482 tmp |= 0x1;
483 writel(tmp, base + 4);
484 mpic->fixups[irq].index = i;
485 mpic->fixups[irq].base = base;
486 /* Apple HT PIC has a non-standard way of doing EOIs */
487 if ((vdid & 0xffff) == 0x106b)
488 mpic->fixups[irq].applebase = devbase + 0x60;
489 else
490 mpic->fixups[irq].applebase = NULL;
491 writeb(0x11 + 2 * i, base + 2);
492 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
493 }
494 }
495
496
497 static void __init mpic_scan_ht_pics(struct mpic *mpic)
498 {
499 unsigned int devfn;
500 u8 __iomem *cfgspace;
501
502 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
503
504 /* Allocate fixups array */
505 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
506 BUG_ON(mpic->fixups == NULL);
507 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
508
509 /* Init spinlock */
510 spin_lock_init(&mpic->fixup_lock);
511
512 /* Map U3 config space. We assume all IO-APICs are on the primary bus
513 * so we only need to map 64kB.
514 */
515 cfgspace = ioremap(0xf2000000, 0x10000);
516 BUG_ON(cfgspace == NULL);
517
518 /* Now we scan all slots. We do a very quick scan, we read the header
519 * type, vendor ID and device ID only, that's plenty enough
520 */
521 for (devfn = 0; devfn < 0x100; devfn++) {
522 u8 __iomem *devbase = cfgspace + (devfn << 8);
523 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
524 u32 l = readl(devbase + PCI_VENDOR_ID);
525 u16 s;
526
527 DBG("devfn %x, l: %x\n", devfn, l);
528
529 /* If no device, skip */
530 if (l == 0xffffffff || l == 0x00000000 ||
531 l == 0x0000ffff || l == 0xffff0000)
532 goto next;
533 /* Check if is supports capability lists */
534 s = readw(devbase + PCI_STATUS);
535 if (!(s & PCI_STATUS_CAP_LIST))
536 goto next;
537
538 mpic_scan_ht_pic(mpic, devbase, devfn, l);
539 mpic_scan_ht_msi(mpic, devbase, devfn);
540
541 next:
542 /* next device, if function 0 */
543 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
544 devfn += 7;
545 }
546 }
547
548 #else /* CONFIG_MPIC_U3_HT_IRQS */
549
550 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
551 {
552 return 0;
553 }
554
555 static void __init mpic_scan_ht_pics(struct mpic *mpic)
556 {
557 }
558
559 #endif /* CONFIG_MPIC_U3_HT_IRQS */
560
561
562 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
563
564 /* Find an mpic associated with a given linux interrupt */
565 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
566 {
567 unsigned int src = mpic_irq_to_hw(irq);
568 struct mpic *mpic;
569
570 if (irq < NUM_ISA_INTERRUPTS)
571 return NULL;
572
573 mpic = irq_desc[irq].chip_data;
574
575 if (is_ipi)
576 *is_ipi = (src >= mpic->ipi_vecs[0] &&
577 src <= mpic->ipi_vecs[3]);
578
579 return mpic;
580 }
581
582 /* Convert a cpu mask from logical to physical cpu numbers. */
583 static inline u32 mpic_physmask(u32 cpumask)
584 {
585 int i;
586 u32 mask = 0;
587
588 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
589 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
590 return mask;
591 }
592
593 #ifdef CONFIG_SMP
594 /* Get the mpic structure from the IPI number */
595 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
596 {
597 return irq_desc[ipi].chip_data;
598 }
599 #endif
600
601 /* Get the mpic structure from the irq number */
602 static inline struct mpic * mpic_from_irq(unsigned int irq)
603 {
604 return irq_desc[irq].chip_data;
605 }
606
607 /* Send an EOI */
608 static inline void mpic_eoi(struct mpic *mpic)
609 {
610 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
611 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
612 }
613
614 #ifdef CONFIG_SMP
615 static irqreturn_t mpic_ipi_action(int irq, void *data)
616 {
617 long ipi = (long)data;
618
619 smp_message_recv(ipi);
620
621 return IRQ_HANDLED;
622 }
623 #endif /* CONFIG_SMP */
624
625 /*
626 * Linux descriptor level callbacks
627 */
628
629
630 void mpic_unmask_irq(unsigned int irq)
631 {
632 unsigned int loops = 100000;
633 struct mpic *mpic = mpic_from_irq(irq);
634 unsigned int src = mpic_irq_to_hw(irq);
635
636 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
637
638 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
639 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
640 ~MPIC_VECPRI_MASK);
641 /* make sure mask gets to controller before we return to user */
642 do {
643 if (!loops--) {
644 printk(KERN_ERR "mpic_enable_irq timeout\n");
645 break;
646 }
647 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
648 }
649
650 void mpic_mask_irq(unsigned int irq)
651 {
652 unsigned int loops = 100000;
653 struct mpic *mpic = mpic_from_irq(irq);
654 unsigned int src = mpic_irq_to_hw(irq);
655
656 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
657
658 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
659 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
660 MPIC_VECPRI_MASK);
661
662 /* make sure mask gets to controller before we return to user */
663 do {
664 if (!loops--) {
665 printk(KERN_ERR "mpic_enable_irq timeout\n");
666 break;
667 }
668 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
669 }
670
671 void mpic_end_irq(unsigned int irq)
672 {
673 struct mpic *mpic = mpic_from_irq(irq);
674
675 #ifdef DEBUG_IRQ
676 DBG("%s: end_irq: %d\n", mpic->name, irq);
677 #endif
678 /* We always EOI on end_irq() even for edge interrupts since that
679 * should only lower the priority, the MPIC should have properly
680 * latched another edge interrupt coming in anyway
681 */
682
683 mpic_eoi(mpic);
684 }
685
686 #ifdef CONFIG_MPIC_U3_HT_IRQS
687
688 static void mpic_unmask_ht_irq(unsigned int irq)
689 {
690 struct mpic *mpic = mpic_from_irq(irq);
691 unsigned int src = mpic_irq_to_hw(irq);
692
693 mpic_unmask_irq(irq);
694
695 if (irq_desc[irq].status & IRQ_LEVEL)
696 mpic_ht_end_irq(mpic, src);
697 }
698
699 static unsigned int mpic_startup_ht_irq(unsigned int irq)
700 {
701 struct mpic *mpic = mpic_from_irq(irq);
702 unsigned int src = mpic_irq_to_hw(irq);
703
704 mpic_unmask_irq(irq);
705 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
706
707 return 0;
708 }
709
710 static void mpic_shutdown_ht_irq(unsigned int irq)
711 {
712 struct mpic *mpic = mpic_from_irq(irq);
713 unsigned int src = mpic_irq_to_hw(irq);
714
715 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
716 mpic_mask_irq(irq);
717 }
718
719 static void mpic_end_ht_irq(unsigned int irq)
720 {
721 struct mpic *mpic = mpic_from_irq(irq);
722 unsigned int src = mpic_irq_to_hw(irq);
723
724 #ifdef DEBUG_IRQ
725 DBG("%s: end_irq: %d\n", mpic->name, irq);
726 #endif
727 /* We always EOI on end_irq() even for edge interrupts since that
728 * should only lower the priority, the MPIC should have properly
729 * latched another edge interrupt coming in anyway
730 */
731
732 if (irq_desc[irq].status & IRQ_LEVEL)
733 mpic_ht_end_irq(mpic, src);
734 mpic_eoi(mpic);
735 }
736 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
737
738 #ifdef CONFIG_SMP
739
740 static void mpic_unmask_ipi(unsigned int irq)
741 {
742 struct mpic *mpic = mpic_from_ipi(irq);
743 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
744
745 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
746 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
747 }
748
749 static void mpic_mask_ipi(unsigned int irq)
750 {
751 /* NEVER disable an IPI... that's just plain wrong! */
752 }
753
754 static void mpic_end_ipi(unsigned int irq)
755 {
756 struct mpic *mpic = mpic_from_ipi(irq);
757
758 /*
759 * IPIs are marked IRQ_PER_CPU. This has the side effect of
760 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
761 * applying to them. We EOI them late to avoid re-entering.
762 * We mark IPI's with IRQF_DISABLED as they must run with
763 * irqs disabled.
764 */
765 mpic_eoi(mpic);
766 }
767
768 #endif /* CONFIG_SMP */
769
770 void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
771 {
772 struct mpic *mpic = mpic_from_irq(irq);
773 unsigned int src = mpic_irq_to_hw(irq);
774
775 cpumask_t tmp;
776
777 cpus_and(tmp, cpumask, cpu_online_map);
778
779 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
780 mpic_physmask(cpus_addr(tmp)[0]));
781 }
782
783 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
784 {
785 /* Now convert sense value */
786 switch(type & IRQ_TYPE_SENSE_MASK) {
787 case IRQ_TYPE_EDGE_RISING:
788 return MPIC_INFO(VECPRI_SENSE_EDGE) |
789 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
790 case IRQ_TYPE_EDGE_FALLING:
791 case IRQ_TYPE_EDGE_BOTH:
792 return MPIC_INFO(VECPRI_SENSE_EDGE) |
793 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
794 case IRQ_TYPE_LEVEL_HIGH:
795 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
796 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
797 case IRQ_TYPE_LEVEL_LOW:
798 default:
799 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
800 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
801 }
802 }
803
804 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
805 {
806 struct mpic *mpic = mpic_from_irq(virq);
807 unsigned int src = mpic_irq_to_hw(virq);
808 struct irq_desc *desc = get_irq_desc(virq);
809 unsigned int vecpri, vold, vnew;
810
811 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
812 mpic, virq, src, flow_type);
813
814 if (src >= mpic->irq_count)
815 return -EINVAL;
816
817 if (flow_type == IRQ_TYPE_NONE)
818 if (mpic->senses && src < mpic->senses_count)
819 flow_type = mpic->senses[src];
820 if (flow_type == IRQ_TYPE_NONE)
821 flow_type = IRQ_TYPE_LEVEL_LOW;
822
823 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
824 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
825 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
826 desc->status |= IRQ_LEVEL;
827
828 if (mpic_is_ht_interrupt(mpic, src))
829 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
830 MPIC_VECPRI_SENSE_EDGE;
831 else
832 vecpri = mpic_type_to_vecpri(mpic, flow_type);
833
834 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
835 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
836 MPIC_INFO(VECPRI_SENSE_MASK));
837 vnew |= vecpri;
838 if (vold != vnew)
839 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
840
841 return 0;
842 }
843
844 void mpic_set_vector(unsigned int virq, unsigned int vector)
845 {
846 struct mpic *mpic = mpic_from_irq(virq);
847 unsigned int src = mpic_irq_to_hw(virq);
848 unsigned int vecpri;
849
850 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
851 mpic, virq, src, vector);
852
853 if (src >= mpic->irq_count)
854 return;
855
856 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
857 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
858 vecpri |= vector;
859 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
860 }
861
862 static struct irq_chip mpic_irq_chip = {
863 .mask = mpic_mask_irq,
864 .unmask = mpic_unmask_irq,
865 .eoi = mpic_end_irq,
866 .set_type = mpic_set_irq_type,
867 };
868
869 #ifdef CONFIG_SMP
870 static struct irq_chip mpic_ipi_chip = {
871 .mask = mpic_mask_ipi,
872 .unmask = mpic_unmask_ipi,
873 .eoi = mpic_end_ipi,
874 };
875 #endif /* CONFIG_SMP */
876
877 #ifdef CONFIG_MPIC_U3_HT_IRQS
878 static struct irq_chip mpic_irq_ht_chip = {
879 .startup = mpic_startup_ht_irq,
880 .shutdown = mpic_shutdown_ht_irq,
881 .mask = mpic_mask_irq,
882 .unmask = mpic_unmask_ht_irq,
883 .eoi = mpic_end_ht_irq,
884 .set_type = mpic_set_irq_type,
885 };
886 #endif /* CONFIG_MPIC_U3_HT_IRQS */
887
888
889 static int mpic_host_match(struct irq_host *h, struct device_node *node)
890 {
891 /* Exact match, unless mpic node is NULL */
892 return h->of_node == NULL || h->of_node == node;
893 }
894
895 static int mpic_host_map(struct irq_host *h, unsigned int virq,
896 irq_hw_number_t hw)
897 {
898 struct mpic *mpic = h->host_data;
899 struct irq_chip *chip;
900
901 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
902
903 if (hw == mpic->spurious_vec)
904 return -EINVAL;
905 if (mpic->protected && test_bit(hw, mpic->protected))
906 return -EINVAL;
907
908 #ifdef CONFIG_SMP
909 else if (hw >= mpic->ipi_vecs[0]) {
910 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
911
912 DBG("mpic: mapping as IPI\n");
913 set_irq_chip_data(virq, mpic);
914 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
915 handle_percpu_irq);
916 return 0;
917 }
918 #endif /* CONFIG_SMP */
919
920 if (hw >= mpic->irq_count)
921 return -EINVAL;
922
923 mpic_msi_reserve_hwirq(mpic, hw);
924
925 /* Default chip */
926 chip = &mpic->hc_irq;
927
928 #ifdef CONFIG_MPIC_U3_HT_IRQS
929 /* Check for HT interrupts, override vecpri */
930 if (mpic_is_ht_interrupt(mpic, hw))
931 chip = &mpic->hc_ht_irq;
932 #endif /* CONFIG_MPIC_U3_HT_IRQS */
933
934 DBG("mpic: mapping to irq chip @%p\n", chip);
935
936 set_irq_chip_data(virq, mpic);
937 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
938
939 /* Set default irq type */
940 set_irq_type(virq, IRQ_TYPE_NONE);
941
942 return 0;
943 }
944
945 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
946 u32 *intspec, unsigned int intsize,
947 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
948
949 {
950 static unsigned char map_mpic_senses[4] = {
951 IRQ_TYPE_EDGE_RISING,
952 IRQ_TYPE_LEVEL_LOW,
953 IRQ_TYPE_LEVEL_HIGH,
954 IRQ_TYPE_EDGE_FALLING,
955 };
956
957 *out_hwirq = intspec[0];
958 if (intsize > 1) {
959 u32 mask = 0x3;
960
961 /* Apple invented a new race of encoding on machines with
962 * an HT APIC. They encode, among others, the index within
963 * the HT APIC. We don't care about it here since thankfully,
964 * it appears that they have the APIC already properly
965 * configured, and thus our current fixup code that reads the
966 * APIC config works fine. However, we still need to mask out
967 * bits in the specifier to make sure we only get bit 0 which
968 * is the level/edge bit (the only sense bit exposed by Apple),
969 * as their bit 1 means something else.
970 */
971 if (machine_is(powermac))
972 mask = 0x1;
973 *out_flags = map_mpic_senses[intspec[1] & mask];
974 } else
975 *out_flags = IRQ_TYPE_NONE;
976
977 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
978 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
979
980 return 0;
981 }
982
983 static struct irq_host_ops mpic_host_ops = {
984 .match = mpic_host_match,
985 .map = mpic_host_map,
986 .xlate = mpic_host_xlate,
987 };
988
989 /*
990 * Exported functions
991 */
992
993 struct mpic * __init mpic_alloc(struct device_node *node,
994 phys_addr_t phys_addr,
995 unsigned int flags,
996 unsigned int isu_size,
997 unsigned int irq_count,
998 const char *name)
999 {
1000 struct mpic *mpic;
1001 u32 reg;
1002 const char *vers;
1003 int i;
1004 int intvec_top;
1005 u64 paddr = phys_addr;
1006
1007 mpic = alloc_bootmem(sizeof(struct mpic));
1008 if (mpic == NULL)
1009 return NULL;
1010
1011 memset(mpic, 0, sizeof(struct mpic));
1012 mpic->name = name;
1013
1014 mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
1015 isu_size, &mpic_host_ops,
1016 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1017 if (mpic->irqhost == NULL) {
1018 of_node_put(node);
1019 return NULL;
1020 }
1021
1022 mpic->irqhost->host_data = mpic;
1023 mpic->hc_irq = mpic_irq_chip;
1024 mpic->hc_irq.typename = name;
1025 if (flags & MPIC_PRIMARY)
1026 mpic->hc_irq.set_affinity = mpic_set_affinity;
1027 #ifdef CONFIG_MPIC_U3_HT_IRQS
1028 mpic->hc_ht_irq = mpic_irq_ht_chip;
1029 mpic->hc_ht_irq.typename = name;
1030 if (flags & MPIC_PRIMARY)
1031 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1032 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1033
1034 #ifdef CONFIG_SMP
1035 mpic->hc_ipi = mpic_ipi_chip;
1036 mpic->hc_ipi.typename = name;
1037 #endif /* CONFIG_SMP */
1038
1039 mpic->flags = flags;
1040 mpic->isu_size = isu_size;
1041 mpic->irq_count = irq_count;
1042 mpic->num_sources = 0; /* so far */
1043
1044 if (flags & MPIC_LARGE_VECTORS)
1045 intvec_top = 2047;
1046 else
1047 intvec_top = 255;
1048
1049 mpic->timer_vecs[0] = intvec_top - 8;
1050 mpic->timer_vecs[1] = intvec_top - 7;
1051 mpic->timer_vecs[2] = intvec_top - 6;
1052 mpic->timer_vecs[3] = intvec_top - 5;
1053 mpic->ipi_vecs[0] = intvec_top - 4;
1054 mpic->ipi_vecs[1] = intvec_top - 3;
1055 mpic->ipi_vecs[2] = intvec_top - 2;
1056 mpic->ipi_vecs[3] = intvec_top - 1;
1057 mpic->spurious_vec = intvec_top;
1058
1059 /* Check for "big-endian" in device-tree */
1060 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1061 mpic->flags |= MPIC_BIG_ENDIAN;
1062
1063 /* Look for protected sources */
1064 if (node) {
1065 unsigned int psize, bits, mapsize;
1066 const u32 *psrc =
1067 of_get_property(node, "protected-sources", &psize);
1068 if (psrc) {
1069 psize /= 4;
1070 bits = intvec_top + 1;
1071 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1072 mpic->protected = alloc_bootmem(mapsize);
1073 BUG_ON(mpic->protected == NULL);
1074 memset(mpic->protected, 0, mapsize);
1075 for (i = 0; i < psize; i++) {
1076 if (psrc[i] > intvec_top)
1077 continue;
1078 __set_bit(psrc[i], mpic->protected);
1079 }
1080 }
1081 }
1082
1083 #ifdef CONFIG_MPIC_WEIRD
1084 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1085 #endif
1086
1087 /* default register type */
1088 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1089 mpic_access_mmio_be : mpic_access_mmio_le;
1090
1091 /* If no physical address is passed in, a device-node is mandatory */
1092 BUG_ON(paddr == 0 && node == NULL);
1093
1094 /* If no physical address passed in, check if it's dcr based */
1095 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1096 #ifdef CONFIG_PPC_DCR
1097 mpic->flags |= MPIC_USES_DCR;
1098 mpic->reg_type = mpic_access_dcr;
1099 #else
1100 BUG();
1101 #endif /* CONFIG_PPC_DCR */
1102 }
1103
1104 /* If the MPIC is not DCR based, and no physical address was passed
1105 * in, try to obtain one
1106 */
1107 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1108 const u32 *reg;
1109 reg = of_get_property(node, "reg", NULL);
1110 BUG_ON(reg == NULL);
1111 paddr = of_translate_address(node, reg);
1112 BUG_ON(paddr == OF_BAD_ADDR);
1113 }
1114
1115 /* Map the global registers */
1116 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1117 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1118
1119 /* Reset */
1120 if (flags & MPIC_WANTS_RESET) {
1121 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1122 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1123 | MPIC_GREG_GCONF_RESET);
1124 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1125 & MPIC_GREG_GCONF_RESET)
1126 mb();
1127 }
1128
1129 /* Read feature register, calculate num CPUs and, for non-ISU
1130 * MPICs, num sources as well. On ISU MPICs, sources are counted
1131 * as ISUs are added
1132 */
1133 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1134 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1135 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1136 if (isu_size == 0)
1137 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1138 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1139
1140 /* Map the per-CPU registers */
1141 for (i = 0; i < mpic->num_cpus; i++) {
1142 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1143 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1144 0x1000);
1145 }
1146
1147 /* Initialize main ISU if none provided */
1148 if (mpic->isu_size == 0) {
1149 mpic->isu_size = mpic->num_sources;
1150 mpic_map(mpic, paddr, &mpic->isus[0],
1151 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1152 }
1153 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1154 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1155
1156 /* Display version */
1157 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1158 case 1:
1159 vers = "1.0";
1160 break;
1161 case 2:
1162 vers = "1.2";
1163 break;
1164 case 3:
1165 vers = "1.3";
1166 break;
1167 default:
1168 vers = "<unknown>";
1169 break;
1170 }
1171 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1172 " max %d CPUs\n",
1173 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1174 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1175 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1176
1177 mpic->next = mpics;
1178 mpics = mpic;
1179
1180 if (flags & MPIC_PRIMARY) {
1181 mpic_primary = mpic;
1182 irq_set_default_host(mpic->irqhost);
1183 }
1184
1185 return mpic;
1186 }
1187
1188 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1189 phys_addr_t paddr)
1190 {
1191 unsigned int isu_first = isu_num * mpic->isu_size;
1192
1193 BUG_ON(isu_num >= MPIC_MAX_ISU);
1194
1195 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1196 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1197 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1198 mpic->num_sources = isu_first + mpic->isu_size;
1199 }
1200
1201 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1202 {
1203 mpic->senses = senses;
1204 mpic->senses_count = count;
1205 }
1206
1207 void __init mpic_init(struct mpic *mpic)
1208 {
1209 int i;
1210
1211 BUG_ON(mpic->num_sources == 0);
1212
1213 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1214
1215 /* Set current processor priority to max */
1216 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1217
1218 /* Initialize timers: just disable them all */
1219 for (i = 0; i < 4; i++) {
1220 mpic_write(mpic->tmregs,
1221 i * MPIC_INFO(TIMER_STRIDE) +
1222 MPIC_INFO(TIMER_DESTINATION), 0);
1223 mpic_write(mpic->tmregs,
1224 i * MPIC_INFO(TIMER_STRIDE) +
1225 MPIC_INFO(TIMER_VECTOR_PRI),
1226 MPIC_VECPRI_MASK |
1227 (mpic->timer_vecs[0] + i));
1228 }
1229
1230 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1231 mpic_test_broken_ipi(mpic);
1232 for (i = 0; i < 4; i++) {
1233 mpic_ipi_write(i,
1234 MPIC_VECPRI_MASK |
1235 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1236 (mpic->ipi_vecs[0] + i));
1237 }
1238
1239 /* Initialize interrupt sources */
1240 if (mpic->irq_count == 0)
1241 mpic->irq_count = mpic->num_sources;
1242
1243 /* Do the HT PIC fixups on U3 broken mpic */
1244 DBG("MPIC flags: %x\n", mpic->flags);
1245 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1246 mpic_scan_ht_pics(mpic);
1247 mpic_u3msi_init(mpic);
1248 }
1249
1250 mpic_pasemi_msi_init(mpic);
1251
1252 for (i = 0; i < mpic->num_sources; i++) {
1253 /* start with vector = source number, and masked */
1254 u32 vecpri = MPIC_VECPRI_MASK | i |
1255 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1256
1257 /* check if protected */
1258 if (mpic->protected && test_bit(i, mpic->protected))
1259 continue;
1260 /* init hw */
1261 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1262 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1263 1 << hard_smp_processor_id());
1264 }
1265
1266 /* Init spurious vector */
1267 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1268
1269 /* Disable 8259 passthrough, if supported */
1270 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1271 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1272 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1273 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1274
1275 /* Set current processor priority to 0 */
1276 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1277
1278 #ifdef CONFIG_PM
1279 /* allocate memory to save mpic state */
1280 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1281 BUG_ON(mpic->save_data == NULL);
1282 #endif
1283 }
1284
1285 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1286 {
1287 u32 v;
1288
1289 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1290 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1291 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1292 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1293 }
1294
1295 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1296 {
1297 unsigned long flags;
1298 u32 v;
1299
1300 spin_lock_irqsave(&mpic_lock, flags);
1301 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1302 if (enable)
1303 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1304 else
1305 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1306 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1307 spin_unlock_irqrestore(&mpic_lock, flags);
1308 }
1309
1310 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1311 {
1312 int is_ipi;
1313 struct mpic *mpic = mpic_find(irq, &is_ipi);
1314 unsigned int src = mpic_irq_to_hw(irq);
1315 unsigned long flags;
1316 u32 reg;
1317
1318 spin_lock_irqsave(&mpic_lock, flags);
1319 if (is_ipi) {
1320 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1321 ~MPIC_VECPRI_PRIORITY_MASK;
1322 mpic_ipi_write(src - mpic->ipi_vecs[0],
1323 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1324 } else {
1325 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1326 & ~MPIC_VECPRI_PRIORITY_MASK;
1327 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1328 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1329 }
1330 spin_unlock_irqrestore(&mpic_lock, flags);
1331 }
1332
1333 unsigned int mpic_irq_get_priority(unsigned int irq)
1334 {
1335 int is_ipi;
1336 struct mpic *mpic = mpic_find(irq, &is_ipi);
1337 unsigned int src = mpic_irq_to_hw(irq);
1338 unsigned long flags;
1339 u32 reg;
1340
1341 spin_lock_irqsave(&mpic_lock, flags);
1342 if (is_ipi)
1343 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1344 else
1345 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1346 spin_unlock_irqrestore(&mpic_lock, flags);
1347 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1348 }
1349
1350 void mpic_setup_this_cpu(void)
1351 {
1352 #ifdef CONFIG_SMP
1353 struct mpic *mpic = mpic_primary;
1354 unsigned long flags;
1355 u32 msk = 1 << hard_smp_processor_id();
1356 unsigned int i;
1357
1358 BUG_ON(mpic == NULL);
1359
1360 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1361
1362 spin_lock_irqsave(&mpic_lock, flags);
1363
1364 /* let the mpic know we want intrs. default affinity is 0xffffffff
1365 * until changed via /proc. That's how it's done on x86. If we want
1366 * it differently, then we should make sure we also change the default
1367 * values of irq_desc[].affinity in irq.c.
1368 */
1369 if (distribute_irqs) {
1370 for (i = 0; i < mpic->num_sources ; i++)
1371 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1372 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1373 }
1374
1375 /* Set current processor priority to 0 */
1376 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1377
1378 spin_unlock_irqrestore(&mpic_lock, flags);
1379 #endif /* CONFIG_SMP */
1380 }
1381
1382 int mpic_cpu_get_priority(void)
1383 {
1384 struct mpic *mpic = mpic_primary;
1385
1386 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1387 }
1388
1389 void mpic_cpu_set_priority(int prio)
1390 {
1391 struct mpic *mpic = mpic_primary;
1392
1393 prio &= MPIC_CPU_TASKPRI_MASK;
1394 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1395 }
1396
1397 /*
1398 * XXX: someone who knows mpic should check this.
1399 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1400 * or can we reset the mpic in the new kernel?
1401 */
1402 void mpic_teardown_this_cpu(int secondary)
1403 {
1404 struct mpic *mpic = mpic_primary;
1405 unsigned long flags;
1406 u32 msk = 1 << hard_smp_processor_id();
1407 unsigned int i;
1408
1409 BUG_ON(mpic == NULL);
1410
1411 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1412 spin_lock_irqsave(&mpic_lock, flags);
1413
1414 /* let the mpic know we don't want intrs. */
1415 for (i = 0; i < mpic->num_sources ; i++)
1416 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1417 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1418
1419 /* Set current processor priority to max */
1420 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1421
1422 spin_unlock_irqrestore(&mpic_lock, flags);
1423 }
1424
1425
1426 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1427 {
1428 struct mpic *mpic = mpic_primary;
1429
1430 BUG_ON(mpic == NULL);
1431
1432 #ifdef DEBUG_IPI
1433 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1434 #endif
1435
1436 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1437 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1438 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1439 }
1440
1441 unsigned int mpic_get_one_irq(struct mpic *mpic)
1442 {
1443 u32 src;
1444
1445 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1446 #ifdef DEBUG_LOW
1447 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1448 #endif
1449 if (unlikely(src == mpic->spurious_vec)) {
1450 if (mpic->flags & MPIC_SPV_EOI)
1451 mpic_eoi(mpic);
1452 return NO_IRQ;
1453 }
1454 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1455 if (printk_ratelimit())
1456 printk(KERN_WARNING "%s: Got protected source %d !\n",
1457 mpic->name, (int)src);
1458 mpic_eoi(mpic);
1459 return NO_IRQ;
1460 }
1461
1462 return irq_linear_revmap(mpic->irqhost, src);
1463 }
1464
1465 unsigned int mpic_get_irq(void)
1466 {
1467 struct mpic *mpic = mpic_primary;
1468
1469 BUG_ON(mpic == NULL);
1470
1471 return mpic_get_one_irq(mpic);
1472 }
1473
1474
1475 #ifdef CONFIG_SMP
1476 void mpic_request_ipis(void)
1477 {
1478 struct mpic *mpic = mpic_primary;
1479 long i, err;
1480 static char *ipi_names[] = {
1481 "IPI0 (call function)",
1482 "IPI1 (reschedule)",
1483 "IPI2 (unused)",
1484 "IPI3 (debugger break)",
1485 };
1486 BUG_ON(mpic == NULL);
1487
1488 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1489
1490 for (i = 0; i < 4; i++) {
1491 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1492 mpic->ipi_vecs[0] + i);
1493 if (vipi == NO_IRQ) {
1494 printk(KERN_ERR "Failed to map IPI %ld\n", i);
1495 break;
1496 }
1497 err = request_irq(vipi, mpic_ipi_action,
1498 IRQF_DISABLED|IRQF_PERCPU,
1499 ipi_names[i], (void *)i);
1500 if (err) {
1501 printk(KERN_ERR "Request of irq %d for IPI %ld failed\n",
1502 vipi, i);
1503 break;
1504 }
1505 }
1506 }
1507
1508 void smp_mpic_message_pass(int target, int msg)
1509 {
1510 /* make sure we're sending something that translates to an IPI */
1511 if ((unsigned int)msg > 3) {
1512 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1513 smp_processor_id(), msg);
1514 return;
1515 }
1516 switch (target) {
1517 case MSG_ALL:
1518 mpic_send_ipi(msg, 0xffffffff);
1519 break;
1520 case MSG_ALL_BUT_SELF:
1521 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1522 break;
1523 default:
1524 mpic_send_ipi(msg, 1 << target);
1525 break;
1526 }
1527 }
1528
1529 int __init smp_mpic_probe(void)
1530 {
1531 int nr_cpus;
1532
1533 DBG("smp_mpic_probe()...\n");
1534
1535 nr_cpus = cpus_weight(cpu_possible_map);
1536
1537 DBG("nr_cpus: %d\n", nr_cpus);
1538
1539 if (nr_cpus > 1)
1540 mpic_request_ipis();
1541
1542 return nr_cpus;
1543 }
1544
1545 void __devinit smp_mpic_setup_cpu(int cpu)
1546 {
1547 mpic_setup_this_cpu();
1548 }
1549 #endif /* CONFIG_SMP */
1550
1551 #ifdef CONFIG_PM
1552 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1553 {
1554 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1555 int i;
1556
1557 for (i = 0; i < mpic->num_sources; i++) {
1558 mpic->save_data[i].vecprio =
1559 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1560 mpic->save_data[i].dest =
1561 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1562 }
1563
1564 return 0;
1565 }
1566
1567 static int mpic_resume(struct sys_device *dev)
1568 {
1569 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1570 int i;
1571
1572 for (i = 0; i < mpic->num_sources; i++) {
1573 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1574 mpic->save_data[i].vecprio);
1575 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1576 mpic->save_data[i].dest);
1577
1578 #ifdef CONFIG_MPIC_U3_HT_IRQS
1579 {
1580 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1581
1582 if (fixup->base) {
1583 /* we use the lowest bit in an inverted meaning */
1584 if ((mpic->save_data[i].fixup_data & 1) == 0)
1585 continue;
1586
1587 /* Enable and configure */
1588 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1589
1590 writel(mpic->save_data[i].fixup_data & ~1,
1591 fixup->base + 4);
1592 }
1593 }
1594 #endif
1595 } /* end for loop */
1596
1597 return 0;
1598 }
1599 #endif
1600
1601 static struct sysdev_class mpic_sysclass = {
1602 #ifdef CONFIG_PM
1603 .resume = mpic_resume,
1604 .suspend = mpic_suspend,
1605 #endif
1606 set_kset_name("mpic"),
1607 };
1608
1609 static int mpic_init_sys(void)
1610 {
1611 struct mpic *mpic = mpics;
1612 int error, id = 0;
1613
1614 error = sysdev_class_register(&mpic_sysclass);
1615
1616 while (mpic && !error) {
1617 mpic->sysdev.cls = &mpic_sysclass;
1618 mpic->sysdev.id = id++;
1619 error = sysdev_register(&mpic->sysdev);
1620 mpic = mpic->next;
1621 }
1622 return error;
1623 }
1624
1625 device_initcall(mpic_init_sys);
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