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[POWERPC] pasemi: Implement MSI support
[linux-2.6/btrfs-unstable.git] / arch / powerpc / sysdev / ipic.c
blob7274750fd9c6fd32674d8d8da565cab3d5626c4a
1 /*
2 * arch/powerpc/sysdev/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <asm/irq.h>
26 #include <asm/io.h>
27 #include <asm/prom.h>
28 #include <asm/ipic.h>
29
30 #include "ipic.h"
31
32 static struct ipic * primary_ipic;
33 static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
34 static DEFINE_SPINLOCK(ipic_lock);
35
36 static struct ipic_info ipic_info[] = {
37 [1] = {
38 .mask = IPIC_SIMSR_H,
39 .prio = IPIC_SIPRR_C,
40 .force = IPIC_SIFCR_H,
41 .bit = 16,
42 .prio_mask = 0,
43 },
44 [2] = {
45 .mask = IPIC_SIMSR_H,
46 .prio = IPIC_SIPRR_C,
47 .force = IPIC_SIFCR_H,
48 .bit = 17,
49 .prio_mask = 1,
50 },
51 [4] = {
52 .mask = IPIC_SIMSR_H,
53 .prio = IPIC_SIPRR_C,
54 .force = IPIC_SIFCR_H,
55 .bit = 19,
56 .prio_mask = 3,
57 },
58 [9] = {
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 24,
63 .prio_mask = 0,
64 },
65 [10] = {
66 .mask = IPIC_SIMSR_H,
67 .prio = IPIC_SIPRR_D,
68 .force = IPIC_SIFCR_H,
69 .bit = 25,
70 .prio_mask = 1,
71 },
72 [11] = {
73 .mask = IPIC_SIMSR_H,
74 .prio = IPIC_SIPRR_D,
75 .force = IPIC_SIFCR_H,
76 .bit = 26,
77 .prio_mask = 2,
78 },
79 [12] = {
80 .mask = IPIC_SIMSR_H,
81 .prio = IPIC_SIPRR_D,
82 .force = IPIC_SIFCR_H,
83 .bit = 27,
84 .prio_mask = 3,
85 },
86 [13] = {
87 .mask = IPIC_SIMSR_H,
88 .prio = IPIC_SIPRR_D,
89 .force = IPIC_SIFCR_H,
90 .bit = 28,
91 .prio_mask = 4,
92 },
93 [14] = {
94 .mask = IPIC_SIMSR_H,
95 .prio = IPIC_SIPRR_D,
96 .force = IPIC_SIFCR_H,
97 .bit = 29,
98 .prio_mask = 5,
99 },
100 [15] = {
101 .mask = IPIC_SIMSR_H,
102 .prio = IPIC_SIPRR_D,
103 .force = IPIC_SIFCR_H,
104 .bit = 30,
105 .prio_mask = 6,
106 },
107 [16] = {
108 .mask = IPIC_SIMSR_H,
109 .prio = IPIC_SIPRR_D,
110 .force = IPIC_SIFCR_H,
111 .bit = 31,
112 .prio_mask = 7,
113 },
114 [17] = {
115 .ack = IPIC_SEPNR,
116 .mask = IPIC_SEMSR,
117 .prio = IPIC_SMPRR_A,
118 .force = IPIC_SEFCR,
119 .bit = 1,
120 .prio_mask = 5,
121 },
122 [18] = {
123 .ack = IPIC_SEPNR,
124 .mask = IPIC_SEMSR,
125 .prio = IPIC_SMPRR_A,
126 .force = IPIC_SEFCR,
127 .bit = 2,
128 .prio_mask = 6,
129 },
130 [19] = {
131 .ack = IPIC_SEPNR,
132 .mask = IPIC_SEMSR,
133 .prio = IPIC_SMPRR_A,
134 .force = IPIC_SEFCR,
135 .bit = 3,
136 .prio_mask = 7,
137 },
138 [20] = {
139 .ack = IPIC_SEPNR,
140 .mask = IPIC_SEMSR,
141 .prio = IPIC_SMPRR_B,
142 .force = IPIC_SEFCR,
143 .bit = 4,
144 .prio_mask = 4,
145 },
146 [21] = {
147 .ack = IPIC_SEPNR,
148 .mask = IPIC_SEMSR,
149 .prio = IPIC_SMPRR_B,
150 .force = IPIC_SEFCR,
151 .bit = 5,
152 .prio_mask = 5,
153 },
154 [22] = {
155 .ack = IPIC_SEPNR,
156 .mask = IPIC_SEMSR,
157 .prio = IPIC_SMPRR_B,
158 .force = IPIC_SEFCR,
159 .bit = 6,
160 .prio_mask = 6,
161 },
162 [23] = {
163 .ack = IPIC_SEPNR,
164 .mask = IPIC_SEMSR,
165 .prio = IPIC_SMPRR_B,
166 .force = IPIC_SEFCR,
167 .bit = 7,
168 .prio_mask = 7,
169 },
170 [32] = {
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 0,
175 .prio_mask = 0,
176 },
177 [33] = {
178 .mask = IPIC_SIMSR_H,
179 .prio = IPIC_SIPRR_A,
180 .force = IPIC_SIFCR_H,
181 .bit = 1,
182 .prio_mask = 1,
183 },
184 [34] = {
185 .mask = IPIC_SIMSR_H,
186 .prio = IPIC_SIPRR_A,
187 .force = IPIC_SIFCR_H,
188 .bit = 2,
189 .prio_mask = 2,
190 },
191 [35] = {
192 .mask = IPIC_SIMSR_H,
193 .prio = IPIC_SIPRR_A,
194 .force = IPIC_SIFCR_H,
195 .bit = 3,
196 .prio_mask = 3,
197 },
198 [36] = {
199 .mask = IPIC_SIMSR_H,
200 .prio = IPIC_SIPRR_A,
201 .force = IPIC_SIFCR_H,
202 .bit = 4,
203 .prio_mask = 4,
204 },
205 [37] = {
206 .mask = IPIC_SIMSR_H,
207 .prio = IPIC_SIPRR_A,
208 .force = IPIC_SIFCR_H,
209 .bit = 5,
210 .prio_mask = 5,
211 },
212 [38] = {
213 .mask = IPIC_SIMSR_H,
214 .prio = IPIC_SIPRR_A,
215 .force = IPIC_SIFCR_H,
216 .bit = 6,
217 .prio_mask = 6,
218 },
219 [39] = {
220 .mask = IPIC_SIMSR_H,
221 .prio = IPIC_SIPRR_A,
222 .force = IPIC_SIFCR_H,
223 .bit = 7,
224 .prio_mask = 7,
225 },
226 [42] = {
227 .mask = IPIC_SIMSR_H,
228 .prio = IPIC_SIPRR_B,
229 .force = IPIC_SIFCR_H,
230 .bit = 10,
231 .prio_mask = 2,
232 },
233 [44] = {
234 .mask = IPIC_SIMSR_H,
235 .prio = IPIC_SIPRR_B,
236 .force = IPIC_SIFCR_H,
237 .bit = 12,
238 .prio_mask = 4,
239 },
240 [45] = {
241 .mask = IPIC_SIMSR_H,
242 .prio = IPIC_SIPRR_B,
243 .force = IPIC_SIFCR_H,
244 .bit = 13,
245 .prio_mask = 5,
246 },
247 [46] = {
248 .mask = IPIC_SIMSR_H,
249 .prio = IPIC_SIPRR_B,
250 .force = IPIC_SIFCR_H,
251 .bit = 14,
252 .prio_mask = 6,
253 },
254 [47] = {
255 .mask = IPIC_SIMSR_H,
256 .prio = IPIC_SIPRR_B,
257 .force = IPIC_SIFCR_H,
258 .bit = 15,
259 .prio_mask = 7,
260 },
261 [48] = {
262 .mask = IPIC_SEMSR,
263 .prio = IPIC_SMPRR_A,
264 .force = IPIC_SEFCR,
265 .bit = 0,
266 .prio_mask = 4,
267 },
268 [64] = {
269 .mask = IPIC_SIMSR_L,
270 .prio = IPIC_SMPRR_A,
271 .force = IPIC_SIFCR_L,
272 .bit = 0,
273 .prio_mask = 0,
274 },
275 [65] = {
276 .mask = IPIC_SIMSR_L,
277 .prio = IPIC_SMPRR_A,
278 .force = IPIC_SIFCR_L,
279 .bit = 1,
280 .prio_mask = 1,
281 },
282 [66] = {
283 .mask = IPIC_SIMSR_L,
284 .prio = IPIC_SMPRR_A,
285 .force = IPIC_SIFCR_L,
286 .bit = 2,
287 .prio_mask = 2,
288 },
289 [67] = {
290 .mask = IPIC_SIMSR_L,
291 .prio = IPIC_SMPRR_A,
292 .force = IPIC_SIFCR_L,
293 .bit = 3,
294 .prio_mask = 3,
295 },
296 [68] = {
297 .mask = IPIC_SIMSR_L,
298 .prio = IPIC_SMPRR_B,
299 .force = IPIC_SIFCR_L,
300 .bit = 4,
301 .prio_mask = 0,
302 },
303 [69] = {
304 .mask = IPIC_SIMSR_L,
305 .prio = IPIC_SMPRR_B,
306 .force = IPIC_SIFCR_L,
307 .bit = 5,
308 .prio_mask = 1,
309 },
310 [70] = {
311 .mask = IPIC_SIMSR_L,
312 .prio = IPIC_SMPRR_B,
313 .force = IPIC_SIFCR_L,
314 .bit = 6,
315 .prio_mask = 2,
316 },
317 [71] = {
318 .mask = IPIC_SIMSR_L,
319 .prio = IPIC_SMPRR_B,
320 .force = IPIC_SIFCR_L,
321 .bit = 7,
322 .prio_mask = 3,
323 },
324 [72] = {
325 .mask = IPIC_SIMSR_L,
326 .prio = 0,
327 .force = IPIC_SIFCR_L,
328 .bit = 8,
329 },
330 [73] = {
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 9,
335 },
336 [74] = {
337 .mask = IPIC_SIMSR_L,
338 .prio = 0,
339 .force = IPIC_SIFCR_L,
340 .bit = 10,
341 },
342 [75] = {
343 .mask = IPIC_SIMSR_L,
344 .prio = 0,
345 .force = IPIC_SIFCR_L,
346 .bit = 11,
347 },
348 [76] = {
349 .mask = IPIC_SIMSR_L,
350 .prio = 0,
351 .force = IPIC_SIFCR_L,
352 .bit = 12,
353 },
354 [77] = {
355 .mask = IPIC_SIMSR_L,
356 .prio = 0,
357 .force = IPIC_SIFCR_L,
358 .bit = 13,
359 },
360 [78] = {
361 .mask = IPIC_SIMSR_L,
362 .prio = 0,
363 .force = IPIC_SIFCR_L,
364 .bit = 14,
365 },
366 [79] = {
367 .mask = IPIC_SIMSR_L,
368 .prio = 0,
369 .force = IPIC_SIFCR_L,
370 .bit = 15,
371 },
372 [80] = {
373 .mask = IPIC_SIMSR_L,
374 .prio = 0,
375 .force = IPIC_SIFCR_L,
376 .bit = 16,
377 },
378 [81] = {
379 .mask = IPIC_SIMSR_L,
380 .prio = 0,
381 .force = IPIC_SIFCR_L,
382 .bit = 17,
383 },
384 [82] = {
385 .mask = IPIC_SIMSR_L,
386 .prio = 0,
387 .force = IPIC_SIFCR_L,
388 .bit = 18,
389 },
390 [84] = {
391 .mask = IPIC_SIMSR_L,
392 .prio = 0,
393 .force = IPIC_SIFCR_L,
394 .bit = 20,
395 },
396 [85] = {
397 .mask = IPIC_SIMSR_L,
398 .prio = 0,
399 .force = IPIC_SIFCR_L,
400 .bit = 21,
401 },
402 [86] = {
403 .mask = IPIC_SIMSR_L,
404 .prio = 0,
405 .force = IPIC_SIFCR_L,
406 .bit = 22,
407 },
408 [87] = {
409 .mask = IPIC_SIMSR_L,
410 .prio = 0,
411 .force = IPIC_SIFCR_L,
412 .bit = 23,
413 },
414 [88] = {
415 .mask = IPIC_SIMSR_L,
416 .prio = 0,
417 .force = IPIC_SIFCR_L,
418 .bit = 24,
419 },
420 [89] = {
421 .mask = IPIC_SIMSR_L,
422 .prio = 0,
423 .force = IPIC_SIFCR_L,
424 .bit = 25,
425 },
426 [90] = {
427 .mask = IPIC_SIMSR_L,
428 .prio = 0,
429 .force = IPIC_SIFCR_L,
430 .bit = 26,
431 },
432 [91] = {
433 .mask = IPIC_SIMSR_L,
434 .prio = 0,
435 .force = IPIC_SIFCR_L,
436 .bit = 27,
437 },
438 };
439
440 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
441 {
442 return in_be32(base + (reg >> 2));
443 }
444
445 static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
446 {
447 out_be32(base + (reg >> 2), value);
448 }
449
450 static inline struct ipic * ipic_from_irq(unsigned int virq)
451 {
452 return primary_ipic;
453 }
454
455 #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
456
457 static void ipic_unmask_irq(unsigned int virq)
458 {
459 struct ipic *ipic = ipic_from_irq(virq);
460 unsigned int src = ipic_irq_to_hw(virq);
461 unsigned long flags;
462 u32 temp;
463
464 spin_lock_irqsave(&ipic_lock, flags);
465
466 temp = ipic_read(ipic->regs, ipic_info[src].mask);
467 temp |= (1 << (31 - ipic_info[src].bit));
468 ipic_write(ipic->regs, ipic_info[src].mask, temp);
469
470 spin_unlock_irqrestore(&ipic_lock, flags);
471 }
472
473 static void ipic_mask_irq(unsigned int virq)
474 {
475 struct ipic *ipic = ipic_from_irq(virq);
476 unsigned int src = ipic_irq_to_hw(virq);
477 unsigned long flags;
478 u32 temp;
479
480 spin_lock_irqsave(&ipic_lock, flags);
481
482 temp = ipic_read(ipic->regs, ipic_info[src].mask);
483 temp &= ~(1 << (31 - ipic_info[src].bit));
484 ipic_write(ipic->regs, ipic_info[src].mask, temp);
485
486 /* mb() can't guarantee that masking is finished. But it does finish
487 * for nearly all cases. */
488 mb();
489
490 spin_unlock_irqrestore(&ipic_lock, flags);
491 }
492
493 static void ipic_ack_irq(unsigned int virq)
494 {
495 struct ipic *ipic = ipic_from_irq(virq);
496 unsigned int src = ipic_irq_to_hw(virq);
497 unsigned long flags;
498 u32 temp;
499
500 spin_lock_irqsave(&ipic_lock, flags);
501
502 temp = ipic_read(ipic->regs, ipic_info[src].ack);
503 temp |= (1 << (31 - ipic_info[src].bit));
504 ipic_write(ipic->regs, ipic_info[src].ack, temp);
505
506 /* mb() can't guarantee that ack is finished. But it does finish
507 * for nearly all cases. */
508 mb();
509
510 spin_unlock_irqrestore(&ipic_lock, flags);
511 }
512
513 static void ipic_mask_irq_and_ack(unsigned int virq)
514 {
515 struct ipic *ipic = ipic_from_irq(virq);
516 unsigned int src = ipic_irq_to_hw(virq);
517 unsigned long flags;
518 u32 temp;
519
520 spin_lock_irqsave(&ipic_lock, flags);
521
522 temp = ipic_read(ipic->regs, ipic_info[src].mask);
523 temp &= ~(1 << (31 - ipic_info[src].bit));
524 ipic_write(ipic->regs, ipic_info[src].mask, temp);
525
526 temp = ipic_read(ipic->regs, ipic_info[src].ack);
527 temp |= (1 << (31 - ipic_info[src].bit));
528 ipic_write(ipic->regs, ipic_info[src].ack, temp);
529
530 /* mb() can't guarantee that ack is finished. But it does finish
531 * for nearly all cases. */
532 mb();
533
534 spin_unlock_irqrestore(&ipic_lock, flags);
535 }
536
537 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
538 {
539 struct ipic *ipic = ipic_from_irq(virq);
540 unsigned int src = ipic_irq_to_hw(virq);
541 struct irq_desc *desc = get_irq_desc(virq);
542 unsigned int vold, vnew, edibit;
543
544 if (flow_type == IRQ_TYPE_NONE)
545 flow_type = IRQ_TYPE_LEVEL_LOW;
546
547 /* ipic supports only low assertion and high-to-low change senses
548 */
549 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
550 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
551 flow_type);
552 return -EINVAL;
553 }
554 /* ipic supports only edge mode on external interrupts */
555 if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
556 printk(KERN_ERR "ipic: edge sense not supported on internal "
557 "interrupts\n");
558 return -EINVAL;
559 }
560
561 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
562 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
563 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
564 desc->status |= IRQ_LEVEL;
565 desc->handle_irq = handle_level_irq;
566 desc->chip = &ipic_level_irq_chip;
567 } else {
568 desc->handle_irq = handle_edge_irq;
569 desc->chip = &ipic_edge_irq_chip;
570 }
571
572 /* only EXT IRQ senses are programmable on ipic
573 * internal IRQ senses are LEVEL_LOW
574 */
575 if (src == IPIC_IRQ_EXT0)
576 edibit = 15;
577 else
578 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
579 edibit = (14 - (src - IPIC_IRQ_EXT1));
580 else
581 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
582
583 vold = ipic_read(ipic->regs, IPIC_SECNR);
584 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
585 vnew = vold | (1 << edibit);
586 } else {
587 vnew = vold & ~(1 << edibit);
588 }
589 if (vold != vnew)
590 ipic_write(ipic->regs, IPIC_SECNR, vnew);
591 return 0;
592 }
593
594 /* level interrupts and edge interrupts have different ack operations */
595 static struct irq_chip ipic_level_irq_chip = {
596 .typename = " IPIC ",
597 .unmask = ipic_unmask_irq,
598 .mask = ipic_mask_irq,
599 .mask_ack = ipic_mask_irq,
600 .set_type = ipic_set_irq_type,
601 };
602
603 static struct irq_chip ipic_edge_irq_chip = {
604 .typename = " IPIC ",
605 .unmask = ipic_unmask_irq,
606 .mask = ipic_mask_irq,
607 .mask_ack = ipic_mask_irq_and_ack,
608 .ack = ipic_ack_irq,
609 .set_type = ipic_set_irq_type,
610 };
611
612 static int ipic_host_match(struct irq_host *h, struct device_node *node)
613 {
614 /* Exact match, unless ipic node is NULL */
615 return h->of_node == NULL || h->of_node == node;
616 }
617
618 static int ipic_host_map(struct irq_host *h, unsigned int virq,
619 irq_hw_number_t hw)
620 {
621 struct ipic *ipic = h->host_data;
622
623 set_irq_chip_data(virq, ipic);
624 set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
625
626 /* Set default irq type */
627 set_irq_type(virq, IRQ_TYPE_NONE);
628
629 return 0;
630 }
631
632 static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
633 u32 *intspec, unsigned int intsize,
634 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
635
636 {
637 /* interrupt sense values coming from the device tree equal either
638 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
639 */
640 *out_hwirq = intspec[0];
641 if (intsize > 1)
642 *out_flags = intspec[1];
643 else
644 *out_flags = IRQ_TYPE_NONE;
645 return 0;
646 }
647
648 static struct irq_host_ops ipic_host_ops = {
649 .match = ipic_host_match,
650 .map = ipic_host_map,
651 .xlate = ipic_host_xlate,
652 };
653
654 struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
655 {
656 struct ipic *ipic;
657 struct resource res;
658 u32 temp = 0, ret;
659
660 ipic = alloc_bootmem(sizeof(struct ipic));
661 if (ipic == NULL)
662 return NULL;
663
664 memset(ipic, 0, sizeof(struct ipic));
665
666 ipic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
667 NR_IPIC_INTS,
668 &ipic_host_ops, 0);
669 if (ipic->irqhost == NULL) {
670 of_node_put(node);
671 return NULL;
672 }
673
674 ret = of_address_to_resource(node, 0, &res);
675 if (ret) {
676 of_node_put(node);
677 return NULL;
678 }
679
680 ipic->regs = ioremap(res.start, res.end - res.start + 1);
681
682 ipic->irqhost->host_data = ipic;
683
684 /* init hw */
685 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
686
687 /* default priority scheme is grouped. If spread mode is required
688 * configure SICFR accordingly */
689 if (flags & IPIC_SPREADMODE_GRP_A)
690 temp |= SICFR_IPSA;
691 if (flags & IPIC_SPREADMODE_GRP_B)
692 temp |= SICFR_IPSB;
693 if (flags & IPIC_SPREADMODE_GRP_C)
694 temp |= SICFR_IPSC;
695 if (flags & IPIC_SPREADMODE_GRP_D)
696 temp |= SICFR_IPSD;
697 if (flags & IPIC_SPREADMODE_MIX_A)
698 temp |= SICFR_MPSA;
699 if (flags & IPIC_SPREADMODE_MIX_B)
700 temp |= SICFR_MPSB;
701
702 ipic_write(ipic->regs, IPIC_SICFR, temp);
703
704 /* handle MCP route */
705 temp = 0;
706 if (flags & IPIC_DISABLE_MCP_OUT)
707 temp = SERCR_MCPR;
708 ipic_write(ipic->regs, IPIC_SERCR, temp);
709
710 /* handle routing of IRQ0 to MCP */
711 temp = ipic_read(ipic->regs, IPIC_SEMSR);
712
713 if (flags & IPIC_IRQ0_MCP)
714 temp |= SEMSR_SIRQ0;
715 else
716 temp &= ~SEMSR_SIRQ0;
717
718 ipic_write(ipic->regs, IPIC_SEMSR, temp);
719
720 primary_ipic = ipic;
721 irq_set_default_host(primary_ipic->irqhost);
722
723 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
724 primary_ipic->regs);
725
726 return ipic;
727 }
728
729 int ipic_set_priority(unsigned int virq, unsigned int priority)
730 {
731 struct ipic *ipic = ipic_from_irq(virq);
732 unsigned int src = ipic_irq_to_hw(virq);
733 u32 temp;
734
735 if (priority > 7)
736 return -EINVAL;
737 if (src > 127)
738 return -EINVAL;
739 if (ipic_info[src].prio == 0)
740 return -EINVAL;
741
742 temp = ipic_read(ipic->regs, ipic_info[src].prio);
743
744 if (priority < 4) {
745 temp &= ~(0x7 << (20 + (3 - priority) * 3));
746 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
747 } else {
748 temp &= ~(0x7 << (4 + (7 - priority) * 3));
749 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
750 }
751
752 ipic_write(ipic->regs, ipic_info[src].prio, temp);
753
754 return 0;
755 }
756
757 void ipic_set_highest_priority(unsigned int virq)
758 {
759 struct ipic *ipic = ipic_from_irq(virq);
760 unsigned int src = ipic_irq_to_hw(virq);
761 u32 temp;
762
763 temp = ipic_read(ipic->regs, IPIC_SICFR);
764
765 /* clear and set HPI */
766 temp &= 0x7f000000;
767 temp |= (src & 0x7f) << 24;
768
769 ipic_write(ipic->regs, IPIC_SICFR, temp);
770 }
771
772 void ipic_set_default_priority(void)
773 {
774 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
775 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
776 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
777 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
778 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
779 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
780 }
781
782 void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
783 {
784 struct ipic *ipic = primary_ipic;
785 u32 temp;
786
787 temp = ipic_read(ipic->regs, IPIC_SERMR);
788 temp |= (1 << (31 - mcp_irq));
789 ipic_write(ipic->regs, IPIC_SERMR, temp);
790 }
791
792 void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
793 {
794 struct ipic *ipic = primary_ipic;
795 u32 temp;
796
797 temp = ipic_read(ipic->regs, IPIC_SERMR);
798 temp &= (1 << (31 - mcp_irq));
799 ipic_write(ipic->regs, IPIC_SERMR, temp);
800 }
801
802 u32 ipic_get_mcp_status(void)
803 {
804 return ipic_read(primary_ipic->regs, IPIC_SERMR);
805 }
806
807 void ipic_clear_mcp_status(u32 mask)
808 {
809 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
810 }
811
812 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
813 unsigned int ipic_get_irq(void)
814 {
815 int irq;
816
817 BUG_ON(primary_ipic == NULL);
818
819 #define IPIC_SIVCR_VECTOR_MASK 0x7f
820 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
821
822 if (irq == 0) /* 0 --> no irq is pending */
823 return NO_IRQ;
824
825 return irq_linear_revmap(primary_ipic->irqhost, irq);
826 }
827
828 static struct sysdev_class ipic_sysclass = {
829 set_kset_name("ipic"),
830 };
831
832 static struct sys_device device_ipic = {
833 .id = 0,
834 .cls = &ipic_sysclass,
835 };
836
837 static int __init init_ipic_sysfs(void)
838 {
839 int rc;
840
841 if (!primary_ipic->regs)
842 return -ENODEV;
843 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
844
845 rc = sysdev_class_register(&ipic_sysclass);
846 if (rc) {
847 printk(KERN_ERR "Failed registering ipic sys class\n");
848 return -ENODEV;
849 }
850 rc = sysdev_register(&device_ipic);
851 if (rc) {
852 printk(KERN_ERR "Failed registering ipic sys device\n");
853 return -ENODEV;
854 }
855 return 0;
856 }
857
858 subsys_initcall(init_ipic_sysfs);
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