drivers/clocksource/timer-fttmr010.c

   1 /*
   2  * Faraday Technology FTTMR010 timer driver
   3  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   4  *
   5  * Based on a rewrite of arch/arm/mach-gemini/timer.c:
   6  * Copyright (C) 2001-2006 Storlink, Corp.
   7  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
   8  */
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/sched_clock.h>
  17 #include <linux/clk.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/delay.h>
  21
  22 /*
  23  * Register definitions for the timers
  24  */
  25 #define TIMER1_COUNT            (0x00)
  26 #define TIMER1_LOAD             (0x04)
  27 #define TIMER1_MATCH1           (0x08)
  28 #define TIMER1_MATCH2           (0x0c)
  29 #define TIMER2_COUNT            (0x10)
  30 #define TIMER2_LOAD             (0x14)
  31 #define TIMER2_MATCH1           (0x18)
  32 #define TIMER2_MATCH2           (0x1c)
  33 #define TIMER3_COUNT            (0x20)
  34 #define TIMER3_LOAD             (0x24)
  35 #define TIMER3_MATCH1           (0x28)
  36 #define TIMER3_MATCH2           (0x2c)
  37 #define TIMER_CR                (0x30)
  38 #define TIMER_INTR_STATE        (0x34)
  39 #define TIMER_INTR_MASK         (0x38)
  40
  41 #define TIMER_1_CR_ENABLE       BIT(0)
  42 #define TIMER_1_CR_CLOCK        BIT(1)
  43 #define TIMER_1_CR_INT          BIT(2)
  44 #define TIMER_2_CR_ENABLE       BIT(3)
  45 #define TIMER_2_CR_CLOCK        BIT(4)
  46 #define TIMER_2_CR_INT          BIT(5)
  47 #define TIMER_3_CR_ENABLE       BIT(6)
  48 #define TIMER_3_CR_CLOCK        BIT(7)
  49 #define TIMER_3_CR_INT          BIT(8)
  50 #define TIMER_1_CR_UPDOWN       BIT(9)
  51 #define TIMER_2_CR_UPDOWN       BIT(10)
  52 #define TIMER_3_CR_UPDOWN       BIT(11)
  53
  54 /*
  55  * The Aspeed AST2400 moves bits around in the control register
  56  * and lacks bits for setting the timer to count upwards.
  57  */
  58 #define TIMER_1_CR_ASPEED_ENABLE        BIT(0)
  59 #define TIMER_1_CR_ASPEED_CLOCK         BIT(1)
  60 #define TIMER_1_CR_ASPEED_INT           BIT(2)
  61 #define TIMER_2_CR_ASPEED_ENABLE        BIT(4)
  62 #define TIMER_2_CR_ASPEED_CLOCK         BIT(5)
  63 #define TIMER_2_CR_ASPEED_INT           BIT(6)
  64 #define TIMER_3_CR_ASPEED_ENABLE        BIT(8)
  65 #define TIMER_3_CR_ASPEED_CLOCK         BIT(9)
  66 #define TIMER_3_CR_ASPEED_INT           BIT(10)
  67
  68 #define TIMER_1_INT_MATCH1      BIT(0)
  69 #define TIMER_1_INT_MATCH2      BIT(1)
  70 #define TIMER_1_INT_OVERFLOW    BIT(2)
  71 #define TIMER_2_INT_MATCH1      BIT(3)
  72 #define TIMER_2_INT_MATCH2      BIT(4)
  73 #define TIMER_2_INT_OVERFLOW    BIT(5)
  74 #define TIMER_3_INT_MATCH1      BIT(6)
  75 #define TIMER_3_INT_MATCH2      BIT(7)
  76 #define TIMER_3_INT_OVERFLOW    BIT(8)
  77 #define TIMER_INT_ALL_MASK      0x1ff
  78
  79 struct fttmr010 {
  80         void __iomem *base;
  81         unsigned int tick_rate;
  82         bool count_down;
  83         u32 t1_enable_val;
  84         struct clock_event_device clkevt;
  85 #ifdef CONFIG_ARM
  86         struct delay_timer delay_timer;
  87 #endif
  88 };
  89
  90 /*
  91  * A local singleton used by sched_clock and delay timer reads, which are
  92  * fast and stateless
  93  */
  94 static struct fttmr010 *local_fttmr;
  95
  96 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
  97 {
  98         return container_of(evt, struct fttmr010, clkevt);
  99 }
 100
 101 static u64 notrace fttmr010_read_sched_clock_up(void)
 102 {
 103         return readl(local_fttmr->base + TIMER2_COUNT);
 104 }
 105
 106 static u64 notrace fttmr010_read_sched_clock_down(void)
 107 {
 108         return ~readl(local_fttmr->base + TIMER2_COUNT);
 109 }
 110
 111 #ifdef CONFIG_ARM
 112
 113 static unsigned long fttmr010_read_current_timer_up(void)
 114 {
 115         return readl(local_fttmr->base + TIMER2_COUNT);
 116 }
 117
 118 static unsigned long fttmr010_read_current_timer_down(void)
 119 {
 120         return ~readl(local_fttmr->base + TIMER2_COUNT);
 121 }
 122
 123 #endif
 124
 125 static int fttmr010_timer_set_next_event(unsigned long cycles,
 126                                        struct clock_event_device *evt)
 127 {
 128         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 129         u32 cr;
 130
 131         /* Stop */
 132         cr = readl(fttmr010->base + TIMER_CR);
 133         cr &= ~fttmr010->t1_enable_val;
 134         writel(cr, fttmr010->base + TIMER_CR);
 135
 136         /* Setup the match register forward/backward in time */
 137         cr = readl(fttmr010->base + TIMER1_COUNT);
 138         if (fttmr010->count_down)
 139                 cr -= cycles;
 140         else
 141                 cr += cycles;
 142         writel(cr, fttmr010->base + TIMER1_MATCH1);
 143
 144         /* Start */
 145         cr = readl(fttmr010->base + TIMER_CR);
 146         cr |= fttmr010->t1_enable_val;
 147         writel(cr, fttmr010->base + TIMER_CR);
 148
 149         return 0;
 150 }
 151
 152 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
 153 {
 154         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 155         u32 cr;
 156
 157         /* Stop */
 158         cr = readl(fttmr010->base + TIMER_CR);
 159         cr &= ~fttmr010->t1_enable_val;
 160         writel(cr, fttmr010->base + TIMER_CR);
 161
 162         return 0;
 163 }
 164
 165 static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
 166 {
 167         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 168         u32 cr;
 169
 170         /* Stop */
 171         cr = readl(fttmr010->base + TIMER_CR);
 172         cr &= ~fttmr010->t1_enable_val;
 173         writel(cr, fttmr010->base + TIMER_CR);
 174
 175         /* Setup counter start from 0 or ~0 */
 176         writel(0, fttmr010->base + TIMER1_COUNT);
 177         if (fttmr010->count_down)
 178                 writel(~0, fttmr010->base + TIMER1_LOAD);
 179         else
 180                 writel(0, fttmr010->base + TIMER1_LOAD);
 181
 182         /* Enable interrupt */
 183         cr = readl(fttmr010->base + TIMER_INTR_MASK);
 184         cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
 185         cr |= TIMER_1_INT_MATCH1;
 186         writel(cr, fttmr010->base + TIMER_INTR_MASK);
 187
 188         return 0;
 189 }
 190
 191 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
 192 {
 193         struct fttmr010 *fttmr010 = to_fttmr010(evt);
 194         u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
 195         u32 cr;
 196
 197         /* Stop */
 198         cr = readl(fttmr010->base + TIMER_CR);
 199         cr &= ~fttmr010->t1_enable_val;
 200         writel(cr, fttmr010->base + TIMER_CR);
 201
 202         /* Setup timer to fire at 1/HZ intervals. */
 203         if (fttmr010->count_down) {
 204                 writel(period, fttmr010->base + TIMER1_LOAD);
 205                 writel(0, fttmr010->base + TIMER1_MATCH1);
 206         } else {
 207                 cr = 0xffffffff - (period - 1);
 208                 writel(cr, fttmr010->base + TIMER1_COUNT);
 209                 writel(cr, fttmr010->base + TIMER1_LOAD);
 210
 211                 /* Enable interrupt on overflow */
 212                 cr = readl(fttmr010->base + TIMER_INTR_MASK);
 213                 cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
 214                 cr |= TIMER_1_INT_OVERFLOW;
 215                 writel(cr, fttmr010->base + TIMER_INTR_MASK);
 216         }
 217
 218         /* Start the timer */
 219         cr = readl(fttmr010->base + TIMER_CR);
 220         cr |= fttmr010->t1_enable_val;
 221         writel(cr, fttmr010->base + TIMER_CR);
 222
 223         return 0;
 224 }
 225
 226 /*
 227  * IRQ handler for the timer
 228  */
 229 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
 230 {
 231         struct clock_event_device *evt = dev_id;
 232
 233         evt->event_handler(evt);
 234         return IRQ_HANDLED;
 235 }
 236
 237 static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
 238 {
 239         struct fttmr010 *fttmr010;
 240         int irq;
 241         struct clk *clk;
 242         int ret;
 243         u32 val;
 244
 245         /*
 246          * These implementations require a clock reference.
 247          * FIXME: we currently only support clocking using PCLK
 248          * and using EXTCLK is not supported in the driver.
 249          */
 250         clk = of_clk_get_by_name(np, "PCLK");
 251         if (IS_ERR(clk)) {
 252                 pr_err("could not get PCLK\n");
 253                 return PTR_ERR(clk);
 254         }
 255         ret = clk_prepare_enable(clk);
 256         if (ret) {
 257                 pr_err("failed to enable PCLK\n");
 258                 return ret;
 259         }
 260
 261         fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
 262         if (!fttmr010) {
 263                 ret = -ENOMEM;
 264                 goto out_disable_clock;
 265         }
 266         fttmr010->tick_rate = clk_get_rate(clk);
 267
 268         fttmr010->base = of_iomap(np, 0);
 269         if (!fttmr010->base) {
 270                 pr_err("Can't remap registers");
 271                 ret = -ENXIO;
 272                 goto out_free;
 273         }
 274         /* IRQ for timer 1 */
 275         irq = irq_of_parse_and_map(np, 0);
 276         if (irq <= 0) {
 277                 pr_err("Can't parse IRQ");
 278                 ret = -EINVAL;
 279                 goto out_unmap;
 280         }
 281
 282         /*
 283          * The Aspeed AST2400 moves bits around in the control register,
 284          * otherwise it works the same.
 285          */
 286         if (is_aspeed) {
 287                 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
 288                         TIMER_1_CR_ASPEED_INT;
 289                 /* Downward not available */
 290                 fttmr010->count_down = true;
 291         } else {
 292                 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
 293         }
 294
 295         /*
 296          * Reset the interrupt mask and status
 297          */
 298         writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
 299         writel(0, fttmr010->base + TIMER_INTR_STATE);
 300
 301         /*
 302          * Enable timer 1 count up, timer 2 count up, except on Aspeed,
 303          * where everything just counts down.
 304          */
 305         if (is_aspeed)
 306                 val = TIMER_2_CR_ASPEED_ENABLE;
 307         else {
 308                 val = TIMER_2_CR_ENABLE;
 309                 if (!fttmr010->count_down)
 310                         val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
 311         }
 312         writel(val, fttmr010->base + TIMER_CR);
 313
 314         /*
 315          * Setup free-running clocksource timer (interrupts
 316          * disabled.)
 317          */
 318         local_fttmr = fttmr010;
 319         writel(0, fttmr010->base + TIMER2_COUNT);
 320         writel(0, fttmr010->base + TIMER2_MATCH1);
 321         writel(0, fttmr010->base + TIMER2_MATCH2);
 322
 323         if (fttmr010->count_down) {
 324                 writel(~0, fttmr010->base + TIMER2_LOAD);
 325                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 326                                       "FTTMR010-TIMER2",
 327                                       fttmr010->tick_rate,
 328                                       300, 32, clocksource_mmio_readl_down);
 329                 sched_clock_register(fttmr010_read_sched_clock_down, 32,
 330                                      fttmr010->tick_rate);
 331         } else {
 332                 writel(0, fttmr010->base + TIMER2_LOAD);
 333                 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
 334                                       "FTTMR010-TIMER2",
 335                                       fttmr010->tick_rate,
 336                                       300, 32, clocksource_mmio_readl_up);
 337                 sched_clock_register(fttmr010_read_sched_clock_up, 32,
 338                                      fttmr010->tick_rate);
 339         }
 340
 341         /*
 342          * Setup clockevent timer (interrupt-driven) on timer 1.
 343          */
 344         writel(0, fttmr010->base + TIMER1_COUNT);
 345         writel(0, fttmr010->base + TIMER1_LOAD);
 346         writel(0, fttmr010->base + TIMER1_MATCH1);
 347         writel(0, fttmr010->base + TIMER1_MATCH2);
 348         ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
 349                           "FTTMR010-TIMER1", &fttmr010->clkevt);
 350         if (ret) {
 351                 pr_err("FTTMR010-TIMER1 no IRQ\n");
 352                 goto out_unmap;
 353         }
 354
 355         fttmr010->clkevt.name = "FTTMR010-TIMER1";
 356         /* Reasonably fast and accurate clock event */
 357         fttmr010->clkevt.rating = 300;
 358         fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
 359                 CLOCK_EVT_FEAT_ONESHOT;
 360         fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
 361         fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
 362         fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
 363         fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
 364         fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
 365         fttmr010->clkevt.cpumask = cpumask_of(0);
 366         fttmr010->clkevt.irq = irq;
 367         clockevents_config_and_register(&fttmr010->clkevt,
 368                                         fttmr010->tick_rate,
 369                                         1, 0xffffffff);
 370
 371 #ifdef CONFIG_ARM
 372         /* Also use this timer for delays */
 373         if (fttmr010->count_down)
 374                 fttmr010->delay_timer.read_current_timer =
 375                         fttmr010_read_current_timer_down;
 376         else
 377                 fttmr010->delay_timer.read_current_timer =
 378                         fttmr010_read_current_timer_up;
 379         fttmr010->delay_timer.freq = fttmr010->tick_rate;
 380         register_current_timer_delay(&fttmr010->delay_timer);
 381 #endif
 382
 383         return 0;
 384
 385 out_unmap:
 386         iounmap(fttmr010->base);
 387 out_free:
 388         kfree(fttmr010);
 389 out_disable_clock:
 390         clk_disable_unprepare(clk);
 391
 392         return ret;
 393 }
 394
 395 static __init int aspeed_timer_init(struct device_node *np)
 396 {
 397         return fttmr010_common_init(np, true);
 398 }
 399
 400 static __init int fttmr010_timer_init(struct device_node *np)
 401 {
 402         return fttmr010_common_init(np, false);
 403 }
 404
 405 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
 406 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
 407 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
 408 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
 409 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);