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media: omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode
[linux-2.6/btrfs-unstable.git] / drivers / media / platform / omap3isp / ispccp2.c
blob47210b102bcb0b803f5610db6c7a8407f97e24dc
1 /*
2 * ispccp2.c
3 *
4 * TI OMAP3 ISP - CCP2 module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2010 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/uaccess.h>
23 #include <linux/regulator/consumer.h>
24
25 #include "isp.h"
26 #include "ispreg.h"
27 #include "ispccp2.h"
28
29 /* Number of LCX channels */
30 #define CCP2_LCx_CHANS_NUM 3
31 /* Max/Min size for CCP2 video port */
32 #define ISPCCP2_DAT_START_MIN 0
33 #define ISPCCP2_DAT_START_MAX 4095
34 #define ISPCCP2_DAT_SIZE_MIN 0
35 #define ISPCCP2_DAT_SIZE_MAX 4095
36 #define ISPCCP2_VPCLK_FRACDIV 65536
37 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
38 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
39 /* Max/Min size for CCP2 memory channel */
40 #define ISPCCP2_LCM_HSIZE_COUNT_MIN 16
41 #define ISPCCP2_LCM_HSIZE_COUNT_MAX 8191
42 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
43 #define ISPCCP2_LCM_HSIZE_SKIP_MAX 8191
44 #define ISPCCP2_LCM_VSIZE_MIN 1
45 #define ISPCCP2_LCM_VSIZE_MAX 8191
46 #define ISPCCP2_LCM_HWORDS_MIN 1
47 #define ISPCCP2_LCM_HWORDS_MAX 4095
48 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X 5
49 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
50 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 2
51 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 2
52 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 3
53 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 3
54 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
55 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM 1
56
57 /* Set only the required bits */
58 #define BIT_SET(var, shift, mask, val) \
59 do { \
60 var = ((var) & ~((mask) << (shift))) \
61 | ((val) << (shift)); \
62 } while (0)
63
64 /*
65 * ccp2_print_status - Print current CCP2 module register values.
66 */
67 #define CCP2_PRINT_REGISTER(isp, name)\
68 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
69 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
70
71 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
72 {
73 struct isp_device *isp = to_isp_device(ccp2);
74
75 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
76
77 CCP2_PRINT_REGISTER(isp, SYSCONFIG);
78 CCP2_PRINT_REGISTER(isp, SYSSTATUS);
79 CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
80 CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
81 CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
82 CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
83 CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
84 CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
85 CCP2_PRINT_REGISTER(isp, CTRL);
86 CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
87 CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
88 CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
89 CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
90 CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
91 CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
92 CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
93 CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
94 CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
95 CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
96 CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
97 CCP2_PRINT_REGISTER(isp, LCM_CTRL);
98 CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
99 CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
100 CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
101 CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
102 CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
103 CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
104 CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
105
106 dev_dbg(isp->dev, "--------------------------------------------\n");
107 }
108
109 /*
110 * ccp2_reset - Reset the CCP2
111 * @ccp2: pointer to ISP CCP2 device
112 */
113 static void ccp2_reset(struct isp_ccp2_device *ccp2)
114 {
115 struct isp_device *isp = to_isp_device(ccp2);
116 int i = 0;
117
118 /* Reset the CSI1/CCP2B and wait for reset to complete */
119 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
120 ISPCCP2_SYSCONFIG_SOFT_RESET);
121 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
122 ISPCCP2_SYSSTATUS_RESET_DONE)) {
123 udelay(10);
124 if (i++ > 10) { /* try read 10 times */
125 dev_warn(isp->dev,
126 "omap3_isp: timeout waiting for ccp2 reset\n");
127 break;
128 }
129 }
130 }
131
132 /*
133 * ccp2_pwr_cfg - Configure the power mode settings
134 * @ccp2: pointer to ISP CCP2 device
135 */
136 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
137 {
138 struct isp_device *isp = to_isp_device(ccp2);
139
140 isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
141 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
142 ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
143 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
144 }
145
146 /*
147 * ccp2_if_enable - Enable CCP2 interface.
148 * @ccp2: pointer to ISP CCP2 device
149 * @enable: enable/disable flag
150 */
151 static int ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
152 {
153 struct isp_device *isp = to_isp_device(ccp2);
154 int ret;
155 int i;
156
157 if (enable && ccp2->vdds_csib) {
158 ret = regulator_enable(ccp2->vdds_csib);
159 if (ret < 0)
160 return ret;
161 }
162
163 /* Enable/Disable all the LCx channels */
164 for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
165 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
166 ISPCCP2_LCx_CTRL_CHAN_EN,
167 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
168
169 /* Enable/Disable ccp2 interface in ccp2 mode */
170 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
171 ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
172 enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
173
174 if (!enable && ccp2->vdds_csib)
175 regulator_disable(ccp2->vdds_csib);
176
177 return 0;
178 }
179
180 /*
181 * ccp2_mem_enable - Enable CCP2 memory interface.
182 * @ccp2: pointer to ISP CCP2 device
183 * @enable: enable/disable flag
184 */
185 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
186 {
187 struct isp_device *isp = to_isp_device(ccp2);
188
189 if (enable)
190 ccp2_if_enable(ccp2, 0);
191
192 /* Enable/Disable ccp2 interface in ccp2 mode */
193 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
194 ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
195
196 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
197 ISPCCP2_LCM_CTRL_CHAN_EN,
198 enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
199 }
200
201 /*
202 * ccp2_phyif_config - Initialize CCP2 phy interface config
203 * @ccp2: Pointer to ISP CCP2 device
204 * @buscfg: CCP2 platform data
205 *
206 * Configure the CCP2 physical interface module from platform data.
207 *
208 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
209 */
210 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
211 const struct isp_ccp2_cfg *buscfg)
212 {
213 struct isp_device *isp = to_isp_device(ccp2);
214 u32 val;
215
216 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
217 ISPCCP2_CTRL_MODE;
218 /* Data/strobe physical layer */
219 BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
220 buscfg->phy_layer);
221 BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT,
222 ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode);
223 BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
224 buscfg->strobe_clk_pol);
225 BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT,
226 ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol);
227 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
228
229 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
230 if (!(val & ISPCCP2_CTRL_MODE)) {
231 if (buscfg->ccp2_mode == ISP_CCP2_MODE_CCP2)
232 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
233 if (buscfg->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
234 /* Strobe mode requires CCP2 */
235 return -EIO;
236 }
237
238 return 0;
239 }
240
241 /*
242 * ccp2_vp_config - Initialize CCP2 video port interface.
243 * @ccp2: Pointer to ISP CCP2 device
244 * @vpclk_div: Video port divisor
245 *
246 * Configure the CCP2 video port with the given clock divisor. The valid divisor
247 * values depend on the ISP revision:
248 *
249 * - revision 1.0 and 2.0 1 to 4
250 * - revision 15.0 1 to 65536
251 *
252 * The exact divisor value used might differ from the requested value, as ISP
253 * revision 15.0 represent the divisor by 65536 divided by an integer.
254 */
255 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
256 unsigned int vpclk_div)
257 {
258 struct isp_device *isp = to_isp_device(ccp2);
259 u32 val;
260
261 /* ISPCCP2_CTRL Video port */
262 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
263 val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
264
265 if (isp->revision == ISP_REVISION_15_0) {
266 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
267 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
268 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
269 ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
270 } else {
271 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
272 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
273 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
274 }
275
276 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
277 }
278
279 /*
280 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
281 * @ccp2: Pointer to ISP CCP2 device
282 * @config: Pointer to ISP LCx config structure.
283 *
284 * This will analyze the parameters passed by the interface config
285 * and configure CSI1/CCP2 logical channel
286 *
287 */
288 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
289 struct isp_interface_lcx_config *config)
290 {
291 struct isp_device *isp = to_isp_device(ccp2);
292 u32 val, format;
293
294 switch (config->format) {
295 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
296 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
297 break;
298 case MEDIA_BUS_FMT_SGRBG10_1X10:
299 default:
300 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP; /* RAW10+VP */
301 break;
302 }
303 /* ISPCCP2_LCx_CTRL logical channel #0 */
304 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
305 | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
306
307 if (isp->revision == ISP_REVISION_15_0) {
308 /* CRC */
309 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
310 ISPCCP2_LCx_CTRL_CRC_MASK,
311 config->crc);
312 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
313 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
314 ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
315 } else {
316 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
317 ISPCCP2_LCx_CTRL_CRC_MASK,
318 config->crc);
319
320 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
321 ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
322 }
323 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
324
325 /* ISPCCP2_DAT_START for logical channel #0 */
326 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
327 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
328
329 /* ISPCCP2_DAT_SIZE for logical channel #0 */
330 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
331 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
332
333 /* Enable error IRQs for logical channel #0 */
334 val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
335 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
336 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
337 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
338 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
339 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
340
341 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
342 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
343 }
344
345 /*
346 * ccp2_if_configure - Configure ccp2 with data from sensor
347 * @ccp2: Pointer to ISP CCP2 device
348 *
349 * Return 0 on success or a negative error code
350 */
351 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
352 {
353 const struct isp_bus_cfg *buscfg;
354 struct v4l2_mbus_framefmt *format;
355 struct media_pad *pad;
356 struct v4l2_subdev *sensor;
357 u32 lines = 0;
358 int ret;
359
360 ccp2_pwr_cfg(ccp2);
361
362 pad = media_entity_remote_pad(&ccp2->pads[CCP2_PAD_SINK]);
363 sensor = media_entity_to_v4l2_subdev(pad->entity);
364 buscfg = sensor->host_priv;
365
366 ret = ccp2_phyif_config(ccp2, &buscfg->bus.ccp2);
367 if (ret < 0)
368 return ret;
369
370 ccp2_vp_config(ccp2, buscfg->bus.ccp2.vpclk_div + 1);
371
372 v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
373
374 format = &ccp2->formats[CCP2_PAD_SINK];
375
376 ccp2->if_cfg.data_start = lines;
377 ccp2->if_cfg.crc = buscfg->bus.ccp2.crc;
378 ccp2->if_cfg.format = format->code;
379 ccp2->if_cfg.data_size = format->height;
380
381 ccp2_lcx_config(ccp2, &ccp2->if_cfg);
382
383 return 0;
384 }
385
386 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
387 {
388 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
389 struct isp_device *isp = to_isp_device(ccp2);
390 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
391 unsigned long l3_ick = pipe->l3_ick;
392 struct v4l2_fract *timeperframe;
393 unsigned int vpclk_div = 2;
394 unsigned int value;
395 u64 bound;
396 u64 area;
397
398 /* Compute the minimum clock divisor, based on the pipeline maximum
399 * data rate. This is an absolute lower bound if we don't want SBL
400 * overflows, so round the value up.
401 */
402 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
403 vpclk_div);
404
405 /* Compute the maximum clock divisor, based on the requested frame rate.
406 * This is a soft lower bound to achieve a frame rate equal or higher
407 * than the requested value, so round the value down.
408 */
409 timeperframe = &pipe->max_timeperframe;
410
411 if (timeperframe->numerator) {
412 area = ofmt->width * ofmt->height;
413 bound = div_u64(area * timeperframe->denominator,
414 timeperframe->numerator);
415 value = min_t(u64, bound, l3_ick);
416 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
417 }
418
419 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
420 vpclk_div);
421
422 return vpclk_div;
423 }
424
425 /*
426 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
427 * @ccp2: Pointer to ISP CCP2 device
428 * @config: Pointer to ISP mem interface config structure
429 *
430 * This will analyze the parameters passed by the interface config
431 * structure, and configure the respective registers for proper
432 * CSI1/CCP2 memory input.
433 */
434 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
435 struct isp_interface_mem_config *config)
436 {
437 struct isp_device *isp = to_isp_device(ccp2);
438 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
439 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
440 unsigned int dpcm_decompress = 0;
441 u32 val, hwords;
442
443 if (sink_pixcode != source_pixcode &&
444 sink_pixcode == MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
445 dpcm_decompress = 1;
446
447 ccp2_pwr_cfg(ccp2);
448
449 /* Hsize, Skip */
450 isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
451 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
452 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
453
454 /* Vsize, no. of lines */
455 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
456 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
457
458 if (ccp2->video_in.bpl_padding == 0)
459 config->src_ofst = 0;
460 else
461 config->src_ofst = ccp2->video_in.bpl_value;
462
463 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
464 ISPCCP2_LCM_SRC_OFST);
465
466 /* Source and Destination formats */
467 val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
468 ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
469
470 if (dpcm_decompress) {
471 /* source format is RAW8 */
472 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
473 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
474
475 /* RAW8 + DPCM10 - simple predictor */
476 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
477
478 /* enable source DPCM decompression */
479 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
480 ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
481 } else {
482 /* source format is RAW10 */
483 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
484 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
485 }
486
487 /* Burst size to 32x64 */
488 val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
489 ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
490
491 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
492
493 /* Prefetch setup */
494 if (dpcm_decompress)
495 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
496 config->hsize_count) >> 3;
497 else
498 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
499 config->hsize_count) >> 2;
500
501 isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
502 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
503
504 /* Video port */
505 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
506 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
507 ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
508
509 /* Clear LCM interrupts */
510 isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
511 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
512 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
513
514 /* Enable LCM interrupts */
515 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
516 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
517 ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
518 }
519
520 /*
521 * ccp2_set_inaddr - Sets memory address of input frame.
522 * @ccp2: Pointer to ISP CCP2 device
523 * @addr: 32bit memory address aligned on 32byte boundary.
524 *
525 * Configures the memory address from which the input frame is to be read.
526 */
527 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
528 {
529 struct isp_device *isp = to_isp_device(ccp2);
530
531 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
532 }
533
534 /* -----------------------------------------------------------------------------
535 * Interrupt handling
536 */
537
538 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
539 {
540 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
541 struct isp_buffer *buffer;
542
543 buffer = omap3isp_video_buffer_next(&ccp2->video_in);
544 if (buffer != NULL)
545 ccp2_set_inaddr(ccp2, buffer->dma);
546
547 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
548
549 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
550 if (isp_pipeline_ready(pipe))
551 omap3isp_pipeline_set_stream(pipe,
552 ISP_PIPELINE_STREAM_SINGLESHOT);
553 }
554 }
555
556 /*
557 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
558 * @ccp2: Pointer to ISP CCP2 device
559 *
560 * This will handle the CCP2 interrupts
561 */
562 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
563 {
564 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
565 struct isp_device *isp = to_isp_device(ccp2);
566 static const u32 ISPCCP2_LC01_ERROR =
567 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
568 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
569 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
570 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
571 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
572 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
573 u32 lcx_irqstatus, lcm_irqstatus;
574
575 /* First clear the interrupts */
576 lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
577 ISPCCP2_LC01_IRQSTATUS);
578 isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
579 ISPCCP2_LC01_IRQSTATUS);
580
581 lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
582 ISPCCP2_LCM_IRQSTATUS);
583 isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
584 ISPCCP2_LCM_IRQSTATUS);
585 /* Errors */
586 if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
587 pipe->error = true;
588 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
589 return;
590 }
591
592 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
593 pipe->error = true;
594 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
595 }
596
597 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
598 return;
599
600 /* Handle queued buffers on frame end interrupts */
601 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
602 ccp2_isr_buffer(ccp2);
603 }
604
605 /* -----------------------------------------------------------------------------
606 * V4L2 subdev operations
607 */
608
609 static const unsigned int ccp2_fmts[] = {
610 MEDIA_BUS_FMT_SGRBG10_1X10,
611 MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
612 };
613
614 /*
615 * __ccp2_get_format - helper function for getting ccp2 format
616 * @ccp2 : Pointer to ISP CCP2 device
617 * @cfg: V4L2 subdev pad configuration
618 * @pad : pad number
619 * @which : wanted subdev format
620 * return format structure or NULL on error
621 */
622 static struct v4l2_mbus_framefmt *
623 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_pad_config *cfg,
624 unsigned int pad, enum v4l2_subdev_format_whence which)
625 {
626 if (which == V4L2_SUBDEV_FORMAT_TRY)
627 return v4l2_subdev_get_try_format(&ccp2->subdev, cfg, pad);
628 else
629 return &ccp2->formats[pad];
630 }
631
632 /*
633 * ccp2_try_format - Handle try format by pad subdev method
634 * @ccp2 : Pointer to ISP CCP2 device
635 * @cfg: V4L2 subdev pad configuration
636 * @pad : pad num
637 * @fmt : pointer to v4l2 mbus format structure
638 * @which : wanted subdev format
639 */
640 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
641 struct v4l2_subdev_pad_config *cfg, unsigned int pad,
642 struct v4l2_mbus_framefmt *fmt,
643 enum v4l2_subdev_format_whence which)
644 {
645 struct v4l2_mbus_framefmt *format;
646
647 switch (pad) {
648 case CCP2_PAD_SINK:
649 if (fmt->code != MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
650 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
651
652 if (ccp2->input == CCP2_INPUT_SENSOR) {
653 fmt->width = clamp_t(u32, fmt->width,
654 ISPCCP2_DAT_START_MIN,
655 ISPCCP2_DAT_START_MAX);
656 fmt->height = clamp_t(u32, fmt->height,
657 ISPCCP2_DAT_SIZE_MIN,
658 ISPCCP2_DAT_SIZE_MAX);
659 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
660 fmt->width = clamp_t(u32, fmt->width,
661 ISPCCP2_LCM_HSIZE_COUNT_MIN,
662 ISPCCP2_LCM_HSIZE_COUNT_MAX);
663 fmt->height = clamp_t(u32, fmt->height,
664 ISPCCP2_LCM_VSIZE_MIN,
665 ISPCCP2_LCM_VSIZE_MAX);
666 }
667 break;
668
669 case CCP2_PAD_SOURCE:
670 /* Source format - copy sink format and change pixel code
671 * to SGRBG10_1X10 as we don't support CCP2 write to memory.
672 * When CCP2 write to memory feature will be added this
673 * should be changed properly.
674 */
675 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK, which);
676 memcpy(fmt, format, sizeof(*fmt));
677 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
678 break;
679 }
680
681 fmt->field = V4L2_FIELD_NONE;
682 fmt->colorspace = V4L2_COLORSPACE_SRGB;
683 }
684
685 /*
686 * ccp2_enum_mbus_code - Handle pixel format enumeration
687 * @sd : pointer to v4l2 subdev structure
688 * @cfg: V4L2 subdev pad configuration
689 * @code : pointer to v4l2_subdev_mbus_code_enum structure
690 * return -EINVAL or zero on success
691 */
692 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
693 struct v4l2_subdev_pad_config *cfg,
694 struct v4l2_subdev_mbus_code_enum *code)
695 {
696 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
697 struct v4l2_mbus_framefmt *format;
698
699 if (code->pad == CCP2_PAD_SINK) {
700 if (code->index >= ARRAY_SIZE(ccp2_fmts))
701 return -EINVAL;
702
703 code->code = ccp2_fmts[code->index];
704 } else {
705 if (code->index != 0)
706 return -EINVAL;
707
708 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK,
709 code->which);
710 code->code = format->code;
711 }
712
713 return 0;
714 }
715
716 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
717 struct v4l2_subdev_pad_config *cfg,
718 struct v4l2_subdev_frame_size_enum *fse)
719 {
720 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
721 struct v4l2_mbus_framefmt format;
722
723 if (fse->index != 0)
724 return -EINVAL;
725
726 format.code = fse->code;
727 format.width = 1;
728 format.height = 1;
729 ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
730 fse->min_width = format.width;
731 fse->min_height = format.height;
732
733 if (format.code != fse->code)
734 return -EINVAL;
735
736 format.code = fse->code;
737 format.width = -1;
738 format.height = -1;
739 ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
740 fse->max_width = format.width;
741 fse->max_height = format.height;
742
743 return 0;
744 }
745
746 /*
747 * ccp2_get_format - Handle get format by pads subdev method
748 * @sd : pointer to v4l2 subdev structure
749 * @cfg: V4L2 subdev pad configuration
750 * @fmt : pointer to v4l2 subdev format structure
751 * return -EINVAL or zero on success
752 */
753 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
754 struct v4l2_subdev_format *fmt)
755 {
756 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
757 struct v4l2_mbus_framefmt *format;
758
759 format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
760 if (format == NULL)
761 return -EINVAL;
762
763 fmt->format = *format;
764 return 0;
765 }
766
767 /*
768 * ccp2_set_format - Handle set format by pads subdev method
769 * @sd : pointer to v4l2 subdev structure
770 * @cfg: V4L2 subdev pad configuration
771 * @fmt : pointer to v4l2 subdev format structure
772 * returns zero
773 */
774 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
775 struct v4l2_subdev_format *fmt)
776 {
777 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
778 struct v4l2_mbus_framefmt *format;
779
780 format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
781 if (format == NULL)
782 return -EINVAL;
783
784 ccp2_try_format(ccp2, cfg, fmt->pad, &fmt->format, fmt->which);
785 *format = fmt->format;
786
787 /* Propagate the format from sink to source */
788 if (fmt->pad == CCP2_PAD_SINK) {
789 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SOURCE,
790 fmt->which);
791 *format = fmt->format;
792 ccp2_try_format(ccp2, cfg, CCP2_PAD_SOURCE, format, fmt->which);
793 }
794
795 return 0;
796 }
797
798 /*
799 * ccp2_init_formats - Initialize formats on all pads
800 * @sd: ISP CCP2 V4L2 subdevice
801 * @fh: V4L2 subdev file handle
802 *
803 * Initialize all pad formats with default values. If fh is not NULL, try
804 * formats are initialized on the file handle. Otherwise active formats are
805 * initialized on the device.
806 */
807 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
808 {
809 struct v4l2_subdev_format format;
810
811 memset(&format, 0, sizeof(format));
812 format.pad = CCP2_PAD_SINK;
813 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
814 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
815 format.format.width = 4096;
816 format.format.height = 4096;
817 ccp2_set_format(sd, fh ? fh->pad : NULL, &format);
818
819 return 0;
820 }
821
822 /*
823 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
824 * @sd : pointer to v4l2 subdev structure
825 * @enable: 1 == Enable, 0 == Disable
826 * return zero
827 */
828 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
829 {
830 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
831 struct isp_device *isp = to_isp_device(ccp2);
832 struct device *dev = to_device(ccp2);
833 int ret;
834
835 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
836 if (enable == ISP_PIPELINE_STREAM_STOPPED)
837 return 0;
838 atomic_set(&ccp2->stopping, 0);
839 }
840
841 switch (enable) {
842 case ISP_PIPELINE_STREAM_CONTINUOUS:
843 if (ccp2->phy) {
844 ret = omap3isp_csiphy_acquire(ccp2->phy);
845 if (ret < 0)
846 return ret;
847 }
848
849 ccp2_if_configure(ccp2);
850 ccp2_print_status(ccp2);
851
852 /* Enable CSI1/CCP2 interface */
853 ret = ccp2_if_enable(ccp2, 1);
854 if (ret < 0) {
855 if (ccp2->phy)
856 omap3isp_csiphy_release(ccp2->phy);
857 return ret;
858 }
859 break;
860
861 case ISP_PIPELINE_STREAM_SINGLESHOT:
862 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
863 struct v4l2_mbus_framefmt *format;
864
865 format = &ccp2->formats[CCP2_PAD_SINK];
866
867 ccp2->mem_cfg.hsize_count = format->width;
868 ccp2->mem_cfg.vsize_count = format->height;
869 ccp2->mem_cfg.src_ofst = 0;
870
871 ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
872 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
873 ccp2_print_status(ccp2);
874 }
875 ccp2_mem_enable(ccp2, 1);
876 break;
877
878 case ISP_PIPELINE_STREAM_STOPPED:
879 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
880 &ccp2->stopping))
881 dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
882 if (ccp2->input == CCP2_INPUT_MEMORY) {
883 ccp2_mem_enable(ccp2, 0);
884 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
885 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
886 /* Disable CSI1/CCP2 interface */
887 ccp2_if_enable(ccp2, 0);
888 if (ccp2->phy)
889 omap3isp_csiphy_release(ccp2->phy);
890 }
891 break;
892 }
893
894 ccp2->state = enable;
895 return 0;
896 }
897
898 /* subdev video operations */
899 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
900 .s_stream = ccp2_s_stream,
901 };
902
903 /* subdev pad operations */
904 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
905 .enum_mbus_code = ccp2_enum_mbus_code,
906 .enum_frame_size = ccp2_enum_frame_size,
907 .get_fmt = ccp2_get_format,
908 .set_fmt = ccp2_set_format,
909 };
910
911 /* subdev operations */
912 static const struct v4l2_subdev_ops ccp2_sd_ops = {
913 .video = &ccp2_sd_video_ops,
914 .pad = &ccp2_sd_pad_ops,
915 };
916
917 /* subdev internal operations */
918 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
919 .open = ccp2_init_formats,
920 };
921
922 /* --------------------------------------------------------------------------
923 * ISP ccp2 video device node
924 */
925
926 /*
927 * ccp2_video_queue - Queue video buffer.
928 * @video : Pointer to isp video structure
929 * @buffer: Pointer to isp_buffer structure
930 * return -EIO or zero on success
931 */
932 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
933 {
934 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
935
936 ccp2_set_inaddr(ccp2, buffer->dma);
937 return 0;
938 }
939
940 static const struct isp_video_operations ccp2_video_ops = {
941 .queue = ccp2_video_queue,
942 };
943
944 /* -----------------------------------------------------------------------------
945 * Media entity operations
946 */
947
948 /*
949 * ccp2_link_setup - Setup ccp2 connections.
950 * @entity : Pointer to media entity structure
951 * @local : Pointer to local pad array
952 * @remote : Pointer to remote pad array
953 * @flags : Link flags
954 * return -EINVAL on error or zero on success
955 */
956 static int ccp2_link_setup(struct media_entity *entity,
957 const struct media_pad *local,
958 const struct media_pad *remote, u32 flags)
959 {
960 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
961 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
962 unsigned int index = local->index;
963
964 /* FIXME: this is actually a hack! */
965 if (is_media_entity_v4l2_subdev(remote->entity))
966 index |= 2 << 16;
967
968 switch (index) {
969 case CCP2_PAD_SINK:
970 /* read from memory */
971 if (flags & MEDIA_LNK_FL_ENABLED) {
972 if (ccp2->input == CCP2_INPUT_SENSOR)
973 return -EBUSY;
974 ccp2->input = CCP2_INPUT_MEMORY;
975 } else {
976 if (ccp2->input == CCP2_INPUT_MEMORY)
977 ccp2->input = CCP2_INPUT_NONE;
978 }
979 break;
980
981 case CCP2_PAD_SINK | 2 << 16:
982 /* read from sensor/phy */
983 if (flags & MEDIA_LNK_FL_ENABLED) {
984 if (ccp2->input == CCP2_INPUT_MEMORY)
985 return -EBUSY;
986 ccp2->input = CCP2_INPUT_SENSOR;
987 } else {
988 if (ccp2->input == CCP2_INPUT_SENSOR)
989 ccp2->input = CCP2_INPUT_NONE;
990 } break;
991
992 case CCP2_PAD_SOURCE | 2 << 16:
993 /* write to video port/ccdc */
994 if (flags & MEDIA_LNK_FL_ENABLED)
995 ccp2->output = CCP2_OUTPUT_CCDC;
996 else
997 ccp2->output = CCP2_OUTPUT_NONE;
998 break;
999
1000 default:
1001 return -EINVAL;
1002 }
1003
1004 return 0;
1005 }
1006
1007 /* media operations */
1008 static const struct media_entity_operations ccp2_media_ops = {
1009 .link_setup = ccp2_link_setup,
1010 .link_validate = v4l2_subdev_link_validate,
1011 };
1012
1013 /*
1014 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1015 * @ccp2: Pointer to ISP CCP2 device
1016 */
1017 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1018 {
1019 v4l2_device_unregister_subdev(&ccp2->subdev);
1020 omap3isp_video_unregister(&ccp2->video_in);
1021 }
1022
1023 /*
1024 * omap3isp_ccp2_register_entities - Register the subdev media entity
1025 * @ccp2: Pointer to ISP CCP2 device
1026 * @vdev: Pointer to v4l device
1027 * return negative error code or zero on success
1028 */
1029
1030 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1031 struct v4l2_device *vdev)
1032 {
1033 int ret;
1034
1035 /* Register the subdev and video nodes. */
1036 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1037 if (ret < 0)
1038 goto error;
1039
1040 ret = omap3isp_video_register(&ccp2->video_in, vdev);
1041 if (ret < 0)
1042 goto error;
1043
1044 return 0;
1045
1046 error:
1047 omap3isp_ccp2_unregister_entities(ccp2);
1048 return ret;
1049 }
1050
1051 /* -----------------------------------------------------------------------------
1052 * ISP ccp2 initialisation and cleanup
1053 */
1054
1055 /*
1056 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1057 * @ccp2: Pointer to ISP CCP2 device
1058 * return negative error code or zero on success
1059 */
1060 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1061 {
1062 struct v4l2_subdev *sd = &ccp2->subdev;
1063 struct media_pad *pads = ccp2->pads;
1064 struct media_entity *me = &sd->entity;
1065 int ret;
1066
1067 ccp2->input = CCP2_INPUT_NONE;
1068 ccp2->output = CCP2_OUTPUT_NONE;
1069
1070 v4l2_subdev_init(sd, &ccp2_sd_ops);
1071 sd->internal_ops = &ccp2_sd_internal_ops;
1072 strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1073 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1074 v4l2_set_subdevdata(sd, ccp2);
1075 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1076
1077 pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1078 | MEDIA_PAD_FL_MUST_CONNECT;
1079 pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1080
1081 me->ops = &ccp2_media_ops;
1082 ret = media_entity_pads_init(me, CCP2_PADS_NUM, pads);
1083 if (ret < 0)
1084 return ret;
1085
1086 ccp2_init_formats(sd, NULL);
1087
1088 /*
1089 * The CCP2 has weird line alignment requirements, possibly caused by
1090 * DPCM8 decompression. Line length for data read from memory must be a
1091 * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1092 * is present at end of lines). Additionally, if padding is used, the
1093 * padded line length must be a multiple of 32 bytes. To simplify the
1094 * implementation we use a fixed 32 bytes alignment regardless of the
1095 * input format and width. If strict 128 bits alignment support is
1096 * required ispvideo will need to be made aware of this special dual
1097 * alignment requirements.
1098 */
1099 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1100 ccp2->video_in.bpl_alignment = 32;
1101 ccp2->video_in.bpl_max = 0xffffffe0;
1102 ccp2->video_in.isp = to_isp_device(ccp2);
1103 ccp2->video_in.ops = &ccp2_video_ops;
1104 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1105
1106 ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1107 if (ret < 0)
1108 goto error;
1109
1110 return 0;
1111
1112 error:
1113 media_entity_cleanup(&ccp2->subdev.entity);
1114 return ret;
1115 }
1116
1117 /*
1118 * omap3isp_ccp2_init - CCP2 initialization.
1119 * @isp : Pointer to ISP device
1120 * return negative error code or zero on success
1121 */
1122 int omap3isp_ccp2_init(struct isp_device *isp)
1123 {
1124 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1125 int ret;
1126
1127 init_waitqueue_head(&ccp2->wait);
1128
1129 /*
1130 * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1131 * complex, which is powered by vdds_csib power rail. Hence the
1132 * request for the regulator.
1133 *
1134 * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1135 * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1136 * configured.
1137 *
1138 * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1139 */
1140 if (isp->revision == ISP_REVISION_2_0) {
1141 ccp2->vdds_csib = devm_regulator_get(isp->dev, "vdds_csib");
1142 if (IS_ERR(ccp2->vdds_csib)) {
1143 if (PTR_ERR(ccp2->vdds_csib) == -EPROBE_DEFER) {
1144 dev_dbg(isp->dev,
1145 "Can't get regulator vdds_csib, deferring probing\n");
1146 return -EPROBE_DEFER;
1147 }
1148 dev_dbg(isp->dev,
1149 "Could not get regulator vdds_csib\n");
1150 ccp2->vdds_csib = NULL;
1151 }
1152 ccp2->phy = &isp->isp_csiphy2;
1153 } else if (isp->revision == ISP_REVISION_15_0) {
1154 ccp2->phy = &isp->isp_csiphy1;
1155 }
1156
1157 ret = ccp2_init_entities(ccp2);
1158 if (ret < 0)
1159 return ret;
1160
1161 ccp2_reset(ccp2);
1162 return 0;
1163 }
1164
1165 /*
1166 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1167 * @isp : Pointer to ISP device
1168 */
1169 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1170 {
1171 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1172
1173 omap3isp_video_cleanup(&ccp2->video_in);
1174 media_entity_cleanup(&ccp2->subdev.entity);
1175 }
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