2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/skbuff.h>
18 #include <linux/inetdevice.h>
19 #include <linux/mbus.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpumask.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_mdio.h>
26 #include <linux/of_net.h>
27 #include <linux/of_address.h>
28 #include <linux/phy.h>
29 #include <linux/clk.h>
30 #include <linux/hrtimer.h>
31 #include <linux/ktime.h>
32 #include <uapi/linux/ppp_defs.h>
36 /* RX Fifo Registers */
37 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
38 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
39 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
40 #define MVPP2_RX_FIFO_INIT_REG 0x64
42 /* RX DMA Top Registers */
43 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
44 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
45 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
46 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
47 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
48 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
49 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
50 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
51 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
52 #define MVPP2_RXQ_POOL_SHORT_MASK 0x700000
53 #define MVPP2_RXQ_POOL_LONG_OFFS 24
54 #define MVPP2_RXQ_POOL_LONG_MASK 0x7000000
55 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
56 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
57 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
59 /* Parser Registers */
60 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
61 #define MVPP2_PRS_PORT_LU_MAX 0xf
62 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
63 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
64 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
65 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
66 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
67 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
68 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
69 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
70 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
71 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
72 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
73 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
74 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
75 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
76 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
78 /* Classifier Registers */
79 #define MVPP2_CLS_MODE_REG 0x1800
80 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
81 #define MVPP2_CLS_PORT_WAY_REG 0x1810
82 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
83 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
84 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
85 #define MVPP2_CLS_LKP_TBL_REG 0x1818
86 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
87 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
88 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
89 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
90 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
91 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
92 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
93 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
94 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
95 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
96 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
97 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
99 /* Descriptor Manager Top Registers */
100 #define MVPP2_RXQ_NUM_REG 0x2040
101 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
102 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
103 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
104 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
105 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
106 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
107 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
108 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
109 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
110 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
111 #define MVPP2_RXQ_THRESH_REG 0x204c
112 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
113 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
114 #define MVPP2_RXQ_INDEX_REG 0x2050
115 #define MVPP2_TXQ_NUM_REG 0x2080
116 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
117 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
118 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
119 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
120 #define MVPP2_TXQ_THRESH_REG 0x2094
121 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
122 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
123 #define MVPP2_TXQ_INDEX_REG 0x2098
124 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
125 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
126 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
127 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
128 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
129 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
130 #define MVPP2_TXQ_PENDING_REG 0x20a0
131 #define MVPP2_TXQ_PENDING_MASK 0x3fff
132 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
133 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
134 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
135 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
136 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
137 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
138 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
139 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
140 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
141 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
142 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
143 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
144 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
145 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
146 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
147 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
149 /* MBUS bridge registers */
150 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
151 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
152 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
153 #define MVPP2_BASE_ADDR_ENABLE 0x4060
155 /* Interrupt Cause and Mask registers */
156 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
157 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0
158 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
159 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
160 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
161 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
162 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
163 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
164 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
165 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
166 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
167 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
168 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
169 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
170 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
171 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
172 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
173 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
174 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
175 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
176 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
178 /* Buffer Manager registers */
179 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
180 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
181 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
182 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
183 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
184 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
185 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
186 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
187 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
188 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
189 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
190 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
191 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
192 #define MVPP2_BM_START_MASK BIT(0)
193 #define MVPP2_BM_STOP_MASK BIT(1)
194 #define MVPP2_BM_STATE_MASK BIT(4)
195 #define MVPP2_BM_LOW_THRESH_OFFS 8
196 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
197 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
198 MVPP2_BM_LOW_THRESH_OFFS)
199 #define MVPP2_BM_HIGH_THRESH_OFFS 16
200 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
201 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
202 MVPP2_BM_HIGH_THRESH_OFFS)
203 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
204 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
205 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
206 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
207 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
208 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
209 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
210 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
211 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
212 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
213 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
214 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
215 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
216 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
217 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
218 #define MVPP2_BM_MC_RLS_REG 0x64c4
219 #define MVPP2_BM_MC_ID_MASK 0xfff
220 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
222 /* TX Scheduler registers */
223 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
224 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
225 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
226 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
227 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
228 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
229 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
230 #define MVPP2_TXP_MTU_MAX 0x7FFFF
231 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
232 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
233 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
234 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
235 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
236 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
237 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
238 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
239 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
240 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
241 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
242 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
243 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
244 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
246 /* TX general registers */
247 #define MVPP2_TX_SNOOP_REG 0x8800
248 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
249 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
252 #define MVPP2_SRC_ADDR_MIDDLE 0x24
253 #define MVPP2_SRC_ADDR_HIGH 0x28
254 #define MVPP2_PHY_AN_CFG0_REG 0x34
255 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
256 #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \
257 0x400 + (port) * 0x400)
258 #define MVPP2_MIB_LATE_COLLISION 0x7c
259 #define MVPP2_ISR_SUM_MASK_REG 0x220c
260 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
261 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
263 /* Per-port registers */
264 #define MVPP2_GMAC_CTRL_0_REG 0x0
265 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
266 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
267 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
268 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
269 #define MVPP2_GMAC_CTRL_1_REG 0x4
270 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
271 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
272 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
273 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
274 #define MVPP2_GMAC_SA_LOW_OFFS 7
275 #define MVPP2_GMAC_CTRL_2_REG 0x8
276 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
277 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
278 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
279 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
280 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
281 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
282 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
283 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
284 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
285 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
286 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
287 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
288 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
289 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
290 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
291 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
292 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
293 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
295 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
297 /* Descriptor ring Macros */
298 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
299 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
301 /* Various constants */
304 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
305 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
306 #define MVPP2_RX_COAL_PKTS 32
307 #define MVPP2_RX_COAL_USEC 100
309 /* The two bytes Marvell header. Either contains a special value used
310 * by Marvell switches when a specific hardware mode is enabled (not
311 * supported by this driver) or is filled automatically by zeroes on
312 * the RX side. Those two bytes being at the front of the Ethernet
313 * header, they allow to have the IP header aligned on a 4 bytes
314 * boundary automatically: the hardware skips those two bytes on its
317 #define MVPP2_MH_SIZE 2
318 #define MVPP2_ETH_TYPE_LEN 2
319 #define MVPP2_PPPOE_HDR_SIZE 8
320 #define MVPP2_VLAN_TAG_LEN 4
322 /* Lbtd 802.3 type */
323 #define MVPP2_IP_LBDT_TYPE 0xfffa
325 #define MVPP2_TX_CSUM_MAX_SIZE 9800
327 /* Timeout constants */
328 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
329 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
331 #define MVPP2_TX_MTU_MAX 0x7ffff
333 /* Maximum number of T-CONTs of PON port */
334 #define MVPP2_MAX_TCONT 16
336 /* Maximum number of supported ports */
337 #define MVPP2_MAX_PORTS 4
339 /* Maximum number of TXQs used by single port */
340 #define MVPP2_MAX_TXQ 8
342 /* Maximum number of RXQs used by single port */
343 #define MVPP2_MAX_RXQ 8
345 /* Dfault number of RXQs in use */
346 #define MVPP2_DEFAULT_RXQ 4
348 /* Total number of RXQs available to all ports */
349 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
351 /* Max number of Rx descriptors */
352 #define MVPP2_MAX_RXD 128
354 /* Max number of Tx descriptors */
355 #define MVPP2_MAX_TXD 1024
357 /* Amount of Tx descriptors that can be reserved at once by CPU */
358 #define MVPP2_CPU_DESC_CHUNK 64
360 /* Max number of Tx descriptors in each aggregated queue */
361 #define MVPP2_AGGR_TXQ_SIZE 256
363 /* Descriptor aligned size */
364 #define MVPP2_DESC_ALIGNED_SIZE 32
366 /* Descriptor alignment mask */
367 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
369 /* RX FIFO constants */
370 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
371 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
372 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
374 /* RX buffer constants */
375 #define MVPP2_SKB_SHINFO_SIZE \
376 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
378 #define MVPP2_RX_PKT_SIZE(mtu) \
379 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
380 ETH_HLEN + ETH_FCS_LEN, cache_line_size())
382 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
383 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
384 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
385 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
387 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
389 /* IPv6 max L3 address size */
390 #define MVPP2_MAX_L3_ADDR_SIZE 16
393 #define MVPP2_F_LOOPBACK BIT(0)
395 /* Marvell tag types */
396 enum mvpp2_tag_type
{
397 MVPP2_TAG_TYPE_NONE
= 0,
398 MVPP2_TAG_TYPE_MH
= 1,
399 MVPP2_TAG_TYPE_DSA
= 2,
400 MVPP2_TAG_TYPE_EDSA
= 3,
401 MVPP2_TAG_TYPE_VLAN
= 4,
402 MVPP2_TAG_TYPE_LAST
= 5
405 /* Parser constants */
406 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
407 #define MVPP2_PRS_TCAM_WORDS 6
408 #define MVPP2_PRS_SRAM_WORDS 4
409 #define MVPP2_PRS_FLOW_ID_SIZE 64
410 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
411 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
412 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
413 #define MVPP2_PRS_IPV4_HEAD 0x40
414 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
415 #define MVPP2_PRS_IPV4_MC 0xe0
416 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
417 #define MVPP2_PRS_IPV4_BC_MASK 0xff
418 #define MVPP2_PRS_IPV4_IHL 0x5
419 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
420 #define MVPP2_PRS_IPV6_MC 0xff
421 #define MVPP2_PRS_IPV6_MC_MASK 0xff
422 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
423 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
424 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
425 #define MVPP2_PRS_DBL_VLANS_MAX 100
428 * - lookup ID - 4 bits
430 * - additional information - 1 byte
431 * - header data - 8 bytes
432 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
434 #define MVPP2_PRS_AI_BITS 8
435 #define MVPP2_PRS_PORT_MASK 0xff
436 #define MVPP2_PRS_LU_MASK 0xf
437 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
438 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
439 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
440 (((offs) * 2) - ((offs) % 2) + 2)
441 #define MVPP2_PRS_TCAM_AI_BYTE 16
442 #define MVPP2_PRS_TCAM_PORT_BYTE 17
443 #define MVPP2_PRS_TCAM_LU_BYTE 20
444 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
445 #define MVPP2_PRS_TCAM_INV_WORD 5
446 /* Tcam entries ID */
447 #define MVPP2_PE_DROP_ALL 0
448 #define MVPP2_PE_FIRST_FREE_TID 1
449 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
450 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
451 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
452 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
453 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
454 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
455 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
456 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
457 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
458 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
459 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
460 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
461 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
462 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
463 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
464 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
465 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
466 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
467 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
468 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
469 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
470 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
471 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
472 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
473 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
476 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
478 #define MVPP2_PRS_SRAM_RI_OFFS 0
479 #define MVPP2_PRS_SRAM_RI_WORD 0
480 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
481 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
482 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
483 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
484 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
485 #define MVPP2_PRS_SRAM_UDF_OFFS 73
486 #define MVPP2_PRS_SRAM_UDF_BITS 8
487 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
488 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
489 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
490 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
491 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
492 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
493 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
494 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
495 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
496 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
497 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
498 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
499 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
500 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
501 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
502 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
503 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
504 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
505 #define MVPP2_PRS_SRAM_AI_OFFS 90
506 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
507 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
508 #define MVPP2_PRS_SRAM_AI_MASK 0xff
509 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
510 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
511 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
512 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
514 /* Sram result info bits assignment */
515 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
516 #define MVPP2_PRS_RI_DSA_MASK 0x2
517 #define MVPP2_PRS_RI_VLAN_MASK 0xc
518 #define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3))
519 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
520 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
521 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
522 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
523 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
524 #define MVPP2_PRS_RI_L2_CAST_MASK 0x600
525 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10))
526 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
527 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
528 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
529 #define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000
530 #define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14))
531 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
532 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
533 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
534 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
535 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
536 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
537 #define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000
538 #define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16))
539 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
540 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
541 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
542 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
543 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
544 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
545 #define MVPP2_PRS_RI_L4_TCP BIT(22)
546 #define MVPP2_PRS_RI_L4_UDP BIT(23)
547 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
548 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
549 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
550 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
552 /* Sram additional info bits assignment */
553 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
554 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
555 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
556 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
557 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
558 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
559 #define MVPP2_PRS_SINGLE_VLAN_AI 0
560 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
563 #define MVPP2_PRS_TAGGED true
564 #define MVPP2_PRS_UNTAGGED false
565 #define MVPP2_PRS_EDSA true
566 #define MVPP2_PRS_DSA false
568 /* MAC entries, shadow udf */
570 MVPP2_PRS_UDF_MAC_DEF
,
571 MVPP2_PRS_UDF_MAC_RANGE
,
572 MVPP2_PRS_UDF_L2_DEF
,
573 MVPP2_PRS_UDF_L2_DEF_COPY
,
574 MVPP2_PRS_UDF_L2_USER
,
578 enum mvpp2_prs_lookup
{
592 enum mvpp2_prs_l3_cast
{
593 MVPP2_PRS_L3_UNI_CAST
,
594 MVPP2_PRS_L3_MULTI_CAST
,
595 MVPP2_PRS_L3_BROAD_CAST
598 /* Classifier constants */
599 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
600 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
601 #define MVPP2_CLS_LKP_TBL_SIZE 64
604 #define MVPP2_BM_POOLS_NUM 8
605 #define MVPP2_BM_LONG_BUF_NUM 1024
606 #define MVPP2_BM_SHORT_BUF_NUM 2048
607 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
608 #define MVPP2_BM_POOL_PTR_ALIGN 128
609 #define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port)
610 #define MVPP2_BM_SWF_SHORT_POOL 3
612 /* BM cookie (32 bits) definition */
613 #define MVPP2_BM_COOKIE_POOL_OFFS 8
614 #define MVPP2_BM_COOKIE_CPU_OFFS 24
616 /* BM short pool packet size
617 * These value assure that for SWF the total number
618 * of bytes allocated for each buffer will be 512
620 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
630 /* Shared Packet Processor resources */
632 /* Shared registers' base addresses */
634 void __iomem
*lms_base
;
640 /* List of pointers to port structures */
641 struct mvpp2_port
**port_list
;
643 /* Aggregated TXQs */
644 struct mvpp2_tx_queue
*aggr_txqs
;
647 struct mvpp2_bm_pool
*bm_pools
;
649 /* PRS shadow table */
650 struct mvpp2_prs_shadow
*prs_shadow
;
651 /* PRS auxiliary table for double vlan entries control */
652 bool *prs_double_vlans
;
658 struct mvpp2_pcpu_stats
{
659 struct u64_stats_sync syncp
;
666 /* Per-CPU port control */
667 struct mvpp2_port_pcpu
{
668 struct hrtimer tx_done_timer
;
669 bool timer_scheduled
;
670 /* Tasklet for egress finalization */
671 struct tasklet_struct tx_done_tasklet
;
681 /* Per-port registers' base address */
684 struct mvpp2_rx_queue
**rxqs
;
685 struct mvpp2_tx_queue
**txqs
;
686 struct net_device
*dev
;
690 u32 pending_cause_rx
;
691 struct napi_struct napi
;
693 /* Per-CPU port control */
694 struct mvpp2_port_pcpu __percpu
*pcpu
;
701 struct mvpp2_pcpu_stats __percpu
*stats
;
703 phy_interface_t phy_interface
;
704 struct device_node
*phy_node
;
709 struct mvpp2_bm_pool
*pool_long
;
710 struct mvpp2_bm_pool
*pool_short
;
712 /* Index of first port's physical RXQ */
716 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
717 * layout of the transmit and reception DMA descriptors, and their
718 * layout is therefore defined by the hardware design
721 #define MVPP2_TXD_L3_OFF_SHIFT 0
722 #define MVPP2_TXD_IP_HLEN_SHIFT 8
723 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
724 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
725 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
726 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
727 #define MVPP2_TXD_L4_UDP BIT(24)
728 #define MVPP2_TXD_L3_IP6 BIT(26)
729 #define MVPP2_TXD_L_DESC BIT(28)
730 #define MVPP2_TXD_F_DESC BIT(29)
732 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
733 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
734 #define MVPP2_RXD_ERR_CRC 0x0
735 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
736 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
737 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
738 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
739 #define MVPP2_RXD_HWF_SYNC BIT(21)
740 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
741 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
742 #define MVPP2_RXD_L4_TCP BIT(25)
743 #define MVPP2_RXD_L4_UDP BIT(26)
744 #define MVPP2_RXD_L3_IP4 BIT(28)
745 #define MVPP2_RXD_L3_IP6 BIT(30)
746 #define MVPP2_RXD_BUF_HDR BIT(31)
748 struct mvpp2_tx_desc
{
749 u32 command
; /* Options used by HW for packet transmitting.*/
750 u8 packet_offset
; /* the offset from the buffer beginning */
751 u8 phys_txq
; /* destination queue ID */
752 u16 data_size
; /* data size of transmitted packet in bytes */
753 u32 buf_phys_addr
; /* physical addr of transmitted buffer */
754 u32 buf_cookie
; /* cookie for access to TX buffer in tx path */
755 u32 reserved1
[3]; /* hw_cmd (for future use, BM, PON, PNC) */
756 u32 reserved2
; /* reserved (for future use) */
759 struct mvpp2_rx_desc
{
760 u32 status
; /* info about received packet */
761 u16 reserved1
; /* parser_info (for future use, PnC) */
762 u16 data_size
; /* size of received packet in bytes */
763 u32 buf_phys_addr
; /* physical address of the buffer */
764 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
765 u16 reserved2
; /* gem_port_id (for future use, PON) */
766 u16 reserved3
; /* csum_l4 (for future use, PnC) */
767 u8 reserved4
; /* bm_qset (for future use, BM) */
769 u16 reserved6
; /* classify_info (for future use, PnC) */
770 u32 reserved7
; /* flow_id (for future use, PnC) */
774 struct mvpp2_txq_pcpu_buf
{
775 /* Transmitted SKB */
778 /* Physical address of transmitted buffer */
781 /* Size transmitted */
785 /* Per-CPU Tx queue control */
786 struct mvpp2_txq_pcpu
{
789 /* Number of Tx DMA descriptors in the descriptor ring */
792 /* Number of currently used Tx DMA descriptor in the
797 /* Number of Tx DMA descriptors reserved for each CPU */
800 /* Infos about transmitted buffers */
801 struct mvpp2_txq_pcpu_buf
*buffs
;
803 /* Index of last TX DMA descriptor that was inserted */
806 /* Index of the TX DMA descriptor to be cleaned up */
810 struct mvpp2_tx_queue
{
811 /* Physical number of this Tx queue */
814 /* Logical number of this Tx queue */
817 /* Number of Tx DMA descriptors in the descriptor ring */
820 /* Number of currently used Tx DMA descriptor in the descriptor ring */
823 /* Per-CPU control of physical Tx queues */
824 struct mvpp2_txq_pcpu __percpu
*pcpu
;
826 /* Array of transmitted skb */
827 struct sk_buff
**tx_skb
;
831 /* Virtual address of thex Tx DMA descriptors array */
832 struct mvpp2_tx_desc
*descs
;
834 /* DMA address of the Tx DMA descriptors array */
835 dma_addr_t descs_phys
;
837 /* Index of the last Tx DMA descriptor */
840 /* Index of the next Tx DMA descriptor to process */
841 int next_desc_to_proc
;
844 struct mvpp2_rx_queue
{
845 /* RX queue number, in the range 0-31 for physical RXQs */
848 /* Num of rx descriptors in the rx descriptor ring */
854 /* Virtual address of the RX DMA descriptors array */
855 struct mvpp2_rx_desc
*descs
;
857 /* DMA address of the RX DMA descriptors array */
858 dma_addr_t descs_phys
;
860 /* Index of the last RX DMA descriptor */
863 /* Index of the next RX DMA descriptor to process */
864 int next_desc_to_proc
;
866 /* ID of port to which physical RXQ is mapped */
869 /* Port's logic RXQ number to which physical RXQ is mapped */
873 union mvpp2_prs_tcam_entry
{
874 u32 word
[MVPP2_PRS_TCAM_WORDS
];
875 u8 byte
[MVPP2_PRS_TCAM_WORDS
* 4];
878 union mvpp2_prs_sram_entry
{
879 u32 word
[MVPP2_PRS_SRAM_WORDS
];
880 u8 byte
[MVPP2_PRS_SRAM_WORDS
* 4];
883 struct mvpp2_prs_entry
{
885 union mvpp2_prs_tcam_entry tcam
;
886 union mvpp2_prs_sram_entry sram
;
889 struct mvpp2_prs_shadow
{
896 /* User defined offset */
904 struct mvpp2_cls_flow_entry
{
906 u32 data
[MVPP2_CLS_FLOWS_TBL_DATA_WORDS
];
909 struct mvpp2_cls_lookup_entry
{
915 struct mvpp2_bm_pool
{
916 /* Pool number in the range 0-7 */
918 enum mvpp2_bm_type type
;
920 /* Buffer Pointers Pool External (BPPE) size */
922 /* Number of buffers for this pool */
924 /* Pool buffer size */
929 /* BPPE virtual base address */
931 /* BPPE physical base address */
932 dma_addr_t phys_addr
;
934 /* Ports using BM pool */
937 /* Occupied buffers indicator */
942 struct mvpp2_buff_hdr
{
943 u32 next_buff_phys_addr
;
944 u32 next_buff_virt_addr
;
947 u8 reserved1
; /* bm_qset (for future use, BM) */
950 /* Buffer header info bits */
951 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff
952 #define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
953 #define MVPP2_B_HDR_INFO_LAST_OFFS 12
954 #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
955 #define MVPP2_B_HDR_INFO_IS_LAST(info) \
956 ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
958 /* Static declaractions */
960 /* Number of RXQs used by single port */
961 static int rxq_number
= MVPP2_DEFAULT_RXQ
;
962 /* Number of TXQs used by single port */
963 static int txq_number
= MVPP2_MAX_TXQ
;
965 #define MVPP2_DRIVER_NAME "mvpp2"
966 #define MVPP2_DRIVER_VERSION "1.0"
968 /* Utility/helper methods */
970 static void mvpp2_write(struct mvpp2
*priv
, u32 offset
, u32 data
)
972 writel(data
, priv
->base
+ offset
);
975 static u32
mvpp2_read(struct mvpp2
*priv
, u32 offset
)
977 return readl(priv
->base
+ offset
);
980 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu
*txq_pcpu
)
982 txq_pcpu
->txq_get_index
++;
983 if (txq_pcpu
->txq_get_index
== txq_pcpu
->size
)
984 txq_pcpu
->txq_get_index
= 0;
987 static void mvpp2_txq_inc_put(struct mvpp2_txq_pcpu
*txq_pcpu
,
989 struct mvpp2_tx_desc
*tx_desc
)
991 struct mvpp2_txq_pcpu_buf
*tx_buf
=
992 txq_pcpu
->buffs
+ txq_pcpu
->txq_put_index
;
994 tx_buf
->size
= tx_desc
->data_size
;
995 tx_buf
->phys
= tx_desc
->buf_phys_addr
+ tx_desc
->packet_offset
;
996 txq_pcpu
->txq_put_index
++;
997 if (txq_pcpu
->txq_put_index
== txq_pcpu
->size
)
998 txq_pcpu
->txq_put_index
= 0;
1001 /* Get number of physical egress port */
1002 static inline int mvpp2_egress_port(struct mvpp2_port
*port
)
1004 return MVPP2_MAX_TCONT
+ port
->id
;
1007 /* Get number of physical TXQ */
1008 static inline int mvpp2_txq_phys(int port
, int txq
)
1010 return (MVPP2_MAX_TCONT
+ port
) * MVPP2_MAX_TXQ
+ txq
;
1013 /* Parser configuration routines */
1015 /* Update parser tcam and sram hw entries */
1016 static int mvpp2_prs_hw_write(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1020 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1023 /* Clear entry invalidation bit */
1024 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] &= ~MVPP2_PRS_TCAM_INV_MASK
;
1026 /* Write tcam index - indirect access */
1027 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1028 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1029 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), pe
->tcam
.word
[i
]);
1031 /* Write sram index - indirect access */
1032 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1033 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1034 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), pe
->sram
.word
[i
]);
1039 /* Read tcam entry from hw */
1040 static int mvpp2_prs_hw_read(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1044 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1047 /* Write tcam index - indirect access */
1048 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1050 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] = mvpp2_read(priv
,
1051 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
));
1052 if (pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] & MVPP2_PRS_TCAM_INV_MASK
)
1053 return MVPP2_PRS_TCAM_ENTRY_INVALID
;
1055 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1056 pe
->tcam
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_TCAM_DATA_REG(i
));
1058 /* Write sram index - indirect access */
1059 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1060 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1061 pe
->sram
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_SRAM_DATA_REG(i
));
1066 /* Invalidate tcam hw entry */
1067 static void mvpp2_prs_hw_inv(struct mvpp2
*priv
, int index
)
1069 /* Write index - indirect access */
1070 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
1071 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
),
1072 MVPP2_PRS_TCAM_INV_MASK
);
1075 /* Enable shadow table entry and set its lookup ID */
1076 static void mvpp2_prs_shadow_set(struct mvpp2
*priv
, int index
, int lu
)
1078 priv
->prs_shadow
[index
].valid
= true;
1079 priv
->prs_shadow
[index
].lu
= lu
;
1082 /* Update ri fields in shadow table entry */
1083 static void mvpp2_prs_shadow_ri_set(struct mvpp2
*priv
, int index
,
1084 unsigned int ri
, unsigned int ri_mask
)
1086 priv
->prs_shadow
[index
].ri_mask
= ri_mask
;
1087 priv
->prs_shadow
[index
].ri
= ri
;
1090 /* Update lookup field in tcam sw entry */
1091 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry
*pe
, unsigned int lu
)
1093 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE
);
1095 pe
->tcam
.byte
[MVPP2_PRS_TCAM_LU_BYTE
] = lu
;
1096 pe
->tcam
.byte
[enable_off
] = MVPP2_PRS_LU_MASK
;
1099 /* Update mask for single port in tcam sw entry */
1100 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry
*pe
,
1101 unsigned int port
, bool add
)
1103 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1106 pe
->tcam
.byte
[enable_off
] &= ~(1 << port
);
1108 pe
->tcam
.byte
[enable_off
] |= 1 << port
;
1111 /* Update port map in tcam sw entry */
1112 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry
*pe
,
1115 unsigned char port_mask
= MVPP2_PRS_PORT_MASK
;
1116 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1118 pe
->tcam
.byte
[MVPP2_PRS_TCAM_PORT_BYTE
] = 0;
1119 pe
->tcam
.byte
[enable_off
] &= ~port_mask
;
1120 pe
->tcam
.byte
[enable_off
] |= ~ports
& MVPP2_PRS_PORT_MASK
;
1123 /* Obtain port map from tcam sw entry */
1124 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry
*pe
)
1126 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1128 return ~(pe
->tcam
.byte
[enable_off
]) & MVPP2_PRS_PORT_MASK
;
1131 /* Set byte of data and its enable bits in tcam sw entry */
1132 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry
*pe
,
1133 unsigned int offs
, unsigned char byte
,
1134 unsigned char enable
)
1136 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)] = byte
;
1137 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)] = enable
;
1140 /* Get byte of data and its enable bits from tcam sw entry */
1141 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry
*pe
,
1142 unsigned int offs
, unsigned char *byte
,
1143 unsigned char *enable
)
1145 *byte
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)];
1146 *enable
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)];
1149 /* Compare tcam data bytes with a pattern */
1150 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry
*pe
, int offs
,
1153 int off
= MVPP2_PRS_TCAM_DATA_BYTE(offs
);
1156 tcam_data
= (8 << pe
->tcam
.byte
[off
+ 1]) | pe
->tcam
.byte
[off
];
1157 if (tcam_data
!= data
)
1162 /* Update ai bits in tcam sw entry */
1163 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry
*pe
,
1164 unsigned int bits
, unsigned int enable
)
1166 int i
, ai_idx
= MVPP2_PRS_TCAM_AI_BYTE
;
1168 for (i
= 0; i
< MVPP2_PRS_AI_BITS
; i
++) {
1170 if (!(enable
& BIT(i
)))
1174 pe
->tcam
.byte
[ai_idx
] |= 1 << i
;
1176 pe
->tcam
.byte
[ai_idx
] &= ~(1 << i
);
1179 pe
->tcam
.byte
[MVPP2_PRS_TCAM_EN_OFFS(ai_idx
)] |= enable
;
1182 /* Get ai bits from tcam sw entry */
1183 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry
*pe
)
1185 return pe
->tcam
.byte
[MVPP2_PRS_TCAM_AI_BYTE
];
1188 /* Set ethertype in tcam sw entry */
1189 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry
*pe
, int offset
,
1190 unsigned short ethertype
)
1192 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 0, ethertype
>> 8, 0xff);
1193 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 1, ethertype
& 0xff, 0xff);
1196 /* Set bits in sram sw entry */
1197 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry
*pe
, int bit_num
,
1200 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] |= (val
<< (bit_num
% 8));
1203 /* Clear bits in sram sw entry */
1204 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry
*pe
, int bit_num
,
1207 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] &= ~(val
<< (bit_num
% 8));
1210 /* Update ri bits in sram sw entry */
1211 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry
*pe
,
1212 unsigned int bits
, unsigned int mask
)
1216 for (i
= 0; i
< MVPP2_PRS_SRAM_RI_CTRL_BITS
; i
++) {
1217 int ri_off
= MVPP2_PRS_SRAM_RI_OFFS
;
1219 if (!(mask
& BIT(i
)))
1223 mvpp2_prs_sram_bits_set(pe
, ri_off
+ i
, 1);
1225 mvpp2_prs_sram_bits_clear(pe
, ri_off
+ i
, 1);
1227 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_RI_CTRL_OFFS
+ i
, 1);
1231 /* Obtain ri bits from sram sw entry */
1232 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry
*pe
)
1234 return pe
->sram
.word
[MVPP2_PRS_SRAM_RI_WORD
];
1237 /* Update ai bits in sram sw entry */
1238 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry
*pe
,
1239 unsigned int bits
, unsigned int mask
)
1242 int ai_off
= MVPP2_PRS_SRAM_AI_OFFS
;
1244 for (i
= 0; i
< MVPP2_PRS_SRAM_AI_CTRL_BITS
; i
++) {
1246 if (!(mask
& BIT(i
)))
1250 mvpp2_prs_sram_bits_set(pe
, ai_off
+ i
, 1);
1252 mvpp2_prs_sram_bits_clear(pe
, ai_off
+ i
, 1);
1254 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_AI_CTRL_OFFS
+ i
, 1);
1258 /* Read ai bits from sram sw entry */
1259 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry
*pe
)
1262 int ai_off
= MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS
);
1263 int ai_en_off
= ai_off
+ 1;
1264 int ai_shift
= MVPP2_PRS_SRAM_AI_OFFS
% 8;
1266 bits
= (pe
->sram
.byte
[ai_off
] >> ai_shift
) |
1267 (pe
->sram
.byte
[ai_en_off
] << (8 - ai_shift
));
1272 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1275 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry
*pe
,
1278 int sram_next_off
= MVPP2_PRS_SRAM_NEXT_LU_OFFS
;
1280 mvpp2_prs_sram_bits_clear(pe
, sram_next_off
,
1281 MVPP2_PRS_SRAM_NEXT_LU_MASK
);
1282 mvpp2_prs_sram_bits_set(pe
, sram_next_off
, lu
);
1285 /* In the sram sw entry set sign and value of the next lookup offset
1286 * and the offset value generated to the classifier
1288 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry
*pe
, int shift
,
1293 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1296 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1300 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS
)] =
1301 (unsigned char)shift
;
1303 /* Reset and set operation */
1304 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
,
1305 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
);
1306 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
, op
);
1308 /* Set base offset as current */
1309 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1312 /* In the sram sw entry set sign and value of the user defined offset
1313 * generated to the classifier
1315 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry
*pe
,
1316 unsigned int type
, int offset
,
1321 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1322 offset
= 0 - offset
;
1324 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1328 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_OFFS
,
1329 MVPP2_PRS_SRAM_UDF_MASK
);
1330 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_OFFS
, offset
);
1331 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1332 MVPP2_PRS_SRAM_UDF_BITS
)] &=
1333 ~(MVPP2_PRS_SRAM_UDF_MASK
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1334 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1335 MVPP2_PRS_SRAM_UDF_BITS
)] |=
1336 (offset
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1338 /* Set offset type */
1339 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
,
1340 MVPP2_PRS_SRAM_UDF_TYPE_MASK
);
1341 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
, type
);
1343 /* Set offset operation */
1344 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
,
1345 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
);
1346 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
, op
);
1348 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1349 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] &=
1350 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
>>
1351 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1353 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1354 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] |=
1355 (op
>> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1357 /* Set base offset as current */
1358 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1361 /* Find parser flow entry */
1362 static struct mvpp2_prs_entry
*mvpp2_prs_flow_find(struct mvpp2
*priv
, int flow
)
1364 struct mvpp2_prs_entry
*pe
;
1367 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1370 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
1372 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1373 for (tid
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1; tid
>= 0; tid
--) {
1376 if (!priv
->prs_shadow
[tid
].valid
||
1377 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_FLOWS
)
1381 mvpp2_prs_hw_read(priv
, pe
);
1382 bits
= mvpp2_prs_sram_ai_get(pe
);
1384 /* Sram store classification lookup ID in AI bits [5:0] */
1385 if ((bits
& MVPP2_PRS_FLOW_ID_MASK
) == flow
)
1393 /* Return first free tcam index, seeking from start to end */
1394 static int mvpp2_prs_tcam_first_free(struct mvpp2
*priv
, unsigned char start
,
1402 if (end
>= MVPP2_PRS_TCAM_SRAM_SIZE
)
1403 end
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1;
1405 for (tid
= start
; tid
<= end
; tid
++) {
1406 if (!priv
->prs_shadow
[tid
].valid
)
1413 /* Enable/disable dropping all mac da's */
1414 static void mvpp2_prs_mac_drop_all_set(struct mvpp2
*priv
, int port
, bool add
)
1416 struct mvpp2_prs_entry pe
;
1418 if (priv
->prs_shadow
[MVPP2_PE_DROP_ALL
].valid
) {
1419 /* Entry exist - update port only */
1420 pe
.index
= MVPP2_PE_DROP_ALL
;
1421 mvpp2_prs_hw_read(priv
, &pe
);
1423 /* Entry doesn't exist - create new */
1424 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1425 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1426 pe
.index
= MVPP2_PE_DROP_ALL
;
1428 /* Non-promiscuous mode for all ports - DROP unknown packets */
1429 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1430 MVPP2_PRS_RI_DROP_MASK
);
1432 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1433 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1435 /* Update shadow table */
1436 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1438 /* Mask all ports */
1439 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1442 /* Update port mask */
1443 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1445 mvpp2_prs_hw_write(priv
, &pe
);
1448 /* Set port to promiscuous mode */
1449 static void mvpp2_prs_mac_promisc_set(struct mvpp2
*priv
, int port
, bool add
)
1451 struct mvpp2_prs_entry pe
;
1453 /* Promiscuous mode - Accept unknown packets */
1455 if (priv
->prs_shadow
[MVPP2_PE_MAC_PROMISCUOUS
].valid
) {
1456 /* Entry exist - update port only */
1457 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1458 mvpp2_prs_hw_read(priv
, &pe
);
1460 /* Entry doesn't exist - create new */
1461 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1462 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1463 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1465 /* Continue - set next lookup */
1466 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1468 /* Set result info bits */
1469 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_UCAST
,
1470 MVPP2_PRS_RI_L2_CAST_MASK
);
1472 /* Shift to ethertype */
1473 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1474 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1476 /* Mask all ports */
1477 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1479 /* Update shadow table */
1480 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1483 /* Update port mask */
1484 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1486 mvpp2_prs_hw_write(priv
, &pe
);
1489 /* Accept multicast */
1490 static void mvpp2_prs_mac_multi_set(struct mvpp2
*priv
, int port
, int index
,
1493 struct mvpp2_prs_entry pe
;
1494 unsigned char da_mc
;
1496 /* Ethernet multicast address first byte is
1497 * 0x01 for IPv4 and 0x33 for IPv6
1499 da_mc
= (index
== MVPP2_PE_MAC_MC_ALL
) ? 0x01 : 0x33;
1501 if (priv
->prs_shadow
[index
].valid
) {
1502 /* Entry exist - update port only */
1504 mvpp2_prs_hw_read(priv
, &pe
);
1506 /* Entry doesn't exist - create new */
1507 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1508 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1511 /* Continue - set next lookup */
1512 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1514 /* Set result info bits */
1515 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_MCAST
,
1516 MVPP2_PRS_RI_L2_CAST_MASK
);
1518 /* Update tcam entry data first byte */
1519 mvpp2_prs_tcam_data_byte_set(&pe
, 0, da_mc
, 0xff);
1521 /* Shift to ethertype */
1522 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1523 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1525 /* Mask all ports */
1526 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1528 /* Update shadow table */
1529 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1532 /* Update port mask */
1533 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1535 mvpp2_prs_hw_write(priv
, &pe
);
1538 /* Set entry for dsa packets */
1539 static void mvpp2_prs_dsa_tag_set(struct mvpp2
*priv
, int port
, bool add
,
1540 bool tagged
, bool extend
)
1542 struct mvpp2_prs_entry pe
;
1546 tid
= tagged
? MVPP2_PE_EDSA_TAGGED
: MVPP2_PE_EDSA_UNTAGGED
;
1549 tid
= tagged
? MVPP2_PE_DSA_TAGGED
: MVPP2_PE_DSA_UNTAGGED
;
1553 if (priv
->prs_shadow
[tid
].valid
) {
1554 /* Entry exist - update port only */
1556 mvpp2_prs_hw_read(priv
, &pe
);
1558 /* Entry doesn't exist - create new */
1559 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1560 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1563 /* Shift 4 bytes if DSA tag or 8 bytes in case of EDSA tag*/
1564 mvpp2_prs_sram_shift_set(&pe
, shift
,
1565 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1567 /* Update shadow table */
1568 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_DSA
);
1571 /* Set tagged bit in DSA tag */
1572 mvpp2_prs_tcam_data_byte_set(&pe
, 0,
1573 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
,
1574 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
);
1575 /* Clear all ai bits for next iteration */
1576 mvpp2_prs_sram_ai_update(&pe
, 0,
1577 MVPP2_PRS_SRAM_AI_MASK
);
1578 /* If packet is tagged continue check vlans */
1579 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
1581 /* Set result info bits to 'no vlans' */
1582 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
1583 MVPP2_PRS_RI_VLAN_MASK
);
1584 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1587 /* Mask all ports */
1588 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1591 /* Update port mask */
1592 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1594 mvpp2_prs_hw_write(priv
, &pe
);
1597 /* Set entry for dsa ethertype */
1598 static void mvpp2_prs_dsa_tag_ethertype_set(struct mvpp2
*priv
, int port
,
1599 bool add
, bool tagged
, bool extend
)
1601 struct mvpp2_prs_entry pe
;
1602 int tid
, shift
, port_mask
;
1605 tid
= tagged
? MVPP2_PE_ETYPE_EDSA_TAGGED
:
1606 MVPP2_PE_ETYPE_EDSA_UNTAGGED
;
1610 tid
= tagged
? MVPP2_PE_ETYPE_DSA_TAGGED
:
1611 MVPP2_PE_ETYPE_DSA_UNTAGGED
;
1612 port_mask
= MVPP2_PRS_PORT_MASK
;
1616 if (priv
->prs_shadow
[tid
].valid
) {
1617 /* Entry exist - update port only */
1619 mvpp2_prs_hw_read(priv
, &pe
);
1621 /* Entry doesn't exist - create new */
1622 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1623 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1627 mvpp2_prs_match_etype(&pe
, 0, ETH_P_EDSA
);
1628 mvpp2_prs_match_etype(&pe
, 2, 0);
1630 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DSA_MASK
,
1631 MVPP2_PRS_RI_DSA_MASK
);
1632 /* Shift ethertype + 2 byte reserved + tag*/
1633 mvpp2_prs_sram_shift_set(&pe
, 2 + MVPP2_ETH_TYPE_LEN
+ shift
,
1634 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1636 /* Update shadow table */
1637 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_DSA
);
1640 /* Set tagged bit in DSA tag */
1641 mvpp2_prs_tcam_data_byte_set(&pe
,
1642 MVPP2_ETH_TYPE_LEN
+ 2 + 3,
1643 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
,
1644 MVPP2_PRS_TCAM_DSA_TAGGED_BIT
);
1645 /* Clear all ai bits for next iteration */
1646 mvpp2_prs_sram_ai_update(&pe
, 0,
1647 MVPP2_PRS_SRAM_AI_MASK
);
1648 /* If packet is tagged continue check vlans */
1649 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
1651 /* Set result info bits to 'no vlans' */
1652 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
1653 MVPP2_PRS_RI_VLAN_MASK
);
1654 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1656 /* Mask/unmask all ports, depending on dsa type */
1657 mvpp2_prs_tcam_port_map_set(&pe
, port_mask
);
1660 /* Update port mask */
1661 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1663 mvpp2_prs_hw_write(priv
, &pe
);
1666 /* Search for existing single/triple vlan entry */
1667 static struct mvpp2_prs_entry
*mvpp2_prs_vlan_find(struct mvpp2
*priv
,
1668 unsigned short tpid
, int ai
)
1670 struct mvpp2_prs_entry
*pe
;
1673 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1676 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
1678 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1679 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
1680 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
1681 unsigned int ri_bits
, ai_bits
;
1684 if (!priv
->prs_shadow
[tid
].valid
||
1685 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_VLAN
)
1690 mvpp2_prs_hw_read(priv
, pe
);
1691 match
= mvpp2_prs_tcam_data_cmp(pe
, 0, swab16(tpid
));
1696 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
1697 ri_bits
&= MVPP2_PRS_RI_VLAN_MASK
;
1699 /* Get current ai value from tcam */
1700 ai_bits
= mvpp2_prs_tcam_ai_get(pe
);
1701 /* Clear double vlan bit */
1702 ai_bits
&= ~MVPP2_PRS_DBL_VLAN_AI_BIT
;
1707 if (ri_bits
== MVPP2_PRS_RI_VLAN_SINGLE
||
1708 ri_bits
== MVPP2_PRS_RI_VLAN_TRIPLE
)
1716 /* Add/update single/triple vlan entry */
1717 static int mvpp2_prs_vlan_add(struct mvpp2
*priv
, unsigned short tpid
, int ai
,
1718 unsigned int port_map
)
1720 struct mvpp2_prs_entry
*pe
;
1724 pe
= mvpp2_prs_vlan_find(priv
, tpid
, ai
);
1727 /* Create new tcam entry */
1728 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_LAST_FREE_TID
,
1729 MVPP2_PE_FIRST_FREE_TID
);
1733 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1737 /* Get last double vlan tid */
1738 for (tid_aux
= MVPP2_PE_LAST_FREE_TID
;
1739 tid_aux
>= MVPP2_PE_FIRST_FREE_TID
; tid_aux
--) {
1740 unsigned int ri_bits
;
1742 if (!priv
->prs_shadow
[tid_aux
].valid
||
1743 priv
->prs_shadow
[tid_aux
].lu
!= MVPP2_PRS_LU_VLAN
)
1746 pe
->index
= tid_aux
;
1747 mvpp2_prs_hw_read(priv
, pe
);
1748 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
1749 if ((ri_bits
& MVPP2_PRS_RI_VLAN_MASK
) ==
1750 MVPP2_PRS_RI_VLAN_DOUBLE
)
1754 if (tid
<= tid_aux
) {
1759 memset(pe
, 0 , sizeof(struct mvpp2_prs_entry
));
1760 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
1763 mvpp2_prs_match_etype(pe
, 0, tpid
);
1765 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_L2
);
1766 /* Shift 4 bytes - skip 1 vlan tag */
1767 mvpp2_prs_sram_shift_set(pe
, MVPP2_VLAN_TAG_LEN
,
1768 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1769 /* Clear all ai bits for next iteration */
1770 mvpp2_prs_sram_ai_update(pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
1772 if (ai
== MVPP2_PRS_SINGLE_VLAN_AI
) {
1773 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_SINGLE
,
1774 MVPP2_PRS_RI_VLAN_MASK
);
1776 ai
|= MVPP2_PRS_DBL_VLAN_AI_BIT
;
1777 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_TRIPLE
,
1778 MVPP2_PRS_RI_VLAN_MASK
);
1780 mvpp2_prs_tcam_ai_update(pe
, ai
, MVPP2_PRS_SRAM_AI_MASK
);
1782 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_VLAN
);
1784 /* Update ports' mask */
1785 mvpp2_prs_tcam_port_map_set(pe
, port_map
);
1787 mvpp2_prs_hw_write(priv
, pe
);
1795 /* Get first free double vlan ai number */
1796 static int mvpp2_prs_double_vlan_ai_free_get(struct mvpp2
*priv
)
1800 for (i
= 1; i
< MVPP2_PRS_DBL_VLANS_MAX
; i
++) {
1801 if (!priv
->prs_double_vlans
[i
])
1808 /* Search for existing double vlan entry */
1809 static struct mvpp2_prs_entry
*mvpp2_prs_double_vlan_find(struct mvpp2
*priv
,
1810 unsigned short tpid1
,
1811 unsigned short tpid2
)
1813 struct mvpp2_prs_entry
*pe
;
1816 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1819 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
1821 /* Go through the all entries with MVPP2_PRS_LU_VLAN */
1822 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
1823 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
1824 unsigned int ri_mask
;
1827 if (!priv
->prs_shadow
[tid
].valid
||
1828 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_VLAN
)
1832 mvpp2_prs_hw_read(priv
, pe
);
1834 match
= mvpp2_prs_tcam_data_cmp(pe
, 0, swab16(tpid1
))
1835 && mvpp2_prs_tcam_data_cmp(pe
, 4, swab16(tpid2
));
1840 ri_mask
= mvpp2_prs_sram_ri_get(pe
) & MVPP2_PRS_RI_VLAN_MASK
;
1841 if (ri_mask
== MVPP2_PRS_RI_VLAN_DOUBLE
)
1849 /* Add or update double vlan entry */
1850 static int mvpp2_prs_double_vlan_add(struct mvpp2
*priv
, unsigned short tpid1
,
1851 unsigned short tpid2
,
1852 unsigned int port_map
)
1854 struct mvpp2_prs_entry
*pe
;
1855 int tid_aux
, tid
, ai
, ret
= 0;
1857 pe
= mvpp2_prs_double_vlan_find(priv
, tpid1
, tpid2
);
1860 /* Create new tcam entry */
1861 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1862 MVPP2_PE_LAST_FREE_TID
);
1866 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1870 /* Set ai value for new double vlan entry */
1871 ai
= mvpp2_prs_double_vlan_ai_free_get(priv
);
1877 /* Get first single/triple vlan tid */
1878 for (tid_aux
= MVPP2_PE_FIRST_FREE_TID
;
1879 tid_aux
<= MVPP2_PE_LAST_FREE_TID
; tid_aux
++) {
1880 unsigned int ri_bits
;
1882 if (!priv
->prs_shadow
[tid_aux
].valid
||
1883 priv
->prs_shadow
[tid_aux
].lu
!= MVPP2_PRS_LU_VLAN
)
1886 pe
->index
= tid_aux
;
1887 mvpp2_prs_hw_read(priv
, pe
);
1888 ri_bits
= mvpp2_prs_sram_ri_get(pe
);
1889 ri_bits
&= MVPP2_PRS_RI_VLAN_MASK
;
1890 if (ri_bits
== MVPP2_PRS_RI_VLAN_SINGLE
||
1891 ri_bits
== MVPP2_PRS_RI_VLAN_TRIPLE
)
1895 if (tid
>= tid_aux
) {
1900 memset(pe
, 0, sizeof(struct mvpp2_prs_entry
));
1901 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
1904 priv
->prs_double_vlans
[ai
] = true;
1906 mvpp2_prs_match_etype(pe
, 0, tpid1
);
1907 mvpp2_prs_match_etype(pe
, 4, tpid2
);
1909 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_VLAN
);
1910 /* Shift 8 bytes - skip 2 vlan tags */
1911 mvpp2_prs_sram_shift_set(pe
, 2 * MVPP2_VLAN_TAG_LEN
,
1912 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1913 mvpp2_prs_sram_ri_update(pe
, MVPP2_PRS_RI_VLAN_DOUBLE
,
1914 MVPP2_PRS_RI_VLAN_MASK
);
1915 mvpp2_prs_sram_ai_update(pe
, ai
| MVPP2_PRS_DBL_VLAN_AI_BIT
,
1916 MVPP2_PRS_SRAM_AI_MASK
);
1918 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_VLAN
);
1921 /* Update ports' mask */
1922 mvpp2_prs_tcam_port_map_set(pe
, port_map
);
1923 mvpp2_prs_hw_write(priv
, pe
);
1930 /* IPv4 header parsing for fragmentation and L4 offset */
1931 static int mvpp2_prs_ip4_proto(struct mvpp2
*priv
, unsigned short proto
,
1932 unsigned int ri
, unsigned int ri_mask
)
1934 struct mvpp2_prs_entry pe
;
1937 if ((proto
!= IPPROTO_TCP
) && (proto
!= IPPROTO_UDP
) &&
1938 (proto
!= IPPROTO_IGMP
))
1941 /* Fragmented packet */
1942 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1943 MVPP2_PE_LAST_FREE_TID
);
1947 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1948 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
1951 /* Set next lu to IPv4 */
1952 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
1953 mvpp2_prs_sram_shift_set(&pe
, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1955 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
1956 sizeof(struct iphdr
) - 4,
1957 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1958 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
1959 MVPP2_PRS_IPV4_DIP_AI_BIT
);
1960 mvpp2_prs_sram_ri_update(&pe
, ri
| MVPP2_PRS_RI_IP_FRAG_MASK
,
1961 ri_mask
| MVPP2_PRS_RI_IP_FRAG_MASK
);
1963 mvpp2_prs_tcam_data_byte_set(&pe
, 5, proto
, MVPP2_PRS_TCAM_PROTO_MASK
);
1964 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV4_DIP_AI_BIT
);
1965 /* Unmask all ports */
1966 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1968 /* Update shadow table and hw entry */
1969 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
1970 mvpp2_prs_hw_write(priv
, &pe
);
1972 /* Not fragmented packet */
1973 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1974 MVPP2_PE_LAST_FREE_TID
);
1979 /* Clear ri before updating */
1980 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
1981 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
1982 mvpp2_prs_sram_ri_update(&pe
, ri
, ri_mask
);
1984 mvpp2_prs_tcam_data_byte_set(&pe
, 2, 0x00, MVPP2_PRS_TCAM_PROTO_MASK_L
);
1985 mvpp2_prs_tcam_data_byte_set(&pe
, 3, 0x00, MVPP2_PRS_TCAM_PROTO_MASK
);
1987 /* Update shadow table and hw entry */
1988 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
1989 mvpp2_prs_hw_write(priv
, &pe
);
1994 /* IPv4 L3 multicast or broadcast */
1995 static int mvpp2_prs_ip4_cast(struct mvpp2
*priv
, unsigned short l3_cast
)
1997 struct mvpp2_prs_entry pe
;
2000 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2001 MVPP2_PE_LAST_FREE_TID
);
2005 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2006 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2010 case MVPP2_PRS_L3_MULTI_CAST
:
2011 mvpp2_prs_tcam_data_byte_set(&pe
, 0, MVPP2_PRS_IPV4_MC
,
2012 MVPP2_PRS_IPV4_MC_MASK
);
2013 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_MCAST
,
2014 MVPP2_PRS_RI_L3_ADDR_MASK
);
2016 case MVPP2_PRS_L3_BROAD_CAST
:
2017 mask
= MVPP2_PRS_IPV4_BC_MASK
;
2018 mvpp2_prs_tcam_data_byte_set(&pe
, 0, mask
, mask
);
2019 mvpp2_prs_tcam_data_byte_set(&pe
, 1, mask
, mask
);
2020 mvpp2_prs_tcam_data_byte_set(&pe
, 2, mask
, mask
);
2021 mvpp2_prs_tcam_data_byte_set(&pe
, 3, mask
, mask
);
2022 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_BCAST
,
2023 MVPP2_PRS_RI_L3_ADDR_MASK
);
2029 /* Finished: go to flowid generation */
2030 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2031 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2033 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
2034 MVPP2_PRS_IPV4_DIP_AI_BIT
);
2035 /* Unmask all ports */
2036 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2038 /* Update shadow table and hw entry */
2039 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2040 mvpp2_prs_hw_write(priv
, &pe
);
2045 /* Set entries for protocols over IPv6 */
2046 static int mvpp2_prs_ip6_proto(struct mvpp2
*priv
, unsigned short proto
,
2047 unsigned int ri
, unsigned int ri_mask
)
2049 struct mvpp2_prs_entry pe
;
2052 if ((proto
!= IPPROTO_TCP
) && (proto
!= IPPROTO_UDP
) &&
2053 (proto
!= IPPROTO_ICMPV6
) && (proto
!= IPPROTO_IPIP
))
2056 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2057 MVPP2_PE_LAST_FREE_TID
);
2061 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2062 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2065 /* Finished: go to flowid generation */
2066 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2067 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2068 mvpp2_prs_sram_ri_update(&pe
, ri
, ri_mask
);
2069 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
2070 sizeof(struct ipv6hdr
) - 6,
2071 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2073 mvpp2_prs_tcam_data_byte_set(&pe
, 0, proto
, MVPP2_PRS_TCAM_PROTO_MASK
);
2074 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2075 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2076 /* Unmask all ports */
2077 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2080 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
2081 mvpp2_prs_hw_write(priv
, &pe
);
2086 /* IPv6 L3 multicast entry */
2087 static int mvpp2_prs_ip6_cast(struct mvpp2
*priv
, unsigned short l3_cast
)
2089 struct mvpp2_prs_entry pe
;
2092 if (l3_cast
!= MVPP2_PRS_L3_MULTI_CAST
)
2095 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2096 MVPP2_PE_LAST_FREE_TID
);
2100 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2101 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2104 /* Finished: go to flowid generation */
2105 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2106 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_MCAST
,
2107 MVPP2_PRS_RI_L3_ADDR_MASK
);
2108 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2109 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2110 /* Shift back to IPv6 NH */
2111 mvpp2_prs_sram_shift_set(&pe
, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2113 mvpp2_prs_tcam_data_byte_set(&pe
, 0, MVPP2_PRS_IPV6_MC
,
2114 MVPP2_PRS_IPV6_MC_MASK
);
2115 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2116 /* Unmask all ports */
2117 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2119 /* Update shadow table and hw entry */
2120 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
2121 mvpp2_prs_hw_write(priv
, &pe
);
2126 /* Parser per-port initialization */
2127 static void mvpp2_prs_hw_port_init(struct mvpp2
*priv
, int port
, int lu_first
,
2128 int lu_max
, int offset
)
2133 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_LOOKUP_REG
);
2134 val
&= ~MVPP2_PRS_PORT_LU_MASK(port
);
2135 val
|= MVPP2_PRS_PORT_LU_VAL(port
, lu_first
);
2136 mvpp2_write(priv
, MVPP2_PRS_INIT_LOOKUP_REG
, val
);
2138 /* Set maximum number of loops for packet received from port */
2139 val
= mvpp2_read(priv
, MVPP2_PRS_MAX_LOOP_REG(port
));
2140 val
&= ~MVPP2_PRS_MAX_LOOP_MASK(port
);
2141 val
|= MVPP2_PRS_MAX_LOOP_VAL(port
, lu_max
);
2142 mvpp2_write(priv
, MVPP2_PRS_MAX_LOOP_REG(port
), val
);
2144 /* Set initial offset for packet header extraction for the first
2147 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_OFFS_REG(port
));
2148 val
&= ~MVPP2_PRS_INIT_OFF_MASK(port
);
2149 val
|= MVPP2_PRS_INIT_OFF_VAL(port
, offset
);
2150 mvpp2_write(priv
, MVPP2_PRS_INIT_OFFS_REG(port
), val
);
2153 /* Default flow entries initialization for all ports */
2154 static void mvpp2_prs_def_flow_init(struct mvpp2
*priv
)
2156 struct mvpp2_prs_entry pe
;
2159 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
2160 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2161 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2162 pe
.index
= MVPP2_PE_FIRST_DEFAULT_FLOW
- port
;
2164 /* Mask all ports */
2165 mvpp2_prs_tcam_port_map_set(&pe
, 0);
2168 mvpp2_prs_sram_ai_update(&pe
, port
, MVPP2_PRS_FLOW_ID_MASK
);
2169 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
2171 /* Update shadow table and hw entry */
2172 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_FLOWS
);
2173 mvpp2_prs_hw_write(priv
, &pe
);
2177 /* Set default entry for Marvell Header field */
2178 static void mvpp2_prs_mh_init(struct mvpp2
*priv
)
2180 struct mvpp2_prs_entry pe
;
2182 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2184 pe
.index
= MVPP2_PE_MH_DEFAULT
;
2185 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MH
);
2186 mvpp2_prs_sram_shift_set(&pe
, MVPP2_MH_SIZE
,
2187 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2188 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
2190 /* Unmask all ports */
2191 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2193 /* Update shadow table and hw entry */
2194 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MH
);
2195 mvpp2_prs_hw_write(priv
, &pe
);
2198 /* Set default entires (place holder) for promiscuous, non-promiscuous and
2199 * multicast MAC addresses
2201 static void mvpp2_prs_mac_init(struct mvpp2
*priv
)
2203 struct mvpp2_prs_entry pe
;
2205 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2207 /* Non-promiscuous mode for all ports - DROP unknown packets */
2208 pe
.index
= MVPP2_PE_MAC_NON_PROMISCUOUS
;
2209 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
2211 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
2212 MVPP2_PRS_RI_DROP_MASK
);
2213 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2214 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2216 /* Unmask all ports */
2217 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2219 /* Update shadow table and hw entry */
2220 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
2221 mvpp2_prs_hw_write(priv
, &pe
);
2223 /* place holders only - no ports */
2224 mvpp2_prs_mac_drop_all_set(priv
, 0, false);
2225 mvpp2_prs_mac_promisc_set(priv
, 0, false);
2226 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_ALL
, 0, false);
2227 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_IP6
, 0, false);
2230 /* Set default entries for various types of dsa packets */
2231 static void mvpp2_prs_dsa_init(struct mvpp2
*priv
)
2233 struct mvpp2_prs_entry pe
;
2235 /* None tagged EDSA entry - place holder */
2236 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_UNTAGGED
,
2239 /* Tagged EDSA entry - place holder */
2240 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
2242 /* None tagged DSA entry - place holder */
2243 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_UNTAGGED
,
2246 /* Tagged DSA entry - place holder */
2247 mvpp2_prs_dsa_tag_set(priv
, 0, false, MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
2249 /* None tagged EDSA ethertype entry - place holder*/
2250 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, false,
2251 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
2253 /* Tagged EDSA ethertype entry - place holder*/
2254 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, false,
2255 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
2257 /* None tagged DSA ethertype entry */
2258 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, true,
2259 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
2261 /* Tagged DSA ethertype entry */
2262 mvpp2_prs_dsa_tag_ethertype_set(priv
, 0, true,
2263 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
2265 /* Set default entry, in case DSA or EDSA tag not found */
2266 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2267 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
2268 pe
.index
= MVPP2_PE_DSA_DEFAULT
;
2269 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2272 mvpp2_prs_sram_shift_set(&pe
, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2273 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
2275 /* Clear all sram ai bits for next iteration */
2276 mvpp2_prs_sram_ai_update(&pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
2278 /* Unmask all ports */
2279 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2281 mvpp2_prs_hw_write(priv
, &pe
);
2284 /* Match basic ethertypes */
2285 static int mvpp2_prs_etype_init(struct mvpp2
*priv
)
2287 struct mvpp2_prs_entry pe
;
2290 /* Ethertype: PPPoE */
2291 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2292 MVPP2_PE_LAST_FREE_TID
);
2296 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2297 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2300 mvpp2_prs_match_etype(&pe
, 0, ETH_P_PPP_SES
);
2302 mvpp2_prs_sram_shift_set(&pe
, MVPP2_PPPOE_HDR_SIZE
,
2303 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2304 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
2305 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_PPPOE_MASK
,
2306 MVPP2_PRS_RI_PPPOE_MASK
);
2308 /* Update shadow table and hw entry */
2309 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2310 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2311 priv
->prs_shadow
[pe
.index
].finish
= false;
2312 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_PPPOE_MASK
,
2313 MVPP2_PRS_RI_PPPOE_MASK
);
2314 mvpp2_prs_hw_write(priv
, &pe
);
2316 /* Ethertype: ARP */
2317 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2318 MVPP2_PE_LAST_FREE_TID
);
2322 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2323 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2326 mvpp2_prs_match_etype(&pe
, 0, ETH_P_ARP
);
2328 /* Generate flow in the next iteration*/
2329 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2330 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2331 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_ARP
,
2332 MVPP2_PRS_RI_L3_PROTO_MASK
);
2334 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2336 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2338 /* Update shadow table and hw entry */
2339 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2340 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2341 priv
->prs_shadow
[pe
.index
].finish
= true;
2342 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_ARP
,
2343 MVPP2_PRS_RI_L3_PROTO_MASK
);
2344 mvpp2_prs_hw_write(priv
, &pe
);
2346 /* Ethertype: LBTD */
2347 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2348 MVPP2_PE_LAST_FREE_TID
);
2352 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2353 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2356 mvpp2_prs_match_etype(&pe
, 0, MVPP2_IP_LBDT_TYPE
);
2358 /* Generate flow in the next iteration*/
2359 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2360 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2361 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2362 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2363 MVPP2_PRS_RI_CPU_CODE_MASK
|
2364 MVPP2_PRS_RI_UDF3_MASK
);
2366 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2368 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2370 /* Update shadow table and hw entry */
2371 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2372 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2373 priv
->prs_shadow
[pe
.index
].finish
= true;
2374 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2375 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2376 MVPP2_PRS_RI_CPU_CODE_MASK
|
2377 MVPP2_PRS_RI_UDF3_MASK
);
2378 mvpp2_prs_hw_write(priv
, &pe
);
2380 /* Ethertype: IPv4 without options */
2381 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2382 MVPP2_PE_LAST_FREE_TID
);
2386 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2387 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2390 mvpp2_prs_match_etype(&pe
, 0, ETH_P_IP
);
2391 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
2392 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
2393 MVPP2_PRS_IPV4_HEAD_MASK
|
2394 MVPP2_PRS_IPV4_IHL_MASK
);
2396 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2397 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
2398 MVPP2_PRS_RI_L3_PROTO_MASK
);
2399 /* Skip eth_type + 4 bytes of IP header */
2400 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
2401 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2403 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2405 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2407 /* Update shadow table and hw entry */
2408 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2409 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2410 priv
->prs_shadow
[pe
.index
].finish
= false;
2411 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4
,
2412 MVPP2_PRS_RI_L3_PROTO_MASK
);
2413 mvpp2_prs_hw_write(priv
, &pe
);
2415 /* Ethertype: IPv4 with options */
2416 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2417 MVPP2_PE_LAST_FREE_TID
);
2423 /* Clear tcam data before updating */
2424 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN
)] = 0x0;
2425 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN
)] = 0x0;
2427 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
2428 MVPP2_PRS_IPV4_HEAD
,
2429 MVPP2_PRS_IPV4_HEAD_MASK
);
2431 /* Clear ri before updating */
2432 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
2433 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
2434 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
2435 MVPP2_PRS_RI_L3_PROTO_MASK
);
2437 /* Update shadow table and hw entry */
2438 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2439 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2440 priv
->prs_shadow
[pe
.index
].finish
= false;
2441 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4_OPT
,
2442 MVPP2_PRS_RI_L3_PROTO_MASK
);
2443 mvpp2_prs_hw_write(priv
, &pe
);
2445 /* Ethertype: IPv6 without options */
2446 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2447 MVPP2_PE_LAST_FREE_TID
);
2451 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2452 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2455 mvpp2_prs_match_etype(&pe
, 0, ETH_P_IPV6
);
2457 /* Skip DIP of IPV6 header */
2458 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 8 +
2459 MVPP2_MAX_L3_ADDR_SIZE
,
2460 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2461 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2462 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
2463 MVPP2_PRS_RI_L3_PROTO_MASK
);
2465 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2467 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2469 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2470 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2471 priv
->prs_shadow
[pe
.index
].finish
= false;
2472 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP6
,
2473 MVPP2_PRS_RI_L3_PROTO_MASK
);
2474 mvpp2_prs_hw_write(priv
, &pe
);
2476 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2477 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2478 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2479 pe
.index
= MVPP2_PE_ETH_TYPE_UN
;
2481 /* Unmask all ports */
2482 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2484 /* Generate flow in the next iteration*/
2485 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2486 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2487 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
2488 MVPP2_PRS_RI_L3_PROTO_MASK
);
2489 /* Set L3 offset even it's unknown L3 */
2490 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2492 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2494 /* Update shadow table and hw entry */
2495 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2496 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2497 priv
->prs_shadow
[pe
.index
].finish
= true;
2498 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_UN
,
2499 MVPP2_PRS_RI_L3_PROTO_MASK
);
2500 mvpp2_prs_hw_write(priv
, &pe
);
2505 /* Configure vlan entries and detect up to 2 successive VLAN tags.
2512 static int mvpp2_prs_vlan_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
2514 struct mvpp2_prs_entry pe
;
2517 priv
->prs_double_vlans
= devm_kcalloc(&pdev
->dev
, sizeof(bool),
2518 MVPP2_PRS_DBL_VLANS_MAX
,
2520 if (!priv
->prs_double_vlans
)
2523 /* Double VLAN: 0x8100, 0x88A8 */
2524 err
= mvpp2_prs_double_vlan_add(priv
, ETH_P_8021Q
, ETH_P_8021AD
,
2525 MVPP2_PRS_PORT_MASK
);
2529 /* Double VLAN: 0x8100, 0x8100 */
2530 err
= mvpp2_prs_double_vlan_add(priv
, ETH_P_8021Q
, ETH_P_8021Q
,
2531 MVPP2_PRS_PORT_MASK
);
2535 /* Single VLAN: 0x88a8 */
2536 err
= mvpp2_prs_vlan_add(priv
, ETH_P_8021AD
, MVPP2_PRS_SINGLE_VLAN_AI
,
2537 MVPP2_PRS_PORT_MASK
);
2541 /* Single VLAN: 0x8100 */
2542 err
= mvpp2_prs_vlan_add(priv
, ETH_P_8021Q
, MVPP2_PRS_SINGLE_VLAN_AI
,
2543 MVPP2_PRS_PORT_MASK
);
2547 /* Set default double vlan entry */
2548 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2549 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2550 pe
.index
= MVPP2_PE_VLAN_DBL
;
2552 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2553 /* Clear ai for next iterations */
2554 mvpp2_prs_sram_ai_update(&pe
, 0, MVPP2_PRS_SRAM_AI_MASK
);
2555 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_DOUBLE
,
2556 MVPP2_PRS_RI_VLAN_MASK
);
2558 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_DBL_VLAN_AI_BIT
,
2559 MVPP2_PRS_DBL_VLAN_AI_BIT
);
2560 /* Unmask all ports */
2561 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2563 /* Update shadow table and hw entry */
2564 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_VLAN
);
2565 mvpp2_prs_hw_write(priv
, &pe
);
2567 /* Set default vlan none entry */
2568 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2569 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_VLAN
);
2570 pe
.index
= MVPP2_PE_VLAN_NONE
;
2572 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2573 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_VLAN_NONE
,
2574 MVPP2_PRS_RI_VLAN_MASK
);
2576 /* Unmask all ports */
2577 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2579 /* Update shadow table and hw entry */
2580 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_VLAN
);
2581 mvpp2_prs_hw_write(priv
, &pe
);
2586 /* Set entries for PPPoE ethertype */
2587 static int mvpp2_prs_pppoe_init(struct mvpp2
*priv
)
2589 struct mvpp2_prs_entry pe
;
2592 /* IPv4 over PPPoE with options */
2593 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2594 MVPP2_PE_LAST_FREE_TID
);
2598 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2599 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
2602 mvpp2_prs_match_etype(&pe
, 0, PPP_IP
);
2604 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2605 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
2606 MVPP2_PRS_RI_L3_PROTO_MASK
);
2607 /* Skip eth_type + 4 bytes of IP header */
2608 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
2609 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2611 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2613 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2615 /* Update shadow table and hw entry */
2616 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
2617 mvpp2_prs_hw_write(priv
, &pe
);
2619 /* IPv4 over PPPoE without options */
2620 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2621 MVPP2_PE_LAST_FREE_TID
);
2627 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
2628 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
2629 MVPP2_PRS_IPV4_HEAD_MASK
|
2630 MVPP2_PRS_IPV4_IHL_MASK
);
2632 /* Clear ri before updating */
2633 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
2634 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
2635 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
2636 MVPP2_PRS_RI_L3_PROTO_MASK
);
2638 /* Update shadow table and hw entry */
2639 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
2640 mvpp2_prs_hw_write(priv
, &pe
);
2642 /* IPv6 over PPPoE */
2643 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2644 MVPP2_PE_LAST_FREE_TID
);
2648 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2649 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
2652 mvpp2_prs_match_etype(&pe
, 0, PPP_IPV6
);
2654 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2655 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
2656 MVPP2_PRS_RI_L3_PROTO_MASK
);
2657 /* Skip eth_type + 4 bytes of IPv6 header */
2658 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
2659 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2661 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2663 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2665 /* Update shadow table and hw entry */
2666 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
2667 mvpp2_prs_hw_write(priv
, &pe
);
2669 /* Non-IP over PPPoE */
2670 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2671 MVPP2_PE_LAST_FREE_TID
);
2675 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2676 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
2679 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
2680 MVPP2_PRS_RI_L3_PROTO_MASK
);
2682 /* Finished: go to flowid generation */
2683 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2684 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2685 /* Set L3 offset even if it's unknown L3 */
2686 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2688 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2690 /* Update shadow table and hw entry */
2691 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_PPPOE
);
2692 mvpp2_prs_hw_write(priv
, &pe
);
2697 /* Initialize entries for IPv4 */
2698 static int mvpp2_prs_ip4_init(struct mvpp2
*priv
)
2700 struct mvpp2_prs_entry pe
;
2703 /* Set entries for TCP, UDP and IGMP over IPv4 */
2704 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_TCP
, MVPP2_PRS_RI_L4_TCP
,
2705 MVPP2_PRS_RI_L4_PROTO_MASK
);
2709 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_UDP
, MVPP2_PRS_RI_L4_UDP
,
2710 MVPP2_PRS_RI_L4_PROTO_MASK
);
2714 err
= mvpp2_prs_ip4_proto(priv
, IPPROTO_IGMP
,
2715 MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2716 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2717 MVPP2_PRS_RI_CPU_CODE_MASK
|
2718 MVPP2_PRS_RI_UDF3_MASK
);
2722 /* IPv4 Broadcast */
2723 err
= mvpp2_prs_ip4_cast(priv
, MVPP2_PRS_L3_BROAD_CAST
);
2727 /* IPv4 Multicast */
2728 err
= mvpp2_prs_ip4_cast(priv
, MVPP2_PRS_L3_MULTI_CAST
);
2732 /* Default IPv4 entry for unknown protocols */
2733 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2734 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2735 pe
.index
= MVPP2_PE_IP4_PROTO_UN
;
2737 /* Set next lu to IPv4 */
2738 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2739 mvpp2_prs_sram_shift_set(&pe
, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2741 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
2742 sizeof(struct iphdr
) - 4,
2743 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2744 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
2745 MVPP2_PRS_IPV4_DIP_AI_BIT
);
2746 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
2747 MVPP2_PRS_RI_L4_PROTO_MASK
);
2749 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV4_DIP_AI_BIT
);
2750 /* Unmask all ports */
2751 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2753 /* Update shadow table and hw entry */
2754 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2755 mvpp2_prs_hw_write(priv
, &pe
);
2757 /* Default IPv4 entry for unicast address */
2758 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2759 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
2760 pe
.index
= MVPP2_PE_IP4_ADDR_UN
;
2762 /* Finished: go to flowid generation */
2763 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2764 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2765 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UCAST
,
2766 MVPP2_PRS_RI_L3_ADDR_MASK
);
2768 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV4_DIP_AI_BIT
,
2769 MVPP2_PRS_IPV4_DIP_AI_BIT
);
2770 /* Unmask all ports */
2771 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2773 /* Update shadow table and hw entry */
2774 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2775 mvpp2_prs_hw_write(priv
, &pe
);
2780 /* Initialize entries for IPv6 */
2781 static int mvpp2_prs_ip6_init(struct mvpp2
*priv
)
2783 struct mvpp2_prs_entry pe
;
2786 /* Set entries for TCP, UDP and ICMP over IPv6 */
2787 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_TCP
,
2788 MVPP2_PRS_RI_L4_TCP
,
2789 MVPP2_PRS_RI_L4_PROTO_MASK
);
2793 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_UDP
,
2794 MVPP2_PRS_RI_L4_UDP
,
2795 MVPP2_PRS_RI_L4_PROTO_MASK
);
2799 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_ICMPV6
,
2800 MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
2801 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
2802 MVPP2_PRS_RI_CPU_CODE_MASK
|
2803 MVPP2_PRS_RI_UDF3_MASK
);
2807 /* IPv4 is the last header. This is similar case as 6-TCP or 17-UDP */
2808 /* Result Info: UDF7=1, DS lite */
2809 err
= mvpp2_prs_ip6_proto(priv
, IPPROTO_IPIP
,
2810 MVPP2_PRS_RI_UDF7_IP6_LITE
,
2811 MVPP2_PRS_RI_UDF7_MASK
);
2815 /* IPv6 multicast */
2816 err
= mvpp2_prs_ip6_cast(priv
, MVPP2_PRS_L3_MULTI_CAST
);
2820 /* Entry for checking hop limit */
2821 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2822 MVPP2_PE_LAST_FREE_TID
);
2826 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2827 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2830 /* Finished: go to flowid generation */
2831 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2832 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2833 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
|
2834 MVPP2_PRS_RI_DROP_MASK
,
2835 MVPP2_PRS_RI_L3_PROTO_MASK
|
2836 MVPP2_PRS_RI_DROP_MASK
);
2838 mvpp2_prs_tcam_data_byte_set(&pe
, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK
);
2839 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2840 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2842 /* Update shadow table and hw entry */
2843 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2844 mvpp2_prs_hw_write(priv
, &pe
);
2846 /* Default IPv6 entry for unknown protocols */
2847 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2848 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2849 pe
.index
= MVPP2_PE_IP6_PROTO_UN
;
2851 /* Finished: go to flowid generation */
2852 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2853 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2854 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
2855 MVPP2_PRS_RI_L4_PROTO_MASK
);
2856 /* Set L4 offset relatively to our current place */
2857 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L4
,
2858 sizeof(struct ipv6hdr
) - 4,
2859 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2861 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2862 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2863 /* Unmask all ports */
2864 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2866 /* Update shadow table and hw entry */
2867 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2868 mvpp2_prs_hw_write(priv
, &pe
);
2870 /* Default IPv6 entry for unknown ext protocols */
2871 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2872 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2873 pe
.index
= MVPP2_PE_IP6_EXT_PROTO_UN
;
2875 /* Finished: go to flowid generation */
2876 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2877 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2878 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L4_OTHER
,
2879 MVPP2_PRS_RI_L4_PROTO_MASK
);
2881 mvpp2_prs_tcam_ai_update(&pe
, MVPP2_PRS_IPV6_EXT_AI_BIT
,
2882 MVPP2_PRS_IPV6_EXT_AI_BIT
);
2883 /* Unmask all ports */
2884 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2886 /* Update shadow table and hw entry */
2887 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP4
);
2888 mvpp2_prs_hw_write(priv
, &pe
);
2890 /* Default IPv6 entry for unicast address */
2891 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2892 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2893 pe
.index
= MVPP2_PE_IP6_ADDR_UN
;
2895 /* Finished: go to IPv6 again */
2896 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2897 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UCAST
,
2898 MVPP2_PRS_RI_L3_ADDR_MASK
);
2899 mvpp2_prs_sram_ai_update(&pe
, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
,
2900 MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2901 /* Shift back to IPV6 NH */
2902 mvpp2_prs_sram_shift_set(&pe
, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2904 mvpp2_prs_tcam_ai_update(&pe
, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT
);
2905 /* Unmask all ports */
2906 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2908 /* Update shadow table and hw entry */
2909 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_IP6
);
2910 mvpp2_prs_hw_write(priv
, &pe
);
2915 /* Parser default initialization */
2916 static int mvpp2_prs_default_init(struct platform_device
*pdev
,
2921 /* Enable tcam table */
2922 mvpp2_write(priv
, MVPP2_PRS_TCAM_CTRL_REG
, MVPP2_PRS_TCAM_EN_MASK
);
2924 /* Clear all tcam and sram entries */
2925 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++) {
2926 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
2927 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
2928 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), 0);
2930 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, index
);
2931 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
2932 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), 0);
2935 /* Invalidate all tcam entries */
2936 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++)
2937 mvpp2_prs_hw_inv(priv
, index
);
2939 priv
->prs_shadow
= devm_kcalloc(&pdev
->dev
, MVPP2_PRS_TCAM_SRAM_SIZE
,
2940 sizeof(struct mvpp2_prs_shadow
),
2942 if (!priv
->prs_shadow
)
2945 /* Always start from lookup = 0 */
2946 for (index
= 0; index
< MVPP2_MAX_PORTS
; index
++)
2947 mvpp2_prs_hw_port_init(priv
, index
, MVPP2_PRS_LU_MH
,
2948 MVPP2_PRS_PORT_LU_MAX
, 0);
2950 mvpp2_prs_def_flow_init(priv
);
2952 mvpp2_prs_mh_init(priv
);
2954 mvpp2_prs_mac_init(priv
);
2956 mvpp2_prs_dsa_init(priv
);
2958 err
= mvpp2_prs_etype_init(priv
);
2962 err
= mvpp2_prs_vlan_init(pdev
, priv
);
2966 err
= mvpp2_prs_pppoe_init(priv
);
2970 err
= mvpp2_prs_ip6_init(priv
);
2974 err
= mvpp2_prs_ip4_init(priv
);
2981 /* Compare MAC DA with tcam entry data */
2982 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry
*pe
,
2983 const u8
*da
, unsigned char *mask
)
2985 unsigned char tcam_byte
, tcam_mask
;
2988 for (index
= 0; index
< ETH_ALEN
; index
++) {
2989 mvpp2_prs_tcam_data_byte_get(pe
, index
, &tcam_byte
, &tcam_mask
);
2990 if (tcam_mask
!= mask
[index
])
2993 if ((tcam_mask
& tcam_byte
) != (da
[index
] & mask
[index
]))
3000 /* Find tcam entry with matched pair <MAC DA, port> */
3001 static struct mvpp2_prs_entry
*
3002 mvpp2_prs_mac_da_range_find(struct mvpp2
*priv
, int pmap
, const u8
*da
,
3003 unsigned char *mask
, int udf_type
)
3005 struct mvpp2_prs_entry
*pe
;
3008 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
3011 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
3013 /* Go through the all entires with MVPP2_PRS_LU_MAC */
3014 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3015 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
3016 unsigned int entry_pmap
;
3018 if (!priv
->prs_shadow
[tid
].valid
||
3019 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
3020 (priv
->prs_shadow
[tid
].udf
!= udf_type
))
3024 mvpp2_prs_hw_read(priv
, pe
);
3025 entry_pmap
= mvpp2_prs_tcam_port_map_get(pe
);
3027 if (mvpp2_prs_mac_range_equals(pe
, da
, mask
) &&
3036 /* Update parser's mac da entry */
3037 static int mvpp2_prs_mac_da_accept(struct mvpp2
*priv
, int port
,
3038 const u8
*da
, bool add
)
3040 struct mvpp2_prs_entry
*pe
;
3041 unsigned int pmap
, len
, ri
;
3042 unsigned char mask
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3045 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
3046 pe
= mvpp2_prs_mac_da_range_find(priv
, (1 << port
), da
, mask
,
3047 MVPP2_PRS_UDF_MAC_DEF
);
3054 /* Create new TCAM entry */
3055 /* Find first range mac entry*/
3056 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3057 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++)
3058 if (priv
->prs_shadow
[tid
].valid
&&
3059 (priv
->prs_shadow
[tid
].lu
== MVPP2_PRS_LU_MAC
) &&
3060 (priv
->prs_shadow
[tid
].udf
==
3061 MVPP2_PRS_UDF_MAC_RANGE
))
3064 /* Go through the all entries from first to last */
3065 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
3070 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
3073 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
3076 /* Mask all ports */
3077 mvpp2_prs_tcam_port_map_set(pe
, 0);
3080 /* Update port mask */
3081 mvpp2_prs_tcam_port_set(pe
, port
, add
);
3083 /* Invalidate the entry if no ports are left enabled */
3084 pmap
= mvpp2_prs_tcam_port_map_get(pe
);
3090 mvpp2_prs_hw_inv(priv
, pe
->index
);
3091 priv
->prs_shadow
[pe
->index
].valid
= false;
3096 /* Continue - set next lookup */
3097 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_DSA
);
3099 /* Set match on DA */
3102 mvpp2_prs_tcam_data_byte_set(pe
, len
, da
[len
], 0xff);
3104 /* Set result info bits */
3105 if (is_broadcast_ether_addr(da
))
3106 ri
= MVPP2_PRS_RI_L2_BCAST
;
3107 else if (is_multicast_ether_addr(da
))
3108 ri
= MVPP2_PRS_RI_L2_MCAST
;
3110 ri
= MVPP2_PRS_RI_L2_UCAST
| MVPP2_PRS_RI_MAC_ME_MASK
;
3112 mvpp2_prs_sram_ri_update(pe
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
3113 MVPP2_PRS_RI_MAC_ME_MASK
);
3114 mvpp2_prs_shadow_ri_set(priv
, pe
->index
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
3115 MVPP2_PRS_RI_MAC_ME_MASK
);
3117 /* Shift to ethertype */
3118 mvpp2_prs_sram_shift_set(pe
, 2 * ETH_ALEN
,
3119 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
3121 /* Update shadow table and hw entry */
3122 priv
->prs_shadow
[pe
->index
].udf
= MVPP2_PRS_UDF_MAC_DEF
;
3123 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_MAC
);
3124 mvpp2_prs_hw_write(priv
, pe
);
3131 static int mvpp2_prs_update_mac_da(struct net_device
*dev
, const u8
*da
)
3133 struct mvpp2_port
*port
= netdev_priv(dev
);
3136 /* Remove old parser entry */
3137 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, dev
->dev_addr
,
3142 /* Add new parser entry */
3143 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, da
, true);
3147 /* Set addr in the device */
3148 ether_addr_copy(dev
->dev_addr
, da
);
3153 /* Delete all port's multicast simple (not range) entries */
3154 static void mvpp2_prs_mcast_del_all(struct mvpp2
*priv
, int port
)
3156 struct mvpp2_prs_entry pe
;
3159 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
3160 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
3161 unsigned char da
[ETH_ALEN
], da_mask
[ETH_ALEN
];
3163 if (!priv
->prs_shadow
[tid
].valid
||
3164 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
3165 (priv
->prs_shadow
[tid
].udf
!= MVPP2_PRS_UDF_MAC_DEF
))
3168 /* Only simple mac entries */
3170 mvpp2_prs_hw_read(priv
, &pe
);
3172 /* Read mac addr from entry */
3173 for (index
= 0; index
< ETH_ALEN
; index
++)
3174 mvpp2_prs_tcam_data_byte_get(&pe
, index
, &da
[index
],
3177 if (is_multicast_ether_addr(da
) && !is_broadcast_ether_addr(da
))
3178 /* Delete this entry */
3179 mvpp2_prs_mac_da_accept(priv
, port
, da
, false);
3183 static int mvpp2_prs_tag_mode_set(struct mvpp2
*priv
, int port
, int type
)
3186 case MVPP2_TAG_TYPE_EDSA
:
3187 /* Add port to EDSA entries */
3188 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3189 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3190 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3191 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3192 /* Remove port from DSA entries */
3193 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3194 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3195 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3196 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3199 case MVPP2_TAG_TYPE_DSA
:
3200 /* Add port to DSA entries */
3201 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3202 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3203 mvpp2_prs_dsa_tag_set(priv
, port
, true,
3204 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3205 /* Remove port from EDSA entries */
3206 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3207 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3208 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3209 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3212 case MVPP2_TAG_TYPE_MH
:
3213 case MVPP2_TAG_TYPE_NONE
:
3214 /* Remove port form EDSA and DSA entries */
3215 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3216 MVPP2_PRS_TAGGED
, MVPP2_PRS_DSA
);
3217 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3218 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_DSA
);
3219 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3220 MVPP2_PRS_TAGGED
, MVPP2_PRS_EDSA
);
3221 mvpp2_prs_dsa_tag_set(priv
, port
, false,
3222 MVPP2_PRS_UNTAGGED
, MVPP2_PRS_EDSA
);
3226 if ((type
< 0) || (type
> MVPP2_TAG_TYPE_EDSA
))
3233 /* Set prs flow for the port */
3234 static int mvpp2_prs_def_flow(struct mvpp2_port
*port
)
3236 struct mvpp2_prs_entry
*pe
;
3239 pe
= mvpp2_prs_flow_find(port
->priv
, port
->id
);
3241 /* Such entry not exist */
3243 /* Go through the all entires from last to first */
3244 tid
= mvpp2_prs_tcam_first_free(port
->priv
,
3245 MVPP2_PE_LAST_FREE_TID
,
3246 MVPP2_PE_FIRST_FREE_TID
);
3250 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
3254 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
3258 mvpp2_prs_sram_ai_update(pe
, port
->id
, MVPP2_PRS_FLOW_ID_MASK
);
3259 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
3261 /* Update shadow table */
3262 mvpp2_prs_shadow_set(port
->priv
, pe
->index
, MVPP2_PRS_LU_FLOWS
);
3265 mvpp2_prs_tcam_port_map_set(pe
, (1 << port
->id
));
3266 mvpp2_prs_hw_write(port
->priv
, pe
);
3272 /* Classifier configuration routines */
3274 /* Update classification flow table registers */
3275 static void mvpp2_cls_flow_write(struct mvpp2
*priv
,
3276 struct mvpp2_cls_flow_entry
*fe
)
3278 mvpp2_write(priv
, MVPP2_CLS_FLOW_INDEX_REG
, fe
->index
);
3279 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL0_REG
, fe
->data
[0]);
3280 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL1_REG
, fe
->data
[1]);
3281 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL2_REG
, fe
->data
[2]);
3284 /* Update classification lookup table register */
3285 static void mvpp2_cls_lookup_write(struct mvpp2
*priv
,
3286 struct mvpp2_cls_lookup_entry
*le
)
3290 val
= (le
->way
<< MVPP2_CLS_LKP_INDEX_WAY_OFFS
) | le
->lkpid
;
3291 mvpp2_write(priv
, MVPP2_CLS_LKP_INDEX_REG
, val
);
3292 mvpp2_write(priv
, MVPP2_CLS_LKP_TBL_REG
, le
->data
);
3295 /* Classifier default initialization */
3296 static void mvpp2_cls_init(struct mvpp2
*priv
)
3298 struct mvpp2_cls_lookup_entry le
;
3299 struct mvpp2_cls_flow_entry fe
;
3302 /* Enable classifier */
3303 mvpp2_write(priv
, MVPP2_CLS_MODE_REG
, MVPP2_CLS_MODE_ACTIVE_MASK
);
3305 /* Clear classifier flow table */
3306 memset(&fe
.data
, 0, sizeof(fe
.data
));
3307 for (index
= 0; index
< MVPP2_CLS_FLOWS_TBL_SIZE
; index
++) {
3309 mvpp2_cls_flow_write(priv
, &fe
);
3312 /* Clear classifier lookup table */
3314 for (index
= 0; index
< MVPP2_CLS_LKP_TBL_SIZE
; index
++) {
3317 mvpp2_cls_lookup_write(priv
, &le
);
3320 mvpp2_cls_lookup_write(priv
, &le
);
3324 static void mvpp2_cls_port_config(struct mvpp2_port
*port
)
3326 struct mvpp2_cls_lookup_entry le
;
3329 /* Set way for the port */
3330 val
= mvpp2_read(port
->priv
, MVPP2_CLS_PORT_WAY_REG
);
3331 val
&= ~MVPP2_CLS_PORT_WAY_MASK(port
->id
);
3332 mvpp2_write(port
->priv
, MVPP2_CLS_PORT_WAY_REG
, val
);
3334 /* Pick the entry to be accessed in lookup ID decoding table
3335 * according to the way and lkpid.
3337 le
.lkpid
= port
->id
;
3341 /* Set initial CPU queue for receiving packets */
3342 le
.data
&= ~MVPP2_CLS_LKP_TBL_RXQ_MASK
;
3343 le
.data
|= port
->first_rxq
;
3345 /* Disable classification engines */
3346 le
.data
&= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK
;
3348 /* Update lookup ID table entry */
3349 mvpp2_cls_lookup_write(port
->priv
, &le
);
3352 /* Set CPU queue number for oversize packets */
3353 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port
*port
)
3357 mvpp2_write(port
->priv
, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port
->id
),
3358 port
->first_rxq
& MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK
);
3360 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_P2HQ_REG(port
->id
),
3361 (port
->first_rxq
>> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS
));
3363 val
= mvpp2_read(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
);
3364 val
|= MVPP2_CLS_SWFWD_PCTRL_MASK(port
->id
);
3365 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
, val
);
3368 /* Buffer Manager configuration routines */
3371 static int mvpp2_bm_pool_create(struct platform_device
*pdev
,
3373 struct mvpp2_bm_pool
*bm_pool
, int size
)
3378 size_bytes
= sizeof(u32
) * size
;
3379 bm_pool
->virt_addr
= dma_alloc_coherent(&pdev
->dev
, size_bytes
,
3380 &bm_pool
->phys_addr
,
3382 if (!bm_pool
->virt_addr
)
3385 if (!IS_ALIGNED((u32
)bm_pool
->virt_addr
, MVPP2_BM_POOL_PTR_ALIGN
)) {
3386 dma_free_coherent(&pdev
->dev
, size_bytes
, bm_pool
->virt_addr
,
3387 bm_pool
->phys_addr
);
3388 dev_err(&pdev
->dev
, "BM pool %d is not %d bytes aligned\n",
3389 bm_pool
->id
, MVPP2_BM_POOL_PTR_ALIGN
);
3393 mvpp2_write(priv
, MVPP2_BM_POOL_BASE_REG(bm_pool
->id
),
3394 bm_pool
->phys_addr
);
3395 mvpp2_write(priv
, MVPP2_BM_POOL_SIZE_REG(bm_pool
->id
), size
);
3397 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
3398 val
|= MVPP2_BM_START_MASK
;
3399 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
3401 bm_pool
->type
= MVPP2_BM_FREE
;
3402 bm_pool
->size
= size
;
3403 bm_pool
->pkt_size
= 0;
3404 bm_pool
->buf_num
= 0;
3405 atomic_set(&bm_pool
->in_use
, 0);
3410 /* Set pool buffer size */
3411 static void mvpp2_bm_pool_bufsize_set(struct mvpp2
*priv
,
3412 struct mvpp2_bm_pool
*bm_pool
,
3417 bm_pool
->buf_size
= buf_size
;
3419 val
= ALIGN(buf_size
, 1 << MVPP2_POOL_BUF_SIZE_OFFSET
);
3420 mvpp2_write(priv
, MVPP2_POOL_BUF_SIZE_REG(bm_pool
->id
), val
);
3423 /* Free all buffers from the pool */
3424 static void mvpp2_bm_bufs_free(struct device
*dev
, struct mvpp2
*priv
,
3425 struct mvpp2_bm_pool
*bm_pool
)
3429 for (i
= 0; i
< bm_pool
->buf_num
; i
++) {
3430 dma_addr_t buf_phys_addr
;
3433 /* Get buffer virtual address (indirect access) */
3434 buf_phys_addr
= mvpp2_read(priv
,
3435 MVPP2_BM_PHY_ALLOC_REG(bm_pool
->id
));
3436 vaddr
= mvpp2_read(priv
, MVPP2_BM_VIRT_ALLOC_REG
);
3438 dma_unmap_single(dev
, buf_phys_addr
,
3439 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
3443 dev_kfree_skb_any((struct sk_buff
*)vaddr
);
3446 /* Update BM driver with number of buffers removed from pool */
3447 bm_pool
->buf_num
-= i
;
3451 static int mvpp2_bm_pool_destroy(struct platform_device
*pdev
,
3453 struct mvpp2_bm_pool
*bm_pool
)
3457 mvpp2_bm_bufs_free(&pdev
->dev
, priv
, bm_pool
);
3458 if (bm_pool
->buf_num
) {
3459 WARN(1, "cannot free all buffers in pool %d\n", bm_pool
->id
);
3463 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
3464 val
|= MVPP2_BM_STOP_MASK
;
3465 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
3467 dma_free_coherent(&pdev
->dev
, sizeof(u32
) * bm_pool
->size
,
3469 bm_pool
->phys_addr
);
3473 static int mvpp2_bm_pools_init(struct platform_device
*pdev
,
3477 struct mvpp2_bm_pool
*bm_pool
;
3479 /* Create all pools with maximum size */
3480 size
= MVPP2_BM_POOL_SIZE_MAX
;
3481 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
3482 bm_pool
= &priv
->bm_pools
[i
];
3484 err
= mvpp2_bm_pool_create(pdev
, priv
, bm_pool
, size
);
3486 goto err_unroll_pools
;
3487 mvpp2_bm_pool_bufsize_set(priv
, bm_pool
, 0);
3492 dev_err(&pdev
->dev
, "failed to create BM pool %d, size %d\n", i
, size
);
3493 for (i
= i
- 1; i
>= 0; i
--)
3494 mvpp2_bm_pool_destroy(pdev
, priv
, &priv
->bm_pools
[i
]);
3498 static int mvpp2_bm_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
3502 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
3503 /* Mask BM all interrupts */
3504 mvpp2_write(priv
, MVPP2_BM_INTR_MASK_REG(i
), 0);
3505 /* Clear BM cause register */
3506 mvpp2_write(priv
, MVPP2_BM_INTR_CAUSE_REG(i
), 0);
3509 /* Allocate and initialize BM pools */
3510 priv
->bm_pools
= devm_kcalloc(&pdev
->dev
, MVPP2_BM_POOLS_NUM
,
3511 sizeof(struct mvpp2_bm_pool
), GFP_KERNEL
);
3512 if (!priv
->bm_pools
)
3515 err
= mvpp2_bm_pools_init(pdev
, priv
);
3521 /* Attach long pool to rxq */
3522 static void mvpp2_rxq_long_pool_set(struct mvpp2_port
*port
,
3523 int lrxq
, int long_pool
)
3528 /* Get queue physical ID */
3529 prxq
= port
->rxqs
[lrxq
]->id
;
3531 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
3532 val
&= ~MVPP2_RXQ_POOL_LONG_MASK
;
3533 val
|= ((long_pool
<< MVPP2_RXQ_POOL_LONG_OFFS
) &
3534 MVPP2_RXQ_POOL_LONG_MASK
);
3536 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
3539 /* Attach short pool to rxq */
3540 static void mvpp2_rxq_short_pool_set(struct mvpp2_port
*port
,
3541 int lrxq
, int short_pool
)
3546 /* Get queue physical ID */
3547 prxq
= port
->rxqs
[lrxq
]->id
;
3549 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
3550 val
&= ~MVPP2_RXQ_POOL_SHORT_MASK
;
3551 val
|= ((short_pool
<< MVPP2_RXQ_POOL_SHORT_OFFS
) &
3552 MVPP2_RXQ_POOL_SHORT_MASK
);
3554 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
3557 /* Allocate skb for BM pool */
3558 static struct sk_buff
*mvpp2_skb_alloc(struct mvpp2_port
*port
,
3559 struct mvpp2_bm_pool
*bm_pool
,
3560 dma_addr_t
*buf_phys_addr
,
3563 struct sk_buff
*skb
;
3564 dma_addr_t phys_addr
;
3566 skb
= __dev_alloc_skb(bm_pool
->pkt_size
, gfp_mask
);
3570 phys_addr
= dma_map_single(port
->dev
->dev
.parent
, skb
->head
,
3571 MVPP2_RX_BUF_SIZE(bm_pool
->pkt_size
),
3573 if (unlikely(dma_mapping_error(port
->dev
->dev
.parent
, phys_addr
))) {
3574 dev_kfree_skb_any(skb
);
3577 *buf_phys_addr
= phys_addr
;
3582 /* Set pool number in a BM cookie */
3583 static inline u32
mvpp2_bm_cookie_pool_set(u32 cookie
, int pool
)
3587 bm
= cookie
& ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS
);
3588 bm
|= ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
);
3593 /* Get pool number from a BM cookie */
3594 static inline int mvpp2_bm_cookie_pool_get(u32 cookie
)
3596 return (cookie
>> MVPP2_BM_COOKIE_POOL_OFFS
) & 0xFF;
3599 /* Release buffer to BM */
3600 static inline void mvpp2_bm_pool_put(struct mvpp2_port
*port
, int pool
,
3601 u32 buf_phys_addr
, u32 buf_virt_addr
)
3603 mvpp2_write(port
->priv
, MVPP2_BM_VIRT_RLS_REG
, buf_virt_addr
);
3604 mvpp2_write(port
->priv
, MVPP2_BM_PHY_RLS_REG(pool
), buf_phys_addr
);
3607 /* Release multicast buffer */
3608 static void mvpp2_bm_pool_mc_put(struct mvpp2_port
*port
, int pool
,
3609 u32 buf_phys_addr
, u32 buf_virt_addr
,
3614 val
|= (mc_id
& MVPP2_BM_MC_ID_MASK
);
3615 mvpp2_write(port
->priv
, MVPP2_BM_MC_RLS_REG
, val
);
3617 mvpp2_bm_pool_put(port
, pool
,
3618 buf_phys_addr
| MVPP2_BM_PHY_RLS_MC_BUFF_MASK
,
3622 /* Refill BM pool */
3623 static void mvpp2_pool_refill(struct mvpp2_port
*port
, u32 bm
,
3624 u32 phys_addr
, u32 cookie
)
3626 int pool
= mvpp2_bm_cookie_pool_get(bm
);
3628 mvpp2_bm_pool_put(port
, pool
, phys_addr
, cookie
);
3631 /* Allocate buffers for the pool */
3632 static int mvpp2_bm_bufs_add(struct mvpp2_port
*port
,
3633 struct mvpp2_bm_pool
*bm_pool
, int buf_num
)
3635 struct sk_buff
*skb
;
3636 int i
, buf_size
, total_size
;
3638 dma_addr_t phys_addr
;
3640 buf_size
= MVPP2_RX_BUF_SIZE(bm_pool
->pkt_size
);
3641 total_size
= MVPP2_RX_TOTAL_SIZE(buf_size
);
3644 (buf_num
+ bm_pool
->buf_num
> bm_pool
->size
)) {
3645 netdev_err(port
->dev
,
3646 "cannot allocate %d buffers for pool %d\n",
3647 buf_num
, bm_pool
->id
);
3651 bm
= mvpp2_bm_cookie_pool_set(0, bm_pool
->id
);
3652 for (i
= 0; i
< buf_num
; i
++) {
3653 skb
= mvpp2_skb_alloc(port
, bm_pool
, &phys_addr
, GFP_KERNEL
);
3657 mvpp2_pool_refill(port
, bm
, (u32
)phys_addr
, (u32
)skb
);
3660 /* Update BM driver with number of buffers added to pool */
3661 bm_pool
->buf_num
+= i
;
3662 bm_pool
->in_use_thresh
= bm_pool
->buf_num
/ 4;
3664 netdev_dbg(port
->dev
,
3665 "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
3666 bm_pool
->type
== MVPP2_BM_SWF_SHORT
? "short" : " long",
3667 bm_pool
->id
, bm_pool
->pkt_size
, buf_size
, total_size
);
3669 netdev_dbg(port
->dev
,
3670 "%s pool %d: %d of %d buffers added\n",
3671 bm_pool
->type
== MVPP2_BM_SWF_SHORT
? "short" : " long",
3672 bm_pool
->id
, i
, buf_num
);
3676 /* Notify the driver that BM pool is being used as specific type and return the
3677 * pool pointer on success
3679 static struct mvpp2_bm_pool
*
3680 mvpp2_bm_pool_use(struct mvpp2_port
*port
, int pool
, enum mvpp2_bm_type type
,
3683 struct mvpp2_bm_pool
*new_pool
= &port
->priv
->bm_pools
[pool
];
3686 if (new_pool
->type
!= MVPP2_BM_FREE
&& new_pool
->type
!= type
) {
3687 netdev_err(port
->dev
, "mixing pool types is forbidden\n");
3691 if (new_pool
->type
== MVPP2_BM_FREE
)
3692 new_pool
->type
= type
;
3694 /* Allocate buffers in case BM pool is used as long pool, but packet
3695 * size doesn't match MTU or BM pool hasn't being used yet
3697 if (((type
== MVPP2_BM_SWF_LONG
) && (pkt_size
> new_pool
->pkt_size
)) ||
3698 (new_pool
->pkt_size
== 0)) {
3701 /* Set default buffer number or free all the buffers in case
3702 * the pool is not empty
3704 pkts_num
= new_pool
->buf_num
;
3706 pkts_num
= type
== MVPP2_BM_SWF_LONG
?
3707 MVPP2_BM_LONG_BUF_NUM
:
3708 MVPP2_BM_SHORT_BUF_NUM
;
3710 mvpp2_bm_bufs_free(port
->dev
->dev
.parent
,
3711 port
->priv
, new_pool
);
3713 new_pool
->pkt_size
= pkt_size
;
3715 /* Allocate buffers for this pool */
3716 num
= mvpp2_bm_bufs_add(port
, new_pool
, pkts_num
);
3717 if (num
!= pkts_num
) {
3718 WARN(1, "pool %d: %d of %d allocated\n",
3719 new_pool
->id
, num
, pkts_num
);
3724 mvpp2_bm_pool_bufsize_set(port
->priv
, new_pool
,
3725 MVPP2_RX_BUF_SIZE(new_pool
->pkt_size
));
3730 /* Initialize pools for swf */
3731 static int mvpp2_swf_bm_pool_init(struct mvpp2_port
*port
)
3735 if (!port
->pool_long
) {
3737 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_LONG_POOL(port
->id
),
3740 if (!port
->pool_long
)
3743 port
->pool_long
->port_map
|= (1 << port
->id
);
3745 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
3746 mvpp2_rxq_long_pool_set(port
, rxq
, port
->pool_long
->id
);
3749 if (!port
->pool_short
) {
3751 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_SHORT_POOL
,
3753 MVPP2_BM_SHORT_PKT_SIZE
);
3754 if (!port
->pool_short
)
3757 port
->pool_short
->port_map
|= (1 << port
->id
);
3759 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
3760 mvpp2_rxq_short_pool_set(port
, rxq
,
3761 port
->pool_short
->id
);
3767 static int mvpp2_bm_update_mtu(struct net_device
*dev
, int mtu
)
3769 struct mvpp2_port
*port
= netdev_priv(dev
);
3770 struct mvpp2_bm_pool
*port_pool
= port
->pool_long
;
3771 int num
, pkts_num
= port_pool
->buf_num
;
3772 int pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
3774 /* Update BM pool with new buffer size */
3775 mvpp2_bm_bufs_free(dev
->dev
.parent
, port
->priv
, port_pool
);
3776 if (port_pool
->buf_num
) {
3777 WARN(1, "cannot free all buffers in pool %d\n", port_pool
->id
);
3781 port_pool
->pkt_size
= pkt_size
;
3782 num
= mvpp2_bm_bufs_add(port
, port_pool
, pkts_num
);
3783 if (num
!= pkts_num
) {
3784 WARN(1, "pool %d: %d of %d allocated\n",
3785 port_pool
->id
, num
, pkts_num
);
3789 mvpp2_bm_pool_bufsize_set(port
->priv
, port_pool
,
3790 MVPP2_RX_BUF_SIZE(port_pool
->pkt_size
));
3792 netdev_update_features(dev
);
3796 static inline void mvpp2_interrupts_enable(struct mvpp2_port
*port
)
3798 int cpu
, cpu_mask
= 0;
3800 for_each_present_cpu(cpu
)
3801 cpu_mask
|= 1 << cpu
;
3802 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
3803 MVPP2_ISR_ENABLE_INTERRUPT(cpu_mask
));
3806 static inline void mvpp2_interrupts_disable(struct mvpp2_port
*port
)
3808 int cpu
, cpu_mask
= 0;
3810 for_each_present_cpu(cpu
)
3811 cpu_mask
|= 1 << cpu
;
3812 mvpp2_write(port
->priv
, MVPP2_ISR_ENABLE_REG(port
->id
),
3813 MVPP2_ISR_DISABLE_INTERRUPT(cpu_mask
));
3816 /* Mask the current CPU's Rx/Tx interrupts */
3817 static void mvpp2_interrupts_mask(void *arg
)
3819 struct mvpp2_port
*port
= arg
;
3821 mvpp2_write(port
->priv
, MVPP2_ISR_RX_TX_MASK_REG(port
->id
), 0);
3824 /* Unmask the current CPU's Rx/Tx interrupts */
3825 static void mvpp2_interrupts_unmask(void *arg
)
3827 struct mvpp2_port
*port
= arg
;
3829 mvpp2_write(port
->priv
, MVPP2_ISR_RX_TX_MASK_REG(port
->id
),
3830 (MVPP2_CAUSE_MISC_SUM_MASK
|
3831 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
));
3834 /* Port configuration routines */
3836 static void mvpp2_port_mii_set(struct mvpp2_port
*port
)
3840 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
3842 switch (port
->phy_interface
) {
3843 case PHY_INTERFACE_MODE_SGMII
:
3844 val
|= MVPP2_GMAC_INBAND_AN_MASK
;
3846 case PHY_INTERFACE_MODE_RGMII
:
3847 val
|= MVPP2_GMAC_PORT_RGMII_MASK
;
3849 val
&= ~MVPP2_GMAC_PCS_ENABLE_MASK
;
3852 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
3855 static void mvpp2_port_fc_adv_enable(struct mvpp2_port
*port
)
3859 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3860 val
|= MVPP2_GMAC_FC_ADV_EN
;
3861 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3864 static void mvpp2_port_enable(struct mvpp2_port
*port
)
3868 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3869 val
|= MVPP2_GMAC_PORT_EN_MASK
;
3870 val
|= MVPP2_GMAC_MIB_CNTR_EN_MASK
;
3871 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3874 static void mvpp2_port_disable(struct mvpp2_port
*port
)
3878 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3879 val
&= ~(MVPP2_GMAC_PORT_EN_MASK
);
3880 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3883 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
3884 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port
*port
)
3888 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
) &
3889 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK
;
3890 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
3893 /* Configure loopback port */
3894 static void mvpp2_port_loopback_set(struct mvpp2_port
*port
)
3898 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
3900 if (port
->speed
== 1000)
3901 val
|= MVPP2_GMAC_GMII_LB_EN_MASK
;
3903 val
&= ~MVPP2_GMAC_GMII_LB_EN_MASK
;
3905 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
3906 val
|= MVPP2_GMAC_PCS_LB_EN_MASK
;
3908 val
&= ~MVPP2_GMAC_PCS_LB_EN_MASK
;
3910 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
3913 static void mvpp2_port_reset(struct mvpp2_port
*port
)
3917 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
3918 ~MVPP2_GMAC_PORT_RESET_MASK
;
3919 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
3921 while (readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
3922 MVPP2_GMAC_PORT_RESET_MASK
)
3926 /* Change maximum receive size of the port */
3927 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port
*port
)
3931 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3932 val
&= ~MVPP2_GMAC_MAX_RX_SIZE_MASK
;
3933 val
|= (((port
->pkt_size
- MVPP2_MH_SIZE
) / 2) <<
3934 MVPP2_GMAC_MAX_RX_SIZE_OFFS
);
3935 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
3938 /* Set defaults to the MVPP2 port */
3939 static void mvpp2_defaults_set(struct mvpp2_port
*port
)
3941 int tx_port_num
, val
, queue
, ptxq
, lrxq
;
3943 /* Configure port to loopback if needed */
3944 if (port
->flags
& MVPP2_F_LOOPBACK
)
3945 mvpp2_port_loopback_set(port
);
3947 /* Update TX FIFO MIN Threshold */
3948 val
= readl(port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
3949 val
&= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
;
3950 /* Min. TX threshold must be less than minimal packet length */
3951 val
|= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3952 writel(val
, port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
3954 /* Disable Legacy WRR, Disable EJP, Release from reset */
3955 tx_port_num
= mvpp2_egress_port(port
);
3956 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
,
3958 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_CMD_1_REG
, 0);
3960 /* Close bandwidth for all queues */
3961 for (queue
= 0; queue
< MVPP2_MAX_TXQ
; queue
++) {
3962 ptxq
= mvpp2_txq_phys(port
->id
, queue
);
3963 mvpp2_write(port
->priv
,
3964 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq
), 0);
3967 /* Set refill period to 1 usec, refill tokens
3968 * and bucket size to maximum
3970 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PERIOD_REG
,
3971 port
->priv
->tclk
/ USEC_PER_SEC
);
3972 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
);
3973 val
&= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK
;
3974 val
|= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3975 val
|= MVPP2_TXP_REFILL_TOKENS_ALL_MASK
;
3976 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
, val
);
3977 val
= MVPP2_TXP_TOKEN_SIZE_MAX
;
3978 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
3980 /* Set MaximumLowLatencyPacketSize value to 256 */
3981 mvpp2_write(port
->priv
, MVPP2_RX_CTRL_REG(port
->id
),
3982 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
|
3983 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3985 /* Enable Rx cache snoop */
3986 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
3987 queue
= port
->rxqs
[lrxq
]->id
;
3988 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
3989 val
|= MVPP2_SNOOP_PKT_SIZE_MASK
|
3990 MVPP2_SNOOP_BUF_HDR_MASK
;
3991 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
3994 /* At default, mask all interrupts to all present cpus */
3995 mvpp2_interrupts_disable(port
);
3998 /* Enable/disable receiving packets */
3999 static void mvpp2_ingress_enable(struct mvpp2_port
*port
)
4004 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
4005 queue
= port
->rxqs
[lrxq
]->id
;
4006 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
4007 val
&= ~MVPP2_RXQ_DISABLE_MASK
;
4008 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
4012 static void mvpp2_ingress_disable(struct mvpp2_port
*port
)
4017 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
4018 queue
= port
->rxqs
[lrxq
]->id
;
4019 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
4020 val
|= MVPP2_RXQ_DISABLE_MASK
;
4021 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
4025 /* Enable transmit via physical egress queue
4026 * - HW starts take descriptors from DRAM
4028 static void mvpp2_egress_enable(struct mvpp2_port
*port
)
4032 int tx_port_num
= mvpp2_egress_port(port
);
4034 /* Enable all initialized TXs. */
4036 for (queue
= 0; queue
< txq_number
; queue
++) {
4037 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
4039 if (txq
->descs
!= NULL
)
4040 qmap
|= (1 << queue
);
4043 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
4044 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
, qmap
);
4047 /* Disable transmit via physical egress queue
4048 * - HW doesn't take descriptors from DRAM
4050 static void mvpp2_egress_disable(struct mvpp2_port
*port
)
4054 int tx_port_num
= mvpp2_egress_port(port
);
4056 /* Issue stop command for active channels only */
4057 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
4058 reg_data
= (mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
)) &
4059 MVPP2_TXP_SCHED_ENQ_MASK
;
4061 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
,
4062 (reg_data
<< MVPP2_TXP_SCHED_DISQ_OFFSET
));
4064 /* Wait for all Tx activity to terminate. */
4067 if (delay
>= MVPP2_TX_DISABLE_TIMEOUT_MSEC
) {
4068 netdev_warn(port
->dev
,
4069 "Tx stop timed out, status=0x%08x\n",
4076 /* Check port TX Command register that all
4077 * Tx queues are stopped
4079 reg_data
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
);
4080 } while (reg_data
& MVPP2_TXP_SCHED_ENQ_MASK
);
4083 /* Rx descriptors helper methods */
4085 /* Get number of Rx descriptors occupied by received packets */
4087 mvpp2_rxq_received(struct mvpp2_port
*port
, int rxq_id
)
4089 u32 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq_id
));
4091 return val
& MVPP2_RXQ_OCCUPIED_MASK
;
4094 /* Update Rx queue status with the number of occupied and available
4095 * Rx descriptor slots.
4098 mvpp2_rxq_status_update(struct mvpp2_port
*port
, int rxq_id
,
4099 int used_count
, int free_count
)
4101 /* Decrement the number of used descriptors and increment count
4102 * increment the number of free descriptors.
4104 u32 val
= used_count
| (free_count
<< MVPP2_RXQ_NUM_NEW_OFFSET
);
4106 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id
), val
);
4109 /* Get pointer to next RX descriptor to be processed by SW */
4110 static inline struct mvpp2_rx_desc
*
4111 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue
*rxq
)
4113 int rx_desc
= rxq
->next_desc_to_proc
;
4115 rxq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(rxq
, rx_desc
);
4116 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
4117 return rxq
->descs
+ rx_desc
;
4120 /* Set rx queue offset */
4121 static void mvpp2_rxq_offset_set(struct mvpp2_port
*port
,
4122 int prxq
, int offset
)
4126 /* Convert offset from bytes to units of 32 bytes */
4127 offset
= offset
>> 5;
4129 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
4130 val
&= ~MVPP2_RXQ_PACKET_OFFSET_MASK
;
4133 val
|= ((offset
<< MVPP2_RXQ_PACKET_OFFSET_OFFS
) &
4134 MVPP2_RXQ_PACKET_OFFSET_MASK
);
4136 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
4139 /* Obtain BM cookie information from descriptor */
4140 static u32
mvpp2_bm_cookie_build(struct mvpp2_rx_desc
*rx_desc
)
4142 int pool
= (rx_desc
->status
& MVPP2_RXD_BM_POOL_ID_MASK
) >>
4143 MVPP2_RXD_BM_POOL_ID_OFFS
;
4144 int cpu
= smp_processor_id();
4146 return ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
) |
4147 ((cpu
& 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS
);
4150 /* Tx descriptors helper methods */
4152 /* Get number of Tx descriptors waiting to be transmitted by HW */
4153 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port
*port
,
4154 struct mvpp2_tx_queue
*txq
)
4158 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4159 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
4161 return val
& MVPP2_TXQ_PENDING_MASK
;
4164 /* Get pointer to next Tx descriptor to be processed (send) by HW */
4165 static struct mvpp2_tx_desc
*
4166 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue
*txq
)
4168 int tx_desc
= txq
->next_desc_to_proc
;
4170 txq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(txq
, tx_desc
);
4171 return txq
->descs
+ tx_desc
;
4174 /* Update HW with number of aggregated Tx descriptors to be sent */
4175 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port
*port
, int pending
)
4177 /* aggregated access - relevant TXQ number is written in TX desc */
4178 mvpp2_write(port
->priv
, MVPP2_AGGR_TXQ_UPDATE_REG
, pending
);
4182 /* Check if there are enough free descriptors in aggregated txq.
4183 * If not, update the number of occupied descriptors and repeat the check.
4185 static int mvpp2_aggr_desc_num_check(struct mvpp2
*priv
,
4186 struct mvpp2_tx_queue
*aggr_txq
, int num
)
4188 if ((aggr_txq
->count
+ num
) > aggr_txq
->size
) {
4189 /* Update number of occupied aggregated Tx descriptors */
4190 int cpu
= smp_processor_id();
4191 u32 val
= mvpp2_read(priv
, MVPP2_AGGR_TXQ_STATUS_REG(cpu
));
4193 aggr_txq
->count
= val
& MVPP2_AGGR_TXQ_PENDING_MASK
;
4196 if ((aggr_txq
->count
+ num
) > aggr_txq
->size
)
4202 /* Reserved Tx descriptors allocation request */
4203 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2
*priv
,
4204 struct mvpp2_tx_queue
*txq
, int num
)
4208 val
= (txq
->id
<< MVPP2_TXQ_RSVD_REQ_Q_OFFSET
) | num
;
4209 mvpp2_write(priv
, MVPP2_TXQ_RSVD_REQ_REG
, val
);
4211 val
= mvpp2_read(priv
, MVPP2_TXQ_RSVD_RSLT_REG
);
4213 return val
& MVPP2_TXQ_RSVD_RSLT_MASK
;
4216 /* Check if there are enough reserved descriptors for transmission.
4217 * If not, request chunk of reserved descriptors and check again.
4219 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2
*priv
,
4220 struct mvpp2_tx_queue
*txq
,
4221 struct mvpp2_txq_pcpu
*txq_pcpu
,
4224 int req
, cpu
, desc_count
;
4226 if (txq_pcpu
->reserved_num
>= num
)
4229 /* Not enough descriptors reserved! Update the reserved descriptor
4230 * count and check again.
4234 /* Compute total of used descriptors */
4235 for_each_present_cpu(cpu
) {
4236 struct mvpp2_txq_pcpu
*txq_pcpu_aux
;
4238 txq_pcpu_aux
= per_cpu_ptr(txq
->pcpu
, cpu
);
4239 desc_count
+= txq_pcpu_aux
->count
;
4240 desc_count
+= txq_pcpu_aux
->reserved_num
;
4243 req
= max(MVPP2_CPU_DESC_CHUNK
, num
- txq_pcpu
->reserved_num
);
4247 (txq
->size
- (num_present_cpus() * MVPP2_CPU_DESC_CHUNK
)))
4250 txq_pcpu
->reserved_num
+= mvpp2_txq_alloc_reserved_desc(priv
, txq
, req
);
4252 /* OK, the descriptor cound has been updated: check again. */
4253 if (txq_pcpu
->reserved_num
< num
)
4258 /* Release the last allocated Tx descriptor. Useful to handle DMA
4259 * mapping failures in the Tx path.
4261 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue
*txq
)
4263 if (txq
->next_desc_to_proc
== 0)
4264 txq
->next_desc_to_proc
= txq
->last_desc
- 1;
4266 txq
->next_desc_to_proc
--;
4269 /* Set Tx descriptors fields relevant for CSUM calculation */
4270 static u32
mvpp2_txq_desc_csum(int l3_offs
, int l3_proto
,
4271 int ip_hdr_len
, int l4_proto
)
4275 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
4276 * G_L4_chk, L4_type required only for checksum calculation
4278 command
= (l3_offs
<< MVPP2_TXD_L3_OFF_SHIFT
);
4279 command
|= (ip_hdr_len
<< MVPP2_TXD_IP_HLEN_SHIFT
);
4280 command
|= MVPP2_TXD_IP_CSUM_DISABLE
;
4282 if (l3_proto
== swab16(ETH_P_IP
)) {
4283 command
&= ~MVPP2_TXD_IP_CSUM_DISABLE
; /* enable IPv4 csum */
4284 command
&= ~MVPP2_TXD_L3_IP6
; /* enable IPv4 */
4286 command
|= MVPP2_TXD_L3_IP6
; /* enable IPv6 */
4289 if (l4_proto
== IPPROTO_TCP
) {
4290 command
&= ~MVPP2_TXD_L4_UDP
; /* enable TCP */
4291 command
&= ~MVPP2_TXD_L4_CSUM_FRAG
; /* generate L4 csum */
4292 } else if (l4_proto
== IPPROTO_UDP
) {
4293 command
|= MVPP2_TXD_L4_UDP
; /* enable UDP */
4294 command
&= ~MVPP2_TXD_L4_CSUM_FRAG
; /* generate L4 csum */
4296 command
|= MVPP2_TXD_L4_CSUM_NOT
;
4302 /* Get number of sent descriptors and decrement counter.
4303 * The number of sent descriptors is returned.
4306 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port
*port
,
4307 struct mvpp2_tx_queue
*txq
)
4311 /* Reading status reg resets transmitted descriptor counter */
4312 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(txq
->id
));
4314 return (val
& MVPP2_TRANSMITTED_COUNT_MASK
) >>
4315 MVPP2_TRANSMITTED_COUNT_OFFSET
;
4318 static void mvpp2_txq_sent_counter_clear(void *arg
)
4320 struct mvpp2_port
*port
= arg
;
4323 for (queue
= 0; queue
< txq_number
; queue
++) {
4324 int id
= port
->txqs
[queue
]->id
;
4326 mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(id
));
4330 /* Set max sizes for Tx queues */
4331 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port
*port
)
4334 int txq
, tx_port_num
;
4336 mtu
= port
->pkt_size
* 8;
4337 if (mtu
> MVPP2_TXP_MTU_MAX
)
4338 mtu
= MVPP2_TXP_MTU_MAX
;
4340 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
4343 /* Indirect access to registers */
4344 tx_port_num
= mvpp2_egress_port(port
);
4345 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
4348 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
);
4349 val
&= ~MVPP2_TXP_MTU_MAX
;
4351 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
, val
);
4353 /* TXP token size and all TXQs token size must be larger that MTU */
4354 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
);
4355 size
= val
& MVPP2_TXP_TOKEN_SIZE_MAX
;
4358 val
&= ~MVPP2_TXP_TOKEN_SIZE_MAX
;
4360 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
4363 for (txq
= 0; txq
< txq_number
; txq
++) {
4364 val
= mvpp2_read(port
->priv
,
4365 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
));
4366 size
= val
& MVPP2_TXQ_TOKEN_SIZE_MAX
;
4370 val
&= ~MVPP2_TXQ_TOKEN_SIZE_MAX
;
4372 mvpp2_write(port
->priv
,
4373 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
),
4379 /* Set the number of packets that will be received before Rx interrupt
4380 * will be generated by HW.
4382 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port
*port
,
4383 struct mvpp2_rx_queue
*rxq
)
4385 if (rxq
->pkts_coal
> MVPP2_OCCUPIED_THRESH_MASK
)
4386 rxq
->pkts_coal
= MVPP2_OCCUPIED_THRESH_MASK
;
4388 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
4389 mvpp2_write(port
->priv
, MVPP2_RXQ_THRESH_REG
,
4393 static u32
mvpp2_usec_to_cycles(u32 usec
, unsigned long clk_hz
)
4395 u64 tmp
= (u64
)clk_hz
* usec
;
4397 do_div(tmp
, USEC_PER_SEC
);
4399 return tmp
> U32_MAX
? U32_MAX
: tmp
;
4402 static u32
mvpp2_cycles_to_usec(u32 cycles
, unsigned long clk_hz
)
4404 u64 tmp
= (u64
)cycles
* USEC_PER_SEC
;
4406 do_div(tmp
, clk_hz
);
4408 return tmp
> U32_MAX
? U32_MAX
: tmp
;
4411 /* Set the time delay in usec before Rx interrupt */
4412 static void mvpp2_rx_time_coal_set(struct mvpp2_port
*port
,
4413 struct mvpp2_rx_queue
*rxq
)
4415 unsigned long freq
= port
->priv
->tclk
;
4416 u32 val
= mvpp2_usec_to_cycles(rxq
->time_coal
, freq
);
4418 if (val
> MVPP2_MAX_ISR_RX_THRESHOLD
) {
4420 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD
, freq
);
4422 /* re-evaluate to get actual register value */
4423 val
= mvpp2_usec_to_cycles(rxq
->time_coal
, freq
);
4426 mvpp2_write(port
->priv
, MVPP2_ISR_RX_THRESHOLD_REG(rxq
->id
), val
);
4429 /* Free Tx queue skbuffs */
4430 static void mvpp2_txq_bufs_free(struct mvpp2_port
*port
,
4431 struct mvpp2_tx_queue
*txq
,
4432 struct mvpp2_txq_pcpu
*txq_pcpu
, int num
)
4436 for (i
= 0; i
< num
; i
++) {
4437 struct mvpp2_txq_pcpu_buf
*tx_buf
=
4438 txq_pcpu
->buffs
+ txq_pcpu
->txq_get_index
;
4440 dma_unmap_single(port
->dev
->dev
.parent
, tx_buf
->phys
,
4441 tx_buf
->size
, DMA_TO_DEVICE
);
4443 dev_kfree_skb_any(tx_buf
->skb
);
4445 mvpp2_txq_inc_get(txq_pcpu
);
4449 static inline struct mvpp2_rx_queue
*mvpp2_get_rx_queue(struct mvpp2_port
*port
,
4452 int queue
= fls(cause
) - 1;
4454 return port
->rxqs
[queue
];
4457 static inline struct mvpp2_tx_queue
*mvpp2_get_tx_queue(struct mvpp2_port
*port
,
4460 int queue
= fls(cause
) - 1;
4462 return port
->txqs
[queue
];
4465 /* Handle end of transmission */
4466 static void mvpp2_txq_done(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
,
4467 struct mvpp2_txq_pcpu
*txq_pcpu
)
4469 struct netdev_queue
*nq
= netdev_get_tx_queue(port
->dev
, txq
->log_id
);
4472 if (txq_pcpu
->cpu
!= smp_processor_id())
4473 netdev_err(port
->dev
, "wrong cpu on the end of Tx processing\n");
4475 tx_done
= mvpp2_txq_sent_desc_proc(port
, txq
);
4478 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, tx_done
);
4480 txq_pcpu
->count
-= tx_done
;
4482 if (netif_tx_queue_stopped(nq
))
4483 if (txq_pcpu
->size
- txq_pcpu
->count
>= MAX_SKB_FRAGS
+ 1)
4484 netif_tx_wake_queue(nq
);
4487 static unsigned int mvpp2_tx_done(struct mvpp2_port
*port
, u32 cause
)
4489 struct mvpp2_tx_queue
*txq
;
4490 struct mvpp2_txq_pcpu
*txq_pcpu
;
4491 unsigned int tx_todo
= 0;
4494 txq
= mvpp2_get_tx_queue(port
, cause
);
4498 txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
4500 if (txq_pcpu
->count
) {
4501 mvpp2_txq_done(port
, txq
, txq_pcpu
);
4502 tx_todo
+= txq_pcpu
->count
;
4505 cause
&= ~(1 << txq
->log_id
);
4510 /* Rx/Tx queue initialization/cleanup methods */
4512 /* Allocate and initialize descriptors for aggr TXQ */
4513 static int mvpp2_aggr_txq_init(struct platform_device
*pdev
,
4514 struct mvpp2_tx_queue
*aggr_txq
,
4515 int desc_num
, int cpu
,
4518 /* Allocate memory for TX descriptors */
4519 aggr_txq
->descs
= dma_alloc_coherent(&pdev
->dev
,
4520 desc_num
* MVPP2_DESC_ALIGNED_SIZE
,
4521 &aggr_txq
->descs_phys
, GFP_KERNEL
);
4522 if (!aggr_txq
->descs
)
4525 aggr_txq
->last_desc
= aggr_txq
->size
- 1;
4527 /* Aggr TXQ no reset WA */
4528 aggr_txq
->next_desc_to_proc
= mvpp2_read(priv
,
4529 MVPP2_AGGR_TXQ_INDEX_REG(cpu
));
4531 /* Set Tx descriptors queue starting address */
4532 /* indirect access */
4533 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu
),
4534 aggr_txq
->descs_phys
);
4535 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu
), desc_num
);
4540 /* Create a specified Rx queue */
4541 static int mvpp2_rxq_init(struct mvpp2_port
*port
,
4542 struct mvpp2_rx_queue
*rxq
)
4545 rxq
->size
= port
->rx_ring_size
;
4547 /* Allocate memory for RX descriptors */
4548 rxq
->descs
= dma_alloc_coherent(port
->dev
->dev
.parent
,
4549 rxq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
4550 &rxq
->descs_phys
, GFP_KERNEL
);
4554 rxq
->last_desc
= rxq
->size
- 1;
4556 /* Zero occupied and non-occupied counters - direct access */
4557 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
4559 /* Set Rx descriptors queue starting address - indirect access */
4560 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
4561 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, rxq
->descs_phys
);
4562 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, rxq
->size
);
4563 mvpp2_write(port
->priv
, MVPP2_RXQ_INDEX_REG
, 0);
4566 mvpp2_rxq_offset_set(port
, rxq
->id
, NET_SKB_PAD
);
4568 /* Set coalescing pkts and time */
4569 mvpp2_rx_pkts_coal_set(port
, rxq
);
4570 mvpp2_rx_time_coal_set(port
, rxq
);
4572 /* Add number of descriptors ready for receiving packets */
4573 mvpp2_rxq_status_update(port
, rxq
->id
, 0, rxq
->size
);
4578 /* Push packets received by the RXQ to BM pool */
4579 static void mvpp2_rxq_drop_pkts(struct mvpp2_port
*port
,
4580 struct mvpp2_rx_queue
*rxq
)
4584 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
4588 for (i
= 0; i
< rx_received
; i
++) {
4589 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
4590 u32 bm
= mvpp2_bm_cookie_build(rx_desc
);
4592 mvpp2_pool_refill(port
, bm
, rx_desc
->buf_phys_addr
,
4593 rx_desc
->buf_cookie
);
4595 mvpp2_rxq_status_update(port
, rxq
->id
, rx_received
, rx_received
);
4598 /* Cleanup Rx queue */
4599 static void mvpp2_rxq_deinit(struct mvpp2_port
*port
,
4600 struct mvpp2_rx_queue
*rxq
)
4602 mvpp2_rxq_drop_pkts(port
, rxq
);
4605 dma_free_coherent(port
->dev
->dev
.parent
,
4606 rxq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
4612 rxq
->next_desc_to_proc
= 0;
4613 rxq
->descs_phys
= 0;
4615 /* Clear Rx descriptors queue starting address and size;
4616 * free descriptor number
4618 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
4619 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
4620 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, 0);
4621 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, 0);
4624 /* Create and initialize a Tx queue */
4625 static int mvpp2_txq_init(struct mvpp2_port
*port
,
4626 struct mvpp2_tx_queue
*txq
)
4629 int cpu
, desc
, desc_per_txq
, tx_port_num
;
4630 struct mvpp2_txq_pcpu
*txq_pcpu
;
4632 txq
->size
= port
->tx_ring_size
;
4634 /* Allocate memory for Tx descriptors */
4635 txq
->descs
= dma_alloc_coherent(port
->dev
->dev
.parent
,
4636 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
4637 &txq
->descs_phys
, GFP_KERNEL
);
4641 txq
->last_desc
= txq
->size
- 1;
4643 /* Set Tx descriptors queue starting address - indirect access */
4644 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4645 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, txq
->descs_phys
);
4646 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, txq
->size
&
4647 MVPP2_TXQ_DESC_SIZE_MASK
);
4648 mvpp2_write(port
->priv
, MVPP2_TXQ_INDEX_REG
, 0);
4649 mvpp2_write(port
->priv
, MVPP2_TXQ_RSVD_CLR_REG
,
4650 txq
->id
<< MVPP2_TXQ_RSVD_CLR_OFFSET
);
4651 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
4652 val
&= ~MVPP2_TXQ_PENDING_MASK
;
4653 mvpp2_write(port
->priv
, MVPP2_TXQ_PENDING_REG
, val
);
4655 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4656 * for each existing TXQ.
4657 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4658 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4661 desc
= (port
->id
* MVPP2_MAX_TXQ
* desc_per_txq
) +
4662 (txq
->log_id
* desc_per_txq
);
4664 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
,
4665 MVPP2_PREF_BUF_PTR(desc
) | MVPP2_PREF_BUF_SIZE_16
|
4666 MVPP2_PREF_BUF_THRESH(desc_per_txq
/2));
4668 /* WRR / EJP configuration - indirect access */
4669 tx_port_num
= mvpp2_egress_port(port
);
4670 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
4672 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
));
4673 val
&= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK
;
4674 val
|= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4675 val
|= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK
;
4676 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
), val
);
4678 val
= MVPP2_TXQ_TOKEN_SIZE_MAX
;
4679 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
->log_id
),
4682 for_each_present_cpu(cpu
) {
4683 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
4684 txq_pcpu
->size
= txq
->size
;
4685 txq_pcpu
->buffs
= kmalloc(txq_pcpu
->size
*
4686 sizeof(struct mvpp2_txq_pcpu_buf
),
4688 if (!txq_pcpu
->buffs
)
4691 txq_pcpu
->count
= 0;
4692 txq_pcpu
->reserved_num
= 0;
4693 txq_pcpu
->txq_put_index
= 0;
4694 txq_pcpu
->txq_get_index
= 0;
4700 for_each_present_cpu(cpu
) {
4701 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
4702 kfree(txq_pcpu
->buffs
);
4705 dma_free_coherent(port
->dev
->dev
.parent
,
4706 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
4707 txq
->descs
, txq
->descs_phys
);
4712 /* Free allocated TXQ resources */
4713 static void mvpp2_txq_deinit(struct mvpp2_port
*port
,
4714 struct mvpp2_tx_queue
*txq
)
4716 struct mvpp2_txq_pcpu
*txq_pcpu
;
4719 for_each_present_cpu(cpu
) {
4720 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
4721 kfree(txq_pcpu
->buffs
);
4725 dma_free_coherent(port
->dev
->dev
.parent
,
4726 txq
->size
* MVPP2_DESC_ALIGNED_SIZE
,
4727 txq
->descs
, txq
->descs_phys
);
4731 txq
->next_desc_to_proc
= 0;
4732 txq
->descs_phys
= 0;
4734 /* Set minimum bandwidth for disabled TXQs */
4735 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq
->id
), 0);
4737 /* Set Tx descriptors queue starting address and size */
4738 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4739 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, 0);
4740 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, 0);
4743 /* Cleanup Tx ports */
4744 static void mvpp2_txq_clean(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
)
4746 struct mvpp2_txq_pcpu
*txq_pcpu
;
4747 int delay
, pending
, cpu
;
4750 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4751 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
);
4752 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
4753 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
4755 /* The napi queue has been stopped so wait for all packets
4756 * to be transmitted.
4760 if (delay
>= MVPP2_TX_PENDING_TIMEOUT_MSEC
) {
4761 netdev_warn(port
->dev
,
4762 "port %d: cleaning queue %d timed out\n",
4763 port
->id
, txq
->log_id
);
4769 pending
= mvpp2_txq_pend_desc_num_get(port
, txq
);
4772 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
4773 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
4775 for_each_present_cpu(cpu
) {
4776 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
4778 /* Release all packets */
4779 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, txq_pcpu
->count
);
4782 txq_pcpu
->count
= 0;
4783 txq_pcpu
->txq_put_index
= 0;
4784 txq_pcpu
->txq_get_index
= 0;
4788 /* Cleanup all Tx queues */
4789 static void mvpp2_cleanup_txqs(struct mvpp2_port
*port
)
4791 struct mvpp2_tx_queue
*txq
;
4795 val
= mvpp2_read(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
);
4797 /* Reset Tx ports and delete Tx queues */
4798 val
|= MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
4799 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
4801 for (queue
= 0; queue
< txq_number
; queue
++) {
4802 txq
= port
->txqs
[queue
];
4803 mvpp2_txq_clean(port
, txq
);
4804 mvpp2_txq_deinit(port
, txq
);
4807 on_each_cpu(mvpp2_txq_sent_counter_clear
, port
, 1);
4809 val
&= ~MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
4810 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
4813 /* Cleanup all Rx queues */
4814 static void mvpp2_cleanup_rxqs(struct mvpp2_port
*port
)
4818 for (queue
= 0; queue
< rxq_number
; queue
++)
4819 mvpp2_rxq_deinit(port
, port
->rxqs
[queue
]);
4822 /* Init all Rx queues for port */
4823 static int mvpp2_setup_rxqs(struct mvpp2_port
*port
)
4827 for (queue
= 0; queue
< rxq_number
; queue
++) {
4828 err
= mvpp2_rxq_init(port
, port
->rxqs
[queue
]);
4835 mvpp2_cleanup_rxqs(port
);
4839 /* Init all tx queues for port */
4840 static int mvpp2_setup_txqs(struct mvpp2_port
*port
)
4842 struct mvpp2_tx_queue
*txq
;
4845 for (queue
= 0; queue
< txq_number
; queue
++) {
4846 txq
= port
->txqs
[queue
];
4847 err
= mvpp2_txq_init(port
, txq
);
4852 on_each_cpu(mvpp2_txq_sent_counter_clear
, port
, 1);
4856 mvpp2_cleanup_txqs(port
);
4860 /* The callback for per-port interrupt */
4861 static irqreturn_t
mvpp2_isr(int irq
, void *dev_id
)
4863 struct mvpp2_port
*port
= (struct mvpp2_port
*)dev_id
;
4865 mvpp2_interrupts_disable(port
);
4867 napi_schedule(&port
->napi
);
4873 static void mvpp2_link_event(struct net_device
*dev
)
4875 struct mvpp2_port
*port
= netdev_priv(dev
);
4876 struct phy_device
*phydev
= dev
->phydev
;
4877 int status_change
= 0;
4881 if ((port
->speed
!= phydev
->speed
) ||
4882 (port
->duplex
!= phydev
->duplex
)) {
4885 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4886 val
&= ~(MVPP2_GMAC_CONFIG_MII_SPEED
|
4887 MVPP2_GMAC_CONFIG_GMII_SPEED
|
4888 MVPP2_GMAC_CONFIG_FULL_DUPLEX
|
4889 MVPP2_GMAC_AN_SPEED_EN
|
4890 MVPP2_GMAC_AN_DUPLEX_EN
);
4893 val
|= MVPP2_GMAC_CONFIG_FULL_DUPLEX
;
4895 if (phydev
->speed
== SPEED_1000
)
4896 val
|= MVPP2_GMAC_CONFIG_GMII_SPEED
;
4897 else if (phydev
->speed
== SPEED_100
)
4898 val
|= MVPP2_GMAC_CONFIG_MII_SPEED
;
4900 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4902 port
->duplex
= phydev
->duplex
;
4903 port
->speed
= phydev
->speed
;
4907 if (phydev
->link
!= port
->link
) {
4908 if (!phydev
->link
) {
4913 port
->link
= phydev
->link
;
4917 if (status_change
) {
4919 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4920 val
|= (MVPP2_GMAC_FORCE_LINK_PASS
|
4921 MVPP2_GMAC_FORCE_LINK_DOWN
);
4922 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
4923 mvpp2_egress_enable(port
);
4924 mvpp2_ingress_enable(port
);
4926 mvpp2_ingress_disable(port
);
4927 mvpp2_egress_disable(port
);
4929 phy_print_status(phydev
);
4933 static void mvpp2_timer_set(struct mvpp2_port_pcpu
*port_pcpu
)
4937 if (!port_pcpu
->timer_scheduled
) {
4938 port_pcpu
->timer_scheduled
= true;
4939 interval
= MVPP2_TXDONE_HRTIMER_PERIOD_NS
;
4940 hrtimer_start(&port_pcpu
->tx_done_timer
, interval
,
4941 HRTIMER_MODE_REL_PINNED
);
4945 static void mvpp2_tx_proc_cb(unsigned long data
)
4947 struct net_device
*dev
= (struct net_device
*)data
;
4948 struct mvpp2_port
*port
= netdev_priv(dev
);
4949 struct mvpp2_port_pcpu
*port_pcpu
= this_cpu_ptr(port
->pcpu
);
4950 unsigned int tx_todo
, cause
;
4952 if (!netif_running(dev
))
4954 port_pcpu
->timer_scheduled
= false;
4956 /* Process all the Tx queues */
4957 cause
= (1 << txq_number
) - 1;
4958 tx_todo
= mvpp2_tx_done(port
, cause
);
4960 /* Set the timer in case not all the packets were processed */
4962 mvpp2_timer_set(port_pcpu
);
4965 static enum hrtimer_restart
mvpp2_hr_timer_cb(struct hrtimer
*timer
)
4967 struct mvpp2_port_pcpu
*port_pcpu
= container_of(timer
,
4968 struct mvpp2_port_pcpu
,
4971 tasklet_schedule(&port_pcpu
->tx_done_tasklet
);
4973 return HRTIMER_NORESTART
;
4976 /* Main RX/TX processing routines */
4978 /* Display more error info */
4979 static void mvpp2_rx_error(struct mvpp2_port
*port
,
4980 struct mvpp2_rx_desc
*rx_desc
)
4982 u32 status
= rx_desc
->status
;
4984 switch (status
& MVPP2_RXD_ERR_CODE_MASK
) {
4985 case MVPP2_RXD_ERR_CRC
:
4986 netdev_err(port
->dev
, "bad rx status %08x (crc error), size=%d\n",
4987 status
, rx_desc
->data_size
);
4989 case MVPP2_RXD_ERR_OVERRUN
:
4990 netdev_err(port
->dev
, "bad rx status %08x (overrun error), size=%d\n",
4991 status
, rx_desc
->data_size
);
4993 case MVPP2_RXD_ERR_RESOURCE
:
4994 netdev_err(port
->dev
, "bad rx status %08x (resource error), size=%d\n",
4995 status
, rx_desc
->data_size
);
5000 /* Handle RX checksum offload */
5001 static void mvpp2_rx_csum(struct mvpp2_port
*port
, u32 status
,
5002 struct sk_buff
*skb
)
5004 if (((status
& MVPP2_RXD_L3_IP4
) &&
5005 !(status
& MVPP2_RXD_IP4_HEADER_ERR
)) ||
5006 (status
& MVPP2_RXD_L3_IP6
))
5007 if (((status
& MVPP2_RXD_L4_UDP
) ||
5008 (status
& MVPP2_RXD_L4_TCP
)) &&
5009 (status
& MVPP2_RXD_L4_CSUM_OK
)) {
5011 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5015 skb
->ip_summed
= CHECKSUM_NONE
;
5018 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
5019 static int mvpp2_rx_refill(struct mvpp2_port
*port
,
5020 struct mvpp2_bm_pool
*bm_pool
,
5021 u32 bm
, int is_recycle
)
5023 struct sk_buff
*skb
;
5024 dma_addr_t phys_addr
;
5027 (atomic_read(&bm_pool
->in_use
) < bm_pool
->in_use_thresh
))
5030 /* No recycle or too many buffers are in use, so allocate a new skb */
5031 skb
= mvpp2_skb_alloc(port
, bm_pool
, &phys_addr
, GFP_ATOMIC
);
5035 mvpp2_pool_refill(port
, bm
, (u32
)phys_addr
, (u32
)skb
);
5036 atomic_dec(&bm_pool
->in_use
);
5040 /* Handle tx checksum */
5041 static u32
mvpp2_skb_tx_csum(struct mvpp2_port
*port
, struct sk_buff
*skb
)
5043 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5047 if (skb
->protocol
== htons(ETH_P_IP
)) {
5048 struct iphdr
*ip4h
= ip_hdr(skb
);
5050 /* Calculate IPv4 checksum and L4 checksum */
5051 ip_hdr_len
= ip4h
->ihl
;
5052 l4_proto
= ip4h
->protocol
;
5053 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
5054 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
5056 /* Read l4_protocol from one of IPv6 extra headers */
5057 if (skb_network_header_len(skb
) > 0)
5058 ip_hdr_len
= (skb_network_header_len(skb
) >> 2);
5059 l4_proto
= ip6h
->nexthdr
;
5061 return MVPP2_TXD_L4_CSUM_NOT
;
5064 return mvpp2_txq_desc_csum(skb_network_offset(skb
),
5065 skb
->protocol
, ip_hdr_len
, l4_proto
);
5068 return MVPP2_TXD_L4_CSUM_NOT
| MVPP2_TXD_IP_CSUM_DISABLE
;
5071 static void mvpp2_buff_hdr_rx(struct mvpp2_port
*port
,
5072 struct mvpp2_rx_desc
*rx_desc
)
5074 struct mvpp2_buff_hdr
*buff_hdr
;
5075 struct sk_buff
*skb
;
5076 u32 rx_status
= rx_desc
->status
;
5079 u32 buff_phys_addr_next
;
5080 u32 buff_virt_addr_next
;
5084 pool_id
= (rx_status
& MVPP2_RXD_BM_POOL_ID_MASK
) >>
5085 MVPP2_RXD_BM_POOL_ID_OFFS
;
5086 buff_phys_addr
= rx_desc
->buf_phys_addr
;
5087 buff_virt_addr
= rx_desc
->buf_cookie
;
5090 skb
= (struct sk_buff
*)buff_virt_addr
;
5091 buff_hdr
= (struct mvpp2_buff_hdr
*)skb
->head
;
5093 mc_id
= MVPP2_B_HDR_INFO_MC_ID(buff_hdr
->info
);
5095 buff_phys_addr_next
= buff_hdr
->next_buff_phys_addr
;
5096 buff_virt_addr_next
= buff_hdr
->next_buff_virt_addr
;
5098 /* Release buffer */
5099 mvpp2_bm_pool_mc_put(port
, pool_id
, buff_phys_addr
,
5100 buff_virt_addr
, mc_id
);
5102 buff_phys_addr
= buff_phys_addr_next
;
5103 buff_virt_addr
= buff_virt_addr_next
;
5105 } while (!MVPP2_B_HDR_INFO_IS_LAST(buff_hdr
->info
));
5108 /* Main rx processing */
5109 static int mvpp2_rx(struct mvpp2_port
*port
, int rx_todo
,
5110 struct mvpp2_rx_queue
*rxq
)
5112 struct net_device
*dev
= port
->dev
;
5118 /* Get number of received packets and clamp the to-do */
5119 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
5120 if (rx_todo
> rx_received
)
5121 rx_todo
= rx_received
;
5123 while (rx_done
< rx_todo
) {
5124 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
5125 struct mvpp2_bm_pool
*bm_pool
;
5126 struct sk_buff
*skb
;
5127 dma_addr_t phys_addr
;
5129 int pool
, rx_bytes
, err
;
5132 rx_status
= rx_desc
->status
;
5133 rx_bytes
= rx_desc
->data_size
- MVPP2_MH_SIZE
;
5134 phys_addr
= rx_desc
->buf_phys_addr
;
5136 bm
= mvpp2_bm_cookie_build(rx_desc
);
5137 pool
= mvpp2_bm_cookie_pool_get(bm
);
5138 bm_pool
= &port
->priv
->bm_pools
[pool
];
5139 /* Check if buffer header is used */
5140 if (rx_status
& MVPP2_RXD_BUF_HDR
) {
5141 mvpp2_buff_hdr_rx(port
, rx_desc
);
5145 /* In case of an error, release the requested buffer pointer
5146 * to the Buffer Manager. This request process is controlled
5147 * by the hardware, and the information about the buffer is
5148 * comprised by the RX descriptor.
5150 if (rx_status
& MVPP2_RXD_ERR_SUMMARY
) {
5152 dev
->stats
.rx_errors
++;
5153 mvpp2_rx_error(port
, rx_desc
);
5154 /* Return the buffer to the pool */
5155 mvpp2_pool_refill(port
, bm
, rx_desc
->buf_phys_addr
,
5156 rx_desc
->buf_cookie
);
5160 skb
= (struct sk_buff
*)rx_desc
->buf_cookie
;
5162 err
= mvpp2_rx_refill(port
, bm_pool
, bm
, 0);
5164 netdev_err(port
->dev
, "failed to refill BM pools\n");
5165 goto err_drop_frame
;
5168 dma_unmap_single(dev
->dev
.parent
, phys_addr
,
5169 bm_pool
->buf_size
, DMA_FROM_DEVICE
);
5172 rcvd_bytes
+= rx_bytes
;
5173 atomic_inc(&bm_pool
->in_use
);
5175 skb_reserve(skb
, MVPP2_MH_SIZE
);
5176 skb_put(skb
, rx_bytes
);
5177 skb
->protocol
= eth_type_trans(skb
, dev
);
5178 mvpp2_rx_csum(port
, rx_status
, skb
);
5180 napi_gro_receive(&port
->napi
, skb
);
5184 struct mvpp2_pcpu_stats
*stats
= this_cpu_ptr(port
->stats
);
5186 u64_stats_update_begin(&stats
->syncp
);
5187 stats
->rx_packets
+= rcvd_pkts
;
5188 stats
->rx_bytes
+= rcvd_bytes
;
5189 u64_stats_update_end(&stats
->syncp
);
5192 /* Update Rx queue management counters */
5194 mvpp2_rxq_status_update(port
, rxq
->id
, rx_done
, rx_done
);
5200 tx_desc_unmap_put(struct device
*dev
, struct mvpp2_tx_queue
*txq
,
5201 struct mvpp2_tx_desc
*desc
)
5203 dma_unmap_single(dev
, desc
->buf_phys_addr
,
5204 desc
->data_size
, DMA_TO_DEVICE
);
5205 mvpp2_txq_desc_put(txq
);
5208 /* Handle tx fragmentation processing */
5209 static int mvpp2_tx_frag_process(struct mvpp2_port
*port
, struct sk_buff
*skb
,
5210 struct mvpp2_tx_queue
*aggr_txq
,
5211 struct mvpp2_tx_queue
*txq
)
5213 struct mvpp2_txq_pcpu
*txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
5214 struct mvpp2_tx_desc
*tx_desc
;
5216 dma_addr_t buf_phys_addr
;
5218 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
5219 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5220 void *addr
= page_address(frag
->page
.p
) + frag
->page_offset
;
5222 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
5223 tx_desc
->phys_txq
= txq
->id
;
5224 tx_desc
->data_size
= frag
->size
;
5226 buf_phys_addr
= dma_map_single(port
->dev
->dev
.parent
, addr
,
5229 if (dma_mapping_error(port
->dev
->dev
.parent
, buf_phys_addr
)) {
5230 mvpp2_txq_desc_put(txq
);
5234 tx_desc
->packet_offset
= buf_phys_addr
& MVPP2_TX_DESC_ALIGN
;
5235 tx_desc
->buf_phys_addr
= buf_phys_addr
& (~MVPP2_TX_DESC_ALIGN
);
5237 if (i
== (skb_shinfo(skb
)->nr_frags
- 1)) {
5238 /* Last descriptor */
5239 tx_desc
->command
= MVPP2_TXD_L_DESC
;
5240 mvpp2_txq_inc_put(txq_pcpu
, skb
, tx_desc
);
5242 /* Descriptor in the middle: Not First, Not Last */
5243 tx_desc
->command
= 0;
5244 mvpp2_txq_inc_put(txq_pcpu
, NULL
, tx_desc
);
5251 /* Release all descriptors that were used to map fragments of
5252 * this packet, as well as the corresponding DMA mappings
5254 for (i
= i
- 1; i
>= 0; i
--) {
5255 tx_desc
= txq
->descs
+ i
;
5256 tx_desc_unmap_put(port
->dev
->dev
.parent
, txq
, tx_desc
);
5262 /* Main tx processing */
5263 static int mvpp2_tx(struct sk_buff
*skb
, struct net_device
*dev
)
5265 struct mvpp2_port
*port
= netdev_priv(dev
);
5266 struct mvpp2_tx_queue
*txq
, *aggr_txq
;
5267 struct mvpp2_txq_pcpu
*txq_pcpu
;
5268 struct mvpp2_tx_desc
*tx_desc
;
5269 dma_addr_t buf_phys_addr
;
5274 txq_id
= skb_get_queue_mapping(skb
);
5275 txq
= port
->txqs
[txq_id
];
5276 txq_pcpu
= this_cpu_ptr(txq
->pcpu
);
5277 aggr_txq
= &port
->priv
->aggr_txqs
[smp_processor_id()];
5279 frags
= skb_shinfo(skb
)->nr_frags
+ 1;
5281 /* Check number of available descriptors */
5282 if (mvpp2_aggr_desc_num_check(port
->priv
, aggr_txq
, frags
) ||
5283 mvpp2_txq_reserved_desc_num_proc(port
->priv
, txq
,
5289 /* Get a descriptor for the first part of the packet */
5290 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
5291 tx_desc
->phys_txq
= txq
->id
;
5292 tx_desc
->data_size
= skb_headlen(skb
);
5294 buf_phys_addr
= dma_map_single(dev
->dev
.parent
, skb
->data
,
5295 tx_desc
->data_size
, DMA_TO_DEVICE
);
5296 if (unlikely(dma_mapping_error(dev
->dev
.parent
, buf_phys_addr
))) {
5297 mvpp2_txq_desc_put(txq
);
5301 tx_desc
->packet_offset
= buf_phys_addr
& MVPP2_TX_DESC_ALIGN
;
5302 tx_desc
->buf_phys_addr
= buf_phys_addr
& ~MVPP2_TX_DESC_ALIGN
;
5304 tx_cmd
= mvpp2_skb_tx_csum(port
, skb
);
5307 /* First and Last descriptor */
5308 tx_cmd
|= MVPP2_TXD_F_DESC
| MVPP2_TXD_L_DESC
;
5309 tx_desc
->command
= tx_cmd
;
5310 mvpp2_txq_inc_put(txq_pcpu
, skb
, tx_desc
);
5312 /* First but not Last */
5313 tx_cmd
|= MVPP2_TXD_F_DESC
| MVPP2_TXD_PADDING_DISABLE
;
5314 tx_desc
->command
= tx_cmd
;
5315 mvpp2_txq_inc_put(txq_pcpu
, NULL
, tx_desc
);
5317 /* Continue with other skb fragments */
5318 if (mvpp2_tx_frag_process(port
, skb
, aggr_txq
, txq
)) {
5319 tx_desc_unmap_put(port
->dev
->dev
.parent
, txq
, tx_desc
);
5325 txq_pcpu
->reserved_num
-= frags
;
5326 txq_pcpu
->count
+= frags
;
5327 aggr_txq
->count
+= frags
;
5329 /* Enable transmit */
5331 mvpp2_aggr_txq_pend_desc_add(port
, frags
);
5333 if (txq_pcpu
->size
- txq_pcpu
->count
< MAX_SKB_FRAGS
+ 1) {
5334 struct netdev_queue
*nq
= netdev_get_tx_queue(dev
, txq_id
);
5336 netif_tx_stop_queue(nq
);
5340 struct mvpp2_pcpu_stats
*stats
= this_cpu_ptr(port
->stats
);
5342 u64_stats_update_begin(&stats
->syncp
);
5343 stats
->tx_packets
++;
5344 stats
->tx_bytes
+= skb
->len
;
5345 u64_stats_update_end(&stats
->syncp
);
5347 dev
->stats
.tx_dropped
++;
5348 dev_kfree_skb_any(skb
);
5351 /* Finalize TX processing */
5352 if (txq_pcpu
->count
>= txq
->done_pkts_coal
)
5353 mvpp2_txq_done(port
, txq
, txq_pcpu
);
5355 /* Set the timer in case not all frags were processed */
5356 if (txq_pcpu
->count
<= frags
&& txq_pcpu
->count
> 0) {
5357 struct mvpp2_port_pcpu
*port_pcpu
= this_cpu_ptr(port
->pcpu
);
5359 mvpp2_timer_set(port_pcpu
);
5362 return NETDEV_TX_OK
;
5365 static inline void mvpp2_cause_error(struct net_device
*dev
, int cause
)
5367 if (cause
& MVPP2_CAUSE_FCS_ERR_MASK
)
5368 netdev_err(dev
, "FCS error\n");
5369 if (cause
& MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK
)
5370 netdev_err(dev
, "rx fifo overrun error\n");
5371 if (cause
& MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK
)
5372 netdev_err(dev
, "tx fifo underrun error\n");
5375 static int mvpp2_poll(struct napi_struct
*napi
, int budget
)
5377 u32 cause_rx_tx
, cause_rx
, cause_misc
;
5379 struct mvpp2_port
*port
= netdev_priv(napi
->dev
);
5381 /* Rx/Tx cause register
5383 * Bits 0-15: each bit indicates received packets on the Rx queue
5384 * (bit 0 is for Rx queue 0).
5386 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
5387 * (bit 16 is for Tx queue 0).
5389 * Each CPU has its own Rx/Tx cause register
5391 cause_rx_tx
= mvpp2_read(port
->priv
,
5392 MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
));
5393 cause_rx_tx
&= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK
;
5394 cause_misc
= cause_rx_tx
& MVPP2_CAUSE_MISC_SUM_MASK
;
5397 mvpp2_cause_error(port
->dev
, cause_misc
);
5399 /* Clear the cause register */
5400 mvpp2_write(port
->priv
, MVPP2_ISR_MISC_CAUSE_REG
, 0);
5401 mvpp2_write(port
->priv
, MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
),
5402 cause_rx_tx
& ~MVPP2_CAUSE_MISC_SUM_MASK
);
5405 cause_rx
= cause_rx_tx
& MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
5407 /* Process RX packets */
5408 cause_rx
|= port
->pending_cause_rx
;
5409 while (cause_rx
&& budget
> 0) {
5411 struct mvpp2_rx_queue
*rxq
;
5413 rxq
= mvpp2_get_rx_queue(port
, cause_rx
);
5417 count
= mvpp2_rx(port
, budget
, rxq
);
5421 /* Clear the bit associated to this Rx queue
5422 * so that next iteration will continue from
5423 * the next Rx queue.
5425 cause_rx
&= ~(1 << rxq
->logic_rxq
);
5431 napi_complete_done(napi
, rx_done
);
5433 mvpp2_interrupts_enable(port
);
5435 port
->pending_cause_rx
= cause_rx
;
5439 /* Set hw internals when starting port */
5440 static void mvpp2_start_dev(struct mvpp2_port
*port
)
5442 struct net_device
*ndev
= port
->dev
;
5444 mvpp2_gmac_max_rx_size_set(port
);
5445 mvpp2_txp_max_tx_size_set(port
);
5447 napi_enable(&port
->napi
);
5449 /* Enable interrupts on all CPUs */
5450 mvpp2_interrupts_enable(port
);
5452 mvpp2_port_enable(port
);
5453 phy_start(ndev
->phydev
);
5454 netif_tx_start_all_queues(port
->dev
);
5457 /* Set hw internals when stopping port */
5458 static void mvpp2_stop_dev(struct mvpp2_port
*port
)
5460 struct net_device
*ndev
= port
->dev
;
5462 /* Stop new packets from arriving to RXQs */
5463 mvpp2_ingress_disable(port
);
5467 /* Disable interrupts on all CPUs */
5468 mvpp2_interrupts_disable(port
);
5470 napi_disable(&port
->napi
);
5472 netif_carrier_off(port
->dev
);
5473 netif_tx_stop_all_queues(port
->dev
);
5475 mvpp2_egress_disable(port
);
5476 mvpp2_port_disable(port
);
5477 phy_stop(ndev
->phydev
);
5480 static int mvpp2_check_ringparam_valid(struct net_device
*dev
,
5481 struct ethtool_ringparam
*ring
)
5483 u16 new_rx_pending
= ring
->rx_pending
;
5484 u16 new_tx_pending
= ring
->tx_pending
;
5486 if (ring
->rx_pending
== 0 || ring
->tx_pending
== 0)
5489 if (ring
->rx_pending
> MVPP2_MAX_RXD
)
5490 new_rx_pending
= MVPP2_MAX_RXD
;
5491 else if (!IS_ALIGNED(ring
->rx_pending
, 16))
5492 new_rx_pending
= ALIGN(ring
->rx_pending
, 16);
5494 if (ring
->tx_pending
> MVPP2_MAX_TXD
)
5495 new_tx_pending
= MVPP2_MAX_TXD
;
5496 else if (!IS_ALIGNED(ring
->tx_pending
, 32))
5497 new_tx_pending
= ALIGN(ring
->tx_pending
, 32);
5499 if (ring
->rx_pending
!= new_rx_pending
) {
5500 netdev_info(dev
, "illegal Rx ring size value %d, round to %d\n",
5501 ring
->rx_pending
, new_rx_pending
);
5502 ring
->rx_pending
= new_rx_pending
;
5505 if (ring
->tx_pending
!= new_tx_pending
) {
5506 netdev_info(dev
, "illegal Tx ring size value %d, round to %d\n",
5507 ring
->tx_pending
, new_tx_pending
);
5508 ring
->tx_pending
= new_tx_pending
;
5514 static void mvpp2_get_mac_address(struct mvpp2_port
*port
, unsigned char *addr
)
5516 u32 mac_addr_l
, mac_addr_m
, mac_addr_h
;
5518 mac_addr_l
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
5519 mac_addr_m
= readl(port
->priv
->lms_base
+ MVPP2_SRC_ADDR_MIDDLE
);
5520 mac_addr_h
= readl(port
->priv
->lms_base
+ MVPP2_SRC_ADDR_HIGH
);
5521 addr
[0] = (mac_addr_h
>> 24) & 0xFF;
5522 addr
[1] = (mac_addr_h
>> 16) & 0xFF;
5523 addr
[2] = (mac_addr_h
>> 8) & 0xFF;
5524 addr
[3] = mac_addr_h
& 0xFF;
5525 addr
[4] = mac_addr_m
& 0xFF;
5526 addr
[5] = (mac_addr_l
>> MVPP2_GMAC_SA_LOW_OFFS
) & 0xFF;
5529 static int mvpp2_phy_connect(struct mvpp2_port
*port
)
5531 struct phy_device
*phy_dev
;
5533 phy_dev
= of_phy_connect(port
->dev
, port
->phy_node
, mvpp2_link_event
, 0,
5534 port
->phy_interface
);
5536 netdev_err(port
->dev
, "cannot connect to phy\n");
5539 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
5540 phy_dev
->advertising
= phy_dev
->supported
;
5549 static void mvpp2_phy_disconnect(struct mvpp2_port
*port
)
5551 struct net_device
*ndev
= port
->dev
;
5553 phy_disconnect(ndev
->phydev
);
5556 static int mvpp2_open(struct net_device
*dev
)
5558 struct mvpp2_port
*port
= netdev_priv(dev
);
5559 unsigned char mac_bcast
[ETH_ALEN
] = {
5560 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
5563 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, mac_bcast
, true);
5565 netdev_err(dev
, "mvpp2_prs_mac_da_accept BC failed\n");
5568 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
,
5569 dev
->dev_addr
, true);
5571 netdev_err(dev
, "mvpp2_prs_mac_da_accept MC failed\n");
5574 err
= mvpp2_prs_tag_mode_set(port
->priv
, port
->id
, MVPP2_TAG_TYPE_MH
);
5576 netdev_err(dev
, "mvpp2_prs_tag_mode_set failed\n");
5579 err
= mvpp2_prs_def_flow(port
);
5581 netdev_err(dev
, "mvpp2_prs_def_flow failed\n");
5585 /* Allocate the Rx/Tx queues */
5586 err
= mvpp2_setup_rxqs(port
);
5588 netdev_err(port
->dev
, "cannot allocate Rx queues\n");
5592 err
= mvpp2_setup_txqs(port
);
5594 netdev_err(port
->dev
, "cannot allocate Tx queues\n");
5595 goto err_cleanup_rxqs
;
5598 err
= request_irq(port
->irq
, mvpp2_isr
, 0, dev
->name
, port
);
5600 netdev_err(port
->dev
, "cannot request IRQ %d\n", port
->irq
);
5601 goto err_cleanup_txqs
;
5604 /* In default link is down */
5605 netif_carrier_off(port
->dev
);
5607 err
= mvpp2_phy_connect(port
);
5611 /* Unmask interrupts on all CPUs */
5612 on_each_cpu(mvpp2_interrupts_unmask
, port
, 1);
5614 mvpp2_start_dev(port
);
5619 free_irq(port
->irq
, port
);
5621 mvpp2_cleanup_txqs(port
);
5623 mvpp2_cleanup_rxqs(port
);
5627 static int mvpp2_stop(struct net_device
*dev
)
5629 struct mvpp2_port
*port
= netdev_priv(dev
);
5630 struct mvpp2_port_pcpu
*port_pcpu
;
5633 mvpp2_stop_dev(port
);
5634 mvpp2_phy_disconnect(port
);
5636 /* Mask interrupts on all CPUs */
5637 on_each_cpu(mvpp2_interrupts_mask
, port
, 1);
5639 free_irq(port
->irq
, port
);
5640 for_each_present_cpu(cpu
) {
5641 port_pcpu
= per_cpu_ptr(port
->pcpu
, cpu
);
5643 hrtimer_cancel(&port_pcpu
->tx_done_timer
);
5644 port_pcpu
->timer_scheduled
= false;
5645 tasklet_kill(&port_pcpu
->tx_done_tasklet
);
5647 mvpp2_cleanup_rxqs(port
);
5648 mvpp2_cleanup_txqs(port
);
5653 static void mvpp2_set_rx_mode(struct net_device
*dev
)
5655 struct mvpp2_port
*port
= netdev_priv(dev
);
5656 struct mvpp2
*priv
= port
->priv
;
5657 struct netdev_hw_addr
*ha
;
5659 bool allmulti
= dev
->flags
& IFF_ALLMULTI
;
5661 mvpp2_prs_mac_promisc_set(priv
, id
, dev
->flags
& IFF_PROMISC
);
5662 mvpp2_prs_mac_multi_set(priv
, id
, MVPP2_PE_MAC_MC_ALL
, allmulti
);
5663 mvpp2_prs_mac_multi_set(priv
, id
, MVPP2_PE_MAC_MC_IP6
, allmulti
);
5665 /* Remove all port->id's mcast enries */
5666 mvpp2_prs_mcast_del_all(priv
, id
);
5668 if (allmulti
&& !netdev_mc_empty(dev
)) {
5669 netdev_for_each_mc_addr(ha
, dev
)
5670 mvpp2_prs_mac_da_accept(priv
, id
, ha
->addr
, true);
5674 static int mvpp2_set_mac_address(struct net_device
*dev
, void *p
)
5676 struct mvpp2_port
*port
= netdev_priv(dev
);
5677 const struct sockaddr
*addr
= p
;
5680 if (!is_valid_ether_addr(addr
->sa_data
)) {
5681 err
= -EADDRNOTAVAIL
;
5685 if (!netif_running(dev
)) {
5686 err
= mvpp2_prs_update_mac_da(dev
, addr
->sa_data
);
5689 /* Reconfigure parser to accept the original MAC address */
5690 err
= mvpp2_prs_update_mac_da(dev
, dev
->dev_addr
);
5695 mvpp2_stop_dev(port
);
5697 err
= mvpp2_prs_update_mac_da(dev
, addr
->sa_data
);
5701 /* Reconfigure parser accept the original MAC address */
5702 err
= mvpp2_prs_update_mac_da(dev
, dev
->dev_addr
);
5706 mvpp2_start_dev(port
);
5707 mvpp2_egress_enable(port
);
5708 mvpp2_ingress_enable(port
);
5712 netdev_err(dev
, "fail to change MAC address\n");
5716 static int mvpp2_change_mtu(struct net_device
*dev
, int mtu
)
5718 struct mvpp2_port
*port
= netdev_priv(dev
);
5721 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu
), 8)) {
5722 netdev_info(dev
, "illegal MTU value %d, round to %d\n", mtu
,
5723 ALIGN(MVPP2_RX_PKT_SIZE(mtu
), 8));
5724 mtu
= ALIGN(MVPP2_RX_PKT_SIZE(mtu
), 8);
5727 if (!netif_running(dev
)) {
5728 err
= mvpp2_bm_update_mtu(dev
, mtu
);
5730 port
->pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
5734 /* Reconfigure BM to the original MTU */
5735 err
= mvpp2_bm_update_mtu(dev
, dev
->mtu
);
5740 mvpp2_stop_dev(port
);
5742 err
= mvpp2_bm_update_mtu(dev
, mtu
);
5744 port
->pkt_size
= MVPP2_RX_PKT_SIZE(mtu
);
5748 /* Reconfigure BM to the original MTU */
5749 err
= mvpp2_bm_update_mtu(dev
, dev
->mtu
);
5754 mvpp2_start_dev(port
);
5755 mvpp2_egress_enable(port
);
5756 mvpp2_ingress_enable(port
);
5761 netdev_err(dev
, "fail to change MTU\n");
5766 mvpp2_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5768 struct mvpp2_port
*port
= netdev_priv(dev
);
5772 for_each_possible_cpu(cpu
) {
5773 struct mvpp2_pcpu_stats
*cpu_stats
;
5779 cpu_stats
= per_cpu_ptr(port
->stats
, cpu
);
5781 start
= u64_stats_fetch_begin_irq(&cpu_stats
->syncp
);
5782 rx_packets
= cpu_stats
->rx_packets
;
5783 rx_bytes
= cpu_stats
->rx_bytes
;
5784 tx_packets
= cpu_stats
->tx_packets
;
5785 tx_bytes
= cpu_stats
->tx_bytes
;
5786 } while (u64_stats_fetch_retry_irq(&cpu_stats
->syncp
, start
));
5788 stats
->rx_packets
+= rx_packets
;
5789 stats
->rx_bytes
+= rx_bytes
;
5790 stats
->tx_packets
+= tx_packets
;
5791 stats
->tx_bytes
+= tx_bytes
;
5794 stats
->rx_errors
= dev
->stats
.rx_errors
;
5795 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
5796 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
5799 static int mvpp2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5806 ret
= phy_mii_ioctl(dev
->phydev
, ifr
, cmd
);
5808 mvpp2_link_event(dev
);
5813 /* Ethtool methods */
5815 /* Set interrupt coalescing for ethtools */
5816 static int mvpp2_ethtool_set_coalesce(struct net_device
*dev
,
5817 struct ethtool_coalesce
*c
)
5819 struct mvpp2_port
*port
= netdev_priv(dev
);
5822 for (queue
= 0; queue
< rxq_number
; queue
++) {
5823 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
5825 rxq
->time_coal
= c
->rx_coalesce_usecs
;
5826 rxq
->pkts_coal
= c
->rx_max_coalesced_frames
;
5827 mvpp2_rx_pkts_coal_set(port
, rxq
);
5828 mvpp2_rx_time_coal_set(port
, rxq
);
5831 for (queue
= 0; queue
< txq_number
; queue
++) {
5832 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
5834 txq
->done_pkts_coal
= c
->tx_max_coalesced_frames
;
5840 /* get coalescing for ethtools */
5841 static int mvpp2_ethtool_get_coalesce(struct net_device
*dev
,
5842 struct ethtool_coalesce
*c
)
5844 struct mvpp2_port
*port
= netdev_priv(dev
);
5846 c
->rx_coalesce_usecs
= port
->rxqs
[0]->time_coal
;
5847 c
->rx_max_coalesced_frames
= port
->rxqs
[0]->pkts_coal
;
5848 c
->tx_max_coalesced_frames
= port
->txqs
[0]->done_pkts_coal
;
5852 static void mvpp2_ethtool_get_drvinfo(struct net_device
*dev
,
5853 struct ethtool_drvinfo
*drvinfo
)
5855 strlcpy(drvinfo
->driver
, MVPP2_DRIVER_NAME
,
5856 sizeof(drvinfo
->driver
));
5857 strlcpy(drvinfo
->version
, MVPP2_DRIVER_VERSION
,
5858 sizeof(drvinfo
->version
));
5859 strlcpy(drvinfo
->bus_info
, dev_name(&dev
->dev
),
5860 sizeof(drvinfo
->bus_info
));
5863 static void mvpp2_ethtool_get_ringparam(struct net_device
*dev
,
5864 struct ethtool_ringparam
*ring
)
5866 struct mvpp2_port
*port
= netdev_priv(dev
);
5868 ring
->rx_max_pending
= MVPP2_MAX_RXD
;
5869 ring
->tx_max_pending
= MVPP2_MAX_TXD
;
5870 ring
->rx_pending
= port
->rx_ring_size
;
5871 ring
->tx_pending
= port
->tx_ring_size
;
5874 static int mvpp2_ethtool_set_ringparam(struct net_device
*dev
,
5875 struct ethtool_ringparam
*ring
)
5877 struct mvpp2_port
*port
= netdev_priv(dev
);
5878 u16 prev_rx_ring_size
= port
->rx_ring_size
;
5879 u16 prev_tx_ring_size
= port
->tx_ring_size
;
5882 err
= mvpp2_check_ringparam_valid(dev
, ring
);
5886 if (!netif_running(dev
)) {
5887 port
->rx_ring_size
= ring
->rx_pending
;
5888 port
->tx_ring_size
= ring
->tx_pending
;
5892 /* The interface is running, so we have to force a
5893 * reallocation of the queues
5895 mvpp2_stop_dev(port
);
5896 mvpp2_cleanup_rxqs(port
);
5897 mvpp2_cleanup_txqs(port
);
5899 port
->rx_ring_size
= ring
->rx_pending
;
5900 port
->tx_ring_size
= ring
->tx_pending
;
5902 err
= mvpp2_setup_rxqs(port
);
5904 /* Reallocate Rx queues with the original ring size */
5905 port
->rx_ring_size
= prev_rx_ring_size
;
5906 ring
->rx_pending
= prev_rx_ring_size
;
5907 err
= mvpp2_setup_rxqs(port
);
5911 err
= mvpp2_setup_txqs(port
);
5913 /* Reallocate Tx queues with the original ring size */
5914 port
->tx_ring_size
= prev_tx_ring_size
;
5915 ring
->tx_pending
= prev_tx_ring_size
;
5916 err
= mvpp2_setup_txqs(port
);
5918 goto err_clean_rxqs
;
5921 mvpp2_start_dev(port
);
5922 mvpp2_egress_enable(port
);
5923 mvpp2_ingress_enable(port
);
5928 mvpp2_cleanup_rxqs(port
);
5930 netdev_err(dev
, "fail to change ring parameters");
5936 static const struct net_device_ops mvpp2_netdev_ops
= {
5937 .ndo_open
= mvpp2_open
,
5938 .ndo_stop
= mvpp2_stop
,
5939 .ndo_start_xmit
= mvpp2_tx
,
5940 .ndo_set_rx_mode
= mvpp2_set_rx_mode
,
5941 .ndo_set_mac_address
= mvpp2_set_mac_address
,
5942 .ndo_change_mtu
= mvpp2_change_mtu
,
5943 .ndo_get_stats64
= mvpp2_get_stats64
,
5944 .ndo_do_ioctl
= mvpp2_ioctl
,
5947 static const struct ethtool_ops mvpp2_eth_tool_ops
= {
5948 .nway_reset
= phy_ethtool_nway_reset
,
5949 .get_link
= ethtool_op_get_link
,
5950 .set_coalesce
= mvpp2_ethtool_set_coalesce
,
5951 .get_coalesce
= mvpp2_ethtool_get_coalesce
,
5952 .get_drvinfo
= mvpp2_ethtool_get_drvinfo
,
5953 .get_ringparam
= mvpp2_ethtool_get_ringparam
,
5954 .set_ringparam
= mvpp2_ethtool_set_ringparam
,
5955 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
5956 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
5959 /* Driver initialization */
5961 static void mvpp2_port_power_up(struct mvpp2_port
*port
)
5963 mvpp2_port_mii_set(port
);
5964 mvpp2_port_periodic_xon_disable(port
);
5965 mvpp2_port_fc_adv_enable(port
);
5966 mvpp2_port_reset(port
);
5969 /* Initialize port HW */
5970 static int mvpp2_port_init(struct mvpp2_port
*port
)
5972 struct device
*dev
= port
->dev
->dev
.parent
;
5973 struct mvpp2
*priv
= port
->priv
;
5974 struct mvpp2_txq_pcpu
*txq_pcpu
;
5975 int queue
, cpu
, err
;
5977 if (port
->first_rxq
+ rxq_number
> MVPP2_RXQ_TOTAL_NUM
)
5981 mvpp2_egress_disable(port
);
5982 mvpp2_port_disable(port
);
5984 port
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*port
->txqs
),
5989 /* Associate physical Tx queues to this port and initialize.
5990 * The mapping is predefined.
5992 for (queue
= 0; queue
< txq_number
; queue
++) {
5993 int queue_phy_id
= mvpp2_txq_phys(port
->id
, queue
);
5994 struct mvpp2_tx_queue
*txq
;
5996 txq
= devm_kzalloc(dev
, sizeof(*txq
), GFP_KERNEL
);
5999 goto err_free_percpu
;
6002 txq
->pcpu
= alloc_percpu(struct mvpp2_txq_pcpu
);
6005 goto err_free_percpu
;
6008 txq
->id
= queue_phy_id
;
6009 txq
->log_id
= queue
;
6010 txq
->done_pkts_coal
= MVPP2_TXDONE_COAL_PKTS_THRESH
;
6011 for_each_present_cpu(cpu
) {
6012 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
6013 txq_pcpu
->cpu
= cpu
;
6016 port
->txqs
[queue
] = txq
;
6019 port
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*port
->rxqs
),
6023 goto err_free_percpu
;
6026 /* Allocate and initialize Rx queue for this port */
6027 for (queue
= 0; queue
< rxq_number
; queue
++) {
6028 struct mvpp2_rx_queue
*rxq
;
6030 /* Map physical Rx queue to port's logical Rx queue */
6031 rxq
= devm_kzalloc(dev
, sizeof(*rxq
), GFP_KERNEL
);
6034 goto err_free_percpu
;
6036 /* Map this Rx queue to a physical queue */
6037 rxq
->id
= port
->first_rxq
+ queue
;
6038 rxq
->port
= port
->id
;
6039 rxq
->logic_rxq
= queue
;
6041 port
->rxqs
[queue
] = rxq
;
6044 /* Configure Rx queue group interrupt for this port */
6045 mvpp2_write(priv
, MVPP2_ISR_RXQ_GROUP_REG(port
->id
), rxq_number
);
6047 /* Create Rx descriptor rings */
6048 for (queue
= 0; queue
< rxq_number
; queue
++) {
6049 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
6051 rxq
->size
= port
->rx_ring_size
;
6052 rxq
->pkts_coal
= MVPP2_RX_COAL_PKTS
;
6053 rxq
->time_coal
= MVPP2_RX_COAL_USEC
;
6056 mvpp2_ingress_disable(port
);
6058 /* Port default configuration */
6059 mvpp2_defaults_set(port
);
6061 /* Port's classifier configuration */
6062 mvpp2_cls_oversize_rxq_set(port
);
6063 mvpp2_cls_port_config(port
);
6065 /* Provide an initial Rx packet size */
6066 port
->pkt_size
= MVPP2_RX_PKT_SIZE(port
->dev
->mtu
);
6068 /* Initialize pools for swf */
6069 err
= mvpp2_swf_bm_pool_init(port
);
6071 goto err_free_percpu
;
6076 for (queue
= 0; queue
< txq_number
; queue
++) {
6077 if (!port
->txqs
[queue
])
6079 free_percpu(port
->txqs
[queue
]->pcpu
);
6084 /* Ports initialization */
6085 static int mvpp2_port_probe(struct platform_device
*pdev
,
6086 struct device_node
*port_node
,
6088 int *next_first_rxq
)
6090 struct device_node
*phy_node
;
6091 struct mvpp2_port
*port
;
6092 struct mvpp2_port_pcpu
*port_pcpu
;
6093 struct net_device
*dev
;
6094 struct resource
*res
;
6095 const char *dt_mac_addr
;
6096 const char *mac_from
;
6097 char hw_mac_addr
[ETH_ALEN
];
6101 int priv_common_regs_num
= 2;
6104 dev
= alloc_etherdev_mqs(sizeof(struct mvpp2_port
), txq_number
,
6109 phy_node
= of_parse_phandle(port_node
, "phy", 0);
6111 dev_err(&pdev
->dev
, "missing phy\n");
6113 goto err_free_netdev
;
6116 phy_mode
= of_get_phy_mode(port_node
);
6118 dev_err(&pdev
->dev
, "incorrect phy mode\n");
6120 goto err_free_netdev
;
6123 if (of_property_read_u32(port_node
, "port-id", &id
)) {
6125 dev_err(&pdev
->dev
, "missing port-id value\n");
6126 goto err_free_netdev
;
6129 dev
->tx_queue_len
= MVPP2_MAX_TXD
;
6130 dev
->watchdog_timeo
= 5 * HZ
;
6131 dev
->netdev_ops
= &mvpp2_netdev_ops
;
6132 dev
->ethtool_ops
= &mvpp2_eth_tool_ops
;
6134 port
= netdev_priv(dev
);
6136 port
->irq
= irq_of_parse_and_map(port_node
, 0);
6137 if (port
->irq
<= 0) {
6139 goto err_free_netdev
;
6142 if (of_property_read_bool(port_node
, "marvell,loopback"))
6143 port
->flags
|= MVPP2_F_LOOPBACK
;
6147 port
->first_rxq
= *next_first_rxq
;
6148 port
->phy_node
= phy_node
;
6149 port
->phy_interface
= phy_mode
;
6151 res
= platform_get_resource(pdev
, IORESOURCE_MEM
,
6152 priv_common_regs_num
+ id
);
6153 port
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
6154 if (IS_ERR(port
->base
)) {
6155 err
= PTR_ERR(port
->base
);
6159 /* Alloc per-cpu stats */
6160 port
->stats
= netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats
);
6166 dt_mac_addr
= of_get_mac_address(port_node
);
6167 if (dt_mac_addr
&& is_valid_ether_addr(dt_mac_addr
)) {
6168 mac_from
= "device tree";
6169 ether_addr_copy(dev
->dev_addr
, dt_mac_addr
);
6171 mvpp2_get_mac_address(port
, hw_mac_addr
);
6172 if (is_valid_ether_addr(hw_mac_addr
)) {
6173 mac_from
= "hardware";
6174 ether_addr_copy(dev
->dev_addr
, hw_mac_addr
);
6176 mac_from
= "random";
6177 eth_hw_addr_random(dev
);
6181 port
->tx_ring_size
= MVPP2_MAX_TXD
;
6182 port
->rx_ring_size
= MVPP2_MAX_RXD
;
6184 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6186 err
= mvpp2_port_init(port
);
6188 dev_err(&pdev
->dev
, "failed to init port %d\n", id
);
6189 goto err_free_stats
;
6191 mvpp2_port_power_up(port
);
6193 port
->pcpu
= alloc_percpu(struct mvpp2_port_pcpu
);
6196 goto err_free_txq_pcpu
;
6199 for_each_present_cpu(cpu
) {
6200 port_pcpu
= per_cpu_ptr(port
->pcpu
, cpu
);
6202 hrtimer_init(&port_pcpu
->tx_done_timer
, CLOCK_MONOTONIC
,
6203 HRTIMER_MODE_REL_PINNED
);
6204 port_pcpu
->tx_done_timer
.function
= mvpp2_hr_timer_cb
;
6205 port_pcpu
->timer_scheduled
= false;
6207 tasklet_init(&port_pcpu
->tx_done_tasklet
, mvpp2_tx_proc_cb
,
6208 (unsigned long)dev
);
6211 netif_napi_add(dev
, &port
->napi
, mvpp2_poll
, NAPI_POLL_WEIGHT
);
6212 features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
6213 dev
->features
= features
| NETIF_F_RXCSUM
;
6214 dev
->hw_features
|= features
| NETIF_F_RXCSUM
| NETIF_F_GRO
;
6215 dev
->vlan_features
|= features
;
6217 /* MTU range: 68 - 9676 */
6218 dev
->min_mtu
= ETH_MIN_MTU
;
6219 /* 9676 == 9700 - 20 and rounding to 8 */
6220 dev
->max_mtu
= 9676;
6222 err
= register_netdev(dev
);
6224 dev_err(&pdev
->dev
, "failed to register netdev\n");
6225 goto err_free_port_pcpu
;
6227 netdev_info(dev
, "Using %s mac address %pM\n", mac_from
, dev
->dev_addr
);
6229 /* Increment the first Rx queue number to be used by the next port */
6230 *next_first_rxq
+= rxq_number
;
6231 priv
->port_list
[id
] = port
;
6235 free_percpu(port
->pcpu
);
6237 for (i
= 0; i
< txq_number
; i
++)
6238 free_percpu(port
->txqs
[i
]->pcpu
);
6240 free_percpu(port
->stats
);
6242 irq_dispose_mapping(port
->irq
);
6244 of_node_put(phy_node
);
6249 /* Ports removal routine */
6250 static void mvpp2_port_remove(struct mvpp2_port
*port
)
6254 unregister_netdev(port
->dev
);
6255 of_node_put(port
->phy_node
);
6256 free_percpu(port
->pcpu
);
6257 free_percpu(port
->stats
);
6258 for (i
= 0; i
< txq_number
; i
++)
6259 free_percpu(port
->txqs
[i
]->pcpu
);
6260 irq_dispose_mapping(port
->irq
);
6261 free_netdev(port
->dev
);
6264 /* Initialize decoding windows */
6265 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info
*dram
,
6271 for (i
= 0; i
< 6; i
++) {
6272 mvpp2_write(priv
, MVPP2_WIN_BASE(i
), 0);
6273 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
), 0);
6276 mvpp2_write(priv
, MVPP2_WIN_REMAP(i
), 0);
6281 for (i
= 0; i
< dram
->num_cs
; i
++) {
6282 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
6284 mvpp2_write(priv
, MVPP2_WIN_BASE(i
),
6285 (cs
->base
& 0xffff0000) | (cs
->mbus_attr
<< 8) |
6286 dram
->mbus_dram_target_id
);
6288 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
),
6289 (cs
->size
- 1) & 0xffff0000);
6291 win_enable
|= (1 << i
);
6294 mvpp2_write(priv
, MVPP2_BASE_ADDR_ENABLE
, win_enable
);
6297 /* Initialize Rx FIFO's */
6298 static void mvpp2_rx_fifo_init(struct mvpp2
*priv
)
6302 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
6303 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
6304 MVPP2_RX_FIFO_PORT_DATA_SIZE
);
6305 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
6306 MVPP2_RX_FIFO_PORT_ATTR_SIZE
);
6309 mvpp2_write(priv
, MVPP2_RX_MIN_PKT_SIZE_REG
,
6310 MVPP2_RX_FIFO_PORT_MIN_PKT
);
6311 mvpp2_write(priv
, MVPP2_RX_FIFO_INIT_REG
, 0x1);
6314 /* Initialize network controller common part HW */
6315 static int mvpp2_init(struct platform_device
*pdev
, struct mvpp2
*priv
)
6317 const struct mbus_dram_target_info
*dram_target_info
;
6321 /* Checks for hardware constraints */
6322 if (rxq_number
% 4 || (rxq_number
> MVPP2_MAX_RXQ
) ||
6323 (txq_number
> MVPP2_MAX_TXQ
)) {
6324 dev_err(&pdev
->dev
, "invalid queue size parameter\n");
6328 /* MBUS windows configuration */
6329 dram_target_info
= mv_mbus_dram_info();
6330 if (dram_target_info
)
6331 mvpp2_conf_mbus_windows(dram_target_info
, priv
);
6333 /* Disable HW PHY polling */
6334 val
= readl(priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
6335 val
|= MVPP2_PHY_AN_STOP_SMI0_MASK
;
6336 writel(val
, priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
6338 /* Allocate and initialize aggregated TXQs */
6339 priv
->aggr_txqs
= devm_kcalloc(&pdev
->dev
, num_present_cpus(),
6340 sizeof(struct mvpp2_tx_queue
),
6342 if (!priv
->aggr_txqs
)
6345 for_each_present_cpu(i
) {
6346 priv
->aggr_txqs
[i
].id
= i
;
6347 priv
->aggr_txqs
[i
].size
= MVPP2_AGGR_TXQ_SIZE
;
6348 err
= mvpp2_aggr_txq_init(pdev
, &priv
->aggr_txqs
[i
],
6349 MVPP2_AGGR_TXQ_SIZE
, i
, priv
);
6355 mvpp2_rx_fifo_init(priv
);
6357 /* Reset Rx queue group interrupt configuration */
6358 for (i
= 0; i
< MVPP2_MAX_PORTS
; i
++)
6359 mvpp2_write(priv
, MVPP2_ISR_RXQ_GROUP_REG(i
), rxq_number
);
6361 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT
,
6362 priv
->lms_base
+ MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG
);
6364 /* Allow cache snoop when transmiting packets */
6365 mvpp2_write(priv
, MVPP2_TX_SNOOP_REG
, 0x1);
6367 /* Buffer Manager initialization */
6368 err
= mvpp2_bm_init(pdev
, priv
);
6372 /* Parser default initialization */
6373 err
= mvpp2_prs_default_init(pdev
, priv
);
6377 /* Classifier default initialization */
6378 mvpp2_cls_init(priv
);
6383 static int mvpp2_probe(struct platform_device
*pdev
)
6385 struct device_node
*dn
= pdev
->dev
.of_node
;
6386 struct device_node
*port_node
;
6388 struct resource
*res
;
6389 int port_count
, first_rxq
;
6392 priv
= devm_kzalloc(&pdev
->dev
, sizeof(struct mvpp2
), GFP_KERNEL
);
6396 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
6397 priv
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
6398 if (IS_ERR(priv
->base
))
6399 return PTR_ERR(priv
->base
);
6401 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
6402 priv
->lms_base
= devm_ioremap_resource(&pdev
->dev
, res
);
6403 if (IS_ERR(priv
->lms_base
))
6404 return PTR_ERR(priv
->lms_base
);
6406 priv
->pp_clk
= devm_clk_get(&pdev
->dev
, "pp_clk");
6407 if (IS_ERR(priv
->pp_clk
))
6408 return PTR_ERR(priv
->pp_clk
);
6409 err
= clk_prepare_enable(priv
->pp_clk
);
6413 priv
->gop_clk
= devm_clk_get(&pdev
->dev
, "gop_clk");
6414 if (IS_ERR(priv
->gop_clk
)) {
6415 err
= PTR_ERR(priv
->gop_clk
);
6418 err
= clk_prepare_enable(priv
->gop_clk
);
6422 /* Get system's tclk rate */
6423 priv
->tclk
= clk_get_rate(priv
->pp_clk
);
6425 /* Initialize network controller */
6426 err
= mvpp2_init(pdev
, priv
);
6428 dev_err(&pdev
->dev
, "failed to initialize controller\n");
6432 port_count
= of_get_available_child_count(dn
);
6433 if (port_count
== 0) {
6434 dev_err(&pdev
->dev
, "no ports enabled\n");
6439 priv
->port_list
= devm_kcalloc(&pdev
->dev
, port_count
,
6440 sizeof(struct mvpp2_port
*),
6442 if (!priv
->port_list
) {
6447 /* Initialize ports */
6449 for_each_available_child_of_node(dn
, port_node
) {
6450 err
= mvpp2_port_probe(pdev
, port_node
, priv
, &first_rxq
);
6455 platform_set_drvdata(pdev
, priv
);
6459 clk_disable_unprepare(priv
->gop_clk
);
6461 clk_disable_unprepare(priv
->pp_clk
);
6465 static int mvpp2_remove(struct platform_device
*pdev
)
6467 struct mvpp2
*priv
= platform_get_drvdata(pdev
);
6468 struct device_node
*dn
= pdev
->dev
.of_node
;
6469 struct device_node
*port_node
;
6472 for_each_available_child_of_node(dn
, port_node
) {
6473 if (priv
->port_list
[i
])
6474 mvpp2_port_remove(priv
->port_list
[i
]);
6478 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
6479 struct mvpp2_bm_pool
*bm_pool
= &priv
->bm_pools
[i
];
6481 mvpp2_bm_pool_destroy(pdev
, priv
, bm_pool
);
6484 for_each_present_cpu(i
) {
6485 struct mvpp2_tx_queue
*aggr_txq
= &priv
->aggr_txqs
[i
];
6487 dma_free_coherent(&pdev
->dev
,
6488 MVPP2_AGGR_TXQ_SIZE
* MVPP2_DESC_ALIGNED_SIZE
,
6490 aggr_txq
->descs_phys
);
6493 clk_disable_unprepare(priv
->pp_clk
);
6494 clk_disable_unprepare(priv
->gop_clk
);
6499 static const struct of_device_id mvpp2_match
[] = {
6500 { .compatible
= "marvell,armada-375-pp2" },
6503 MODULE_DEVICE_TABLE(of
, mvpp2_match
);
6505 static struct platform_driver mvpp2_driver
= {
6506 .probe
= mvpp2_probe
,
6507 .remove
= mvpp2_remove
,
6509 .name
= MVPP2_DRIVER_NAME
,
6510 .of_match_table
= mvpp2_match
,
6514 module_platform_driver(mvpp2_driver
);
6516 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
6517 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
6518 MODULE_LICENSE("GPL v2");