2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos5260 SoC.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/syscore_ops.h>
19 #include "clk-exynos5260.h"
23 #include <dt-bindings/clock/exynos5260-clk.h>
25 static LIST_HEAD(clock_reg_cache_list
);
27 struct exynos5260_clock_reg_cache
{
28 struct list_head node
;
29 void __iomem
*reg_base
;
30 struct samsung_clk_reg_dump
*rdump
;
34 struct exynos5260_cmu_info
{
35 /* list of pll clocks and respective count */
36 struct samsung_pll_clock
*pll_clks
;
37 unsigned int nr_pll_clks
;
38 /* list of mux clocks and respective count */
39 struct samsung_mux_clock
*mux_clks
;
40 unsigned int nr_mux_clks
;
41 /* list of div clocks and respective count */
42 struct samsung_div_clock
*div_clks
;
43 unsigned int nr_div_clks
;
44 /* list of gate clocks and respective count */
45 struct samsung_gate_clock
*gate_clks
;
46 unsigned int nr_gate_clks
;
47 /* list of fixed clocks and respective count */
48 struct samsung_fixed_rate_clock
*fixed_clks
;
49 unsigned int nr_fixed_clks
;
50 /* total number of clocks with IDs assigned*/
51 unsigned int nr_clk_ids
;
53 /* list and number of clocks registers */
54 unsigned long *clk_regs
;
55 unsigned int nr_clk_regs
;
59 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
60 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
62 static struct samsung_pll_rate_table pll2550_24mhz_tbl
[] __initdata
= {
63 PLL_35XX_RATE(1700000000, 425, 6, 0),
64 PLL_35XX_RATE(1600000000, 200, 3, 0),
65 PLL_35XX_RATE(1500000000, 250, 4, 0),
66 PLL_35XX_RATE(1400000000, 175, 3, 0),
67 PLL_35XX_RATE(1300000000, 325, 6, 0),
68 PLL_35XX_RATE(1200000000, 400, 4, 1),
69 PLL_35XX_RATE(1100000000, 275, 3, 1),
70 PLL_35XX_RATE(1000000000, 250, 3, 1),
71 PLL_35XX_RATE(933000000, 311, 4, 1),
72 PLL_35XX_RATE(900000000, 300, 4, 1),
73 PLL_35XX_RATE(800000000, 200, 3, 1),
74 PLL_35XX_RATE(733000000, 733, 12, 1),
75 PLL_35XX_RATE(700000000, 175, 3, 1),
76 PLL_35XX_RATE(667000000, 667, 12, 1),
77 PLL_35XX_RATE(633000000, 211, 4, 1),
78 PLL_35XX_RATE(620000000, 310, 3, 2),
79 PLL_35XX_RATE(600000000, 400, 4, 2),
80 PLL_35XX_RATE(543000000, 362, 4, 2),
81 PLL_35XX_RATE(533000000, 533, 6, 2),
82 PLL_35XX_RATE(500000000, 250, 3, 2),
83 PLL_35XX_RATE(450000000, 300, 4, 2),
84 PLL_35XX_RATE(400000000, 200, 3, 2),
85 PLL_35XX_RATE(350000000, 175, 3, 2),
86 PLL_35XX_RATE(300000000, 400, 4, 3),
87 PLL_35XX_RATE(266000000, 266, 3, 3),
88 PLL_35XX_RATE(200000000, 200, 3, 3),
89 PLL_35XX_RATE(160000000, 160, 3, 3),
93 * Applicable for 2650 Type PLL for AUD_PLL.
95 static struct samsung_pll_rate_table pll2650_24mhz_tbl
[] __initdata
= {
96 PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
97 PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
98 PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
99 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
100 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
101 PLL_36XX_RATE(532000000, 266, 3, 2, 0),
102 PLL_36XX_RATE(480000000, 160, 2, 2, 0),
103 PLL_36XX_RATE(432000000, 144, 2, 2, 0),
104 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
105 PLL_36XX_RATE(394073130, 459, 7, 2, 49282),
106 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
107 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
108 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
109 PLL_36XX_RATE(200000000, 200, 3, 3, 0),
110 PLL_36XX_RATE(166000000, 166, 3, 3, 0),
111 PLL_36XX_RATE(133000000, 266, 3, 4, 0),
112 PLL_36XX_RATE(100000000, 200, 3, 4, 0),
113 PLL_36XX_RATE(66000000, 176, 2, 5, 0),
116 #ifdef CONFIG_PM_SLEEP
118 static int exynos5260_clk_suspend(void)
120 struct exynos5260_clock_reg_cache
*cache
;
122 list_for_each_entry(cache
, &clock_reg_cache_list
, node
)
123 samsung_clk_save(cache
->reg_base
, cache
->rdump
,
129 static void exynos5260_clk_resume(void)
131 struct exynos5260_clock_reg_cache
*cache
;
133 list_for_each_entry(cache
, &clock_reg_cache_list
, node
)
134 samsung_clk_restore(cache
->reg_base
, cache
->rdump
,
138 static struct syscore_ops exynos5260_clk_syscore_ops
= {
139 .suspend
= exynos5260_clk_suspend
,
140 .resume
= exynos5260_clk_resume
,
143 static void exynos5260_clk_sleep_init(void __iomem
*reg_base
,
144 unsigned long *rdump
,
145 unsigned long nr_rdump
)
147 struct exynos5260_clock_reg_cache
*reg_cache
;
149 reg_cache
= kzalloc(sizeof(struct exynos5260_clock_reg_cache
),
152 panic("could not allocate register cache.\n");
154 reg_cache
->rdump
= samsung_clk_alloc_reg_dump(rdump
, nr_rdump
);
156 if (!reg_cache
->rdump
)
157 panic("could not allocate register dump storage.\n");
159 if (list_empty(&clock_reg_cache_list
))
160 register_syscore_ops(&exynos5260_clk_syscore_ops
);
162 reg_cache
->rd_num
= nr_rdump
;
163 reg_cache
->reg_base
= reg_base
;
164 list_add_tail(®_cache
->node
, &clock_reg_cache_list
);
168 static void exynos5260_clk_sleep_init(void __iomem
*reg_base
,
169 unsigned long *rdump
,
170 unsigned long nr_rdump
){}
174 * Common function which registers plls, muxes, dividers and gates
175 * for each CMU. It also add CMU register list to register cache.
178 void __init
exynos5260_cmu_register_one(struct device_node
*np
,
179 struct exynos5260_cmu_info
*cmu
)
181 void __iomem
*reg_base
;
182 struct samsung_clk_provider
*ctx
;
184 reg_base
= of_iomap(np
, 0);
186 panic("%s: failed to map registers\n", __func__
);
188 ctx
= samsung_clk_init(np
, reg_base
, cmu
->nr_clk_ids
);
190 panic("%s: unable to alllocate ctx\n", __func__
);
193 samsung_clk_register_pll(ctx
, cmu
->pll_clks
, cmu
->nr_pll_clks
,
196 samsung_clk_register_mux(ctx
, cmu
->mux_clks
,
199 samsung_clk_register_div(ctx
, cmu
->div_clks
, cmu
->nr_div_clks
);
201 samsung_clk_register_gate(ctx
, cmu
->gate_clks
,
204 samsung_clk_register_fixed_rate(ctx
, cmu
->fixed_clks
,
207 exynos5260_clk_sleep_init(reg_base
, cmu
->clk_regs
,
214 static unsigned long aud_clk_regs
[] __initdata
= {
224 PNAME(mout_aud_pll_user_p
) = {"fin_pll", "fout_aud_pll"};
225 PNAME(mout_sclk_aud_i2s_p
) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
226 PNAME(mout_sclk_aud_pcm_p
) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
228 struct samsung_mux_clock aud_mux_clks
[] __initdata
= {
229 MUX(AUD_MOUT_AUD_PLL_USER
, "mout_aud_pll_user", mout_aud_pll_user_p
,
231 MUX(AUD_MOUT_SCLK_AUD_I2S
, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p
,
233 MUX(AUD_MOUT_SCLK_AUD_PCM
, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p
,
237 struct samsung_div_clock aud_div_clks
[] __initdata
= {
238 DIV(AUD_DOUT_ACLK_AUD_131
, "dout_aclk_aud_131", "mout_aud_pll_user",
241 DIV(AUD_DOUT_SCLK_AUD_I2S
, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
243 DIV(AUD_DOUT_SCLK_AUD_PCM
, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
245 DIV(AUD_DOUT_SCLK_AUD_UART
, "dout_sclk_aud_uart", "mout_aud_pll_user",
249 struct samsung_gate_clock aud_gate_clks
[] __initdata
= {
250 GATE(AUD_SCLK_I2S
, "sclk_aud_i2s", "dout_sclk_aud_i2s",
251 EN_SCLK_AUD
, 0, CLK_SET_RATE_PARENT
, 0),
252 GATE(AUD_SCLK_PCM
, "sclk_aud_pcm", "dout_sclk_aud_pcm",
253 EN_SCLK_AUD
, 1, CLK_SET_RATE_PARENT
, 0),
254 GATE(AUD_SCLK_AUD_UART
, "sclk_aud_uart", "dout_sclk_aud_uart",
255 EN_SCLK_AUD
, 2, CLK_SET_RATE_PARENT
, 0),
257 GATE(AUD_CLK_SRAMC
, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD
,
259 GATE(AUD_CLK_DMAC
, "clk_dmac", "dout_aclk_aud_131",
261 GATE(AUD_CLK_I2S
, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD
, 2, 0, 0),
262 GATE(AUD_CLK_PCM
, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD
, 3, 0, 0),
263 GATE(AUD_CLK_AUD_UART
, "clk_aud_uart", "dout_aclk_aud_131",
267 static void __init
exynos5260_clk_aud_init(struct device_node
*np
)
269 struct exynos5260_cmu_info cmu
= {0};
271 cmu
.mux_clks
= aud_mux_clks
;
272 cmu
.nr_mux_clks
= ARRAY_SIZE(aud_mux_clks
);
273 cmu
.div_clks
= aud_div_clks
;
274 cmu
.nr_div_clks
= ARRAY_SIZE(aud_div_clks
);
275 cmu
.gate_clks
= aud_gate_clks
;
276 cmu
.nr_gate_clks
= ARRAY_SIZE(aud_gate_clks
);
277 cmu
.nr_clk_ids
= AUD_NR_CLK
;
278 cmu
.clk_regs
= aud_clk_regs
;
279 cmu
.nr_clk_regs
= ARRAY_SIZE(aud_clk_regs
);
281 exynos5260_cmu_register_one(np
, &cmu
);
284 CLK_OF_DECLARE(exynos5260_clk_aud
, "samsung,exynos5260-clock-aud",
285 exynos5260_clk_aud_init
);
290 static unsigned long disp_clk_regs
[] __initdata
= {
305 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p
) = {"fin_pll",
306 "phyclk_dptx_phy_ch3_txd_clk"};
307 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p
) = {"fin_pll",
308 "phyclk_dptx_phy_ch2_txd_clk"};
309 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p
) = {"fin_pll",
310 "phyclk_dptx_phy_ch1_txd_clk"};
311 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p
) = {"fin_pll",
312 "phyclk_dptx_phy_ch0_txd_clk"};
313 PNAME(mout_aclk_disp_222_user_p
) = {"fin_pll", "dout_aclk_disp_222"};
314 PNAME(mout_sclk_disp_pixel_user_p
) = {"fin_pll", "dout_sclk_disp_pixel"};
315 PNAME(mout_aclk_disp_333_user_p
) = {"fin_pll", "dout_aclk_disp_333"};
316 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p
) = {"fin_pll",
317 "phyclk_hdmi_phy_tmds_clko"};
318 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p
) = {"fin_pll",
319 "phyclk_hdmi_phy_ref_clko"};
320 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p
) = {"fin_pll",
321 "phyclk_hdmi_phy_pixel_clko"};
322 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p
) = {"fin_pll",
323 "phyclk_hdmi_link_o_tmds_clkhi"};
324 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p
) = {"fin_pll",
325 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
326 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p
) = {"fin_pll",
327 "phyclk_dptx_phy_o_ref_clk_24m"};
328 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p
) = {"fin_pll",
329 "phyclk_dptx_phy_clk_div2"};
330 PNAME(mout_sclk_hdmi_pixel_p
) = {"mout_sclk_disp_pixel_user",
331 "mout_aclk_disp_222_user"};
332 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p
) = {"fin_pll",
333 "phyclk_mipi_dphy_4l_m_rxclkesc0"};
334 PNAME(mout_sclk_hdmi_spdif_p
) = {"fin_pll", "ioclk_spdif_extclk",
335 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
337 struct samsung_mux_clock disp_mux_clks
[] __initdata
= {
338 MUX(DISP_MOUT_ACLK_DISP_333_USER
, "mout_aclk_disp_333_user",
339 mout_aclk_disp_333_user_p
,
340 MUX_SEL_DISP0
, 0, 1),
341 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER
, "mout_sclk_disp_pixel_user",
342 mout_sclk_disp_pixel_user_p
,
343 MUX_SEL_DISP0
, 4, 1),
344 MUX(DISP_MOUT_ACLK_DISP_222_USER
, "mout_aclk_disp_222_user",
345 mout_aclk_disp_222_user_p
,
346 MUX_SEL_DISP0
, 8, 1),
347 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER
,
348 "mout_phyclk_dptx_phy_ch0_txd_clk_user",
349 mout_phyclk_dptx_phy_ch0_txd_clk_user_p
,
350 MUX_SEL_DISP0
, 16, 1),
351 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER
,
352 "mout_phyclk_dptx_phy_ch1_txd_clk_user",
353 mout_phyclk_dptx_phy_ch1_txd_clk_user_p
,
354 MUX_SEL_DISP0
, 20, 1),
355 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER
,
356 "mout_phyclk_dptx_phy_ch2_txd_clk_user",
357 mout_phyclk_dptx_phy_ch2_txd_clk_user_p
,
358 MUX_SEL_DISP0
, 24, 1),
359 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER
,
360 "mout_phyclk_dptx_phy_ch3_txd_clk_user",
361 mout_phyclk_dptx_phy_ch3_txd_clk_user_p
,
362 MUX_SEL_DISP0
, 28, 1),
364 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER
,
365 "mout_phyclk_dptx_phy_clk_div2_user",
366 mout_phyclk_dptx_phy_clk_div2_user_p
,
367 MUX_SEL_DISP1
, 0, 1),
368 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER
,
369 "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
370 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p
,
371 MUX_SEL_DISP1
, 4, 1),
372 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS
,
373 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
374 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p
,
375 MUX_SEL_DISP1
, 8, 1),
376 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER
,
377 "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
378 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p
,
379 MUX_SEL_DISP1
, 16, 1),
380 MUX(DISP_MOUT_HDMI_PHY_PIXEL
,
381 "mout_phyclk_hdmi_phy_pixel_clko_user",
382 mout_phyclk_hdmi_phy_pixel_clko_user_p
,
383 MUX_SEL_DISP1
, 20, 1),
384 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER
,
385 "mout_phyclk_hdmi_phy_ref_clko_user",
386 mout_phyclk_hdmi_phy_ref_clko_user_p
,
387 MUX_SEL_DISP1
, 24, 1),
388 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER
,
389 "mout_phyclk_hdmi_phy_tmds_clko_user",
390 mout_phyclk_hdmi_phy_tmds_clko_user_p
,
391 MUX_SEL_DISP1
, 28, 1),
393 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER
,
394 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
395 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p
,
396 MUX_SEL_DISP2
, 0, 1),
397 MUX(DISP_MOUT_SCLK_HDMI_PIXEL
, "mout_sclk_hdmi_pixel",
398 mout_sclk_hdmi_pixel_p
,
399 MUX_SEL_DISP2
, 4, 1),
401 MUX(DISP_MOUT_SCLK_HDMI_SPDIF
, "mout_sclk_hdmi_spdif",
402 mout_sclk_hdmi_spdif_p
,
403 MUX_SEL_DISP4
, 4, 2),
406 struct samsung_div_clock disp_div_clks
[] __initdata
= {
407 DIV(DISP_DOUT_PCLK_DISP_111
, "dout_pclk_disp_111",
408 "mout_aclk_disp_222_user",
410 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL
, "dout_sclk_fimd1_extclkpll",
411 "mout_sclk_disp_pixel_user",
413 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI
,
414 "dout_sclk_hdmi_phy_pixel_clki",
415 "mout_sclk_hdmi_pixel",
419 struct samsung_gate_clock disp_gate_clks
[] __initdata
= {
420 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER
, "sclk_hdmi_link_i_pixel",
421 "mout_phyclk_hdmi_phy_pixel_clko_user",
422 EN_SCLK_DISP0
, 26, CLK_SET_RATE_PARENT
, 0),
423 GATE(DISP_SCLK_PIXEL
, "sclk_hdmi_phy_pixel_clki",
424 "dout_sclk_hdmi_phy_pixel_clki",
425 EN_SCLK_DISP0
, 29, CLK_SET_RATE_PARENT
, 0),
427 GATE(DISP_CLK_DP
, "clk_dptx_link", "mout_aclk_disp_222_user",
428 EN_IP_DISP
, 4, 0, 0),
429 GATE(DISP_CLK_DPPHY
, "clk_dptx_phy", "mout_aclk_disp_222_user",
430 EN_IP_DISP
, 5, 0, 0),
431 GATE(DISP_CLK_DSIM1
, "clk_dsim1", "mout_aclk_disp_222_user",
432 EN_IP_DISP
, 6, 0, 0),
433 GATE(DISP_CLK_FIMD1
, "clk_fimd1", "mout_aclk_disp_222_user",
434 EN_IP_DISP
, 7, 0, 0),
435 GATE(DISP_CLK_HDMI
, "clk_hdmi", "mout_aclk_disp_222_user",
436 EN_IP_DISP
, 8, 0, 0),
437 GATE(DISP_CLK_HDMIPHY
, "clk_hdmiphy", "mout_aclk_disp_222_user",
438 EN_IP_DISP
, 9, 0, 0),
439 GATE(DISP_CLK_MIPIPHY
, "clk_mipi_dphy", "mout_aclk_disp_222_user",
440 EN_IP_DISP
, 10, 0, 0),
441 GATE(DISP_CLK_MIXER
, "clk_mixer", "mout_aclk_disp_222_user",
442 EN_IP_DISP
, 11, 0, 0),
443 GATE(DISP_CLK_PIXEL_DISP
, "clk_pixel_disp", "mout_aclk_disp_222_user",
444 EN_IP_DISP
, 12, CLK_IGNORE_UNUSED
, 0),
445 GATE(DISP_CLK_PIXEL_MIXER
, "clk_pixel_mixer", "mout_aclk_disp_222_user",
446 EN_IP_DISP
, 13, CLK_IGNORE_UNUSED
, 0),
447 GATE(DISP_CLK_SMMU_FIMD1M0
, "clk_smmu3_fimd1m0",
448 "mout_aclk_disp_222_user",
449 EN_IP_DISP
, 22, 0, 0),
450 GATE(DISP_CLK_SMMU_FIMD1M1
, "clk_smmu3_fimd1m1",
451 "mout_aclk_disp_222_user",
452 EN_IP_DISP
, 23, 0, 0),
453 GATE(DISP_CLK_SMMU_TV
, "clk_smmu3_tv", "mout_aclk_disp_222_user",
454 EN_IP_DISP
, 25, 0, 0),
457 static void __init
exynos5260_clk_disp_init(struct device_node
*np
)
459 struct exynos5260_cmu_info cmu
= {0};
461 cmu
.mux_clks
= disp_mux_clks
;
462 cmu
.nr_mux_clks
= ARRAY_SIZE(disp_mux_clks
);
463 cmu
.div_clks
= disp_div_clks
;
464 cmu
.nr_div_clks
= ARRAY_SIZE(disp_div_clks
);
465 cmu
.gate_clks
= disp_gate_clks
;
466 cmu
.nr_gate_clks
= ARRAY_SIZE(disp_gate_clks
);
467 cmu
.nr_clk_ids
= DISP_NR_CLK
;
468 cmu
.clk_regs
= disp_clk_regs
;
469 cmu
.nr_clk_regs
= ARRAY_SIZE(disp_clk_regs
);
471 exynos5260_cmu_register_one(np
, &cmu
);
474 CLK_OF_DECLARE(exynos5260_clk_disp
, "samsung,exynos5260-clock-disp",
475 exynos5260_clk_disp_init
);
480 static unsigned long egl_clk_regs
[] __initdata
= {
494 PNAME(mout_egl_b_p
) = {"mout_egl_pll", "dout_bus_pll"};
495 PNAME(mout_egl_pll_p
) = {"fin_pll", "fout_egl_pll"};
497 struct samsung_mux_clock egl_mux_clks
[] __initdata
= {
498 MUX(EGL_MOUT_EGL_PLL
, "mout_egl_pll", mout_egl_pll_p
,
500 MUX(EGL_MOUT_EGL_B
, "mout_egl_b", mout_egl_b_p
, MUX_SEL_EGL
, 16, 1),
503 struct samsung_div_clock egl_div_clks
[] __initdata
= {
504 DIV(EGL_DOUT_EGL1
, "dout_egl1", "mout_egl_b", DIV_EGL
, 0, 3),
505 DIV(EGL_DOUT_EGL2
, "dout_egl2", "dout_egl1", DIV_EGL
, 4, 3),
506 DIV(EGL_DOUT_ACLK_EGL
, "dout_aclk_egl", "dout_egl2", DIV_EGL
, 8, 3),
507 DIV(EGL_DOUT_PCLK_EGL
, "dout_pclk_egl", "dout_egl_atclk",
509 DIV(EGL_DOUT_EGL_ATCLK
, "dout_egl_atclk", "dout_egl2", DIV_EGL
, 16, 3),
510 DIV(EGL_DOUT_EGL_PCLK_DBG
, "dout_egl_pclk_dbg", "dout_egl_atclk",
512 DIV(EGL_DOUT_EGL_PLL
, "dout_egl_pll", "mout_egl_b", DIV_EGL
, 24, 3),
515 static struct samsung_pll_clock egl_pll_clks
[] __initdata
= {
516 PLL(pll_2550xx
, EGL_FOUT_EGL_PLL
, "fout_egl_pll", "fin_pll",
517 EGL_PLL_LOCK
, EGL_PLL_CON0
,
521 static void __init
exynos5260_clk_egl_init(struct device_node
*np
)
523 struct exynos5260_cmu_info cmu
= {0};
525 cmu
.pll_clks
= egl_pll_clks
;
526 cmu
.nr_pll_clks
= ARRAY_SIZE(egl_pll_clks
);
527 cmu
.mux_clks
= egl_mux_clks
;
528 cmu
.nr_mux_clks
= ARRAY_SIZE(egl_mux_clks
);
529 cmu
.div_clks
= egl_div_clks
;
530 cmu
.nr_div_clks
= ARRAY_SIZE(egl_div_clks
);
531 cmu
.nr_clk_ids
= EGL_NR_CLK
;
532 cmu
.clk_regs
= egl_clk_regs
;
533 cmu
.nr_clk_regs
= ARRAY_SIZE(egl_clk_regs
);
535 exynos5260_cmu_register_one(np
, &cmu
);
538 CLK_OF_DECLARE(exynos5260_clk_egl
, "samsung,exynos5260-clock-egl",
539 exynos5260_clk_egl_init
);
544 static unsigned long fsys_clk_regs
[] __initdata
= {
548 EN_ACLK_FSYS_SECURE_RTIC
,
549 EN_ACLK_FSYS_SECURE_SMMU_RTIC
,
552 EN_IP_FSYS_SECURE_RTIC
,
553 EN_IP_FSYS_SECURE_SMMU_RTIC
,
556 PNAME(mout_phyclk_usbhost20_phyclk_user_p
) = {"fin_pll",
557 "phyclk_usbhost20_phy_phyclock"};
558 PNAME(mout_phyclk_usbhost20_freeclk_user_p
) = {"fin_pll",
559 "phyclk_usbhost20_phy_freeclk"};
560 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p
) = {"fin_pll",
561 "phyclk_usbhost20_phy_clk48mohci"};
562 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p
) = {"fin_pll",
563 "phyclk_usbdrd30_udrd30_pipe_pclk"};
564 PNAME(mout_phyclk_usbdrd30_phyclock_user_p
) = {"fin_pll",
565 "phyclk_usbdrd30_udrd30_phyclock"};
567 struct samsung_mux_clock fsys_mux_clks
[] __initdata
= {
568 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER
,
569 "mout_phyclk_usbdrd30_phyclock_user",
570 mout_phyclk_usbdrd30_phyclock_user_p
,
571 MUX_SEL_FSYS1
, 0, 1),
572 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER
,
573 "mout_phyclk_usbdrd30_pipe_pclk_user",
574 mout_phyclk_usbdrd30_pipe_pclk_user_p
,
575 MUX_SEL_FSYS1
, 4, 1),
576 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER
,
577 "mout_phyclk_usbhost20_clk48mohci_user",
578 mout_phyclk_usbhost20_clk48mohci_user_p
,
579 MUX_SEL_FSYS1
, 8, 1),
580 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER
,
581 "mout_phyclk_usbhost20_freeclk_user",
582 mout_phyclk_usbhost20_freeclk_user_p
,
583 MUX_SEL_FSYS1
, 12, 1),
584 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER
,
585 "mout_phyclk_usbhost20_phyclk_user",
586 mout_phyclk_usbhost20_phyclk_user_p
,
587 MUX_SEL_FSYS1
, 16, 1),
590 struct samsung_gate_clock fsys_gate_clks
[] __initdata
= {
591 GATE(FSYS_PHYCLK_USBHOST20
, "phyclk_usbhost20_phyclock",
592 "mout_phyclk_usbdrd30_phyclock_user",
593 EN_SCLK_FSYS
, 1, 0, 0),
594 GATE(FSYS_PHYCLK_USBDRD30
, "phyclk_usbdrd30_udrd30_phyclock_g",
595 "mout_phyclk_usbdrd30_phyclock_user",
596 EN_SCLK_FSYS
, 7, 0, 0),
598 GATE(FSYS_CLK_MMC0
, "clk_mmc0", "dout_aclk_fsys_200",
599 EN_IP_FSYS
, 6, 0, 0),
600 GATE(FSYS_CLK_MMC1
, "clk_mmc1", "dout_aclk_fsys_200",
601 EN_IP_FSYS
, 7, 0, 0),
602 GATE(FSYS_CLK_MMC2
, "clk_mmc2", "dout_aclk_fsys_200",
603 EN_IP_FSYS
, 8, 0, 0),
604 GATE(FSYS_CLK_PDMA
, "clk_pdma", "dout_aclk_fsys_200",
605 EN_IP_FSYS
, 9, 0, 0),
606 GATE(FSYS_CLK_SROMC
, "clk_sromc", "dout_aclk_fsys_200",
607 EN_IP_FSYS
, 13, 0, 0),
608 GATE(FSYS_CLK_USBDRD30
, "clk_usbdrd30", "dout_aclk_fsys_200",
609 EN_IP_FSYS
, 14, 0, 0),
610 GATE(FSYS_CLK_USBHOST20
, "clk_usbhost20", "dout_aclk_fsys_200",
611 EN_IP_FSYS
, 15, 0, 0),
612 GATE(FSYS_CLK_USBLINK
, "clk_usblink", "dout_aclk_fsys_200",
613 EN_IP_FSYS
, 18, 0, 0),
614 GATE(FSYS_CLK_TSI
, "clk_tsi", "dout_aclk_fsys_200",
615 EN_IP_FSYS
, 20, 0, 0),
617 GATE(FSYS_CLK_RTIC
, "clk_rtic", "dout_aclk_fsys_200",
618 EN_IP_FSYS_SECURE_RTIC
, 11, 0, 0),
619 GATE(FSYS_CLK_SMMU_RTIC
, "clk_smmu_rtic", "dout_aclk_fsys_200",
620 EN_IP_FSYS_SECURE_SMMU_RTIC
, 12, 0, 0),
623 static void __init
exynos5260_clk_fsys_init(struct device_node
*np
)
625 struct exynos5260_cmu_info cmu
= {0};
627 cmu
.mux_clks
= fsys_mux_clks
;
628 cmu
.nr_mux_clks
= ARRAY_SIZE(fsys_mux_clks
);
629 cmu
.gate_clks
= fsys_gate_clks
;
630 cmu
.nr_gate_clks
= ARRAY_SIZE(fsys_gate_clks
);
631 cmu
.nr_clk_ids
= FSYS_NR_CLK
;
632 cmu
.clk_regs
= fsys_clk_regs
;
633 cmu
.nr_clk_regs
= ARRAY_SIZE(fsys_clk_regs
);
635 exynos5260_cmu_register_one(np
, &cmu
);
638 CLK_OF_DECLARE(exynos5260_clk_fsys
, "samsung,exynos5260-clock-fsys",
639 exynos5260_clk_fsys_init
);
644 static unsigned long g2d_clk_regs
[] __initdata
= {
649 EN_ACLK_G2D_SECURE_SSS
,
650 EN_ACLK_G2D_SECURE_SLIM_SSS
,
651 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS
,
652 EN_ACLK_G2D_SECURE_SMMU_SSS
,
653 EN_ACLK_G2D_SECURE_SMMU_MDMA
,
654 EN_ACLK_G2D_SECURE_SMMU_G2D
,
656 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS
,
657 EN_PCLK_G2D_SECURE_SMMU_SSS
,
658 EN_PCLK_G2D_SECURE_SMMU_MDMA
,
659 EN_PCLK_G2D_SECURE_SMMU_G2D
,
661 EN_IP_G2D_SECURE_SSS
,
662 EN_IP_G2D_SECURE_SLIM_SSS
,
663 EN_IP_G2D_SECURE_SMMU_SLIM_SSS
,
664 EN_IP_G2D_SECURE_SMMU_SSS
,
665 EN_IP_G2D_SECURE_SMMU_MDMA
,
666 EN_IP_G2D_SECURE_SMMU_G2D
,
669 PNAME(mout_aclk_g2d_333_user_p
) = {"fin_pll", "dout_aclk_g2d_333"};
671 struct samsung_mux_clock g2d_mux_clks
[] __initdata
= {
672 MUX(G2D_MOUT_ACLK_G2D_333_USER
, "mout_aclk_g2d_333_user",
673 mout_aclk_g2d_333_user_p
,
677 struct samsung_div_clock g2d_div_clks
[] __initdata
= {
678 DIV(G2D_DOUT_PCLK_G2D_83
, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
682 struct samsung_gate_clock g2d_gate_clks
[] __initdata
= {
683 GATE(G2D_CLK_G2D
, "clk_g2d", "mout_aclk_g2d_333_user",
685 GATE(G2D_CLK_JPEG
, "clk_jpeg", "mout_aclk_g2d_333_user",
687 GATE(G2D_CLK_MDMA
, "clk_mdma", "mout_aclk_g2d_333_user",
689 GATE(G2D_CLK_SMMU3_JPEG
, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
690 EN_IP_G2D
, 16, 0, 0),
692 GATE(G2D_CLK_SSS
, "clk_sss", "mout_aclk_g2d_333_user",
693 EN_IP_G2D_SECURE_SSS
, 17, 0, 0),
695 GATE(G2D_CLK_SLIM_SSS
, "clk_slim_sss", "mout_aclk_g2d_333_user",
696 EN_IP_G2D_SECURE_SLIM_SSS
, 11, 0, 0),
698 GATE(G2D_CLK_SMMU_SLIM_SSS
, "clk_smmu_slim_sss",
699 "mout_aclk_g2d_333_user",
700 EN_IP_G2D_SECURE_SMMU_SLIM_SSS
, 13, 0, 0),
702 GATE(G2D_CLK_SMMU_SSS
, "clk_smmu_sss", "mout_aclk_g2d_333_user",
703 EN_IP_G2D_SECURE_SMMU_SSS
, 14, 0, 0),
705 GATE(G2D_CLK_SMMU_MDMA
, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
706 EN_IP_G2D_SECURE_SMMU_MDMA
, 12, 0, 0),
708 GATE(G2D_CLK_SMMU3_G2D
, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
709 EN_IP_G2D_SECURE_SMMU_G2D
, 15, 0, 0),
712 static void __init
exynos5260_clk_g2d_init(struct device_node
*np
)
714 struct exynos5260_cmu_info cmu
= {0};
716 cmu
.mux_clks
= g2d_mux_clks
;
717 cmu
.nr_mux_clks
= ARRAY_SIZE(g2d_mux_clks
);
718 cmu
.div_clks
= g2d_div_clks
;
719 cmu
.nr_div_clks
= ARRAY_SIZE(g2d_div_clks
);
720 cmu
.gate_clks
= g2d_gate_clks
;
721 cmu
.nr_gate_clks
= ARRAY_SIZE(g2d_gate_clks
);
722 cmu
.nr_clk_ids
= G2D_NR_CLK
;
723 cmu
.clk_regs
= g2d_clk_regs
;
724 cmu
.nr_clk_regs
= ARRAY_SIZE(g2d_clk_regs
);
726 exynos5260_cmu_register_one(np
, &cmu
);
729 CLK_OF_DECLARE(exynos5260_clk_g2d
, "samsung,exynos5260-clock-g2d",
730 exynos5260_clk_g2d_init
);
735 static unsigned long g3d_clk_regs
[] __initdata
= {
749 PNAME(mout_g3d_pll_p
) = {"fin_pll", "fout_g3d_pll"};
751 struct samsung_mux_clock g3d_mux_clks
[] __initdata
= {
752 MUX(G3D_MOUT_G3D_PLL
, "mout_g3d_pll", mout_g3d_pll_p
,
756 struct samsung_div_clock g3d_div_clks
[] __initdata
= {
757 DIV(G3D_DOUT_PCLK_G3D
, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D
, 0, 3),
758 DIV(G3D_DOUT_ACLK_G3D
, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D
, 4, 3),
761 struct samsung_gate_clock g3d_gate_clks
[] __initdata
= {
762 GATE(G3D_CLK_G3D
, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D
, 2, 0, 0),
763 GATE(G3D_CLK_G3D_HPM
, "clk_g3d_hpm", "dout_aclk_g3d",
767 static struct samsung_pll_clock g3d_pll_clks
[] __initdata
= {
768 PLL(pll_2550
, G3D_FOUT_G3D_PLL
, "fout_g3d_pll", "fin_pll",
769 G3D_PLL_LOCK
, G3D_PLL_CON0
,
773 static void __init
exynos5260_clk_g3d_init(struct device_node
*np
)
775 struct exynos5260_cmu_info cmu
= {0};
777 cmu
.pll_clks
= g3d_pll_clks
;
778 cmu
.nr_pll_clks
= ARRAY_SIZE(g3d_pll_clks
);
779 cmu
.mux_clks
= g3d_mux_clks
;
780 cmu
.nr_mux_clks
= ARRAY_SIZE(g3d_mux_clks
);
781 cmu
.div_clks
= g3d_div_clks
;
782 cmu
.nr_div_clks
= ARRAY_SIZE(g3d_div_clks
);
783 cmu
.gate_clks
= g3d_gate_clks
;
784 cmu
.nr_gate_clks
= ARRAY_SIZE(g3d_gate_clks
);
785 cmu
.nr_clk_ids
= G3D_NR_CLK
;
786 cmu
.clk_regs
= g3d_clk_regs
;
787 cmu
.nr_clk_regs
= ARRAY_SIZE(g3d_clk_regs
);
789 exynos5260_cmu_register_one(np
, &cmu
);
792 CLK_OF_DECLARE(exynos5260_clk_g3d
, "samsung,exynos5260-clock-g3d",
793 exynos5260_clk_g3d_init
);
798 static unsigned long gscl_clk_regs
[] __initdata
= {
803 EN_ACLK_GSCL_SECURE_SMMU_GSCL0
,
804 EN_ACLK_GSCL_SECURE_SMMU_GSCL1
,
805 EN_ACLK_GSCL_SECURE_SMMU_MSCL0
,
806 EN_ACLK_GSCL_SECURE_SMMU_MSCL1
,
809 EN_PCLK_GSCL_SECURE_SMMU_GSCL0
,
810 EN_PCLK_GSCL_SECURE_SMMU_GSCL1
,
811 EN_PCLK_GSCL_SECURE_SMMU_MSCL0
,
812 EN_PCLK_GSCL_SECURE_SMMU_MSCL1
,
817 EN_IP_GSCL_SECURE_SMMU_GSCL0
,
818 EN_IP_GSCL_SECURE_SMMU_GSCL1
,
819 EN_IP_GSCL_SECURE_SMMU_MSCL0
,
820 EN_IP_GSCL_SECURE_SMMU_MSCL1
,
823 PNAME(mout_aclk_gscl_333_user_p
) = {"fin_pll", "dout_aclk_gscl_333"};
824 PNAME(mout_aclk_m2m_400_user_p
) = {"fin_pll", "dout_aclk_gscl_400"};
825 PNAME(mout_aclk_gscl_fimc_user_p
) = {"fin_pll", "dout_aclk_gscl_400"};
826 PNAME(mout_aclk_csis_p
) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
828 struct samsung_mux_clock gscl_mux_clks
[] __initdata
= {
829 MUX(GSCL_MOUT_ACLK_GSCL_333_USER
, "mout_aclk_gscl_333_user",
830 mout_aclk_gscl_333_user_p
,
832 MUX(GSCL_MOUT_ACLK_M2M_400_USER
, "mout_aclk_m2m_400_user",
833 mout_aclk_m2m_400_user_p
,
835 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER
, "mout_aclk_gscl_fimc_user",
836 mout_aclk_gscl_fimc_user_p
,
838 MUX(GSCL_MOUT_ACLK_CSIS
, "mout_aclk_csis", mout_aclk_csis_p
,
839 MUX_SEL_GSCL
, 24, 1),
842 struct samsung_div_clock gscl_div_clks
[] __initdata
= {
843 DIV(GSCL_DOUT_PCLK_M2M_100
, "dout_pclk_m2m_100",
844 "mout_aclk_m2m_400_user",
846 DIV(GSCL_DOUT_ACLK_CSIS_200
, "dout_aclk_csis_200",
847 "mout_aclk_m2m_400_user",
851 struct samsung_gate_clock gscl_gate_clks
[] __initdata
= {
852 GATE(GSCL_SCLK_CSIS0_WRAP
, "sclk_csis0_wrap", "dout_aclk_csis_200",
853 EN_SCLK_GSCL_FIMC
, 0, CLK_SET_RATE_PARENT
, 0),
854 GATE(GSCL_SCLK_CSIS1_WRAP
, "sclk_csis1_wrap", "dout_aclk_csis_200",
855 EN_SCLK_GSCL_FIMC
, 1, CLK_SET_RATE_PARENT
, 0),
857 GATE(GSCL_CLK_GSCL0
, "clk_gscl0", "mout_aclk_gscl_333_user",
858 EN_IP_GSCL
, 2, 0, 0),
859 GATE(GSCL_CLK_GSCL1
, "clk_gscl1", "mout_aclk_gscl_333_user",
860 EN_IP_GSCL
, 3, 0, 0),
861 GATE(GSCL_CLK_MSCL0
, "clk_mscl0", "mout_aclk_gscl_333_user",
862 EN_IP_GSCL
, 4, 0, 0),
863 GATE(GSCL_CLK_MSCL1
, "clk_mscl1", "mout_aclk_gscl_333_user",
864 EN_IP_GSCL
, 5, 0, 0),
865 GATE(GSCL_CLK_PIXEL_GSCL0
, "clk_pixel_gscl0",
866 "mout_aclk_gscl_333_user",
867 EN_IP_GSCL
, 8, 0, 0),
868 GATE(GSCL_CLK_PIXEL_GSCL1
, "clk_pixel_gscl1",
869 "mout_aclk_gscl_333_user",
870 EN_IP_GSCL
, 9, 0, 0),
872 GATE(GSCL_CLK_SMMU3_LITE_A
, "clk_smmu3_lite_a",
873 "mout_aclk_gscl_fimc_user",
874 EN_IP_GSCL_FIMC
, 5, 0, 0),
875 GATE(GSCL_CLK_SMMU3_LITE_B
, "clk_smmu3_lite_b",
876 "mout_aclk_gscl_fimc_user",
877 EN_IP_GSCL_FIMC
, 6, 0, 0),
878 GATE(GSCL_CLK_SMMU3_LITE_D
, "clk_smmu3_lite_d",
879 "mout_aclk_gscl_fimc_user",
880 EN_IP_GSCL_FIMC
, 7, 0, 0),
881 GATE(GSCL_CLK_CSIS0
, "clk_csis0", "mout_aclk_gscl_fimc_user",
882 EN_IP_GSCL_FIMC
, 8, 0, 0),
883 GATE(GSCL_CLK_CSIS1
, "clk_csis1", "mout_aclk_gscl_fimc_user",
884 EN_IP_GSCL_FIMC
, 9, 0, 0),
885 GATE(GSCL_CLK_FIMC_LITE_A
, "clk_fimc_lite_a",
886 "mout_aclk_gscl_fimc_user",
887 EN_IP_GSCL_FIMC
, 10, 0, 0),
888 GATE(GSCL_CLK_FIMC_LITE_B
, "clk_fimc_lite_b",
889 "mout_aclk_gscl_fimc_user",
890 EN_IP_GSCL_FIMC
, 11, 0, 0),
891 GATE(GSCL_CLK_FIMC_LITE_D
, "clk_fimc_lite_d",
892 "mout_aclk_gscl_fimc_user",
893 EN_IP_GSCL_FIMC
, 12, 0, 0),
895 GATE(GSCL_CLK_SMMU3_GSCL0
, "clk_smmu3_gscl0",
896 "mout_aclk_gscl_333_user",
897 EN_IP_GSCL_SECURE_SMMU_GSCL0
, 17, 0, 0),
898 GATE(GSCL_CLK_SMMU3_GSCL1
, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
899 EN_IP_GSCL_SECURE_SMMU_GSCL1
, 18, 0, 0),
900 GATE(GSCL_CLK_SMMU3_MSCL0
, "clk_smmu3_mscl0",
901 "mout_aclk_m2m_400_user",
902 EN_IP_GSCL_SECURE_SMMU_MSCL0
, 19, 0, 0),
903 GATE(GSCL_CLK_SMMU3_MSCL1
, "clk_smmu3_mscl1",
904 "mout_aclk_m2m_400_user",
905 EN_IP_GSCL_SECURE_SMMU_MSCL1
, 20, 0, 0),
908 static void __init
exynos5260_clk_gscl_init(struct device_node
*np
)
910 struct exynos5260_cmu_info cmu
= {0};
912 cmu
.mux_clks
= gscl_mux_clks
;
913 cmu
.nr_mux_clks
= ARRAY_SIZE(gscl_mux_clks
);
914 cmu
.div_clks
= gscl_div_clks
;
915 cmu
.nr_div_clks
= ARRAY_SIZE(gscl_div_clks
);
916 cmu
.gate_clks
= gscl_gate_clks
;
917 cmu
.nr_gate_clks
= ARRAY_SIZE(gscl_gate_clks
);
918 cmu
.nr_clk_ids
= GSCL_NR_CLK
;
919 cmu
.clk_regs
= gscl_clk_regs
;
920 cmu
.nr_clk_regs
= ARRAY_SIZE(gscl_clk_regs
);
922 exynos5260_cmu_register_one(np
, &cmu
);
925 CLK_OF_DECLARE(exynos5260_clk_gscl
, "samsung,exynos5260-clock-gscl",
926 exynos5260_clk_gscl_init
);
931 static unsigned long isp_clk_regs
[] __initdata
= {
944 PNAME(mout_isp_400_user_p
) = {"fin_pll", "dout_aclk_isp1_400"};
945 PNAME(mout_isp_266_user_p
) = {"fin_pll", "dout_aclk_isp1_266"};
947 struct samsung_mux_clock isp_mux_clks
[] __initdata
= {
948 MUX(ISP_MOUT_ISP_266_USER
, "mout_isp_266_user", mout_isp_266_user_p
,
950 MUX(ISP_MOUT_ISP_400_USER
, "mout_isp_400_user", mout_isp_400_user_p
,
954 struct samsung_div_clock isp_div_clks
[] __initdata
= {
955 DIV(ISP_DOUT_PCLK_ISP_66
, "dout_pclk_isp_66", "mout_kfc",
957 DIV(ISP_DOUT_PCLK_ISP_133
, "dout_pclk_isp_133", "mout_kfc",
959 DIV(ISP_DOUT_CA5_ATCLKIN
, "dout_ca5_atclkin", "mout_kfc",
961 DIV(ISP_DOUT_CA5_PCLKDBG
, "dout_ca5_pclkdbg", "mout_kfc",
963 DIV(ISP_DOUT_SCLK_MPWM
, "dout_sclk_mpwm", "mout_kfc", DIV_ISP
, 20, 2),
966 struct samsung_gate_clock isp_gate_clks
[] __initdata
= {
967 GATE(ISP_CLK_GIC
, "clk_isp_gic", "mout_aclk_isp1_266",
968 EN_IP_ISP0
, 15, 0, 0),
970 GATE(ISP_CLK_CA5
, "clk_isp_ca5", "mout_aclk_isp1_266",
971 EN_IP_ISP1
, 1, 0, 0),
972 GATE(ISP_CLK_FIMC_DRC
, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
973 EN_IP_ISP1
, 2, 0, 0),
974 GATE(ISP_CLK_FIMC_FD
, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
975 EN_IP_ISP1
, 3, 0, 0),
976 GATE(ISP_CLK_FIMC
, "clk_isp_fimc", "mout_aclk_isp1_266",
977 EN_IP_ISP1
, 4, 0, 0),
978 GATE(ISP_CLK_FIMC_SCALERC
, "clk_isp_fimc_scalerc",
979 "mout_aclk_isp1_266",
980 EN_IP_ISP1
, 5, 0, 0),
981 GATE(ISP_CLK_FIMC_SCALERP
, "clk_isp_fimc_scalerp",
982 "mout_aclk_isp1_266",
983 EN_IP_ISP1
, 6, 0, 0),
984 GATE(ISP_CLK_I2C0
, "clk_isp_i2c0", "mout_aclk_isp1_266",
985 EN_IP_ISP1
, 7, 0, 0),
986 GATE(ISP_CLK_I2C1
, "clk_isp_i2c1", "mout_aclk_isp1_266",
987 EN_IP_ISP1
, 8, 0, 0),
988 GATE(ISP_CLK_MCUCTL
, "clk_isp_mcuctl", "mout_aclk_isp1_266",
989 EN_IP_ISP1
, 9, 0, 0),
990 GATE(ISP_CLK_MPWM
, "clk_isp_mpwm", "mout_aclk_isp1_266",
991 EN_IP_ISP1
, 10, 0, 0),
992 GATE(ISP_CLK_MTCADC
, "clk_isp_mtcadc", "mout_aclk_isp1_266",
993 EN_IP_ISP1
, 11, 0, 0),
994 GATE(ISP_CLK_PWM
, "clk_isp_pwm", "mout_aclk_isp1_266",
995 EN_IP_ISP1
, 14, 0, 0),
996 GATE(ISP_CLK_SMMU_DRC
, "clk_smmu_drc", "mout_aclk_isp1_266",
997 EN_IP_ISP1
, 21, 0, 0),
998 GATE(ISP_CLK_SMMU_FD
, "clk_smmu_fd", "mout_aclk_isp1_266",
999 EN_IP_ISP1
, 22, 0, 0),
1000 GATE(ISP_CLK_SMMU_ISP
, "clk_smmu_isp", "mout_aclk_isp1_266",
1001 EN_IP_ISP1
, 23, 0, 0),
1002 GATE(ISP_CLK_SMMU_ISPCX
, "clk_smmu_ispcx", "mout_aclk_isp1_266",
1003 EN_IP_ISP1
, 24, 0, 0),
1004 GATE(ISP_CLK_SMMU_SCALERC
, "clk_isp_smmu_scalerc",
1005 "mout_aclk_isp1_266",
1006 EN_IP_ISP1
, 25, 0, 0),
1007 GATE(ISP_CLK_SMMU_SCALERP
, "clk_isp_smmu_scalerp",
1008 "mout_aclk_isp1_266",
1009 EN_IP_ISP1
, 26, 0, 0),
1010 GATE(ISP_CLK_SPI0
, "clk_isp_spi0", "mout_aclk_isp1_266",
1011 EN_IP_ISP1
, 27, 0, 0),
1012 GATE(ISP_CLK_SPI1
, "clk_isp_spi1", "mout_aclk_isp1_266",
1013 EN_IP_ISP1
, 28, 0, 0),
1014 GATE(ISP_CLK_WDT
, "clk_isp_wdt", "mout_aclk_isp1_266",
1015 EN_IP_ISP1
, 31, 0, 0),
1016 GATE(ISP_CLK_UART
, "clk_isp_uart", "mout_aclk_isp1_266",
1017 EN_IP_ISP1
, 30, 0, 0),
1019 GATE(ISP_SCLK_UART_EXT
, "sclk_isp_uart_ext", "fin_pll",
1020 EN_SCLK_ISP
, 7, CLK_SET_RATE_PARENT
, 0),
1021 GATE(ISP_SCLK_SPI1_EXT
, "sclk_isp_spi1_ext", "fin_pll",
1022 EN_SCLK_ISP
, 8, CLK_SET_RATE_PARENT
, 0),
1023 GATE(ISP_SCLK_SPI0_EXT
, "sclk_isp_spi0_ext", "fin_pll",
1024 EN_SCLK_ISP
, 9, CLK_SET_RATE_PARENT
, 0),
1027 static void __init
exynos5260_clk_isp_init(struct device_node
*np
)
1029 struct exynos5260_cmu_info cmu
= {0};
1031 cmu
.mux_clks
= isp_mux_clks
;
1032 cmu
.nr_mux_clks
= ARRAY_SIZE(isp_mux_clks
);
1033 cmu
.div_clks
= isp_div_clks
;
1034 cmu
.nr_div_clks
= ARRAY_SIZE(isp_div_clks
);
1035 cmu
.gate_clks
= isp_gate_clks
;
1036 cmu
.nr_gate_clks
= ARRAY_SIZE(isp_gate_clks
);
1037 cmu
.nr_clk_ids
= ISP_NR_CLK
;
1038 cmu
.clk_regs
= isp_clk_regs
;
1039 cmu
.nr_clk_regs
= ARRAY_SIZE(isp_clk_regs
);
1041 exynos5260_cmu_register_one(np
, &cmu
);
1044 CLK_OF_DECLARE(exynos5260_clk_isp
, "samsung,exynos5260-clock-isp",
1045 exynos5260_clk_isp_init
);
1050 static unsigned long kfc_clk_regs
[] __initdata
= {
1065 PNAME(mout_kfc_pll_p
) = {"fin_pll", "fout_kfc_pll"};
1066 PNAME(mout_kfc_p
) = {"mout_kfc_pll", "dout_media_pll"};
1068 struct samsung_mux_clock kfc_mux_clks
[] __initdata
= {
1069 MUX(KFC_MOUT_KFC_PLL
, "mout_kfc_pll", mout_kfc_pll_p
,
1070 MUX_SEL_KFC0
, 0, 1),
1071 MUX(KFC_MOUT_KFC
, "mout_kfc", mout_kfc_p
, MUX_SEL_KFC2
, 0, 1),
1074 struct samsung_div_clock kfc_div_clks
[] __initdata
= {
1075 DIV(KFC_DOUT_KFC1
, "dout_kfc1", "mout_kfc", DIV_KFC
, 0, 3),
1076 DIV(KFC_DOUT_KFC2
, "dout_kfc2", "dout_kfc1", DIV_KFC
, 4, 3),
1077 DIV(KFC_DOUT_KFC_ATCLK
, "dout_kfc_atclk", "dout_kfc2", DIV_KFC
, 8, 3),
1078 DIV(KFC_DOUT_KFC_PCLK_DBG
, "dout_kfc_pclk_dbg", "dout_kfc2",
1080 DIV(KFC_DOUT_ACLK_KFC
, "dout_aclk_kfc", "dout_kfc2", DIV_KFC
, 16, 3),
1081 DIV(KFC_DOUT_PCLK_KFC
, "dout_pclk_kfc", "dout_kfc2", DIV_KFC
, 20, 3),
1082 DIV(KFC_DOUT_KFC_PLL
, "dout_kfc_pll", "mout_kfc", DIV_KFC
, 24, 3),
1085 static struct samsung_pll_clock kfc_pll_clks
[] __initdata
= {
1086 PLL(pll_2550xx
, KFC_FOUT_KFC_PLL
, "fout_kfc_pll", "fin_pll",
1087 KFC_PLL_LOCK
, KFC_PLL_CON0
,
1091 static void __init
exynos5260_clk_kfc_init(struct device_node
*np
)
1093 struct exynos5260_cmu_info cmu
= {0};
1095 cmu
.pll_clks
= kfc_pll_clks
;
1096 cmu
.nr_pll_clks
= ARRAY_SIZE(kfc_pll_clks
);
1097 cmu
.mux_clks
= kfc_mux_clks
;
1098 cmu
.nr_mux_clks
= ARRAY_SIZE(kfc_mux_clks
);
1099 cmu
.div_clks
= kfc_div_clks
;
1100 cmu
.nr_div_clks
= ARRAY_SIZE(kfc_div_clks
);
1101 cmu
.nr_clk_ids
= KFC_NR_CLK
;
1102 cmu
.clk_regs
= kfc_clk_regs
;
1103 cmu
.nr_clk_regs
= ARRAY_SIZE(kfc_clk_regs
);
1105 exynos5260_cmu_register_one(np
, &cmu
);
1108 CLK_OF_DECLARE(exynos5260_clk_kfc
, "samsung,exynos5260-clock-kfc",
1109 exynos5260_clk_kfc_init
);
1114 static unsigned long mfc_clk_regs
[] __initdata
= {
1118 EN_ACLK_SECURE_SMMU2_MFC
,
1120 EN_PCLK_SECURE_SMMU2_MFC
,
1122 EN_IP_MFC_SECURE_SMMU2_MFC
,
1125 PNAME(mout_aclk_mfc_333_user_p
) = {"fin_pll", "dout_aclk_mfc_333"};
1127 struct samsung_mux_clock mfc_mux_clks
[] __initdata
= {
1128 MUX(MFC_MOUT_ACLK_MFC_333_USER
, "mout_aclk_mfc_333_user",
1129 mout_aclk_mfc_333_user_p
,
1133 struct samsung_div_clock mfc_div_clks
[] __initdata
= {
1134 DIV(MFC_DOUT_PCLK_MFC_83
, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1138 struct samsung_gate_clock mfc_gate_clks
[] __initdata
= {
1139 GATE(MFC_CLK_MFC
, "clk_mfc", "mout_aclk_mfc_333_user",
1140 EN_IP_MFC
, 1, 0, 0),
1141 GATE(MFC_CLK_SMMU2_MFCM0
, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
1142 EN_IP_MFC_SECURE_SMMU2_MFC
, 6, 0, 0),
1143 GATE(MFC_CLK_SMMU2_MFCM1
, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
1144 EN_IP_MFC_SECURE_SMMU2_MFC
, 7, 0, 0),
1147 static void __init
exynos5260_clk_mfc_init(struct device_node
*np
)
1149 struct exynos5260_cmu_info cmu
= {0};
1151 cmu
.mux_clks
= mfc_mux_clks
;
1152 cmu
.nr_mux_clks
= ARRAY_SIZE(mfc_mux_clks
);
1153 cmu
.div_clks
= mfc_div_clks
;
1154 cmu
.nr_div_clks
= ARRAY_SIZE(mfc_div_clks
);
1155 cmu
.gate_clks
= mfc_gate_clks
;
1156 cmu
.nr_gate_clks
= ARRAY_SIZE(mfc_gate_clks
);
1157 cmu
.nr_clk_ids
= MFC_NR_CLK
;
1158 cmu
.clk_regs
= mfc_clk_regs
;
1159 cmu
.nr_clk_regs
= ARRAY_SIZE(mfc_clk_regs
);
1161 exynos5260_cmu_register_one(np
, &cmu
);
1164 CLK_OF_DECLARE(exynos5260_clk_mfc
, "samsung,exynos5260-clock-mfc",
1165 exynos5260_clk_mfc_init
);
1170 static unsigned long mif_clk_regs
[] __initdata
= {
1187 EN_ACLK_MIF_SECURE_DREX1_TZ
,
1188 EN_ACLK_MIF_SECURE_DREX0_TZ
,
1189 EN_ACLK_MIF_SECURE_INTMEM
,
1191 EN_PCLK_MIF_SECURE_MONOCNT
,
1192 EN_PCLK_MIF_SECURE_RTC_APBIF
,
1193 EN_PCLK_MIF_SECURE_DREX1_TZ
,
1194 EN_PCLK_MIF_SECURE_DREX0_TZ
,
1197 EN_IP_MIF_SECURE_MONOCNT
,
1198 EN_IP_MIF_SECURE_RTC_APBIF
,
1199 EN_IP_MIF_SECURE_DREX1_TZ
,
1200 EN_IP_MIF_SECURE_DREX0_TZ
,
1201 EN_IP_MIF_SECURE_INTEMEM
,
1204 PNAME(mout_mem_pll_p
) = {"fin_pll", "fout_mem_pll"};
1205 PNAME(mout_bus_pll_p
) = {"fin_pll", "fout_bus_pll"};
1206 PNAME(mout_media_pll_p
) = {"fin_pll", "fout_media_pll"};
1207 PNAME(mout_mif_drex_p
) = {"dout_mem_pll", "dout_bus_pll"};
1208 PNAME(mout_mif_drex2x_p
) = {"dout_mem_pll", "dout_bus_pll"};
1209 PNAME(mout_clkm_phy_p
) = {"mout_mif_drex", "dout_media_pll"};
1210 PNAME(mout_clk2x_phy_p
) = {"mout_mif_drex2x", "dout_media_pll"};
1212 struct samsung_mux_clock mif_mux_clks
[] __initdata
= {
1213 MUX(MIF_MOUT_MEM_PLL
, "mout_mem_pll", mout_mem_pll_p
,
1215 MUX(MIF_MOUT_BUS_PLL
, "mout_bus_pll", mout_bus_pll_p
,
1217 MUX(MIF_MOUT_MEDIA_PLL
, "mout_media_pll", mout_media_pll_p
,
1219 MUX(MIF_MOUT_MIF_DREX
, "mout_mif_drex", mout_mif_drex_p
,
1220 MUX_SEL_MIF
, 12, 1),
1221 MUX(MIF_MOUT_CLKM_PHY
, "mout_clkm_phy", mout_clkm_phy_p
,
1222 MUX_SEL_MIF
, 16, 1),
1223 MUX(MIF_MOUT_MIF_DREX2X
, "mout_mif_drex2x", mout_mif_drex2x_p
,
1224 MUX_SEL_MIF
, 20, 1),
1225 MUX(MIF_MOUT_CLK2X_PHY
, "mout_clk2x_phy", mout_clk2x_phy_p
,
1226 MUX_SEL_MIF
, 24, 1),
1229 struct samsung_div_clock mif_div_clks
[] __initdata
= {
1230 DIV(MIF_DOUT_MEDIA_PLL
, "dout_media_pll", "mout_media_pll",
1232 DIV(MIF_DOUT_MEM_PLL
, "dout_mem_pll", "mout_mem_pll",
1234 DIV(MIF_DOUT_BUS_PLL
, "dout_bus_pll", "mout_bus_pll",
1236 DIV(MIF_DOUT_CLKM_PHY
, "dout_clkm_phy", "mout_clkm_phy",
1238 DIV(MIF_DOUT_CLK2X_PHY
, "dout_clk2x_phy", "mout_clk2x_phy",
1240 DIV(MIF_DOUT_ACLK_MIF_466
, "dout_aclk_mif_466", "dout_clk2x_phy",
1242 DIV(MIF_DOUT_ACLK_BUS_200
, "dout_aclk_bus_200", "dout_bus_pll",
1244 DIV(MIF_DOUT_ACLK_BUS_100
, "dout_aclk_bus_100", "dout_bus_pll",
1248 struct samsung_gate_clock mif_gate_clks
[] __initdata
= {
1249 GATE(MIF_CLK_LPDDR3PHY_WRAP0
, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1250 EN_IP_MIF
, 12, CLK_IGNORE_UNUSED
, 0),
1251 GATE(MIF_CLK_LPDDR3PHY_WRAP1
, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
1252 EN_IP_MIF
, 13, CLK_IGNORE_UNUSED
, 0),
1254 GATE(MIF_CLK_MONOCNT
, "clk_monocnt", "dout_aclk_bus_100",
1255 EN_IP_MIF_SECURE_MONOCNT
, 22,
1256 CLK_IGNORE_UNUSED
, 0),
1258 GATE(MIF_CLK_MIF_RTC
, "clk_mif_rtc", "dout_aclk_bus_100",
1259 EN_IP_MIF_SECURE_RTC_APBIF
, 23,
1260 CLK_IGNORE_UNUSED
, 0),
1262 GATE(MIF_CLK_DREX1
, "clk_drex1", "dout_aclk_mif_466",
1263 EN_IP_MIF_SECURE_DREX1_TZ
, 9,
1264 CLK_IGNORE_UNUSED
, 0),
1266 GATE(MIF_CLK_DREX0
, "clk_drex0", "dout_aclk_mif_466",
1267 EN_IP_MIF_SECURE_DREX0_TZ
, 9,
1268 CLK_IGNORE_UNUSED
, 0),
1270 GATE(MIF_CLK_INTMEM
, "clk_intmem", "dout_aclk_bus_200",
1271 EN_IP_MIF_SECURE_INTEMEM
, 11,
1272 CLK_IGNORE_UNUSED
, 0),
1274 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0
, "sclk_lpddr3phy_wrap_u0",
1275 "dout_clkm_phy", EN_SCLK_MIF
, 0,
1276 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1277 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1
, "sclk_lpddr3phy_wrap_u1",
1278 "dout_clkm_phy", EN_SCLK_MIF
, 1,
1279 CLK_IGNORE_UNUSED
| CLK_SET_RATE_PARENT
, 0),
1282 static struct samsung_pll_clock mif_pll_clks
[] __initdata
= {
1283 PLL(pll_2550xx
, MIF_FOUT_MEM_PLL
, "fout_mem_pll", "fin_pll",
1284 MEM_PLL_LOCK
, MEM_PLL_CON0
,
1286 PLL(pll_2550xx
, MIF_FOUT_BUS_PLL
, "fout_bus_pll", "fin_pll",
1287 BUS_PLL_LOCK
, BUS_PLL_CON0
,
1289 PLL(pll_2550xx
, MIF_FOUT_MEDIA_PLL
, "fout_media_pll", "fin_pll",
1290 MEDIA_PLL_LOCK
, MEDIA_PLL_CON0
,
1294 static void __init
exynos5260_clk_mif_init(struct device_node
*np
)
1296 struct exynos5260_cmu_info cmu
= {0};
1298 cmu
.pll_clks
= mif_pll_clks
;
1299 cmu
.nr_pll_clks
= ARRAY_SIZE(mif_pll_clks
);
1300 cmu
.mux_clks
= mif_mux_clks
;
1301 cmu
.nr_mux_clks
= ARRAY_SIZE(mif_mux_clks
);
1302 cmu
.div_clks
= mif_div_clks
;
1303 cmu
.nr_div_clks
= ARRAY_SIZE(mif_div_clks
);
1304 cmu
.gate_clks
= mif_gate_clks
;
1305 cmu
.nr_gate_clks
= ARRAY_SIZE(mif_gate_clks
);
1306 cmu
.nr_clk_ids
= MIF_NR_CLK
;
1307 cmu
.clk_regs
= mif_clk_regs
;
1308 cmu
.nr_clk_regs
= ARRAY_SIZE(mif_clk_regs
);
1310 exynos5260_cmu_register_one(np
, &cmu
);
1313 CLK_OF_DECLARE(exynos5260_clk_mif
, "samsung,exynos5260-clock-mif",
1314 exynos5260_clk_mif_init
);
1319 static unsigned long peri_clk_regs
[] __initdata
= {
1327 EN_PCLK_PERI_SECURE_CHIPID
,
1328 EN_PCLK_PERI_SECURE_PROVKEY0
,
1329 EN_PCLK_PERI_SECURE_PROVKEY1
,
1330 EN_PCLK_PERI_SECURE_SECKEY
,
1331 EN_PCLK_PERI_SECURE_ANTIRBKCNT
,
1332 EN_PCLK_PERI_SECURE_TOP_RTC
,
1333 EN_PCLK_PERI_SECURE_TZPC
,
1335 EN_SCLK_PERI_SECURE_TOP_RTC
,
1339 EN_IP_PERI_SECURE_CHIPID
,
1340 EN_IP_PERI_SECURE_PROVKEY0
,
1341 EN_IP_PERI_SECURE_PROVKEY1
,
1342 EN_IP_PERI_SECURE_SECKEY
,
1343 EN_IP_PERI_SECURE_ANTIRBKCNT
,
1344 EN_IP_PERI_SECURE_TOP_RTC
,
1345 EN_IP_PERI_SECURE_TZPC
,
1348 PNAME(mout_sclk_pcm_p
) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
1349 "phyclk_hdmi_phy_ref_cko"};
1350 PNAME(mout_sclk_i2scod_p
) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1351 "phyclk_hdmi_phy_ref_cko"};
1352 PNAME(mout_sclk_spdif_p
) = {"ioclk_spdif_extclk", "fin_pll",
1353 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1355 struct samsung_mux_clock peri_mux_clks
[] __initdata
= {
1356 MUX(PERI_MOUT_SCLK_PCM
, "mout_sclk_pcm", mout_sclk_pcm_p
,
1357 MUX_SEL_PERI1
, 4, 2),
1358 MUX(PERI_MOUT_SCLK_I2SCOD
, "mout_sclk_i2scod", mout_sclk_i2scod_p
,
1359 MUX_SEL_PERI1
, 12, 2),
1360 MUX(PERI_MOUT_SCLK_SPDIF
, "mout_sclk_spdif", mout_sclk_spdif_p
,
1361 MUX_SEL_PERI1
, 20, 2),
1364 struct samsung_div_clock peri_div_clks
[] __initdata
= {
1365 DIV(PERI_DOUT_PCM
, "dout_pcm", "mout_sclk_pcm", DIV_PERI
, 0, 8),
1366 DIV(PERI_DOUT_I2S
, "dout_i2s", "mout_sclk_i2scod", DIV_PERI
, 8, 6),
1369 struct samsung_gate_clock peri_gate_clks
[] __initdata
= {
1370 GATE(PERI_SCLK_PCM1
, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI
, 0,
1371 CLK_SET_RATE_PARENT
, 0),
1372 GATE(PERI_SCLK_I2S
, "sclk_i2s", "dout_i2s", EN_SCLK_PERI
, 1,
1373 CLK_SET_RATE_PARENT
, 0),
1374 GATE(PERI_SCLK_SPDIF
, "sclk_spdif", "dout_sclk_peri_spi0_b",
1375 EN_SCLK_PERI
, 2, CLK_SET_RATE_PARENT
, 0),
1376 GATE(PERI_SCLK_SPI0
, "sclk_spi0", "dout_sclk_peri_spi0_b",
1377 EN_SCLK_PERI
, 7, CLK_SET_RATE_PARENT
, 0),
1378 GATE(PERI_SCLK_SPI1
, "sclk_spi1", "dout_sclk_peri_spi1_b",
1379 EN_SCLK_PERI
, 8, CLK_SET_RATE_PARENT
, 0),
1380 GATE(PERI_SCLK_SPI2
, "sclk_spi2", "dout_sclk_peri_spi2_b",
1381 EN_SCLK_PERI
, 9, CLK_SET_RATE_PARENT
, 0),
1382 GATE(PERI_SCLK_UART0
, "sclk_uart0", "dout_sclk_peri_uart0",
1383 EN_SCLK_PERI
, 10, CLK_SET_RATE_PARENT
, 0),
1384 GATE(PERI_SCLK_UART1
, "sclk_uart1", "dout_sclk_peri_uart1",
1385 EN_SCLK_PERI
, 11, CLK_SET_RATE_PARENT
, 0),
1386 GATE(PERI_SCLK_UART2
, "sclk_uart2", "dout_sclk_peri_uart2",
1387 EN_SCLK_PERI
, 12, CLK_SET_RATE_PARENT
, 0),
1389 GATE(PERI_CLK_ABB
, "clk_abb", "dout_aclk_peri_66",
1390 EN_IP_PERI0
, 1, 0, 0),
1391 GATE(PERI_CLK_EFUSE_WRITER
, "clk_efuse_writer", "dout_aclk_peri_66",
1392 EN_IP_PERI0
, 5, 0, 0),
1393 GATE(PERI_CLK_HDMICEC
, "clk_hdmicec", "dout_aclk_peri_66",
1394 EN_IP_PERI0
, 6, 0, 0),
1395 GATE(PERI_CLK_I2C10
, "clk_i2c10", "dout_aclk_peri_66",
1396 EN_IP_PERI0
, 7, 0, 0),
1397 GATE(PERI_CLK_I2C11
, "clk_i2c11", "dout_aclk_peri_66",
1398 EN_IP_PERI0
, 8, 0, 0),
1399 GATE(PERI_CLK_I2C8
, "clk_i2c8", "dout_aclk_peri_66",
1400 EN_IP_PERI0
, 9, 0, 0),
1401 GATE(PERI_CLK_I2C9
, "clk_i2c9", "dout_aclk_peri_66",
1402 EN_IP_PERI0
, 10, 0, 0),
1403 GATE(PERI_CLK_I2C4
, "clk_i2c4", "dout_aclk_peri_66",
1404 EN_IP_PERI0
, 11, 0, 0),
1405 GATE(PERI_CLK_I2C5
, "clk_i2c5", "dout_aclk_peri_66",
1406 EN_IP_PERI0
, 12, 0, 0),
1407 GATE(PERI_CLK_I2C6
, "clk_i2c6", "dout_aclk_peri_66",
1408 EN_IP_PERI0
, 13, 0, 0),
1409 GATE(PERI_CLK_I2C7
, "clk_i2c7", "dout_aclk_peri_66",
1410 EN_IP_PERI0
, 14, 0, 0),
1411 GATE(PERI_CLK_I2CHDMI
, "clk_i2chdmi", "dout_aclk_peri_66",
1412 EN_IP_PERI0
, 15, 0, 0),
1413 GATE(PERI_CLK_I2S
, "clk_peri_i2s", "dout_aclk_peri_66",
1414 EN_IP_PERI0
, 16, 0, 0),
1415 GATE(PERI_CLK_MCT
, "clk_mct", "dout_aclk_peri_66",
1416 EN_IP_PERI0
, 17, 0, 0),
1417 GATE(PERI_CLK_PCM
, "clk_peri_pcm", "dout_aclk_peri_66",
1418 EN_IP_PERI0
, 18, 0, 0),
1419 GATE(PERI_CLK_HSIC0
, "clk_hsic0", "dout_aclk_peri_66",
1420 EN_IP_PERI0
, 20, 0, 0),
1421 GATE(PERI_CLK_HSIC1
, "clk_hsic1", "dout_aclk_peri_66",
1422 EN_IP_PERI0
, 21, 0, 0),
1423 GATE(PERI_CLK_HSIC2
, "clk_hsic2", "dout_aclk_peri_66",
1424 EN_IP_PERI0
, 22, 0, 0),
1425 GATE(PERI_CLK_HSIC3
, "clk_hsic3", "dout_aclk_peri_66",
1426 EN_IP_PERI0
, 23, 0, 0),
1427 GATE(PERI_CLK_WDT_EGL
, "clk_wdt_egl", "dout_aclk_peri_66",
1428 EN_IP_PERI0
, 24, 0, 0),
1429 GATE(PERI_CLK_WDT_KFC
, "clk_wdt_kfc", "dout_aclk_peri_66",
1430 EN_IP_PERI0
, 25, 0, 0),
1432 GATE(PERI_CLK_UART4
, "clk_uart4", "dout_aclk_peri_66",
1433 EN_IP_PERI2
, 0, 0, 0),
1434 GATE(PERI_CLK_PWM
, "clk_pwm", "dout_aclk_peri_66",
1435 EN_IP_PERI2
, 3, 0, 0),
1436 GATE(PERI_CLK_SPDIF
, "clk_spdif", "dout_aclk_peri_66",
1437 EN_IP_PERI2
, 6, 0, 0),
1438 GATE(PERI_CLK_SPI0
, "clk_spi0", "dout_aclk_peri_66",
1439 EN_IP_PERI2
, 7, 0, 0),
1440 GATE(PERI_CLK_SPI1
, "clk_spi1", "dout_aclk_peri_66",
1441 EN_IP_PERI2
, 8, 0, 0),
1442 GATE(PERI_CLK_SPI2
, "clk_spi2", "dout_aclk_peri_66",
1443 EN_IP_PERI2
, 9, 0, 0),
1444 GATE(PERI_CLK_TMU0
, "clk_tmu0", "dout_aclk_peri_66",
1445 EN_IP_PERI2
, 10, 0, 0),
1446 GATE(PERI_CLK_TMU1
, "clk_tmu1", "dout_aclk_peri_66",
1447 EN_IP_PERI2
, 11, 0, 0),
1448 GATE(PERI_CLK_TMU2
, "clk_tmu2", "dout_aclk_peri_66",
1449 EN_IP_PERI2
, 12, 0, 0),
1450 GATE(PERI_CLK_TMU3
, "clk_tmu3", "dout_aclk_peri_66",
1451 EN_IP_PERI2
, 13, 0, 0),
1452 GATE(PERI_CLK_TMU4
, "clk_tmu4", "dout_aclk_peri_66",
1453 EN_IP_PERI2
, 14, 0, 0),
1454 GATE(PERI_CLK_ADC
, "clk_adc", "dout_aclk_peri_66",
1455 EN_IP_PERI2
, 18, 0, 0),
1456 GATE(PERI_CLK_UART0
, "clk_uart0", "dout_aclk_peri_66",
1457 EN_IP_PERI2
, 19, 0, 0),
1458 GATE(PERI_CLK_UART1
, "clk_uart1", "dout_aclk_peri_66",
1459 EN_IP_PERI2
, 20, 0, 0),
1460 GATE(PERI_CLK_UART2
, "clk_uart2", "dout_aclk_peri_66",
1461 EN_IP_PERI2
, 21, 0, 0),
1463 GATE(PERI_CLK_CHIPID
, "clk_chipid", "dout_aclk_peri_66",
1464 EN_IP_PERI_SECURE_CHIPID
, 2, 0, 0),
1466 GATE(PERI_CLK_PROVKEY0
, "clk_provkey0", "dout_aclk_peri_66",
1467 EN_IP_PERI_SECURE_PROVKEY0
, 1, 0, 0),
1469 GATE(PERI_CLK_PROVKEY1
, "clk_provkey1", "dout_aclk_peri_66",
1470 EN_IP_PERI_SECURE_PROVKEY1
, 2, 0, 0),
1472 GATE(PERI_CLK_SECKEY
, "clk_seckey", "dout_aclk_peri_66",
1473 EN_IP_PERI_SECURE_SECKEY
, 5, 0, 0),
1475 GATE(PERI_CLK_TOP_RTC
, "clk_top_rtc", "dout_aclk_peri_66",
1476 EN_IP_PERI_SECURE_TOP_RTC
, 5, 0, 0),
1478 GATE(PERI_CLK_TZPC0
, "clk_tzpc0", "dout_aclk_peri_66",
1479 EN_IP_PERI_SECURE_TZPC
, 10, 0, 0),
1480 GATE(PERI_CLK_TZPC1
, "clk_tzpc1", "dout_aclk_peri_66",
1481 EN_IP_PERI_SECURE_TZPC
, 11, 0, 0),
1482 GATE(PERI_CLK_TZPC2
, "clk_tzpc2", "dout_aclk_peri_66",
1483 EN_IP_PERI_SECURE_TZPC
, 12, 0, 0),
1484 GATE(PERI_CLK_TZPC3
, "clk_tzpc3", "dout_aclk_peri_66",
1485 EN_IP_PERI_SECURE_TZPC
, 13, 0, 0),
1486 GATE(PERI_CLK_TZPC4
, "clk_tzpc4", "dout_aclk_peri_66",
1487 EN_IP_PERI_SECURE_TZPC
, 14, 0, 0),
1488 GATE(PERI_CLK_TZPC5
, "clk_tzpc5", "dout_aclk_peri_66",
1489 EN_IP_PERI_SECURE_TZPC
, 15, 0, 0),
1490 GATE(PERI_CLK_TZPC6
, "clk_tzpc6", "dout_aclk_peri_66",
1491 EN_IP_PERI_SECURE_TZPC
, 16, 0, 0),
1492 GATE(PERI_CLK_TZPC7
, "clk_tzpc7", "dout_aclk_peri_66",
1493 EN_IP_PERI_SECURE_TZPC
, 17, 0, 0),
1494 GATE(PERI_CLK_TZPC8
, "clk_tzpc8", "dout_aclk_peri_66",
1495 EN_IP_PERI_SECURE_TZPC
, 18, 0, 0),
1496 GATE(PERI_CLK_TZPC9
, "clk_tzpc9", "dout_aclk_peri_66",
1497 EN_IP_PERI_SECURE_TZPC
, 19, 0, 0),
1498 GATE(PERI_CLK_TZPC10
, "clk_tzpc10", "dout_aclk_peri_66",
1499 EN_IP_PERI_SECURE_TZPC
, 20, 0, 0),
1502 static void __init
exynos5260_clk_peri_init(struct device_node
*np
)
1504 struct exynos5260_cmu_info cmu
= {0};
1506 cmu
.mux_clks
= peri_mux_clks
;
1507 cmu
.nr_mux_clks
= ARRAY_SIZE(peri_mux_clks
);
1508 cmu
.div_clks
= peri_div_clks
;
1509 cmu
.nr_div_clks
= ARRAY_SIZE(peri_div_clks
);
1510 cmu
.gate_clks
= peri_gate_clks
;
1511 cmu
.nr_gate_clks
= ARRAY_SIZE(peri_gate_clks
);
1512 cmu
.nr_clk_ids
= PERI_NR_CLK
;
1513 cmu
.clk_regs
= peri_clk_regs
;
1514 cmu
.nr_clk_regs
= ARRAY_SIZE(peri_clk_regs
);
1516 exynos5260_cmu_register_one(np
, &cmu
);
1519 CLK_OF_DECLARE(exynos5260_clk_peri
, "samsung,exynos5260-clock-peri",
1520 exynos5260_clk_peri_init
);
1525 static unsigned long top_clk_regs
[] __initdata
= {
1565 /* fixed rate clocks generated inside the soc */
1566 struct samsung_fixed_rate_clock fixed_rate_clks
[] __initdata
= {
1567 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK
, "phyclk_dptx_phy_ch3_txd_clk", NULL
,
1568 CLK_IS_ROOT
, 270000000),
1569 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK
, "phyclk_dptx_phy_ch2_txd_clk", NULL
,
1570 CLK_IS_ROOT
, 270000000),
1571 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK
, "phyclk_dptx_phy_ch1_txd_clk", NULL
,
1572 CLK_IS_ROOT
, 270000000),
1573 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK
, "phyclk_dptx_phy_ch0_txd_clk", NULL
,
1574 CLK_IS_ROOT
, 270000000),
1575 FRATE(phyclk_hdmi_phy_tmds_clko
, "phyclk_hdmi_phy_tmds_clko", NULL
,
1576 CLK_IS_ROOT
, 250000000),
1577 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO
, "phyclk_hdmi_phy_pixel_clko", NULL
,
1578 CLK_IS_ROOT
, 1660000000),
1579 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI
, "phyclk_hdmi_link_o_tmds_clkhi",
1580 NULL
, CLK_IS_ROOT
, 125000000),
1581 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS
,
1582 "phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL
,
1583 CLK_IS_ROOT
, 187500000),
1584 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M
, "phyclk_dptx_phy_o_ref_clk_24m",
1585 NULL
, CLK_IS_ROOT
, 24000000),
1586 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2
, "phyclk_dptx_phy_clk_div2", NULL
,
1587 CLK_IS_ROOT
, 135000000),
1588 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0
,
1589 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL
,
1590 CLK_IS_ROOT
, 20000000),
1591 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK
, "phyclk_usbhost20_phy_phyclock",
1592 NULL
, CLK_IS_ROOT
, 60000000),
1593 FRATE(PHYCLK_USBHOST20_PHY_FREECLK
, "phyclk_usbhost20_phy_freeclk",
1594 NULL
, CLK_IS_ROOT
, 60000000),
1595 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI
,
1596 "phyclk_usbhost20_phy_clk48mohci",
1597 NULL
, CLK_IS_ROOT
, 48000000),
1598 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK
,
1599 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL
,
1600 CLK_IS_ROOT
, 125000000),
1601 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK
,
1602 "phyclk_usbdrd30_udrd30_phyclock", NULL
,
1603 CLK_IS_ROOT
, 60000000),
1606 PNAME(mout_memtop_pll_user_p
) = {"fin_pll", "dout_mem_pll"};
1607 PNAME(mout_bustop_pll_user_p
) = {"fin_pll", "dout_bus_pll"};
1608 PNAME(mout_mediatop_pll_user_p
) = {"fin_pll", "dout_media_pll"};
1609 PNAME(mout_audtop_pll_user_p
) = {"fin_pll", "mout_aud_pll"};
1610 PNAME(mout_aud_pll_p
) = {"fin_pll", "fout_aud_pll"};
1611 PNAME(mout_disp_pll_p
) = {"fin_pll", "fout_disp_pll"};
1612 PNAME(mout_mfc_bustop_333_p
) = {"mout_bustop_pll_user", "mout_disp_pll"};
1613 PNAME(mout_aclk_mfc_333_p
) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
1614 PNAME(mout_g2d_bustop_333_p
) = {"mout_bustop_pll_user", "mout_disp_pll"};
1615 PNAME(mout_aclk_g2d_333_p
) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
1616 PNAME(mout_gscl_bustop_333_p
) = {"mout_bustop_pll_user", "mout_disp_pll"};
1617 PNAME(mout_aclk_gscl_333_p
) = {"mout_mediatop_pll_user",
1618 "mout_gscl_bustop_333"};
1619 PNAME(mout_m2m_mediatop_400_p
) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1620 PNAME(mout_aclk_gscl_400_p
) = {"mout_bustop_pll_user",
1621 "mout_m2m_mediatop_400"};
1622 PNAME(mout_gscl_bustop_fimc_p
) = {"mout_bustop_pll_user", "mout_disp_pll"};
1623 PNAME(mout_aclk_gscl_fimc_p
) = {"mout_mediatop_pll_user",
1624 "mout_gscl_bustop_fimc"};
1625 PNAME(mout_isp1_media_266_p
) = {"mout_mediatop_pll_user",
1626 "mout_memtop_pll_user"};
1627 PNAME(mout_aclk_isp1_266_p
) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
1628 PNAME(mout_isp1_media_400_p
) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1629 PNAME(mout_aclk_isp1_400_p
) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
1630 PNAME(mout_sclk_isp_spi_p
) = {"fin_pll", "mout_bustop_pll_user"};
1631 PNAME(mout_sclk_isp_uart_p
) = {"fin_pll", "mout_bustop_pll_user"};
1632 PNAME(mout_sclk_isp_sensor_p
) = {"fin_pll", "mout_bustop_pll_user"};
1633 PNAME(mout_disp_disp_333_p
) = {"mout_disp_pll", "mout_bustop_pll_user"};
1634 PNAME(mout_aclk_disp_333_p
) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
1635 PNAME(mout_disp_disp_222_p
) = {"mout_disp_pll", "mout_bustop_pll_user"};
1636 PNAME(mout_aclk_disp_222_p
) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
1637 PNAME(mout_disp_media_pixel_p
) = {"mout_mediatop_pll_user",
1638 "mout_bustop_pll_user"};
1639 PNAME(mout_sclk_disp_pixel_p
) = {"mout_disp_pll", "mout_disp_media_pixel"};
1640 PNAME(mout_bus_bustop_400_p
) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1641 PNAME(mout_bus_bustop_100_p
) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1642 PNAME(mout_sclk_peri_spi_clk_p
) = {"fin_pll", "mout_bustop_pll_user"};
1643 PNAME(mout_sclk_peri_uart_uclk_p
) = {"fin_pll", "mout_bustop_pll_user"};
1644 PNAME(mout_sclk_fsys_usb_p
) = {"fin_pll", "mout_bustop_pll_user"};
1645 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p
) = {"fin_pll", "mout_bustop_pll_user"};
1646 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p
) = {"mout_sclk_fsys_mmc0_sdclkin_a",
1647 "mout_mediatop_pll_user"};
1648 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p
) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1649 "mout_mediatop_pll_user"};
1650 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p
) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1651 "mout_mediatop_pll_user"};
1653 struct samsung_mux_clock top_mux_clks
[] __initdata
= {
1654 MUX(TOP_MOUT_MEDIATOP_PLL_USER
, "mout_mediatop_pll_user",
1655 mout_mediatop_pll_user_p
,
1656 MUX_SEL_TOP_PLL0
, 0, 1),
1657 MUX(TOP_MOUT_MEMTOP_PLL_USER
, "mout_memtop_pll_user",
1658 mout_memtop_pll_user_p
,
1659 MUX_SEL_TOP_PLL0
, 4, 1),
1660 MUX(TOP_MOUT_BUSTOP_PLL_USER
, "mout_bustop_pll_user",
1661 mout_bustop_pll_user_p
,
1662 MUX_SEL_TOP_PLL0
, 8, 1),
1663 MUX(TOP_MOUT_DISP_PLL
, "mout_disp_pll", mout_disp_pll_p
,
1664 MUX_SEL_TOP_PLL0
, 12, 1),
1665 MUX(TOP_MOUT_AUD_PLL
, "mout_aud_pll", mout_aud_pll_p
,
1666 MUX_SEL_TOP_PLL0
, 16, 1),
1667 MUX(TOP_MOUT_AUDTOP_PLL_USER
, "mout_audtop_pll_user",
1668 mout_audtop_pll_user_p
,
1669 MUX_SEL_TOP_PLL0
, 24, 1),
1671 MUX(TOP_MOUT_DISP_DISP_333
, "mout_disp_disp_333", mout_disp_disp_333_p
,
1672 MUX_SEL_TOP_DISP0
, 0, 1),
1673 MUX(TOP_MOUT_ACLK_DISP_333
, "mout_aclk_disp_333", mout_aclk_disp_333_p
,
1674 MUX_SEL_TOP_DISP0
, 8, 1),
1675 MUX(TOP_MOUT_DISP_DISP_222
, "mout_disp_disp_222", mout_disp_disp_222_p
,
1676 MUX_SEL_TOP_DISP0
, 12, 1),
1677 MUX(TOP_MOUT_ACLK_DISP_222
, "mout_aclk_disp_222", mout_aclk_disp_222_p
,
1678 MUX_SEL_TOP_DISP0
, 20, 1),
1680 MUX(TOP_MOUT_FIMD1
, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p
,
1681 MUX_SEL_TOP_DISP1
, 0, 1),
1682 MUX(TOP_MOUT_DISP_MEDIA_PIXEL
, "mout_disp_media_pixel",
1683 mout_disp_media_pixel_p
,
1684 MUX_SEL_TOP_DISP1
, 8, 1),
1686 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK
, "mout_sclk_peri_spi2_clk",
1687 mout_sclk_peri_spi_clk_p
,
1688 MUX_SEL_TOP_PERI1
, 0, 1),
1689 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK
, "mout_sclk_peri_spi1_clk",
1690 mout_sclk_peri_spi_clk_p
,
1691 MUX_SEL_TOP_PERI1
, 4, 1),
1692 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK
, "mout_sclk_peri_spi0_clk",
1693 mout_sclk_peri_spi_clk_p
,
1694 MUX_SEL_TOP_PERI1
, 8, 1),
1695 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK
, "mout_sclk_peri_uart1_uclk",
1696 mout_sclk_peri_uart_uclk_p
,
1697 MUX_SEL_TOP_PERI1
, 12, 1),
1698 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK
, "mout_sclk_peri_uart2_uclk",
1699 mout_sclk_peri_uart_uclk_p
,
1700 MUX_SEL_TOP_PERI1
, 16, 1),
1701 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK
, "mout_sclk_peri_uart0_uclk",
1702 mout_sclk_peri_uart_uclk_p
,
1703 MUX_SEL_TOP_PERI1
, 20, 1),
1706 MUX(TOP_MOUT_BUS1_BUSTOP_400
, "mout_bus1_bustop_400",
1707 mout_bus_bustop_400_p
,
1708 MUX_SEL_TOP_BUS
, 0, 1),
1709 MUX(TOP_MOUT_BUS1_BUSTOP_100
, "mout_bus1_bustop_100",
1710 mout_bus_bustop_100_p
,
1711 MUX_SEL_TOP_BUS
, 4, 1),
1712 MUX(TOP_MOUT_BUS2_BUSTOP_100
, "mout_bus2_bustop_100",
1713 mout_bus_bustop_100_p
,
1714 MUX_SEL_TOP_BUS
, 8, 1),
1715 MUX(TOP_MOUT_BUS2_BUSTOP_400
, "mout_bus2_bustop_400",
1716 mout_bus_bustop_400_p
,
1717 MUX_SEL_TOP_BUS
, 12, 1),
1718 MUX(TOP_MOUT_BUS3_BUSTOP_400
, "mout_bus3_bustop_400",
1719 mout_bus_bustop_400_p
,
1720 MUX_SEL_TOP_BUS
, 16, 1),
1721 MUX(TOP_MOUT_BUS3_BUSTOP_100
, "mout_bus3_bustop_100",
1722 mout_bus_bustop_100_p
,
1723 MUX_SEL_TOP_BUS
, 20, 1),
1724 MUX(TOP_MOUT_BUS4_BUSTOP_400
, "mout_bus4_bustop_400",
1725 mout_bus_bustop_400_p
,
1726 MUX_SEL_TOP_BUS
, 24, 1),
1727 MUX(TOP_MOUT_BUS4_BUSTOP_100
, "mout_bus4_bustop_100",
1728 mout_bus_bustop_100_p
,
1729 MUX_SEL_TOP_BUS
, 28, 1),
1731 MUX(TOP_MOUT_SCLK_FSYS_USB
, "mout_sclk_fsys_usb",
1732 mout_sclk_fsys_usb_p
,
1733 MUX_SEL_TOP_FSYS
, 0, 1),
1734 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A
, "mout_sclk_fsys_mmc2_sdclkin_a",
1735 mout_sclk_fsys_mmc_sdclkin_a_p
,
1736 MUX_SEL_TOP_FSYS
, 4, 1),
1737 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B
, "mout_sclk_fsys_mmc2_sdclkin_b",
1738 mout_sclk_fsys_mmc2_sdclkin_b_p
,
1739 MUX_SEL_TOP_FSYS
, 8, 1),
1740 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A
, "mout_sclk_fsys_mmc1_sdclkin_a",
1741 mout_sclk_fsys_mmc_sdclkin_a_p
,
1742 MUX_SEL_TOP_FSYS
, 12, 1),
1743 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B
, "mout_sclk_fsys_mmc1_sdclkin_b",
1744 mout_sclk_fsys_mmc1_sdclkin_b_p
,
1745 MUX_SEL_TOP_FSYS
, 16, 1),
1746 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A
, "mout_sclk_fsys_mmc0_sdclkin_a",
1747 mout_sclk_fsys_mmc_sdclkin_a_p
,
1748 MUX_SEL_TOP_FSYS
, 20, 1),
1749 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B
, "mout_sclk_fsys_mmc0_sdclkin_b",
1750 mout_sclk_fsys_mmc0_sdclkin_b_p
,
1751 MUX_SEL_TOP_FSYS
, 24, 1),
1753 MUX(TOP_MOUT_ISP1_MEDIA_400
, "mout_isp1_media_400",
1754 mout_isp1_media_400_p
,
1755 MUX_SEL_TOP_ISP10
, 4, 1),
1756 MUX(TOP_MOUT_ACLK_ISP1_400
, "mout_aclk_isp1_400", mout_aclk_isp1_400_p
,
1757 MUX_SEL_TOP_ISP10
, 8 , 1),
1758 MUX(TOP_MOUT_ISP1_MEDIA_266
, "mout_isp1_media_266",
1759 mout_isp1_media_266_p
,
1760 MUX_SEL_TOP_ISP10
, 16, 1),
1761 MUX(TOP_MOUT_ACLK_ISP1_266
, "mout_aclk_isp1_266", mout_aclk_isp1_266_p
,
1762 MUX_SEL_TOP_ISP10
, 20, 1),
1764 MUX(TOP_MOUT_SCLK_ISP1_SPI0
, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p
,
1765 MUX_SEL_TOP_ISP11
, 4, 1),
1766 MUX(TOP_MOUT_SCLK_ISP1_SPI1
, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p
,
1767 MUX_SEL_TOP_ISP11
, 8, 1),
1768 MUX(TOP_MOUT_SCLK_ISP1_UART
, "mout_sclk_isp1_uart",
1769 mout_sclk_isp_uart_p
,
1770 MUX_SEL_TOP_ISP11
, 12, 1),
1771 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0
, "mout_sclk_isp1_sensor0",
1772 mout_sclk_isp_sensor_p
,
1773 MUX_SEL_TOP_ISP11
, 16, 1),
1774 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1
, "mout_sclk_isp1_sensor1",
1775 mout_sclk_isp_sensor_p
,
1776 MUX_SEL_TOP_ISP11
, 20, 1),
1777 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2
, "mout_sclk_isp1_sensor2",
1778 mout_sclk_isp_sensor_p
,
1779 MUX_SEL_TOP_ISP11
, 24, 1),
1781 MUX(TOP_MOUT_MFC_BUSTOP_333
, "mout_mfc_bustop_333",
1782 mout_mfc_bustop_333_p
,
1783 MUX_SEL_TOP_MFC
, 4, 1),
1784 MUX(TOP_MOUT_ACLK_MFC_333
, "mout_aclk_mfc_333", mout_aclk_mfc_333_p
,
1785 MUX_SEL_TOP_MFC
, 8, 1),
1787 MUX(TOP_MOUT_G2D_BUSTOP_333
, "mout_g2d_bustop_333",
1788 mout_g2d_bustop_333_p
,
1789 MUX_SEL_TOP_G2D
, 4, 1),
1790 MUX(TOP_MOUT_ACLK_G2D_333
, "mout_aclk_g2d_333", mout_aclk_g2d_333_p
,
1791 MUX_SEL_TOP_G2D
, 8, 1),
1793 MUX(TOP_MOUT_M2M_MEDIATOP_400
, "mout_m2m_mediatop_400",
1794 mout_m2m_mediatop_400_p
,
1795 MUX_SEL_TOP_GSCL
, 0, 1),
1796 MUX(TOP_MOUT_ACLK_GSCL_400
, "mout_aclk_gscl_400",
1797 mout_aclk_gscl_400_p
,
1798 MUX_SEL_TOP_GSCL
, 4, 1),
1799 MUX(TOP_MOUT_GSCL_BUSTOP_333
, "mout_gscl_bustop_333",
1800 mout_gscl_bustop_333_p
,
1801 MUX_SEL_TOP_GSCL
, 8, 1),
1802 MUX(TOP_MOUT_ACLK_GSCL_333
, "mout_aclk_gscl_333",
1803 mout_aclk_gscl_333_p
,
1804 MUX_SEL_TOP_GSCL
, 12, 1),
1805 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC
, "mout_gscl_bustop_fimc",
1806 mout_gscl_bustop_fimc_p
,
1807 MUX_SEL_TOP_GSCL
, 16, 1),
1808 MUX(TOP_MOUT_ACLK_GSCL_FIMC
, "mout_aclk_gscl_fimc",
1809 mout_aclk_gscl_fimc_p
,
1810 MUX_SEL_TOP_GSCL
, 20, 1),
1813 struct samsung_div_clock top_div_clks
[] __initdata
= {
1814 DIV(TOP_DOUT_ACLK_G2D_333
, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1815 DIV_TOP_G2D_MFC
, 0, 3),
1816 DIV(TOP_DOUT_ACLK_MFC_333
, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
1817 DIV_TOP_G2D_MFC
, 4, 3),
1819 DIV(TOP_DOUT_ACLK_GSCL_333
, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
1820 DIV_TOP_GSCL_ISP0
, 0, 3),
1821 DIV(TOP_DOUT_ACLK_GSCL_400
, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
1822 DIV_TOP_GSCL_ISP0
, 4, 3),
1823 DIV(TOP_DOUT_ACLK_GSCL_FIMC
, "dout_aclk_gscl_fimc",
1824 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0
, 8, 3),
1825 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A
, "dout_sclk_isp1_sensor0_a",
1826 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0
, 16, 4),
1827 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A
, "dout_sclk_isp1_sensor1_a",
1828 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0
, 20, 4),
1829 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A
, "dout_sclk_isp1_sensor2_a",
1830 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0
, 24, 4),
1832 DIV(TOP_DOUT_ACLK_ISP1_266
, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
1833 DIV_TOP_ISP10
, 0, 3),
1834 DIV(TOP_DOUT_ACLK_ISP1_400
, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
1835 DIV_TOP_ISP10
, 4, 3),
1836 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A
, "dout_sclk_isp1_spi0_a",
1837 "mout_sclk_isp1_spi0", DIV_TOP_ISP10
, 12, 4),
1838 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B
, "dout_sclk_isp1_spi0_b",
1839 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10
, 16, 8),
1841 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A
, "dout_sclk_isp1_spi1_a",
1842 "mout_sclk_isp1_spi1", DIV_TOP_ISP11
, 0, 4),
1843 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B
, "dout_sclk_isp1_spi1_b",
1844 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11
, 4, 8),
1845 DIV(TOP_DOUT_SCLK_ISP1_UART
, "dout_sclk_isp1_uart",
1846 "mout_sclk_isp1_uart", DIV_TOP_ISP11
, 12, 4),
1847 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B
, "dout_sclk_isp1_sensor0_b",
1848 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11
, 16, 4),
1849 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B
, "dout_sclk_isp1_sensor1_b",
1850 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11
, 20, 4),
1851 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B
, "dout_sclk_isp1_sensor2_b",
1852 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11
, 24, 4),
1854 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK
, "dout_sclk_hpm_targetclk",
1855 "mout_bustop_pll_user", DIV_TOP_HPM
, 0, 3),
1857 DIV(TOP_DOUT_ACLK_DISP_333
, "dout_aclk_disp_333", "mout_aclk_disp_333",
1858 DIV_TOP_DISP
, 0, 3),
1859 DIV(TOP_DOUT_ACLK_DISP_222
, "dout_aclk_disp_222", "mout_aclk_disp_222",
1860 DIV_TOP_DISP
, 4, 3),
1861 DIV(TOP_DOUT_SCLK_DISP_PIXEL
, "dout_sclk_disp_pixel",
1862 "mout_sclk_disp_pixel", DIV_TOP_DISP
, 8, 3),
1864 DIV(TOP_DOUT_ACLK_BUS1_400
, "dout_aclk_bus1_400",
1865 "mout_bus1_bustop_400", DIV_TOP_BUS
, 0, 3),
1866 DIV(TOP_DOUT_ACLK_BUS1_100
, "dout_aclk_bus1_100",
1867 "mout_bus1_bustop_100", DIV_TOP_BUS
, 4, 4),
1868 DIV(TOP_DOUT_ACLK_BUS2_400
, "dout_aclk_bus2_400",
1869 "mout_bus2_bustop_400", DIV_TOP_BUS
, 8, 3),
1870 DIV(TOP_DOUT_ACLK_BUS2_100
, "dout_aclk_bus2_100",
1871 "mout_bus2_bustop_100", DIV_TOP_BUS
, 12, 4),
1872 DIV(TOP_DOUT_ACLK_BUS3_400
, "dout_aclk_bus3_400",
1873 "mout_bus3_bustop_400", DIV_TOP_BUS
, 16, 3),
1874 DIV(TOP_DOUT_ACLK_BUS3_100
, "dout_aclk_bus3_100",
1875 "mout_bus3_bustop_100", DIV_TOP_BUS
, 20, 4),
1876 DIV(TOP_DOUT_ACLK_BUS4_400
, "dout_aclk_bus4_400",
1877 "mout_bus4_bustop_400", DIV_TOP_BUS
, 24, 3),
1878 DIV(TOP_DOUT_ACLK_BUS4_100
, "dout_aclk_bus4_100",
1879 "mout_bus4_bustop_100", DIV_TOP_BUS
, 28, 4),
1881 DIV(TOP_DOUT_SCLK_PERI_SPI0_A
, "dout_sclk_peri_spi0_a",
1882 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0
, 4, 4),
1883 DIV(TOP_DOUT_SCLK_PERI_SPI0_B
, "dout_sclk_peri_spi0_b",
1884 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0
, 8, 8),
1885 DIV(TOP_DOUT_SCLK_PERI_SPI1_A
, "dout_sclk_peri_spi1_a",
1886 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0
, 16, 4),
1887 DIV(TOP_DOUT_SCLK_PERI_SPI1_B
, "dout_sclk_peri_spi1_b",
1888 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0
, 20, 8),
1890 DIV(TOP_DOUT_SCLK_PERI_SPI2_A
, "dout_sclk_peri_spi2_a",
1891 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1
, 0, 4),
1892 DIV(TOP_DOUT_SCLK_PERI_SPI2_B
, "dout_sclk_peri_spi2_b",
1893 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1
, 4, 8),
1894 DIV(TOP_DOUT_SCLK_PERI_UART1
, "dout_sclk_peri_uart1",
1895 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1
, 16, 4),
1896 DIV(TOP_DOUT_SCLK_PERI_UART2
, "dout_sclk_peri_uart2",
1897 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1
, 20, 4),
1898 DIV(TOP_DOUT_SCLK_PERI_UART0
, "dout_sclk_peri_uart0",
1899 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1
, 24, 4),
1901 DIV(TOP_DOUT_ACLK_PERI_66
, "dout_aclk_peri_66", "mout_bustop_pll_user",
1902 DIV_TOP_PERI2
, 20, 4),
1903 DIV(TOP_DOUT_ACLK_PERI_AUD
, "dout_aclk_peri_aud",
1904 "mout_audtop_pll_user", DIV_TOP_PERI2
, 24, 3),
1906 DIV(TOP_DOUT_ACLK_FSYS_200
, "dout_aclk_fsys_200",
1907 "mout_bustop_pll_user", DIV_TOP_FSYS0
, 0, 3),
1908 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK
,
1909 "dout_sclk_fsys_usbdrd30_suspend_clk",
1910 "mout_sclk_fsys_usb", DIV_TOP_FSYS0
, 4, 4),
1911 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A
, "dout_sclk_fsys_mmc0_sdclkin_a",
1912 "mout_sclk_fsys_mmc0_sdclkin_b",
1913 DIV_TOP_FSYS0
, 12, 4),
1914 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B
, "dout_sclk_fsys_mmc0_sdclkin_b",
1915 "dout_sclk_fsys_mmc0_sdclkin_a",
1916 DIV_TOP_FSYS0
, 16, 8),
1919 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A
, "dout_sclk_fsys_mmc1_sdclkin_a",
1920 "mout_sclk_fsys_mmc1_sdclkin_b",
1921 DIV_TOP_FSYS1
, 0, 4),
1922 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B
, "dout_sclk_fsys_mmc1_sdclkin_b",
1923 "dout_sclk_fsys_mmc1_sdclkin_a",
1924 DIV_TOP_FSYS1
, 4, 8),
1925 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A
, "dout_sclk_fsys_mmc2_sdclkin_a",
1926 "mout_sclk_fsys_mmc2_sdclkin_b",
1927 DIV_TOP_FSYS1
, 12, 4),
1928 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B
, "dout_sclk_fsys_mmc2_sdclkin_b",
1929 "dout_sclk_fsys_mmc2_sdclkin_a",
1930 DIV_TOP_FSYS1
, 16, 8),
1934 struct samsung_gate_clock top_gate_clks
[] __initdata
= {
1935 GATE(TOP_SCLK_MMC0
, "sclk_fsys_mmc0_sdclkin",
1936 "dout_sclk_fsys_mmc0_sdclkin_b",
1937 EN_SCLK_TOP
, 7, CLK_SET_RATE_PARENT
, 0),
1938 GATE(TOP_SCLK_MMC1
, "sclk_fsys_mmc1_sdclkin",
1939 "dout_sclk_fsys_mmc1_sdclkin_b",
1940 EN_SCLK_TOP
, 8, CLK_SET_RATE_PARENT
, 0),
1941 GATE(TOP_SCLK_MMC2
, "sclk_fsys_mmc2_sdclkin",
1942 "dout_sclk_fsys_mmc2_sdclkin_b",
1943 EN_SCLK_TOP
, 9, CLK_SET_RATE_PARENT
, 0),
1944 GATE(TOP_SCLK_FIMD1
, "sclk_disp_pixel", "dout_sclk_disp_pixel",
1945 EN_ACLK_TOP
, 10, CLK_IGNORE_UNUSED
|
1946 CLK_SET_RATE_PARENT
, 0),
1949 static struct samsung_pll_clock top_pll_clks
[] __initdata
= {
1950 PLL(pll_2550xx
, TOP_FOUT_DISP_PLL
, "fout_disp_pll", "fin_pll",
1951 DISP_PLL_LOCK
, DISP_PLL_CON0
,
1953 PLL(pll_2650xx
, TOP_FOUT_AUD_PLL
, "fout_aud_pll", "fin_pll",
1954 AUD_PLL_LOCK
, AUD_PLL_CON0
,
1958 static void __init
exynos5260_clk_top_init(struct device_node
*np
)
1960 struct exynos5260_cmu_info cmu
= {0};
1962 cmu
.pll_clks
= top_pll_clks
;
1963 cmu
.nr_pll_clks
= ARRAY_SIZE(top_pll_clks
);
1964 cmu
.mux_clks
= top_mux_clks
;
1965 cmu
.nr_mux_clks
= ARRAY_SIZE(top_mux_clks
);
1966 cmu
.div_clks
= top_div_clks
;
1967 cmu
.nr_div_clks
= ARRAY_SIZE(top_div_clks
);
1968 cmu
.gate_clks
= top_gate_clks
;
1969 cmu
.nr_gate_clks
= ARRAY_SIZE(top_gate_clks
);
1970 cmu
.fixed_clks
= fixed_rate_clks
;
1971 cmu
.nr_fixed_clks
= ARRAY_SIZE(fixed_rate_clks
);
1972 cmu
.nr_clk_ids
= TOP_NR_CLK
;
1973 cmu
.clk_regs
= top_clk_regs
;
1974 cmu
.nr_clk_regs
= ARRAY_SIZE(top_clk_regs
);
1976 exynos5260_cmu_register_one(np
, &cmu
);
1979 CLK_OF_DECLARE(exynos5260_clk_top
, "samsung,exynos5260-clock-top",
1980 exynos5260_clk_top_init
);