2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
40 static const u8 gcc_xo_gpll0_map
[] = {
45 static const char *gcc_xo_gpll0
[] = {
50 static const u8 gcc_xo_gpll0_gpll4_map
[] = {
56 static const char *gcc_xo_gpll0_gpll4
[] = {
62 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
64 static struct clk_pll gpll0
= {
72 .clkr
.hw
.init
= &(struct clk_init_data
){
74 .parent_names
= (const char *[]){ "xo" },
80 static struct clk_regmap gpll0_vote
= {
82 .enable_mask
= BIT(0),
83 .hw
.init
= &(struct clk_init_data
){
85 .parent_names
= (const char *[]){ "gpll0" },
87 .ops
= &clk_pll_vote_ops
,
91 static struct clk_rcg2 config_noc_clk_src
= {
94 .parent_map
= gcc_xo_gpll0_map
,
95 .clkr
.hw
.init
= &(struct clk_init_data
){
96 .name
= "config_noc_clk_src",
97 .parent_names
= gcc_xo_gpll0
,
103 static struct clk_rcg2 periph_noc_clk_src
= {
106 .parent_map
= gcc_xo_gpll0_map
,
107 .clkr
.hw
.init
= &(struct clk_init_data
){
108 .name
= "periph_noc_clk_src",
109 .parent_names
= gcc_xo_gpll0
,
111 .ops
= &clk_rcg2_ops
,
115 static struct clk_rcg2 system_noc_clk_src
= {
118 .parent_map
= gcc_xo_gpll0_map
,
119 .clkr
.hw
.init
= &(struct clk_init_data
){
120 .name
= "system_noc_clk_src",
121 .parent_names
= gcc_xo_gpll0
,
123 .ops
= &clk_rcg2_ops
,
127 static struct clk_pll gpll1
= {
131 .config_reg
= 0x0054,
133 .status_reg
= 0x005c,
135 .clkr
.hw
.init
= &(struct clk_init_data
){
137 .parent_names
= (const char *[]){ "xo" },
143 static struct clk_regmap gpll1_vote
= {
144 .enable_reg
= 0x1480,
145 .enable_mask
= BIT(1),
146 .hw
.init
= &(struct clk_init_data
){
147 .name
= "gpll1_vote",
148 .parent_names
= (const char *[]){ "gpll1" },
150 .ops
= &clk_pll_vote_ops
,
154 static struct clk_pll gpll4
= {
158 .config_reg
= 0x1dd4,
160 .status_reg
= 0x1ddc,
162 .clkr
.hw
.init
= &(struct clk_init_data
){
164 .parent_names
= (const char *[]){ "xo" },
170 static struct clk_regmap gpll4_vote
= {
171 .enable_reg
= 0x1480,
172 .enable_mask
= BIT(4),
173 .hw
.init
= &(struct clk_init_data
){
174 .name
= "gpll4_vote",
175 .parent_names
= (const char *[]){ "gpll4" },
177 .ops
= &clk_pll_vote_ops
,
181 static const struct freq_tbl ftbl_gcc_usb30_master_clk
[] = {
182 F(125000000, P_GPLL0
, 1, 5, 24),
186 static struct clk_rcg2 usb30_master_clk_src
= {
190 .parent_map
= gcc_xo_gpll0_map
,
191 .freq_tbl
= ftbl_gcc_usb30_master_clk
,
192 .clkr
.hw
.init
= &(struct clk_init_data
){
193 .name
= "usb30_master_clk_src",
194 .parent_names
= gcc_xo_gpll0
,
196 .ops
= &clk_rcg2_ops
,
200 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
[] = {
201 F(19200000, P_XO
, 1, 0, 0),
202 F(37500000, P_GPLL0
, 16, 0, 0),
203 F(50000000, P_GPLL0
, 12, 0, 0),
207 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src
= {
210 .parent_map
= gcc_xo_gpll0_map
,
211 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
212 .clkr
.hw
.init
= &(struct clk_init_data
){
213 .name
= "blsp1_qup1_i2c_apps_clk_src",
214 .parent_names
= gcc_xo_gpll0
,
216 .ops
= &clk_rcg2_ops
,
220 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
[] = {
221 F(960000, P_XO
, 10, 1, 2),
222 F(4800000, P_XO
, 4, 0, 0),
223 F(9600000, P_XO
, 2, 0, 0),
224 F(15000000, P_GPLL0
, 10, 1, 4),
225 F(19200000, P_XO
, 1, 0, 0),
226 F(25000000, P_GPLL0
, 12, 1, 2),
227 F(50000000, P_GPLL0
, 12, 0, 0),
231 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src
= {
235 .parent_map
= gcc_xo_gpll0_map
,
236 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
237 .clkr
.hw
.init
= &(struct clk_init_data
){
238 .name
= "blsp1_qup1_spi_apps_clk_src",
239 .parent_names
= gcc_xo_gpll0
,
241 .ops
= &clk_rcg2_ops
,
245 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src
= {
248 .parent_map
= gcc_xo_gpll0_map
,
249 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
250 .clkr
.hw
.init
= &(struct clk_init_data
){
251 .name
= "blsp1_qup2_i2c_apps_clk_src",
252 .parent_names
= gcc_xo_gpll0
,
254 .ops
= &clk_rcg2_ops
,
258 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src
= {
262 .parent_map
= gcc_xo_gpll0_map
,
263 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
264 .clkr
.hw
.init
= &(struct clk_init_data
){
265 .name
= "blsp1_qup2_spi_apps_clk_src",
266 .parent_names
= gcc_xo_gpll0
,
268 .ops
= &clk_rcg2_ops
,
272 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src
= {
275 .parent_map
= gcc_xo_gpll0_map
,
276 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
277 .clkr
.hw
.init
= &(struct clk_init_data
){
278 .name
= "blsp1_qup3_i2c_apps_clk_src",
279 .parent_names
= gcc_xo_gpll0
,
281 .ops
= &clk_rcg2_ops
,
285 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src
= {
289 .parent_map
= gcc_xo_gpll0_map
,
290 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
291 .clkr
.hw
.init
= &(struct clk_init_data
){
292 .name
= "blsp1_qup3_spi_apps_clk_src",
293 .parent_names
= gcc_xo_gpll0
,
295 .ops
= &clk_rcg2_ops
,
299 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src
= {
302 .parent_map
= gcc_xo_gpll0_map
,
303 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
304 .clkr
.hw
.init
= &(struct clk_init_data
){
305 .name
= "blsp1_qup4_i2c_apps_clk_src",
306 .parent_names
= gcc_xo_gpll0
,
308 .ops
= &clk_rcg2_ops
,
312 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src
= {
316 .parent_map
= gcc_xo_gpll0_map
,
317 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
318 .clkr
.hw
.init
= &(struct clk_init_data
){
319 .name
= "blsp1_qup4_spi_apps_clk_src",
320 .parent_names
= gcc_xo_gpll0
,
322 .ops
= &clk_rcg2_ops
,
326 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src
= {
329 .parent_map
= gcc_xo_gpll0_map
,
330 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
331 .clkr
.hw
.init
= &(struct clk_init_data
){
332 .name
= "blsp1_qup5_i2c_apps_clk_src",
333 .parent_names
= gcc_xo_gpll0
,
335 .ops
= &clk_rcg2_ops
,
339 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src
= {
343 .parent_map
= gcc_xo_gpll0_map
,
344 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
345 .clkr
.hw
.init
= &(struct clk_init_data
){
346 .name
= "blsp1_qup5_spi_apps_clk_src",
347 .parent_names
= gcc_xo_gpll0
,
349 .ops
= &clk_rcg2_ops
,
353 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src
= {
356 .parent_map
= gcc_xo_gpll0_map
,
357 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
358 .clkr
.hw
.init
= &(struct clk_init_data
){
359 .name
= "blsp1_qup6_i2c_apps_clk_src",
360 .parent_names
= gcc_xo_gpll0
,
362 .ops
= &clk_rcg2_ops
,
366 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src
= {
370 .parent_map
= gcc_xo_gpll0_map
,
371 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
372 .clkr
.hw
.init
= &(struct clk_init_data
){
373 .name
= "blsp1_qup6_spi_apps_clk_src",
374 .parent_names
= gcc_xo_gpll0
,
376 .ops
= &clk_rcg2_ops
,
380 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk
[] = {
381 F(3686400, P_GPLL0
, 1, 96, 15625),
382 F(7372800, P_GPLL0
, 1, 192, 15625),
383 F(14745600, P_GPLL0
, 1, 384, 15625),
384 F(16000000, P_GPLL0
, 5, 2, 15),
385 F(19200000, P_XO
, 1, 0, 0),
386 F(24000000, P_GPLL0
, 5, 1, 5),
387 F(32000000, P_GPLL0
, 1, 4, 75),
388 F(40000000, P_GPLL0
, 15, 0, 0),
389 F(46400000, P_GPLL0
, 1, 29, 375),
390 F(48000000, P_GPLL0
, 12.5, 0, 0),
391 F(51200000, P_GPLL0
, 1, 32, 375),
392 F(56000000, P_GPLL0
, 1, 7, 75),
393 F(58982400, P_GPLL0
, 1, 1536, 15625),
394 F(60000000, P_GPLL0
, 10, 0, 0),
395 F(63160000, P_GPLL0
, 9.5, 0, 0),
399 static struct clk_rcg2 blsp1_uart1_apps_clk_src
= {
403 .parent_map
= gcc_xo_gpll0_map
,
404 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
405 .clkr
.hw
.init
= &(struct clk_init_data
){
406 .name
= "blsp1_uart1_apps_clk_src",
407 .parent_names
= gcc_xo_gpll0
,
409 .ops
= &clk_rcg2_ops
,
413 static struct clk_rcg2 blsp1_uart2_apps_clk_src
= {
417 .parent_map
= gcc_xo_gpll0_map
,
418 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
419 .clkr
.hw
.init
= &(struct clk_init_data
){
420 .name
= "blsp1_uart2_apps_clk_src",
421 .parent_names
= gcc_xo_gpll0
,
423 .ops
= &clk_rcg2_ops
,
427 static struct clk_rcg2 blsp1_uart3_apps_clk_src
= {
431 .parent_map
= gcc_xo_gpll0_map
,
432 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
433 .clkr
.hw
.init
= &(struct clk_init_data
){
434 .name
= "blsp1_uart3_apps_clk_src",
435 .parent_names
= gcc_xo_gpll0
,
437 .ops
= &clk_rcg2_ops
,
441 static struct clk_rcg2 blsp1_uart4_apps_clk_src
= {
445 .parent_map
= gcc_xo_gpll0_map
,
446 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
447 .clkr
.hw
.init
= &(struct clk_init_data
){
448 .name
= "blsp1_uart4_apps_clk_src",
449 .parent_names
= gcc_xo_gpll0
,
451 .ops
= &clk_rcg2_ops
,
455 static struct clk_rcg2 blsp1_uart5_apps_clk_src
= {
459 .parent_map
= gcc_xo_gpll0_map
,
460 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
461 .clkr
.hw
.init
= &(struct clk_init_data
){
462 .name
= "blsp1_uart5_apps_clk_src",
463 .parent_names
= gcc_xo_gpll0
,
465 .ops
= &clk_rcg2_ops
,
469 static struct clk_rcg2 blsp1_uart6_apps_clk_src
= {
473 .parent_map
= gcc_xo_gpll0_map
,
474 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
475 .clkr
.hw
.init
= &(struct clk_init_data
){
476 .name
= "blsp1_uart6_apps_clk_src",
477 .parent_names
= gcc_xo_gpll0
,
479 .ops
= &clk_rcg2_ops
,
483 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src
= {
486 .parent_map
= gcc_xo_gpll0_map
,
487 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
488 .clkr
.hw
.init
= &(struct clk_init_data
){
489 .name
= "blsp2_qup1_i2c_apps_clk_src",
490 .parent_names
= gcc_xo_gpll0
,
492 .ops
= &clk_rcg2_ops
,
496 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src
= {
500 .parent_map
= gcc_xo_gpll0_map
,
501 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
502 .clkr
.hw
.init
= &(struct clk_init_data
){
503 .name
= "blsp2_qup1_spi_apps_clk_src",
504 .parent_names
= gcc_xo_gpll0
,
506 .ops
= &clk_rcg2_ops
,
510 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src
= {
513 .parent_map
= gcc_xo_gpll0_map
,
514 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
515 .clkr
.hw
.init
= &(struct clk_init_data
){
516 .name
= "blsp2_qup2_i2c_apps_clk_src",
517 .parent_names
= gcc_xo_gpll0
,
519 .ops
= &clk_rcg2_ops
,
523 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src
= {
527 .parent_map
= gcc_xo_gpll0_map
,
528 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
529 .clkr
.hw
.init
= &(struct clk_init_data
){
530 .name
= "blsp2_qup2_spi_apps_clk_src",
531 .parent_names
= gcc_xo_gpll0
,
533 .ops
= &clk_rcg2_ops
,
537 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src
= {
540 .parent_map
= gcc_xo_gpll0_map
,
541 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
542 .clkr
.hw
.init
= &(struct clk_init_data
){
543 .name
= "blsp2_qup3_i2c_apps_clk_src",
544 .parent_names
= gcc_xo_gpll0
,
546 .ops
= &clk_rcg2_ops
,
550 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src
= {
554 .parent_map
= gcc_xo_gpll0_map
,
555 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
556 .clkr
.hw
.init
= &(struct clk_init_data
){
557 .name
= "blsp2_qup3_spi_apps_clk_src",
558 .parent_names
= gcc_xo_gpll0
,
560 .ops
= &clk_rcg2_ops
,
564 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src
= {
567 .parent_map
= gcc_xo_gpll0_map
,
568 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
569 .clkr
.hw
.init
= &(struct clk_init_data
){
570 .name
= "blsp2_qup4_i2c_apps_clk_src",
571 .parent_names
= gcc_xo_gpll0
,
573 .ops
= &clk_rcg2_ops
,
577 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src
= {
581 .parent_map
= gcc_xo_gpll0_map
,
582 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
583 .clkr
.hw
.init
= &(struct clk_init_data
){
584 .name
= "blsp2_qup4_spi_apps_clk_src",
585 .parent_names
= gcc_xo_gpll0
,
587 .ops
= &clk_rcg2_ops
,
591 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src
= {
594 .parent_map
= gcc_xo_gpll0_map
,
595 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
596 .clkr
.hw
.init
= &(struct clk_init_data
){
597 .name
= "blsp2_qup5_i2c_apps_clk_src",
598 .parent_names
= gcc_xo_gpll0
,
600 .ops
= &clk_rcg2_ops
,
604 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src
= {
608 .parent_map
= gcc_xo_gpll0_map
,
609 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
610 .clkr
.hw
.init
= &(struct clk_init_data
){
611 .name
= "blsp2_qup5_spi_apps_clk_src",
612 .parent_names
= gcc_xo_gpll0
,
614 .ops
= &clk_rcg2_ops
,
618 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src
= {
621 .parent_map
= gcc_xo_gpll0_map
,
622 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
623 .clkr
.hw
.init
= &(struct clk_init_data
){
624 .name
= "blsp2_qup6_i2c_apps_clk_src",
625 .parent_names
= gcc_xo_gpll0
,
627 .ops
= &clk_rcg2_ops
,
631 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src
= {
635 .parent_map
= gcc_xo_gpll0_map
,
636 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
637 .clkr
.hw
.init
= &(struct clk_init_data
){
638 .name
= "blsp2_qup6_spi_apps_clk_src",
639 .parent_names
= gcc_xo_gpll0
,
641 .ops
= &clk_rcg2_ops
,
645 static struct clk_rcg2 blsp2_uart1_apps_clk_src
= {
649 .parent_map
= gcc_xo_gpll0_map
,
650 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
651 .clkr
.hw
.init
= &(struct clk_init_data
){
652 .name
= "blsp2_uart1_apps_clk_src",
653 .parent_names
= gcc_xo_gpll0
,
655 .ops
= &clk_rcg2_ops
,
659 static struct clk_rcg2 blsp2_uart2_apps_clk_src
= {
663 .parent_map
= gcc_xo_gpll0_map
,
664 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
665 .clkr
.hw
.init
= &(struct clk_init_data
){
666 .name
= "blsp2_uart2_apps_clk_src",
667 .parent_names
= gcc_xo_gpll0
,
669 .ops
= &clk_rcg2_ops
,
673 static struct clk_rcg2 blsp2_uart3_apps_clk_src
= {
677 .parent_map
= gcc_xo_gpll0_map
,
678 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
679 .clkr
.hw
.init
= &(struct clk_init_data
){
680 .name
= "blsp2_uart3_apps_clk_src",
681 .parent_names
= gcc_xo_gpll0
,
683 .ops
= &clk_rcg2_ops
,
687 static struct clk_rcg2 blsp2_uart4_apps_clk_src
= {
691 .parent_map
= gcc_xo_gpll0_map
,
692 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
693 .clkr
.hw
.init
= &(struct clk_init_data
){
694 .name
= "blsp2_uart4_apps_clk_src",
695 .parent_names
= gcc_xo_gpll0
,
697 .ops
= &clk_rcg2_ops
,
701 static struct clk_rcg2 blsp2_uart5_apps_clk_src
= {
705 .parent_map
= gcc_xo_gpll0_map
,
706 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
707 .clkr
.hw
.init
= &(struct clk_init_data
){
708 .name
= "blsp2_uart5_apps_clk_src",
709 .parent_names
= gcc_xo_gpll0
,
711 .ops
= &clk_rcg2_ops
,
715 static struct clk_rcg2 blsp2_uart6_apps_clk_src
= {
719 .parent_map
= gcc_xo_gpll0_map
,
720 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
721 .clkr
.hw
.init
= &(struct clk_init_data
){
722 .name
= "blsp2_uart6_apps_clk_src",
723 .parent_names
= gcc_xo_gpll0
,
725 .ops
= &clk_rcg2_ops
,
729 static const struct freq_tbl ftbl_gcc_ce1_clk
[] = {
730 F(50000000, P_GPLL0
, 12, 0, 0),
731 F(75000000, P_GPLL0
, 8, 0, 0),
732 F(100000000, P_GPLL0
, 6, 0, 0),
733 F(150000000, P_GPLL0
, 4, 0, 0),
737 static struct clk_rcg2 ce1_clk_src
= {
740 .parent_map
= gcc_xo_gpll0_map
,
741 .freq_tbl
= ftbl_gcc_ce1_clk
,
742 .clkr
.hw
.init
= &(struct clk_init_data
){
743 .name
= "ce1_clk_src",
744 .parent_names
= gcc_xo_gpll0
,
746 .ops
= &clk_rcg2_ops
,
750 static const struct freq_tbl ftbl_gcc_ce2_clk
[] = {
751 F(50000000, P_GPLL0
, 12, 0, 0),
752 F(75000000, P_GPLL0
, 8, 0, 0),
753 F(100000000, P_GPLL0
, 6, 0, 0),
754 F(150000000, P_GPLL0
, 4, 0, 0),
758 static struct clk_rcg2 ce2_clk_src
= {
761 .parent_map
= gcc_xo_gpll0_map
,
762 .freq_tbl
= ftbl_gcc_ce2_clk
,
763 .clkr
.hw
.init
= &(struct clk_init_data
){
764 .name
= "ce2_clk_src",
765 .parent_names
= gcc_xo_gpll0
,
767 .ops
= &clk_rcg2_ops
,
771 static const struct freq_tbl ftbl_gcc_gp_clk
[] = {
772 F(4800000, P_XO
, 4, 0, 0),
773 F(6000000, P_GPLL0
, 10, 1, 10),
774 F(6750000, P_GPLL0
, 1, 1, 89),
775 F(8000000, P_GPLL0
, 15, 1, 5),
776 F(9600000, P_XO
, 2, 0, 0),
777 F(16000000, P_GPLL0
, 1, 2, 75),
778 F(19200000, P_XO
, 1, 0, 0),
779 F(24000000, P_GPLL0
, 5, 1, 5),
784 static struct clk_rcg2 gp1_clk_src
= {
788 .parent_map
= gcc_xo_gpll0_map
,
789 .freq_tbl
= ftbl_gcc_gp_clk
,
790 .clkr
.hw
.init
= &(struct clk_init_data
){
791 .name
= "gp1_clk_src",
792 .parent_names
= gcc_xo_gpll0
,
794 .ops
= &clk_rcg2_ops
,
798 static struct clk_rcg2 gp2_clk_src
= {
802 .parent_map
= gcc_xo_gpll0_map
,
803 .freq_tbl
= ftbl_gcc_gp_clk
,
804 .clkr
.hw
.init
= &(struct clk_init_data
){
805 .name
= "gp2_clk_src",
806 .parent_names
= gcc_xo_gpll0
,
808 .ops
= &clk_rcg2_ops
,
812 static struct clk_rcg2 gp3_clk_src
= {
816 .parent_map
= gcc_xo_gpll0_map
,
817 .freq_tbl
= ftbl_gcc_gp_clk
,
818 .clkr
.hw
.init
= &(struct clk_init_data
){
819 .name
= "gp3_clk_src",
820 .parent_names
= gcc_xo_gpll0
,
822 .ops
= &clk_rcg2_ops
,
826 static const struct freq_tbl ftbl_gcc_pdm2_clk
[] = {
827 F(60000000, P_GPLL0
, 10, 0, 0),
831 static struct clk_rcg2 pdm2_clk_src
= {
834 .parent_map
= gcc_xo_gpll0_map
,
835 .freq_tbl
= ftbl_gcc_pdm2_clk
,
836 .clkr
.hw
.init
= &(struct clk_init_data
){
837 .name
= "pdm2_clk_src",
838 .parent_names
= gcc_xo_gpll0
,
840 .ops
= &clk_rcg2_ops
,
844 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk
[] = {
845 F(144000, P_XO
, 16, 3, 25),
846 F(400000, P_XO
, 12, 1, 4),
847 F(20000000, P_GPLL0
, 15, 1, 2),
848 F(25000000, P_GPLL0
, 12, 1, 2),
849 F(50000000, P_GPLL0
, 12, 0, 0),
850 F(100000000, P_GPLL0
, 6, 0, 0),
851 F(200000000, P_GPLL0
, 3, 0, 0),
855 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro
[] = {
856 F(144000, P_XO
, 16, 3, 25),
857 F(400000, P_XO
, 12, 1, 4),
858 F(20000000, P_GPLL0
, 15, 1, 2),
859 F(25000000, P_GPLL0
, 12, 1, 2),
860 F(50000000, P_GPLL0
, 12, 0, 0),
861 F(100000000, P_GPLL0
, 6, 0, 0),
862 F(192000000, P_GPLL4
, 4, 0, 0),
863 F(200000000, P_GPLL0
, 3, 0, 0),
864 F(384000000, P_GPLL4
, 2, 0, 0),
868 static struct clk_init_data sdcc1_apps_clk_src_init
= {
869 .name
= "sdcc1_apps_clk_src",
870 .parent_names
= gcc_xo_gpll0
,
872 .ops
= &clk_rcg2_ops
,
875 static struct clk_rcg2 sdcc1_apps_clk_src
= {
879 .parent_map
= gcc_xo_gpll0_map
,
880 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
881 .clkr
.hw
.init
= &sdcc1_apps_clk_src_init
,
884 static struct clk_rcg2 sdcc2_apps_clk_src
= {
888 .parent_map
= gcc_xo_gpll0_map
,
889 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
890 .clkr
.hw
.init
= &(struct clk_init_data
){
891 .name
= "sdcc2_apps_clk_src",
892 .parent_names
= gcc_xo_gpll0
,
894 .ops
= &clk_rcg2_ops
,
898 static struct clk_rcg2 sdcc3_apps_clk_src
= {
902 .parent_map
= gcc_xo_gpll0_map
,
903 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
904 .clkr
.hw
.init
= &(struct clk_init_data
){
905 .name
= "sdcc3_apps_clk_src",
906 .parent_names
= gcc_xo_gpll0
,
908 .ops
= &clk_rcg2_ops
,
912 static struct clk_rcg2 sdcc4_apps_clk_src
= {
916 .parent_map
= gcc_xo_gpll0_map
,
917 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
918 .clkr
.hw
.init
= &(struct clk_init_data
){
919 .name
= "sdcc4_apps_clk_src",
920 .parent_names
= gcc_xo_gpll0
,
922 .ops
= &clk_rcg2_ops
,
926 static const struct freq_tbl ftbl_gcc_tsif_ref_clk
[] = {
927 F(105000, P_XO
, 2, 1, 91),
931 static struct clk_rcg2 tsif_ref_clk_src
= {
935 .parent_map
= gcc_xo_gpll0_map
,
936 .freq_tbl
= ftbl_gcc_tsif_ref_clk
,
937 .clkr
.hw
.init
= &(struct clk_init_data
){
938 .name
= "tsif_ref_clk_src",
939 .parent_names
= gcc_xo_gpll0
,
941 .ops
= &clk_rcg2_ops
,
945 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk
[] = {
946 F(60000000, P_GPLL0
, 10, 0, 0),
950 static struct clk_rcg2 usb30_mock_utmi_clk_src
= {
953 .parent_map
= gcc_xo_gpll0_map
,
954 .freq_tbl
= ftbl_gcc_usb30_mock_utmi_clk
,
955 .clkr
.hw
.init
= &(struct clk_init_data
){
956 .name
= "usb30_mock_utmi_clk_src",
957 .parent_names
= gcc_xo_gpll0
,
959 .ops
= &clk_rcg2_ops
,
963 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk
[] = {
964 F(60000000, P_GPLL0
, 10, 0, 0),
965 F(75000000, P_GPLL0
, 8, 0, 0),
969 static struct clk_rcg2 usb_hs_system_clk_src
= {
972 .parent_map
= gcc_xo_gpll0_map
,
973 .freq_tbl
= ftbl_gcc_usb_hs_system_clk
,
974 .clkr
.hw
.init
= &(struct clk_init_data
){
975 .name
= "usb_hs_system_clk_src",
976 .parent_names
= gcc_xo_gpll0
,
978 .ops
= &clk_rcg2_ops
,
982 static const struct freq_tbl ftbl_gcc_usb_hsic_clk
[] = {
983 F(480000000, P_GPLL1
, 1, 0, 0),
987 static u8 usb_hsic_clk_src_map
[] = {
992 static struct clk_rcg2 usb_hsic_clk_src
= {
995 .parent_map
= usb_hsic_clk_src_map
,
996 .freq_tbl
= ftbl_gcc_usb_hsic_clk
,
997 .clkr
.hw
.init
= &(struct clk_init_data
){
998 .name
= "usb_hsic_clk_src",
999 .parent_names
= (const char *[]){
1004 .ops
= &clk_rcg2_ops
,
1008 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk
[] = {
1009 F(9600000, P_XO
, 2, 0, 0),
1013 static struct clk_rcg2 usb_hsic_io_cal_clk_src
= {
1016 .parent_map
= gcc_xo_gpll0_map
,
1017 .freq_tbl
= ftbl_gcc_usb_hsic_io_cal_clk
,
1018 .clkr
.hw
.init
= &(struct clk_init_data
){
1019 .name
= "usb_hsic_io_cal_clk_src",
1020 .parent_names
= gcc_xo_gpll0
,
1022 .ops
= &clk_rcg2_ops
,
1026 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk
[] = {
1027 F(60000000, P_GPLL0
, 10, 0, 0),
1028 F(75000000, P_GPLL0
, 8, 0, 0),
1032 static struct clk_rcg2 usb_hsic_system_clk_src
= {
1035 .parent_map
= gcc_xo_gpll0_map
,
1036 .freq_tbl
= ftbl_gcc_usb_hsic_system_clk
,
1037 .clkr
.hw
.init
= &(struct clk_init_data
){
1038 .name
= "usb_hsic_system_clk_src",
1039 .parent_names
= gcc_xo_gpll0
,
1041 .ops
= &clk_rcg2_ops
,
1045 static struct clk_regmap gcc_mmss_gpll0_clk_src
= {
1046 .enable_reg
= 0x1484,
1047 .enable_mask
= BIT(26),
1048 .hw
.init
= &(struct clk_init_data
){
1049 .name
= "mmss_gpll0_vote",
1050 .parent_names
= (const char *[]){
1054 .ops
= &clk_branch_simple_ops
,
1058 static struct clk_branch gcc_bam_dma_ahb_clk
= {
1060 .halt_check
= BRANCH_HALT_VOTED
,
1062 .enable_reg
= 0x1484,
1063 .enable_mask
= BIT(12),
1064 .hw
.init
= &(struct clk_init_data
){
1065 .name
= "gcc_bam_dma_ahb_clk",
1066 .parent_names
= (const char *[]){
1067 "periph_noc_clk_src",
1070 .ops
= &clk_branch2_ops
,
1075 static struct clk_branch gcc_blsp1_ahb_clk
= {
1077 .halt_check
= BRANCH_HALT_VOTED
,
1079 .enable_reg
= 0x1484,
1080 .enable_mask
= BIT(17),
1081 .hw
.init
= &(struct clk_init_data
){
1082 .name
= "gcc_blsp1_ahb_clk",
1083 .parent_names
= (const char *[]){
1084 "periph_noc_clk_src",
1087 .ops
= &clk_branch2_ops
,
1092 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk
= {
1095 .enable_reg
= 0x0648,
1096 .enable_mask
= BIT(0),
1097 .hw
.init
= &(struct clk_init_data
){
1098 .name
= "gcc_blsp1_qup1_i2c_apps_clk",
1099 .parent_names
= (const char *[]){
1100 "blsp1_qup1_i2c_apps_clk_src",
1103 .flags
= CLK_SET_RATE_PARENT
,
1104 .ops
= &clk_branch2_ops
,
1109 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk
= {
1112 .enable_reg
= 0x0644,
1113 .enable_mask
= BIT(0),
1114 .hw
.init
= &(struct clk_init_data
){
1115 .name
= "gcc_blsp1_qup1_spi_apps_clk",
1116 .parent_names
= (const char *[]){
1117 "blsp1_qup1_spi_apps_clk_src",
1120 .flags
= CLK_SET_RATE_PARENT
,
1121 .ops
= &clk_branch2_ops
,
1126 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk
= {
1129 .enable_reg
= 0x06c8,
1130 .enable_mask
= BIT(0),
1131 .hw
.init
= &(struct clk_init_data
){
1132 .name
= "gcc_blsp1_qup2_i2c_apps_clk",
1133 .parent_names
= (const char *[]){
1134 "blsp1_qup2_i2c_apps_clk_src",
1137 .flags
= CLK_SET_RATE_PARENT
,
1138 .ops
= &clk_branch2_ops
,
1143 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk
= {
1146 .enable_reg
= 0x06c4,
1147 .enable_mask
= BIT(0),
1148 .hw
.init
= &(struct clk_init_data
){
1149 .name
= "gcc_blsp1_qup2_spi_apps_clk",
1150 .parent_names
= (const char *[]){
1151 "blsp1_qup2_spi_apps_clk_src",
1154 .flags
= CLK_SET_RATE_PARENT
,
1155 .ops
= &clk_branch2_ops
,
1160 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk
= {
1163 .enable_reg
= 0x0748,
1164 .enable_mask
= BIT(0),
1165 .hw
.init
= &(struct clk_init_data
){
1166 .name
= "gcc_blsp1_qup3_i2c_apps_clk",
1167 .parent_names
= (const char *[]){
1168 "blsp1_qup3_i2c_apps_clk_src",
1171 .flags
= CLK_SET_RATE_PARENT
,
1172 .ops
= &clk_branch2_ops
,
1177 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk
= {
1180 .enable_reg
= 0x0744,
1181 .enable_mask
= BIT(0),
1182 .hw
.init
= &(struct clk_init_data
){
1183 .name
= "gcc_blsp1_qup3_spi_apps_clk",
1184 .parent_names
= (const char *[]){
1185 "blsp1_qup3_spi_apps_clk_src",
1188 .flags
= CLK_SET_RATE_PARENT
,
1189 .ops
= &clk_branch2_ops
,
1194 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk
= {
1197 .enable_reg
= 0x07c8,
1198 .enable_mask
= BIT(0),
1199 .hw
.init
= &(struct clk_init_data
){
1200 .name
= "gcc_blsp1_qup4_i2c_apps_clk",
1201 .parent_names
= (const char *[]){
1202 "blsp1_qup4_i2c_apps_clk_src",
1205 .flags
= CLK_SET_RATE_PARENT
,
1206 .ops
= &clk_branch2_ops
,
1211 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk
= {
1214 .enable_reg
= 0x07c4,
1215 .enable_mask
= BIT(0),
1216 .hw
.init
= &(struct clk_init_data
){
1217 .name
= "gcc_blsp1_qup4_spi_apps_clk",
1218 .parent_names
= (const char *[]){
1219 "blsp1_qup4_spi_apps_clk_src",
1222 .flags
= CLK_SET_RATE_PARENT
,
1223 .ops
= &clk_branch2_ops
,
1228 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk
= {
1231 .enable_reg
= 0x0848,
1232 .enable_mask
= BIT(0),
1233 .hw
.init
= &(struct clk_init_data
){
1234 .name
= "gcc_blsp1_qup5_i2c_apps_clk",
1235 .parent_names
= (const char *[]){
1236 "blsp1_qup5_i2c_apps_clk_src",
1239 .flags
= CLK_SET_RATE_PARENT
,
1240 .ops
= &clk_branch2_ops
,
1245 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk
= {
1248 .enable_reg
= 0x0844,
1249 .enable_mask
= BIT(0),
1250 .hw
.init
= &(struct clk_init_data
){
1251 .name
= "gcc_blsp1_qup5_spi_apps_clk",
1252 .parent_names
= (const char *[]){
1253 "blsp1_qup5_spi_apps_clk_src",
1256 .flags
= CLK_SET_RATE_PARENT
,
1257 .ops
= &clk_branch2_ops
,
1262 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk
= {
1265 .enable_reg
= 0x08c8,
1266 .enable_mask
= BIT(0),
1267 .hw
.init
= &(struct clk_init_data
){
1268 .name
= "gcc_blsp1_qup6_i2c_apps_clk",
1269 .parent_names
= (const char *[]){
1270 "blsp1_qup6_i2c_apps_clk_src",
1273 .flags
= CLK_SET_RATE_PARENT
,
1274 .ops
= &clk_branch2_ops
,
1279 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk
= {
1282 .enable_reg
= 0x08c4,
1283 .enable_mask
= BIT(0),
1284 .hw
.init
= &(struct clk_init_data
){
1285 .name
= "gcc_blsp1_qup6_spi_apps_clk",
1286 .parent_names
= (const char *[]){
1287 "blsp1_qup6_spi_apps_clk_src",
1290 .flags
= CLK_SET_RATE_PARENT
,
1291 .ops
= &clk_branch2_ops
,
1296 static struct clk_branch gcc_blsp1_uart1_apps_clk
= {
1299 .enable_reg
= 0x0684,
1300 .enable_mask
= BIT(0),
1301 .hw
.init
= &(struct clk_init_data
){
1302 .name
= "gcc_blsp1_uart1_apps_clk",
1303 .parent_names
= (const char *[]){
1304 "blsp1_uart1_apps_clk_src",
1307 .flags
= CLK_SET_RATE_PARENT
,
1308 .ops
= &clk_branch2_ops
,
1313 static struct clk_branch gcc_blsp1_uart2_apps_clk
= {
1316 .enable_reg
= 0x0704,
1317 .enable_mask
= BIT(0),
1318 .hw
.init
= &(struct clk_init_data
){
1319 .name
= "gcc_blsp1_uart2_apps_clk",
1320 .parent_names
= (const char *[]){
1321 "blsp1_uart2_apps_clk_src",
1324 .flags
= CLK_SET_RATE_PARENT
,
1325 .ops
= &clk_branch2_ops
,
1330 static struct clk_branch gcc_blsp1_uart3_apps_clk
= {
1333 .enable_reg
= 0x0784,
1334 .enable_mask
= BIT(0),
1335 .hw
.init
= &(struct clk_init_data
){
1336 .name
= "gcc_blsp1_uart3_apps_clk",
1337 .parent_names
= (const char *[]){
1338 "blsp1_uart3_apps_clk_src",
1341 .flags
= CLK_SET_RATE_PARENT
,
1342 .ops
= &clk_branch2_ops
,
1347 static struct clk_branch gcc_blsp1_uart4_apps_clk
= {
1350 .enable_reg
= 0x0804,
1351 .enable_mask
= BIT(0),
1352 .hw
.init
= &(struct clk_init_data
){
1353 .name
= "gcc_blsp1_uart4_apps_clk",
1354 .parent_names
= (const char *[]){
1355 "blsp1_uart4_apps_clk_src",
1358 .flags
= CLK_SET_RATE_PARENT
,
1359 .ops
= &clk_branch2_ops
,
1364 static struct clk_branch gcc_blsp1_uart5_apps_clk
= {
1367 .enable_reg
= 0x0884,
1368 .enable_mask
= BIT(0),
1369 .hw
.init
= &(struct clk_init_data
){
1370 .name
= "gcc_blsp1_uart5_apps_clk",
1371 .parent_names
= (const char *[]){
1372 "blsp1_uart5_apps_clk_src",
1375 .flags
= CLK_SET_RATE_PARENT
,
1376 .ops
= &clk_branch2_ops
,
1381 static struct clk_branch gcc_blsp1_uart6_apps_clk
= {
1384 .enable_reg
= 0x0904,
1385 .enable_mask
= BIT(0),
1386 .hw
.init
= &(struct clk_init_data
){
1387 .name
= "gcc_blsp1_uart6_apps_clk",
1388 .parent_names
= (const char *[]){
1389 "blsp1_uart6_apps_clk_src",
1392 .flags
= CLK_SET_RATE_PARENT
,
1393 .ops
= &clk_branch2_ops
,
1398 static struct clk_branch gcc_blsp2_ahb_clk
= {
1400 .halt_check
= BRANCH_HALT_VOTED
,
1402 .enable_reg
= 0x1484,
1403 .enable_mask
= BIT(15),
1404 .hw
.init
= &(struct clk_init_data
){
1405 .name
= "gcc_blsp2_ahb_clk",
1406 .parent_names
= (const char *[]){
1407 "periph_noc_clk_src",
1410 .ops
= &clk_branch2_ops
,
1415 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk
= {
1418 .enable_reg
= 0x0988,
1419 .enable_mask
= BIT(0),
1420 .hw
.init
= &(struct clk_init_data
){
1421 .name
= "gcc_blsp2_qup1_i2c_apps_clk",
1422 .parent_names
= (const char *[]){
1423 "blsp2_qup1_i2c_apps_clk_src",
1426 .flags
= CLK_SET_RATE_PARENT
,
1427 .ops
= &clk_branch2_ops
,
1432 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk
= {
1435 .enable_reg
= 0x0984,
1436 .enable_mask
= BIT(0),
1437 .hw
.init
= &(struct clk_init_data
){
1438 .name
= "gcc_blsp2_qup1_spi_apps_clk",
1439 .parent_names
= (const char *[]){
1440 "blsp2_qup1_spi_apps_clk_src",
1443 .flags
= CLK_SET_RATE_PARENT
,
1444 .ops
= &clk_branch2_ops
,
1449 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk
= {
1452 .enable_reg
= 0x0a08,
1453 .enable_mask
= BIT(0),
1454 .hw
.init
= &(struct clk_init_data
){
1455 .name
= "gcc_blsp2_qup2_i2c_apps_clk",
1456 .parent_names
= (const char *[]){
1457 "blsp2_qup2_i2c_apps_clk_src",
1460 .flags
= CLK_SET_RATE_PARENT
,
1461 .ops
= &clk_branch2_ops
,
1466 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk
= {
1469 .enable_reg
= 0x0a04,
1470 .enable_mask
= BIT(0),
1471 .hw
.init
= &(struct clk_init_data
){
1472 .name
= "gcc_blsp2_qup2_spi_apps_clk",
1473 .parent_names
= (const char *[]){
1474 "blsp2_qup2_spi_apps_clk_src",
1477 .flags
= CLK_SET_RATE_PARENT
,
1478 .ops
= &clk_branch2_ops
,
1483 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk
= {
1486 .enable_reg
= 0x0a88,
1487 .enable_mask
= BIT(0),
1488 .hw
.init
= &(struct clk_init_data
){
1489 .name
= "gcc_blsp2_qup3_i2c_apps_clk",
1490 .parent_names
= (const char *[]){
1491 "blsp2_qup3_i2c_apps_clk_src",
1494 .flags
= CLK_SET_RATE_PARENT
,
1495 .ops
= &clk_branch2_ops
,
1500 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk
= {
1503 .enable_reg
= 0x0a84,
1504 .enable_mask
= BIT(0),
1505 .hw
.init
= &(struct clk_init_data
){
1506 .name
= "gcc_blsp2_qup3_spi_apps_clk",
1507 .parent_names
= (const char *[]){
1508 "blsp2_qup3_spi_apps_clk_src",
1511 .flags
= CLK_SET_RATE_PARENT
,
1512 .ops
= &clk_branch2_ops
,
1517 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk
= {
1520 .enable_reg
= 0x0b08,
1521 .enable_mask
= BIT(0),
1522 .hw
.init
= &(struct clk_init_data
){
1523 .name
= "gcc_blsp2_qup4_i2c_apps_clk",
1524 .parent_names
= (const char *[]){
1525 "blsp2_qup4_i2c_apps_clk_src",
1528 .flags
= CLK_SET_RATE_PARENT
,
1529 .ops
= &clk_branch2_ops
,
1534 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk
= {
1537 .enable_reg
= 0x0b04,
1538 .enable_mask
= BIT(0),
1539 .hw
.init
= &(struct clk_init_data
){
1540 .name
= "gcc_blsp2_qup4_spi_apps_clk",
1541 .parent_names
= (const char *[]){
1542 "blsp2_qup4_spi_apps_clk_src",
1545 .flags
= CLK_SET_RATE_PARENT
,
1546 .ops
= &clk_branch2_ops
,
1551 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk
= {
1554 .enable_reg
= 0x0b88,
1555 .enable_mask
= BIT(0),
1556 .hw
.init
= &(struct clk_init_data
){
1557 .name
= "gcc_blsp2_qup5_i2c_apps_clk",
1558 .parent_names
= (const char *[]){
1559 "blsp2_qup5_i2c_apps_clk_src",
1562 .flags
= CLK_SET_RATE_PARENT
,
1563 .ops
= &clk_branch2_ops
,
1568 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk
= {
1571 .enable_reg
= 0x0b84,
1572 .enable_mask
= BIT(0),
1573 .hw
.init
= &(struct clk_init_data
){
1574 .name
= "gcc_blsp2_qup5_spi_apps_clk",
1575 .parent_names
= (const char *[]){
1576 "blsp2_qup5_spi_apps_clk_src",
1579 .flags
= CLK_SET_RATE_PARENT
,
1580 .ops
= &clk_branch2_ops
,
1585 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk
= {
1588 .enable_reg
= 0x0c08,
1589 .enable_mask
= BIT(0),
1590 .hw
.init
= &(struct clk_init_data
){
1591 .name
= "gcc_blsp2_qup6_i2c_apps_clk",
1592 .parent_names
= (const char *[]){
1593 "blsp2_qup6_i2c_apps_clk_src",
1596 .flags
= CLK_SET_RATE_PARENT
,
1597 .ops
= &clk_branch2_ops
,
1602 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk
= {
1605 .enable_reg
= 0x0c04,
1606 .enable_mask
= BIT(0),
1607 .hw
.init
= &(struct clk_init_data
){
1608 .name
= "gcc_blsp2_qup6_spi_apps_clk",
1609 .parent_names
= (const char *[]){
1610 "blsp2_qup6_spi_apps_clk_src",
1613 .flags
= CLK_SET_RATE_PARENT
,
1614 .ops
= &clk_branch2_ops
,
1619 static struct clk_branch gcc_blsp2_uart1_apps_clk
= {
1622 .enable_reg
= 0x09c4,
1623 .enable_mask
= BIT(0),
1624 .hw
.init
= &(struct clk_init_data
){
1625 .name
= "gcc_blsp2_uart1_apps_clk",
1626 .parent_names
= (const char *[]){
1627 "blsp2_uart1_apps_clk_src",
1630 .flags
= CLK_SET_RATE_PARENT
,
1631 .ops
= &clk_branch2_ops
,
1636 static struct clk_branch gcc_blsp2_uart2_apps_clk
= {
1639 .enable_reg
= 0x0a44,
1640 .enable_mask
= BIT(0),
1641 .hw
.init
= &(struct clk_init_data
){
1642 .name
= "gcc_blsp2_uart2_apps_clk",
1643 .parent_names
= (const char *[]){
1644 "blsp2_uart2_apps_clk_src",
1647 .flags
= CLK_SET_RATE_PARENT
,
1648 .ops
= &clk_branch2_ops
,
1653 static struct clk_branch gcc_blsp2_uart3_apps_clk
= {
1656 .enable_reg
= 0x0ac4,
1657 .enable_mask
= BIT(0),
1658 .hw
.init
= &(struct clk_init_data
){
1659 .name
= "gcc_blsp2_uart3_apps_clk",
1660 .parent_names
= (const char *[]){
1661 "blsp2_uart3_apps_clk_src",
1664 .flags
= CLK_SET_RATE_PARENT
,
1665 .ops
= &clk_branch2_ops
,
1670 static struct clk_branch gcc_blsp2_uart4_apps_clk
= {
1673 .enable_reg
= 0x0b44,
1674 .enable_mask
= BIT(0),
1675 .hw
.init
= &(struct clk_init_data
){
1676 .name
= "gcc_blsp2_uart4_apps_clk",
1677 .parent_names
= (const char *[]){
1678 "blsp2_uart4_apps_clk_src",
1681 .flags
= CLK_SET_RATE_PARENT
,
1682 .ops
= &clk_branch2_ops
,
1687 static struct clk_branch gcc_blsp2_uart5_apps_clk
= {
1690 .enable_reg
= 0x0bc4,
1691 .enable_mask
= BIT(0),
1692 .hw
.init
= &(struct clk_init_data
){
1693 .name
= "gcc_blsp2_uart5_apps_clk",
1694 .parent_names
= (const char *[]){
1695 "blsp2_uart5_apps_clk_src",
1698 .flags
= CLK_SET_RATE_PARENT
,
1699 .ops
= &clk_branch2_ops
,
1704 static struct clk_branch gcc_blsp2_uart6_apps_clk
= {
1707 .enable_reg
= 0x0c44,
1708 .enable_mask
= BIT(0),
1709 .hw
.init
= &(struct clk_init_data
){
1710 .name
= "gcc_blsp2_uart6_apps_clk",
1711 .parent_names
= (const char *[]){
1712 "blsp2_uart6_apps_clk_src",
1715 .flags
= CLK_SET_RATE_PARENT
,
1716 .ops
= &clk_branch2_ops
,
1721 static struct clk_branch gcc_boot_rom_ahb_clk
= {
1723 .halt_check
= BRANCH_HALT_VOTED
,
1725 .enable_reg
= 0x1484,
1726 .enable_mask
= BIT(10),
1727 .hw
.init
= &(struct clk_init_data
){
1728 .name
= "gcc_boot_rom_ahb_clk",
1729 .parent_names
= (const char *[]){
1730 "config_noc_clk_src",
1733 .ops
= &clk_branch2_ops
,
1738 static struct clk_branch gcc_ce1_ahb_clk
= {
1740 .halt_check
= BRANCH_HALT_VOTED
,
1742 .enable_reg
= 0x1484,
1743 .enable_mask
= BIT(3),
1744 .hw
.init
= &(struct clk_init_data
){
1745 .name
= "gcc_ce1_ahb_clk",
1746 .parent_names
= (const char *[]){
1747 "config_noc_clk_src",
1750 .ops
= &clk_branch2_ops
,
1755 static struct clk_branch gcc_ce1_axi_clk
= {
1757 .halt_check
= BRANCH_HALT_VOTED
,
1759 .enable_reg
= 0x1484,
1760 .enable_mask
= BIT(4),
1761 .hw
.init
= &(struct clk_init_data
){
1762 .name
= "gcc_ce1_axi_clk",
1763 .parent_names
= (const char *[]){
1764 "system_noc_clk_src",
1767 .ops
= &clk_branch2_ops
,
1772 static struct clk_branch gcc_ce1_clk
= {
1774 .halt_check
= BRANCH_HALT_VOTED
,
1776 .enable_reg
= 0x1484,
1777 .enable_mask
= BIT(5),
1778 .hw
.init
= &(struct clk_init_data
){
1779 .name
= "gcc_ce1_clk",
1780 .parent_names
= (const char *[]){
1784 .ops
= &clk_branch2_ops
,
1789 static struct clk_branch gcc_ce2_ahb_clk
= {
1791 .halt_check
= BRANCH_HALT_VOTED
,
1793 .enable_reg
= 0x1484,
1794 .enable_mask
= BIT(0),
1795 .hw
.init
= &(struct clk_init_data
){
1796 .name
= "gcc_ce2_ahb_clk",
1797 .parent_names
= (const char *[]){
1798 "config_noc_clk_src",
1801 .ops
= &clk_branch2_ops
,
1806 static struct clk_branch gcc_ce2_axi_clk
= {
1808 .halt_check
= BRANCH_HALT_VOTED
,
1810 .enable_reg
= 0x1484,
1811 .enable_mask
= BIT(1),
1812 .hw
.init
= &(struct clk_init_data
){
1813 .name
= "gcc_ce2_axi_clk",
1814 .parent_names
= (const char *[]){
1815 "system_noc_clk_src",
1818 .ops
= &clk_branch2_ops
,
1823 static struct clk_branch gcc_ce2_clk
= {
1825 .halt_check
= BRANCH_HALT_VOTED
,
1827 .enable_reg
= 0x1484,
1828 .enable_mask
= BIT(2),
1829 .hw
.init
= &(struct clk_init_data
){
1830 .name
= "gcc_ce2_clk",
1831 .parent_names
= (const char *[]){
1835 .flags
= CLK_SET_RATE_PARENT
,
1836 .ops
= &clk_branch2_ops
,
1841 static struct clk_branch gcc_gp1_clk
= {
1844 .enable_reg
= 0x1900,
1845 .enable_mask
= BIT(0),
1846 .hw
.init
= &(struct clk_init_data
){
1847 .name
= "gcc_gp1_clk",
1848 .parent_names
= (const char *[]){
1852 .flags
= CLK_SET_RATE_PARENT
,
1853 .ops
= &clk_branch2_ops
,
1858 static struct clk_branch gcc_gp2_clk
= {
1861 .enable_reg
= 0x1940,
1862 .enable_mask
= BIT(0),
1863 .hw
.init
= &(struct clk_init_data
){
1864 .name
= "gcc_gp2_clk",
1865 .parent_names
= (const char *[]){
1869 .flags
= CLK_SET_RATE_PARENT
,
1870 .ops
= &clk_branch2_ops
,
1875 static struct clk_branch gcc_gp3_clk
= {
1878 .enable_reg
= 0x1980,
1879 .enable_mask
= BIT(0),
1880 .hw
.init
= &(struct clk_init_data
){
1881 .name
= "gcc_gp3_clk",
1882 .parent_names
= (const char *[]){
1886 .flags
= CLK_SET_RATE_PARENT
,
1887 .ops
= &clk_branch2_ops
,
1892 static struct clk_branch gcc_lpass_q6_axi_clk
= {
1895 .enable_reg
= 0x11c0,
1896 .enable_mask
= BIT(0),
1897 .hw
.init
= &(struct clk_init_data
){
1898 .name
= "gcc_lpass_q6_axi_clk",
1899 .parent_names
= (const char *[]){
1900 "system_noc_clk_src",
1903 .ops
= &clk_branch2_ops
,
1908 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk
= {
1911 .enable_reg
= 0x024c,
1912 .enable_mask
= BIT(0),
1913 .hw
.init
= &(struct clk_init_data
){
1914 .name
= "gcc_mmss_noc_cfg_ahb_clk",
1915 .parent_names
= (const char *[]){
1916 "config_noc_clk_src",
1919 .ops
= &clk_branch2_ops
,
1920 .flags
= CLK_IGNORE_UNUSED
,
1925 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk
= {
1928 .enable_reg
= 0x0248,
1929 .enable_mask
= BIT(0),
1930 .hw
.init
= &(struct clk_init_data
){
1931 .name
= "gcc_ocmem_noc_cfg_ahb_clk",
1932 .parent_names
= (const char *[]){
1933 "config_noc_clk_src",
1936 .ops
= &clk_branch2_ops
,
1941 static struct clk_branch gcc_mss_cfg_ahb_clk
= {
1944 .enable_reg
= 0x0280,
1945 .enable_mask
= BIT(0),
1946 .hw
.init
= &(struct clk_init_data
){
1947 .name
= "gcc_mss_cfg_ahb_clk",
1948 .parent_names
= (const char *[]){
1949 "config_noc_clk_src",
1952 .ops
= &clk_branch2_ops
,
1957 static struct clk_branch gcc_mss_q6_bimc_axi_clk
= {
1960 .enable_reg
= 0x0284,
1961 .enable_mask
= BIT(0),
1962 .hw
.init
= &(struct clk_init_data
){
1963 .name
= "gcc_mss_q6_bimc_axi_clk",
1964 .flags
= CLK_IS_ROOT
,
1965 .ops
= &clk_branch2_ops
,
1970 static struct clk_branch gcc_pdm2_clk
= {
1973 .enable_reg
= 0x0ccc,
1974 .enable_mask
= BIT(0),
1975 .hw
.init
= &(struct clk_init_data
){
1976 .name
= "gcc_pdm2_clk",
1977 .parent_names
= (const char *[]){
1981 .flags
= CLK_SET_RATE_PARENT
,
1982 .ops
= &clk_branch2_ops
,
1987 static struct clk_branch gcc_pdm_ahb_clk
= {
1990 .enable_reg
= 0x0cc4,
1991 .enable_mask
= BIT(0),
1992 .hw
.init
= &(struct clk_init_data
){
1993 .name
= "gcc_pdm_ahb_clk",
1994 .parent_names
= (const char *[]){
1995 "periph_noc_clk_src",
1998 .ops
= &clk_branch2_ops
,
2003 static struct clk_branch gcc_prng_ahb_clk
= {
2005 .halt_check
= BRANCH_HALT_VOTED
,
2007 .enable_reg
= 0x1484,
2008 .enable_mask
= BIT(13),
2009 .hw
.init
= &(struct clk_init_data
){
2010 .name
= "gcc_prng_ahb_clk",
2011 .parent_names
= (const char *[]){
2012 "periph_noc_clk_src",
2015 .ops
= &clk_branch2_ops
,
2020 static struct clk_branch gcc_sdcc1_ahb_clk
= {
2023 .enable_reg
= 0x04c8,
2024 .enable_mask
= BIT(0),
2025 .hw
.init
= &(struct clk_init_data
){
2026 .name
= "gcc_sdcc1_ahb_clk",
2027 .parent_names
= (const char *[]){
2028 "periph_noc_clk_src",
2031 .ops
= &clk_branch2_ops
,
2036 static struct clk_branch gcc_sdcc1_apps_clk
= {
2039 .enable_reg
= 0x04c4,
2040 .enable_mask
= BIT(0),
2041 .hw
.init
= &(struct clk_init_data
){
2042 .name
= "gcc_sdcc1_apps_clk",
2043 .parent_names
= (const char *[]){
2044 "sdcc1_apps_clk_src",
2047 .flags
= CLK_SET_RATE_PARENT
,
2048 .ops
= &clk_branch2_ops
,
2053 static struct clk_branch gcc_sdcc1_cdccal_ff_clk
= {
2056 .enable_reg
= 0x04e8,
2057 .enable_mask
= BIT(0),
2058 .hw
.init
= &(struct clk_init_data
){
2059 .name
= "gcc_sdcc1_cdccal_ff_clk",
2060 .parent_names
= (const char *[]){
2064 .ops
= &clk_branch2_ops
,
2069 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk
= {
2072 .enable_reg
= 0x04e4,
2073 .enable_mask
= BIT(0),
2074 .hw
.init
= &(struct clk_init_data
){
2075 .name
= "gcc_sdcc1_cdccal_sleep_clk",
2076 .parent_names
= (const char *[]){
2080 .ops
= &clk_branch2_ops
,
2085 static struct clk_branch gcc_sdcc2_ahb_clk
= {
2088 .enable_reg
= 0x0508,
2089 .enable_mask
= BIT(0),
2090 .hw
.init
= &(struct clk_init_data
){
2091 .name
= "gcc_sdcc2_ahb_clk",
2092 .parent_names
= (const char *[]){
2093 "periph_noc_clk_src",
2096 .ops
= &clk_branch2_ops
,
2101 static struct clk_branch gcc_sdcc2_apps_clk
= {
2104 .enable_reg
= 0x0504,
2105 .enable_mask
= BIT(0),
2106 .hw
.init
= &(struct clk_init_data
){
2107 .name
= "gcc_sdcc2_apps_clk",
2108 .parent_names
= (const char *[]){
2109 "sdcc2_apps_clk_src",
2112 .flags
= CLK_SET_RATE_PARENT
,
2113 .ops
= &clk_branch2_ops
,
2118 static struct clk_branch gcc_sdcc3_ahb_clk
= {
2121 .enable_reg
= 0x0548,
2122 .enable_mask
= BIT(0),
2123 .hw
.init
= &(struct clk_init_data
){
2124 .name
= "gcc_sdcc3_ahb_clk",
2125 .parent_names
= (const char *[]){
2126 "periph_noc_clk_src",
2129 .ops
= &clk_branch2_ops
,
2134 static struct clk_branch gcc_sdcc3_apps_clk
= {
2137 .enable_reg
= 0x0544,
2138 .enable_mask
= BIT(0),
2139 .hw
.init
= &(struct clk_init_data
){
2140 .name
= "gcc_sdcc3_apps_clk",
2141 .parent_names
= (const char *[]){
2142 "sdcc3_apps_clk_src",
2145 .flags
= CLK_SET_RATE_PARENT
,
2146 .ops
= &clk_branch2_ops
,
2151 static struct clk_branch gcc_sdcc4_ahb_clk
= {
2154 .enable_reg
= 0x0588,
2155 .enable_mask
= BIT(0),
2156 .hw
.init
= &(struct clk_init_data
){
2157 .name
= "gcc_sdcc4_ahb_clk",
2158 .parent_names
= (const char *[]){
2159 "periph_noc_clk_src",
2162 .ops
= &clk_branch2_ops
,
2167 static struct clk_branch gcc_sdcc4_apps_clk
= {
2170 .enable_reg
= 0x0584,
2171 .enable_mask
= BIT(0),
2172 .hw
.init
= &(struct clk_init_data
){
2173 .name
= "gcc_sdcc4_apps_clk",
2174 .parent_names
= (const char *[]){
2175 "sdcc4_apps_clk_src",
2178 .flags
= CLK_SET_RATE_PARENT
,
2179 .ops
= &clk_branch2_ops
,
2184 static struct clk_branch gcc_sys_noc_usb3_axi_clk
= {
2187 .enable_reg
= 0x0108,
2188 .enable_mask
= BIT(0),
2189 .hw
.init
= &(struct clk_init_data
){
2190 .name
= "gcc_sys_noc_usb3_axi_clk",
2191 .parent_names
= (const char *[]){
2192 "usb30_master_clk_src",
2195 .flags
= CLK_SET_RATE_PARENT
,
2196 .ops
= &clk_branch2_ops
,
2201 static struct clk_branch gcc_tsif_ahb_clk
= {
2204 .enable_reg
= 0x0d84,
2205 .enable_mask
= BIT(0),
2206 .hw
.init
= &(struct clk_init_data
){
2207 .name
= "gcc_tsif_ahb_clk",
2208 .parent_names
= (const char *[]){
2209 "periph_noc_clk_src",
2212 .ops
= &clk_branch2_ops
,
2217 static struct clk_branch gcc_tsif_ref_clk
= {
2220 .enable_reg
= 0x0d88,
2221 .enable_mask
= BIT(0),
2222 .hw
.init
= &(struct clk_init_data
){
2223 .name
= "gcc_tsif_ref_clk",
2224 .parent_names
= (const char *[]){
2228 .flags
= CLK_SET_RATE_PARENT
,
2229 .ops
= &clk_branch2_ops
,
2234 static struct clk_branch gcc_usb2a_phy_sleep_clk
= {
2237 .enable_reg
= 0x04ac,
2238 .enable_mask
= BIT(0),
2239 .hw
.init
= &(struct clk_init_data
){
2240 .name
= "gcc_usb2a_phy_sleep_clk",
2241 .parent_names
= (const char *[]){
2245 .ops
= &clk_branch2_ops
,
2250 static struct clk_branch gcc_usb2b_phy_sleep_clk
= {
2253 .enable_reg
= 0x04b4,
2254 .enable_mask
= BIT(0),
2255 .hw
.init
= &(struct clk_init_data
){
2256 .name
= "gcc_usb2b_phy_sleep_clk",
2257 .parent_names
= (const char *[]){
2261 .ops
= &clk_branch2_ops
,
2266 static struct clk_branch gcc_usb30_master_clk
= {
2269 .enable_reg
= 0x03c8,
2270 .enable_mask
= BIT(0),
2271 .hw
.init
= &(struct clk_init_data
){
2272 .name
= "gcc_usb30_master_clk",
2273 .parent_names
= (const char *[]){
2274 "usb30_master_clk_src",
2277 .flags
= CLK_SET_RATE_PARENT
,
2278 .ops
= &clk_branch2_ops
,
2283 static struct clk_branch gcc_usb30_mock_utmi_clk
= {
2286 .enable_reg
= 0x03d0,
2287 .enable_mask
= BIT(0),
2288 .hw
.init
= &(struct clk_init_data
){
2289 .name
= "gcc_usb30_mock_utmi_clk",
2290 .parent_names
= (const char *[]){
2291 "usb30_mock_utmi_clk_src",
2294 .flags
= CLK_SET_RATE_PARENT
,
2295 .ops
= &clk_branch2_ops
,
2300 static struct clk_branch gcc_usb30_sleep_clk
= {
2303 .enable_reg
= 0x03cc,
2304 .enable_mask
= BIT(0),
2305 .hw
.init
= &(struct clk_init_data
){
2306 .name
= "gcc_usb30_sleep_clk",
2307 .parent_names
= (const char *[]){
2311 .ops
= &clk_branch2_ops
,
2316 static struct clk_branch gcc_usb_hs_ahb_clk
= {
2319 .enable_reg
= 0x0488,
2320 .enable_mask
= BIT(0),
2321 .hw
.init
= &(struct clk_init_data
){
2322 .name
= "gcc_usb_hs_ahb_clk",
2323 .parent_names
= (const char *[]){
2324 "periph_noc_clk_src",
2327 .ops
= &clk_branch2_ops
,
2332 static struct clk_branch gcc_usb_hs_system_clk
= {
2335 .enable_reg
= 0x0484,
2336 .enable_mask
= BIT(0),
2337 .hw
.init
= &(struct clk_init_data
){
2338 .name
= "gcc_usb_hs_system_clk",
2339 .parent_names
= (const char *[]){
2340 "usb_hs_system_clk_src",
2343 .flags
= CLK_SET_RATE_PARENT
,
2344 .ops
= &clk_branch2_ops
,
2349 static struct clk_branch gcc_usb_hsic_ahb_clk
= {
2352 .enable_reg
= 0x0408,
2353 .enable_mask
= BIT(0),
2354 .hw
.init
= &(struct clk_init_data
){
2355 .name
= "gcc_usb_hsic_ahb_clk",
2356 .parent_names
= (const char *[]){
2357 "periph_noc_clk_src",
2360 .ops
= &clk_branch2_ops
,
2365 static struct clk_branch gcc_usb_hsic_clk
= {
2368 .enable_reg
= 0x0410,
2369 .enable_mask
= BIT(0),
2370 .hw
.init
= &(struct clk_init_data
){
2371 .name
= "gcc_usb_hsic_clk",
2372 .parent_names
= (const char *[]){
2376 .flags
= CLK_SET_RATE_PARENT
,
2377 .ops
= &clk_branch2_ops
,
2382 static struct clk_branch gcc_usb_hsic_io_cal_clk
= {
2385 .enable_reg
= 0x0414,
2386 .enable_mask
= BIT(0),
2387 .hw
.init
= &(struct clk_init_data
){
2388 .name
= "gcc_usb_hsic_io_cal_clk",
2389 .parent_names
= (const char *[]){
2390 "usb_hsic_io_cal_clk_src",
2393 .flags
= CLK_SET_RATE_PARENT
,
2394 .ops
= &clk_branch2_ops
,
2399 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk
= {
2402 .enable_reg
= 0x0418,
2403 .enable_mask
= BIT(0),
2404 .hw
.init
= &(struct clk_init_data
){
2405 .name
= "gcc_usb_hsic_io_cal_sleep_clk",
2406 .parent_names
= (const char *[]){
2410 .ops
= &clk_branch2_ops
,
2415 static struct clk_branch gcc_usb_hsic_system_clk
= {
2418 .enable_reg
= 0x040c,
2419 .enable_mask
= BIT(0),
2420 .hw
.init
= &(struct clk_init_data
){
2421 .name
= "gcc_usb_hsic_system_clk",
2422 .parent_names
= (const char *[]){
2423 "usb_hsic_system_clk_src",
2426 .flags
= CLK_SET_RATE_PARENT
,
2427 .ops
= &clk_branch2_ops
,
2432 static struct clk_regmap
*gcc_msm8974_clocks
[] = {
2433 [GPLL0
] = &gpll0
.clkr
,
2434 [GPLL0_VOTE
] = &gpll0_vote
,
2435 [CONFIG_NOC_CLK_SRC
] = &config_noc_clk_src
.clkr
,
2436 [PERIPH_NOC_CLK_SRC
] = &periph_noc_clk_src
.clkr
,
2437 [SYSTEM_NOC_CLK_SRC
] = &system_noc_clk_src
.clkr
,
2438 [GPLL1
] = &gpll1
.clkr
,
2439 [GPLL1_VOTE
] = &gpll1_vote
,
2440 [USB30_MASTER_CLK_SRC
] = &usb30_master_clk_src
.clkr
,
2441 [BLSP1_QUP1_I2C_APPS_CLK_SRC
] = &blsp1_qup1_i2c_apps_clk_src
.clkr
,
2442 [BLSP1_QUP1_SPI_APPS_CLK_SRC
] = &blsp1_qup1_spi_apps_clk_src
.clkr
,
2443 [BLSP1_QUP2_I2C_APPS_CLK_SRC
] = &blsp1_qup2_i2c_apps_clk_src
.clkr
,
2444 [BLSP1_QUP2_SPI_APPS_CLK_SRC
] = &blsp1_qup2_spi_apps_clk_src
.clkr
,
2445 [BLSP1_QUP3_I2C_APPS_CLK_SRC
] = &blsp1_qup3_i2c_apps_clk_src
.clkr
,
2446 [BLSP1_QUP3_SPI_APPS_CLK_SRC
] = &blsp1_qup3_spi_apps_clk_src
.clkr
,
2447 [BLSP1_QUP4_I2C_APPS_CLK_SRC
] = &blsp1_qup4_i2c_apps_clk_src
.clkr
,
2448 [BLSP1_QUP4_SPI_APPS_CLK_SRC
] = &blsp1_qup4_spi_apps_clk_src
.clkr
,
2449 [BLSP1_QUP5_I2C_APPS_CLK_SRC
] = &blsp1_qup5_i2c_apps_clk_src
.clkr
,
2450 [BLSP1_QUP5_SPI_APPS_CLK_SRC
] = &blsp1_qup5_spi_apps_clk_src
.clkr
,
2451 [BLSP1_QUP6_I2C_APPS_CLK_SRC
] = &blsp1_qup6_i2c_apps_clk_src
.clkr
,
2452 [BLSP1_QUP6_SPI_APPS_CLK_SRC
] = &blsp1_qup6_spi_apps_clk_src
.clkr
,
2453 [BLSP1_UART1_APPS_CLK_SRC
] = &blsp1_uart1_apps_clk_src
.clkr
,
2454 [BLSP1_UART2_APPS_CLK_SRC
] = &blsp1_uart2_apps_clk_src
.clkr
,
2455 [BLSP1_UART3_APPS_CLK_SRC
] = &blsp1_uart3_apps_clk_src
.clkr
,
2456 [BLSP1_UART4_APPS_CLK_SRC
] = &blsp1_uart4_apps_clk_src
.clkr
,
2457 [BLSP1_UART5_APPS_CLK_SRC
] = &blsp1_uart5_apps_clk_src
.clkr
,
2458 [BLSP1_UART6_APPS_CLK_SRC
] = &blsp1_uart6_apps_clk_src
.clkr
,
2459 [BLSP2_QUP1_I2C_APPS_CLK_SRC
] = &blsp2_qup1_i2c_apps_clk_src
.clkr
,
2460 [BLSP2_QUP1_SPI_APPS_CLK_SRC
] = &blsp2_qup1_spi_apps_clk_src
.clkr
,
2461 [BLSP2_QUP2_I2C_APPS_CLK_SRC
] = &blsp2_qup2_i2c_apps_clk_src
.clkr
,
2462 [BLSP2_QUP2_SPI_APPS_CLK_SRC
] = &blsp2_qup2_spi_apps_clk_src
.clkr
,
2463 [BLSP2_QUP3_I2C_APPS_CLK_SRC
] = &blsp2_qup3_i2c_apps_clk_src
.clkr
,
2464 [BLSP2_QUP3_SPI_APPS_CLK_SRC
] = &blsp2_qup3_spi_apps_clk_src
.clkr
,
2465 [BLSP2_QUP4_I2C_APPS_CLK_SRC
] = &blsp2_qup4_i2c_apps_clk_src
.clkr
,
2466 [BLSP2_QUP4_SPI_APPS_CLK_SRC
] = &blsp2_qup4_spi_apps_clk_src
.clkr
,
2467 [BLSP2_QUP5_I2C_APPS_CLK_SRC
] = &blsp2_qup5_i2c_apps_clk_src
.clkr
,
2468 [BLSP2_QUP5_SPI_APPS_CLK_SRC
] = &blsp2_qup5_spi_apps_clk_src
.clkr
,
2469 [BLSP2_QUP6_I2C_APPS_CLK_SRC
] = &blsp2_qup6_i2c_apps_clk_src
.clkr
,
2470 [BLSP2_QUP6_SPI_APPS_CLK_SRC
] = &blsp2_qup6_spi_apps_clk_src
.clkr
,
2471 [BLSP2_UART1_APPS_CLK_SRC
] = &blsp2_uart1_apps_clk_src
.clkr
,
2472 [BLSP2_UART2_APPS_CLK_SRC
] = &blsp2_uart2_apps_clk_src
.clkr
,
2473 [BLSP2_UART3_APPS_CLK_SRC
] = &blsp2_uart3_apps_clk_src
.clkr
,
2474 [BLSP2_UART4_APPS_CLK_SRC
] = &blsp2_uart4_apps_clk_src
.clkr
,
2475 [BLSP2_UART5_APPS_CLK_SRC
] = &blsp2_uart5_apps_clk_src
.clkr
,
2476 [BLSP2_UART6_APPS_CLK_SRC
] = &blsp2_uart6_apps_clk_src
.clkr
,
2477 [CE1_CLK_SRC
] = &ce1_clk_src
.clkr
,
2478 [CE2_CLK_SRC
] = &ce2_clk_src
.clkr
,
2479 [GP1_CLK_SRC
] = &gp1_clk_src
.clkr
,
2480 [GP2_CLK_SRC
] = &gp2_clk_src
.clkr
,
2481 [GP3_CLK_SRC
] = &gp3_clk_src
.clkr
,
2482 [PDM2_CLK_SRC
] = &pdm2_clk_src
.clkr
,
2483 [SDCC1_APPS_CLK_SRC
] = &sdcc1_apps_clk_src
.clkr
,
2484 [SDCC2_APPS_CLK_SRC
] = &sdcc2_apps_clk_src
.clkr
,
2485 [SDCC3_APPS_CLK_SRC
] = &sdcc3_apps_clk_src
.clkr
,
2486 [SDCC4_APPS_CLK_SRC
] = &sdcc4_apps_clk_src
.clkr
,
2487 [TSIF_REF_CLK_SRC
] = &tsif_ref_clk_src
.clkr
,
2488 [USB30_MOCK_UTMI_CLK_SRC
] = &usb30_mock_utmi_clk_src
.clkr
,
2489 [USB_HS_SYSTEM_CLK_SRC
] = &usb_hs_system_clk_src
.clkr
,
2490 [USB_HSIC_CLK_SRC
] = &usb_hsic_clk_src
.clkr
,
2491 [USB_HSIC_IO_CAL_CLK_SRC
] = &usb_hsic_io_cal_clk_src
.clkr
,
2492 [USB_HSIC_SYSTEM_CLK_SRC
] = &usb_hsic_system_clk_src
.clkr
,
2493 [GCC_BAM_DMA_AHB_CLK
] = &gcc_bam_dma_ahb_clk
.clkr
,
2494 [GCC_BLSP1_AHB_CLK
] = &gcc_blsp1_ahb_clk
.clkr
,
2495 [GCC_BLSP1_QUP1_I2C_APPS_CLK
] = &gcc_blsp1_qup1_i2c_apps_clk
.clkr
,
2496 [GCC_BLSP1_QUP1_SPI_APPS_CLK
] = &gcc_blsp1_qup1_spi_apps_clk
.clkr
,
2497 [GCC_BLSP1_QUP2_I2C_APPS_CLK
] = &gcc_blsp1_qup2_i2c_apps_clk
.clkr
,
2498 [GCC_BLSP1_QUP2_SPI_APPS_CLK
] = &gcc_blsp1_qup2_spi_apps_clk
.clkr
,
2499 [GCC_BLSP1_QUP3_I2C_APPS_CLK
] = &gcc_blsp1_qup3_i2c_apps_clk
.clkr
,
2500 [GCC_BLSP1_QUP3_SPI_APPS_CLK
] = &gcc_blsp1_qup3_spi_apps_clk
.clkr
,
2501 [GCC_BLSP1_QUP4_I2C_APPS_CLK
] = &gcc_blsp1_qup4_i2c_apps_clk
.clkr
,
2502 [GCC_BLSP1_QUP4_SPI_APPS_CLK
] = &gcc_blsp1_qup4_spi_apps_clk
.clkr
,
2503 [GCC_BLSP1_QUP5_I2C_APPS_CLK
] = &gcc_blsp1_qup5_i2c_apps_clk
.clkr
,
2504 [GCC_BLSP1_QUP5_SPI_APPS_CLK
] = &gcc_blsp1_qup5_spi_apps_clk
.clkr
,
2505 [GCC_BLSP1_QUP6_I2C_APPS_CLK
] = &gcc_blsp1_qup6_i2c_apps_clk
.clkr
,
2506 [GCC_BLSP1_QUP6_SPI_APPS_CLK
] = &gcc_blsp1_qup6_spi_apps_clk
.clkr
,
2507 [GCC_BLSP1_UART1_APPS_CLK
] = &gcc_blsp1_uart1_apps_clk
.clkr
,
2508 [GCC_BLSP1_UART2_APPS_CLK
] = &gcc_blsp1_uart2_apps_clk
.clkr
,
2509 [GCC_BLSP1_UART3_APPS_CLK
] = &gcc_blsp1_uart3_apps_clk
.clkr
,
2510 [GCC_BLSP1_UART4_APPS_CLK
] = &gcc_blsp1_uart4_apps_clk
.clkr
,
2511 [GCC_BLSP1_UART5_APPS_CLK
] = &gcc_blsp1_uart5_apps_clk
.clkr
,
2512 [GCC_BLSP1_UART6_APPS_CLK
] = &gcc_blsp1_uart6_apps_clk
.clkr
,
2513 [GCC_BLSP2_AHB_CLK
] = &gcc_blsp2_ahb_clk
.clkr
,
2514 [GCC_BLSP2_QUP1_I2C_APPS_CLK
] = &gcc_blsp2_qup1_i2c_apps_clk
.clkr
,
2515 [GCC_BLSP2_QUP1_SPI_APPS_CLK
] = &gcc_blsp2_qup1_spi_apps_clk
.clkr
,
2516 [GCC_BLSP2_QUP2_I2C_APPS_CLK
] = &gcc_blsp2_qup2_i2c_apps_clk
.clkr
,
2517 [GCC_BLSP2_QUP2_SPI_APPS_CLK
] = &gcc_blsp2_qup2_spi_apps_clk
.clkr
,
2518 [GCC_BLSP2_QUP3_I2C_APPS_CLK
] = &gcc_blsp2_qup3_i2c_apps_clk
.clkr
,
2519 [GCC_BLSP2_QUP3_SPI_APPS_CLK
] = &gcc_blsp2_qup3_spi_apps_clk
.clkr
,
2520 [GCC_BLSP2_QUP4_I2C_APPS_CLK
] = &gcc_blsp2_qup4_i2c_apps_clk
.clkr
,
2521 [GCC_BLSP2_QUP4_SPI_APPS_CLK
] = &gcc_blsp2_qup4_spi_apps_clk
.clkr
,
2522 [GCC_BLSP2_QUP5_I2C_APPS_CLK
] = &gcc_blsp2_qup5_i2c_apps_clk
.clkr
,
2523 [GCC_BLSP2_QUP5_SPI_APPS_CLK
] = &gcc_blsp2_qup5_spi_apps_clk
.clkr
,
2524 [GCC_BLSP2_QUP6_I2C_APPS_CLK
] = &gcc_blsp2_qup6_i2c_apps_clk
.clkr
,
2525 [GCC_BLSP2_QUP6_SPI_APPS_CLK
] = &gcc_blsp2_qup6_spi_apps_clk
.clkr
,
2526 [GCC_BLSP2_UART1_APPS_CLK
] = &gcc_blsp2_uart1_apps_clk
.clkr
,
2527 [GCC_BLSP2_UART2_APPS_CLK
] = &gcc_blsp2_uart2_apps_clk
.clkr
,
2528 [GCC_BLSP2_UART3_APPS_CLK
] = &gcc_blsp2_uart3_apps_clk
.clkr
,
2529 [GCC_BLSP2_UART4_APPS_CLK
] = &gcc_blsp2_uart4_apps_clk
.clkr
,
2530 [GCC_BLSP2_UART5_APPS_CLK
] = &gcc_blsp2_uart5_apps_clk
.clkr
,
2531 [GCC_BLSP2_UART6_APPS_CLK
] = &gcc_blsp2_uart6_apps_clk
.clkr
,
2532 [GCC_BOOT_ROM_AHB_CLK
] = &gcc_boot_rom_ahb_clk
.clkr
,
2533 [GCC_CE1_AHB_CLK
] = &gcc_ce1_ahb_clk
.clkr
,
2534 [GCC_CE1_AXI_CLK
] = &gcc_ce1_axi_clk
.clkr
,
2535 [GCC_CE1_CLK
] = &gcc_ce1_clk
.clkr
,
2536 [GCC_CE2_AHB_CLK
] = &gcc_ce2_ahb_clk
.clkr
,
2537 [GCC_CE2_AXI_CLK
] = &gcc_ce2_axi_clk
.clkr
,
2538 [GCC_CE2_CLK
] = &gcc_ce2_clk
.clkr
,
2539 [GCC_GP1_CLK
] = &gcc_gp1_clk
.clkr
,
2540 [GCC_GP2_CLK
] = &gcc_gp2_clk
.clkr
,
2541 [GCC_GP3_CLK
] = &gcc_gp3_clk
.clkr
,
2542 [GCC_LPASS_Q6_AXI_CLK
] = &gcc_lpass_q6_axi_clk
.clkr
,
2543 [GCC_MMSS_NOC_CFG_AHB_CLK
] = &gcc_mmss_noc_cfg_ahb_clk
.clkr
,
2544 [GCC_OCMEM_NOC_CFG_AHB_CLK
] = &gcc_ocmem_noc_cfg_ahb_clk
.clkr
,
2545 [GCC_MSS_CFG_AHB_CLK
] = &gcc_mss_cfg_ahb_clk
.clkr
,
2546 [GCC_MSS_Q6_BIMC_AXI_CLK
] = &gcc_mss_q6_bimc_axi_clk
.clkr
,
2547 [GCC_PDM2_CLK
] = &gcc_pdm2_clk
.clkr
,
2548 [GCC_PDM_AHB_CLK
] = &gcc_pdm_ahb_clk
.clkr
,
2549 [GCC_PRNG_AHB_CLK
] = &gcc_prng_ahb_clk
.clkr
,
2550 [GCC_SDCC1_AHB_CLK
] = &gcc_sdcc1_ahb_clk
.clkr
,
2551 [GCC_SDCC1_APPS_CLK
] = &gcc_sdcc1_apps_clk
.clkr
,
2552 [GCC_SDCC2_AHB_CLK
] = &gcc_sdcc2_ahb_clk
.clkr
,
2553 [GCC_SDCC2_APPS_CLK
] = &gcc_sdcc2_apps_clk
.clkr
,
2554 [GCC_SDCC3_AHB_CLK
] = &gcc_sdcc3_ahb_clk
.clkr
,
2555 [GCC_SDCC3_APPS_CLK
] = &gcc_sdcc3_apps_clk
.clkr
,
2556 [GCC_SDCC4_AHB_CLK
] = &gcc_sdcc4_ahb_clk
.clkr
,
2557 [GCC_SDCC4_APPS_CLK
] = &gcc_sdcc4_apps_clk
.clkr
,
2558 [GCC_SYS_NOC_USB3_AXI_CLK
] = &gcc_sys_noc_usb3_axi_clk
.clkr
,
2559 [GCC_TSIF_AHB_CLK
] = &gcc_tsif_ahb_clk
.clkr
,
2560 [GCC_TSIF_REF_CLK
] = &gcc_tsif_ref_clk
.clkr
,
2561 [GCC_USB2A_PHY_SLEEP_CLK
] = &gcc_usb2a_phy_sleep_clk
.clkr
,
2562 [GCC_USB2B_PHY_SLEEP_CLK
] = &gcc_usb2b_phy_sleep_clk
.clkr
,
2563 [GCC_USB30_MASTER_CLK
] = &gcc_usb30_master_clk
.clkr
,
2564 [GCC_USB30_MOCK_UTMI_CLK
] = &gcc_usb30_mock_utmi_clk
.clkr
,
2565 [GCC_USB30_SLEEP_CLK
] = &gcc_usb30_sleep_clk
.clkr
,
2566 [GCC_USB_HS_AHB_CLK
] = &gcc_usb_hs_ahb_clk
.clkr
,
2567 [GCC_USB_HS_SYSTEM_CLK
] = &gcc_usb_hs_system_clk
.clkr
,
2568 [GCC_USB_HSIC_AHB_CLK
] = &gcc_usb_hsic_ahb_clk
.clkr
,
2569 [GCC_USB_HSIC_CLK
] = &gcc_usb_hsic_clk
.clkr
,
2570 [GCC_USB_HSIC_IO_CAL_CLK
] = &gcc_usb_hsic_io_cal_clk
.clkr
,
2571 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK
] = &gcc_usb_hsic_io_cal_sleep_clk
.clkr
,
2572 [GCC_USB_HSIC_SYSTEM_CLK
] = &gcc_usb_hsic_system_clk
.clkr
,
2573 [GCC_MMSS_GPLL0_CLK_SRC
] = &gcc_mmss_gpll0_clk_src
,
2575 [GPLL4_VOTE
] = NULL
,
2576 [GCC_SDCC1_CDCCAL_SLEEP_CLK
] = NULL
,
2577 [GCC_SDCC1_CDCCAL_FF_CLK
] = NULL
,
2580 static const struct qcom_reset_map gcc_msm8974_resets
[] = {
2581 [GCC_SYSTEM_NOC_BCR
] = { 0x0100 },
2582 [GCC_CONFIG_NOC_BCR
] = { 0x0140 },
2583 [GCC_PERIPH_NOC_BCR
] = { 0x0180 },
2584 [GCC_IMEM_BCR
] = { 0x0200 },
2585 [GCC_MMSS_BCR
] = { 0x0240 },
2586 [GCC_QDSS_BCR
] = { 0x0300 },
2587 [GCC_USB_30_BCR
] = { 0x03c0 },
2588 [GCC_USB3_PHY_BCR
] = { 0x03fc },
2589 [GCC_USB_HS_HSIC_BCR
] = { 0x0400 },
2590 [GCC_USB_HS_BCR
] = { 0x0480 },
2591 [GCC_USB2A_PHY_BCR
] = { 0x04a8 },
2592 [GCC_USB2B_PHY_BCR
] = { 0x04b0 },
2593 [GCC_SDCC1_BCR
] = { 0x04c0 },
2594 [GCC_SDCC2_BCR
] = { 0x0500 },
2595 [GCC_SDCC3_BCR
] = { 0x0540 },
2596 [GCC_SDCC4_BCR
] = { 0x0580 },
2597 [GCC_BLSP1_BCR
] = { 0x05c0 },
2598 [GCC_BLSP1_QUP1_BCR
] = { 0x0640 },
2599 [GCC_BLSP1_UART1_BCR
] = { 0x0680 },
2600 [GCC_BLSP1_QUP2_BCR
] = { 0x06c0 },
2601 [GCC_BLSP1_UART2_BCR
] = { 0x0700 },
2602 [GCC_BLSP1_QUP3_BCR
] = { 0x0740 },
2603 [GCC_BLSP1_UART3_BCR
] = { 0x0780 },
2604 [GCC_BLSP1_QUP4_BCR
] = { 0x07c0 },
2605 [GCC_BLSP1_UART4_BCR
] = { 0x0800 },
2606 [GCC_BLSP1_QUP5_BCR
] = { 0x0840 },
2607 [GCC_BLSP1_UART5_BCR
] = { 0x0880 },
2608 [GCC_BLSP1_QUP6_BCR
] = { 0x08c0 },
2609 [GCC_BLSP1_UART6_BCR
] = { 0x0900 },
2610 [GCC_BLSP2_BCR
] = { 0x0940 },
2611 [GCC_BLSP2_QUP1_BCR
] = { 0x0980 },
2612 [GCC_BLSP2_UART1_BCR
] = { 0x09c0 },
2613 [GCC_BLSP2_QUP2_BCR
] = { 0x0a00 },
2614 [GCC_BLSP2_UART2_BCR
] = { 0x0a40 },
2615 [GCC_BLSP2_QUP3_BCR
] = { 0x0a80 },
2616 [GCC_BLSP2_UART3_BCR
] = { 0x0ac0 },
2617 [GCC_BLSP2_QUP4_BCR
] = { 0x0b00 },
2618 [GCC_BLSP2_UART4_BCR
] = { 0x0b40 },
2619 [GCC_BLSP2_QUP5_BCR
] = { 0x0b80 },
2620 [GCC_BLSP2_UART5_BCR
] = { 0x0bc0 },
2621 [GCC_BLSP2_QUP6_BCR
] = { 0x0c00 },
2622 [GCC_BLSP2_UART6_BCR
] = { 0x0c40 },
2623 [GCC_PDM_BCR
] = { 0x0cc0 },
2624 [GCC_BAM_DMA_BCR
] = { 0x0d40 },
2625 [GCC_TSIF_BCR
] = { 0x0d80 },
2626 [GCC_TCSR_BCR
] = { 0x0dc0 },
2627 [GCC_BOOT_ROM_BCR
] = { 0x0e00 },
2628 [GCC_MSG_RAM_BCR
] = { 0x0e40 },
2629 [GCC_TLMM_BCR
] = { 0x0e80 },
2630 [GCC_MPM_BCR
] = { 0x0ec0 },
2631 [GCC_SEC_CTRL_BCR
] = { 0x0f40 },
2632 [GCC_SPMI_BCR
] = { 0x0fc0 },
2633 [GCC_SPDM_BCR
] = { 0x1000 },
2634 [GCC_CE1_BCR
] = { 0x1040 },
2635 [GCC_CE2_BCR
] = { 0x1080 },
2636 [GCC_BIMC_BCR
] = { 0x1100 },
2637 [GCC_MPM_NON_AHB_RESET
] = { 0x0ec4, 2 },
2638 [GCC_MPM_AHB_RESET
] = { 0x0ec4, 1 },
2639 [GCC_SNOC_BUS_TIMEOUT0_BCR
] = { 0x1240 },
2640 [GCC_SNOC_BUS_TIMEOUT2_BCR
] = { 0x1248 },
2641 [GCC_PNOC_BUS_TIMEOUT0_BCR
] = { 0x1280 },
2642 [GCC_PNOC_BUS_TIMEOUT1_BCR
] = { 0x1288 },
2643 [GCC_PNOC_BUS_TIMEOUT2_BCR
] = { 0x1290 },
2644 [GCC_PNOC_BUS_TIMEOUT3_BCR
] = { 0x1298 },
2645 [GCC_PNOC_BUS_TIMEOUT4_BCR
] = { 0x12a0 },
2646 [GCC_CNOC_BUS_TIMEOUT0_BCR
] = { 0x12c0 },
2647 [GCC_CNOC_BUS_TIMEOUT1_BCR
] = { 0x12c8 },
2648 [GCC_CNOC_BUS_TIMEOUT2_BCR
] = { 0x12d0 },
2649 [GCC_CNOC_BUS_TIMEOUT3_BCR
] = { 0x12d8 },
2650 [GCC_CNOC_BUS_TIMEOUT4_BCR
] = { 0x12e0 },
2651 [GCC_CNOC_BUS_TIMEOUT5_BCR
] = { 0x12e8 },
2652 [GCC_CNOC_BUS_TIMEOUT6_BCR
] = { 0x12f0 },
2653 [GCC_DEHR_BCR
] = { 0x1300 },
2654 [GCC_RBCPR_BCR
] = { 0x1380 },
2655 [GCC_MSS_RESTART
] = { 0x1680 },
2656 [GCC_LPASS_RESTART
] = { 0x16c0 },
2657 [GCC_WCSS_RESTART
] = { 0x1700 },
2658 [GCC_VENUS_RESTART
] = { 0x1740 },
2661 static const struct regmap_config gcc_msm8974_regmap_config
= {
2665 .max_register
= 0x1fc0,
2669 static const struct qcom_cc_desc gcc_msm8974_desc
= {
2670 .config
= &gcc_msm8974_regmap_config
,
2671 .clks
= gcc_msm8974_clocks
,
2672 .num_clks
= ARRAY_SIZE(gcc_msm8974_clocks
),
2673 .resets
= gcc_msm8974_resets
,
2674 .num_resets
= ARRAY_SIZE(gcc_msm8974_resets
),
2677 static const struct of_device_id gcc_msm8974_match_table
[] = {
2678 { .compatible
= "qcom,gcc-msm8974" },
2679 { .compatible
= "qcom,gcc-msm8974pro" , .data
= (void *)1UL },
2680 { .compatible
= "qcom,gcc-msm8974pro-ac", .data
= (void *)1UL },
2683 MODULE_DEVICE_TABLE(of
, gcc_msm8974_match_table
);
2685 static void msm8974_pro_clock_override(void)
2687 sdcc1_apps_clk_src_init
.parent_names
= gcc_xo_gpll0_gpll4
;
2688 sdcc1_apps_clk_src_init
.num_parents
= 3;
2689 sdcc1_apps_clk_src
.freq_tbl
= ftbl_gcc_sdcc1_apps_clk_pro
;
2690 sdcc1_apps_clk_src
.parent_map
= gcc_xo_gpll0_gpll4_map
;
2692 gcc_msm8974_clocks
[GPLL4
] = &gpll4
.clkr
;
2693 gcc_msm8974_clocks
[GPLL4_VOTE
] = &gpll4_vote
;
2694 gcc_msm8974_clocks
[GCC_SDCC1_CDCCAL_SLEEP_CLK
] =
2695 &gcc_sdcc1_cdccal_sleep_clk
.clkr
;
2696 gcc_msm8974_clocks
[GCC_SDCC1_CDCCAL_FF_CLK
] =
2697 &gcc_sdcc1_cdccal_ff_clk
.clkr
;
2700 static int gcc_msm8974_probe(struct platform_device
*pdev
)
2703 struct device
*dev
= &pdev
->dev
;
2705 const struct of_device_id
*id
;
2707 id
= of_match_device(gcc_msm8974_match_table
, dev
);
2713 msm8974_pro_clock_override();
2715 /* Temporary until RPM clocks supported */
2716 clk
= clk_register_fixed_rate(dev
, "xo", NULL
, CLK_IS_ROOT
, 19200000);
2718 return PTR_ERR(clk
);
2720 /* Should move to DT node? */
2721 clk
= clk_register_fixed_rate(dev
, "sleep_clk_src", NULL
,
2722 CLK_IS_ROOT
, 32768);
2724 return PTR_ERR(clk
);
2726 return qcom_cc_probe(pdev
, &gcc_msm8974_desc
);
2729 static int gcc_msm8974_remove(struct platform_device
*pdev
)
2731 qcom_cc_remove(pdev
);
2735 static struct platform_driver gcc_msm8974_driver
= {
2736 .probe
= gcc_msm8974_probe
,
2737 .remove
= gcc_msm8974_remove
,
2739 .name
= "gcc-msm8974",
2740 .owner
= THIS_MODULE
,
2741 .of_match_table
= gcc_msm8974_match_table
,
2745 static int __init
gcc_msm8974_init(void)
2747 return platform_driver_register(&gcc_msm8974_driver
);
2749 core_initcall(gcc_msm8974_init
);
2751 static void __exit
gcc_msm8974_exit(void)
2753 platform_driver_unregister(&gcc_msm8974_driver
);
2755 module_exit(gcc_msm8974_exit
);
2757 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2758 MODULE_LICENSE("GPL v2");
2759 MODULE_ALIAS("platform:gcc-msm8974");