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staging: rtl8192e: Fix LONG_LINE warnings
[linux-2.6/btrfs-unstable.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_phy.c
blob0765c97e06a87734474ae148a3e1a106e69d4537
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12 *
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
15 *
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19
20 #include "rtl_core.h"
21 #include "r8192E_hw.h"
22 #include "r8192E_phyreg.h"
23 #include "r8190P_rtl8256.h"
24 #include "r8192E_phy.h"
25 #include "rtl_dm.h"
26
27 #include "r8192E_hwimg.h"
28
29 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
30 0,
31 0x085c,
32 0x08dc,
33 0x095c,
34 0x09dc,
35 0x0a5c,
36 0x0adc,
37 0x0b5c,
38 0x0bdc,
39 0x0c5c,
40 0x0cdc,
41 0x0d5c,
42 0x0ddc,
43 0x0e5c,
44 0x0f72,
45 };
46
47 /*************************Define local function prototype**********************/
48
49 static u32 phy_FwRFSerialRead(struct net_device *dev,
50 enum rf90_radio_path eRFPath,
51 u32 Offset);
52 static void phy_FwRFSerialWrite(struct net_device *dev,
53 enum rf90_radio_path eRFPath,
54 u32 Offset, u32 Data);
55
56 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
57 {
58 u32 i;
59
60 for (i = 0; i <= 31; i++) {
61 if (((dwBitMask >> i) & 0x1) == 1)
62 break;
63 }
64 return i;
65 }
66
67 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
68 {
69 u8 ret = 1;
70 struct r8192_priv *priv = rtllib_priv(dev);
71
72 if (priv->rf_type == RF_2T4R)
73 ret = 0;
74 else if (priv->rf_type == RF_1T2R) {
75 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
76 ret = 1;
77 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
78 ret = 0;
79 }
80 return ret;
81 }
82
83 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
84 u32 dwData)
85 {
86
87 u32 OriginalValue, BitShift, NewValue;
88
89 if (dwBitMask != bMaskDWord) {
90 OriginalValue = read_nic_dword(dev, dwRegAddr);
91 BitShift = rtl8192_CalculateBitShift(dwBitMask);
92 NewValue = (((OriginalValue) & (~dwBitMask)) |
93 (dwData << BitShift));
94 write_nic_dword(dev, dwRegAddr, NewValue);
95 } else
96 write_nic_dword(dev, dwRegAddr, dwData);
97 }
98
99 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
100 {
101 u32 Ret = 0, OriginalValue, BitShift;
102
103 OriginalValue = read_nic_dword(dev, dwRegAddr);
104 BitShift = rtl8192_CalculateBitShift(dwBitMask);
105 Ret = (OriginalValue & dwBitMask) >> BitShift;
106
107 return Ret;
108 }
109 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
110 enum rf90_radio_path eRFPath, u32 Offset)
111 {
112 struct r8192_priv *priv = rtllib_priv(dev);
113 u32 ret = 0;
114 u32 NewOffset = 0;
115 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
116
117 Offset &= 0x3f;
118
119 if (priv->rf_chip == RF_8256) {
120 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
121 if (Offset >= 31) {
122 priv->RfReg0Value[eRFPath] |= 0x140;
123 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
124 bMaskDWord,
125 (priv->RfReg0Value[eRFPath]<<16));
126 NewOffset = Offset - 30;
127 } else if (Offset >= 16) {
128 priv->RfReg0Value[eRFPath] |= 0x100;
129 priv->RfReg0Value[eRFPath] &= (~0x40);
130 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
131 bMaskDWord,
132 (priv->RfReg0Value[eRFPath]<<16));
133
134 NewOffset = Offset - 15;
135 } else
136 NewOffset = Offset;
137 } else {
138 RT_TRACE((COMP_PHY|COMP_ERR),
139 "check RF type here, need to be 8256\n");
140 NewOffset = Offset;
141 }
142 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
143 NewOffset);
144 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
146
147 mdelay(1);
148
149 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
150 bLSSIReadBackData);
151
152 if (priv->rf_chip == RF_8256) {
153 priv->RfReg0Value[eRFPath] &= 0xebf;
154
155 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
156 (priv->RfReg0Value[eRFPath] << 16));
157
158 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
159 }
160
161
162 return ret;
163
164 }
165
166 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
167 enum rf90_radio_path eRFPath, u32 Offset,
168 u32 Data)
169 {
170 struct r8192_priv *priv = rtllib_priv(dev);
171 u32 DataAndAddr = 0, NewOffset = 0;
172 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
173
174 Offset &= 0x3f;
175 if (priv->rf_chip == RF_8256) {
176 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
177
178 if (Offset >= 31) {
179 priv->RfReg0Value[eRFPath] |= 0x140;
180 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
181 bMaskDWord,
182 (priv->RfReg0Value[eRFPath] << 16));
183 NewOffset = Offset - 30;
184 } else if (Offset >= 16) {
185 priv->RfReg0Value[eRFPath] |= 0x100;
186 priv->RfReg0Value[eRFPath] &= (~0x40);
187 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
188 bMaskDWord,
189 (priv->RfReg0Value[eRFPath] << 16));
190 NewOffset = Offset - 15;
191 } else
192 NewOffset = Offset;
193 } else {
194 RT_TRACE((COMP_PHY|COMP_ERR),
195 "check RF type here, need to be 8256\n");
196 NewOffset = Offset;
197 }
198
199 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
200
201 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
202
203 if (Offset == 0x0)
204 priv->RfReg0Value[eRFPath] = Data;
205
206 if (priv->rf_chip == RF_8256) {
207 if (Offset != 0) {
208 priv->RfReg0Value[eRFPath] &= 0xebf;
209 rtl8192_setBBreg(
210 dev,
211 pPhyReg->rf3wireOffset,
212 bMaskDWord,
213 (priv->RfReg0Value[eRFPath] << 16));
214 }
215 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
216 }
217 }
218
219 void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
220 u32 RegAddr, u32 BitMask, u32 Data)
221 {
222 struct r8192_priv *priv = rtllib_priv(dev);
223 u32 Original_Value, BitShift, New_Value;
224
225 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
226 return;
227 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
228 return;
229
230 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
231 if (priv->Rf_Mode == RF_OP_By_FW) {
232 if (BitMask != bMask12Bits) {
233 Original_Value = phy_FwRFSerialRead(dev, eRFPath,
234 RegAddr);
235 BitShift = rtl8192_CalculateBitShift(BitMask);
236 New_Value = (((Original_Value) & (~BitMask)) |
237 (Data << BitShift));
238
239 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
240 } else
241 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
242 udelay(200);
243
244 } else {
245 if (BitMask != bMask12Bits) {
246 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
247 RegAddr);
248 BitShift = rtl8192_CalculateBitShift(BitMask);
249 New_Value = (((Original_Value) & (~BitMask)) |
250 (Data << BitShift));
251
252 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
253 New_Value);
254 } else
255 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
256 }
257 }
258
259 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
260 u32 RegAddr, u32 BitMask)
261 {
262 u32 Original_Value, Readback_Value, BitShift;
263 struct r8192_priv *priv = rtllib_priv(dev);
264
265 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
266 return 0;
267 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
268 return 0;
269 down(&priv->rf_sem);
270 if (priv->Rf_Mode == RF_OP_By_FW) {
271 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
272 udelay(200);
273 } else {
274 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
275 RegAddr);
276 }
277 BitShift = rtl8192_CalculateBitShift(BitMask);
278 Readback_Value = (Original_Value & BitMask) >> BitShift;
279 up(&priv->rf_sem);
280 return Readback_Value;
281 }
282
283 static u32 phy_FwRFSerialRead(struct net_device *dev,
284 enum rf90_radio_path eRFPath, u32 Offset)
285 {
286 u32 Data = 0;
287 u8 time = 0;
288
289 Data |= ((Offset & 0xFF) << 12);
290 Data |= ((eRFPath & 0x3) << 20);
291 Data |= 0x80000000;
292 while (read_nic_dword(dev, QPNR)&0x80000000) {
293 if (time++ < 100)
294 udelay(10);
295 else
296 break;
297 }
298 write_nic_dword(dev, QPNR, Data);
299 while (read_nic_dword(dev, QPNR) & 0x80000000) {
300 if (time++ < 100)
301 udelay(10);
302 else
303 return 0;
304 }
305 return read_nic_dword(dev, RF_DATA);
306
307 }
308
309 static void phy_FwRFSerialWrite(struct net_device *dev,
310 enum rf90_radio_path eRFPath,
311 u32 Offset, u32 Data)
312 {
313 u8 time = 0;
314
315 Data |= ((Offset & 0xFF) << 12);
316 Data |= ((eRFPath & 0x3) << 20);
317 Data |= 0x400000;
318 Data |= 0x80000000;
319
320 while (read_nic_dword(dev, QPNR) & 0x80000000) {
321 if (time++ < 100)
322 udelay(10);
323 else
324 break;
325 }
326 write_nic_dword(dev, QPNR, Data);
327
328 }
329
330
331 void rtl8192_phy_configmac(struct net_device *dev)
332 {
333 u32 dwArrayLen = 0, i = 0;
334 u32 *pdwArray = NULL;
335 struct r8192_priv *priv = rtllib_priv(dev);
336
337 if (priv->bTXPowerDataReadFromEEPORM) {
338 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
339 dwArrayLen = MACPHY_Array_PGLength;
340 pdwArray = Rtl819XMACPHY_Array_PG;
341
342 } else {
343 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
344 dwArrayLen = MACPHY_ArrayLength;
345 pdwArray = Rtl819XMACPHY_Array;
346 }
347 for (i = 0; i < dwArrayLen; i += 3) {
348 RT_TRACE(COMP_DBG,
349 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
350 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
351 if (pdwArray[i] == 0x318)
352 pdwArray[i+2] = 0x00000800;
353 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
354 pdwArray[i+2]);
355 }
356 return;
357
358 }
359
360 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
361 {
362 int i;
363 u32 *Rtl819XPHY_REGArray_Table = NULL;
364 u32 *Rtl819XAGCTAB_Array_Table = NULL;
365 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
366 struct r8192_priv *priv = rtllib_priv(dev);
367
368 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
369 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
370 if (priv->rf_type == RF_2T4R) {
371 PHY_REGArrayLen = PHY_REGArrayLength;
372 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
373 } else if (priv->rf_type == RF_1T2R) {
374 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
375 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
376 }
377
378 if (ConfigType == BaseBand_Config_PHY_REG) {
379 for (i = 0; i < PHY_REGArrayLen; i += 2) {
380 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
381 bMaskDWord,
382 Rtl819XPHY_REGArray_Table[i+1]);
383 RT_TRACE(COMP_DBG,
384 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
385 i, Rtl819XPHY_REGArray_Table[i],
386 Rtl819XPHY_REGArray_Table[i+1]);
387 }
388 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
389 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
390 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
391 bMaskDWord,
392 Rtl819XAGCTAB_Array_Table[i+1]);
393 RT_TRACE(COMP_DBG,
394 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
395 i, Rtl819XAGCTAB_Array_Table[i],
396 Rtl819XAGCTAB_Array_Table[i+1]);
397 }
398 }
399 }
400
401 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
402 {
403 struct r8192_priv *priv = rtllib_priv(dev);
404
405 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
406 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
407 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
408 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
409
410 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
411 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
412 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
413 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
414
415 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
416 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
417 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
418 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
419
420 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
421 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
422 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
423 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
424
425 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
426 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
427 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
428 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
429
430 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
431 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
432 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
433 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
434
435 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
436 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
437 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
438 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
439
440 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
441 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
442 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
443 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
444
445 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
446 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
447 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
448 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
449
450 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
451 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
452 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
453 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
454
455 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
456 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
457 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
458 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
459
460 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
461 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
462 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
463 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
464
465 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
466 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
467 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
468 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
469
470 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
471 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
472 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
473 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
474
475 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
476 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
477 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
478 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
479
480 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
481 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
482 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
483 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
484
485 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
486 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
487 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
488 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
489
490 }
491
492 bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
493 enum hw90_block CheckBlock,
494 enum rf90_radio_path eRFPath)
495 {
496 bool ret = true;
497 u32 i, CheckTimes = 4, dwRegRead = 0;
498 u32 WriteAddr[4];
499 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
500
501 WriteAddr[HW90_BLOCK_MAC] = 0x100;
502 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
503 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
504 WriteAddr[HW90_BLOCK_RF] = 0x3;
505 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
506 CheckBlock);
507 for (i = 0; i < CheckTimes; i++) {
508 switch (CheckBlock) {
509 case HW90_BLOCK_MAC:
510 RT_TRACE(COMP_ERR,
511 "PHY_CheckBBRFOK(): Never Write 0x100 here!");
512 break;
513
514 case HW90_BLOCK_PHY0:
515 case HW90_BLOCK_PHY1:
516 write_nic_dword(dev, WriteAddr[CheckBlock],
517 WriteData[i]);
518 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
519 break;
520
521 case HW90_BLOCK_RF:
522 WriteData[i] &= 0xfff;
523 rtl8192_phy_SetRFReg(dev, eRFPath,
524 WriteAddr[HW90_BLOCK_RF],
525 bMask12Bits, WriteData[i]);
526 mdelay(10);
527 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
528 WriteAddr[HW90_BLOCK_RF],
529 bMaskDWord);
530 mdelay(10);
531 break;
532
533 default:
534 ret = false;
535 break;
536 }
537
538
539 if (dwRegRead != WriteData[i]) {
540 RT_TRACE(COMP_ERR,
541 "====>error=====dwRegRead: %x, WriteData: %x\n",
542 dwRegRead, WriteData[i]);
543 ret = false;
544 break;
545 }
546 }
547
548 return ret;
549 }
550
551 static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
552 {
553 struct r8192_priv *priv = rtllib_priv(dev);
554 bool rtStatus = true;
555 u8 bRegValue = 0, eCheckItem = 0;
556 u32 dwRegValue = 0;
557
558 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
559 write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
560
561 dwRegValue = read_nic_dword(dev, CPU_GEN);
562 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
563
564 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
565 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
566 rtStatus = rtl8192_phy_checkBBAndRF(dev,
567 (enum hw90_block)eCheckItem,
568 (enum rf90_radio_path)0);
569 if (!rtStatus) {
570 RT_TRACE((COMP_ERR | COMP_PHY),
571 "PHY_RF8256_Config():Check PHY%d Fail!!\n",
572 eCheckItem-1);
573 return rtStatus;
574 }
575 }
576 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
577 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
578
579 dwRegValue = read_nic_dword(dev, CPU_GEN);
580 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
581
582 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
583
584 if (priv->IC_Cut > VERSION_8190_BD) {
585 if (priv->rf_type == RF_2T4R)
586 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
587 priv->AntennaTxPwDiff[1]<<4 |
588 priv->AntennaTxPwDiff[0]);
589 else
590 dwRegValue = 0x0;
591 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
592 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
593
594
595 dwRegValue = priv->CrystalCap;
596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
597 dwRegValue);
598 }
599
600 return rtStatus;
601 }
602 bool rtl8192_BBConfig(struct net_device *dev)
603 {
604 rtl8192_InitBBRFRegDef(dev);
605 return rtl8192_BB_Config_ParaFile(dev);
606 }
607
608 void rtl8192_phy_getTxPower(struct net_device *dev)
609 {
610 struct r8192_priv *priv = rtllib_priv(dev);
611
612 priv->MCSTxPowerLevelOriginalOffset[0] =
613 read_nic_dword(dev, rTxAGC_Rate18_06);
614 priv->MCSTxPowerLevelOriginalOffset[1] =
615 read_nic_dword(dev, rTxAGC_Rate54_24);
616 priv->MCSTxPowerLevelOriginalOffset[2] =
617 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
618 priv->MCSTxPowerLevelOriginalOffset[3] =
619 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
620 priv->MCSTxPowerLevelOriginalOffset[4] =
621 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
622 priv->MCSTxPowerLevelOriginalOffset[5] =
623 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
624
625 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
626 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
627 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
628 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
629 RT_TRACE(COMP_INIT,
630 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
631 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
632 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
633
634 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
635 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
636 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
637 rOFDM0_RxDetector3, priv->framesync);
638 priv->SifsTime = read_nic_word(dev, SIFS);
639 }
640
641 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
642 {
643 struct r8192_priv *priv = rtllib_priv(dev);
644 u8 powerlevel = 0, powerlevelOFDM24G = 0;
645 char ant_pwr_diff;
646 u32 u4RegValue;
647
648 if (priv->epromtype == EEPROM_93C46) {
649 powerlevel = priv->TxPowerLevelCCK[channel-1];
650 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
651 } else if (priv->epromtype == EEPROM_93C56) {
652 if (priv->rf_type == RF_1T2R) {
653 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
654 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
655 } else if (priv->rf_type == RF_2T4R) {
656 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
657 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
658
659 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
660 - priv->TxPowerLevelOFDM24G_A[channel-1];
661
662 priv->RF_C_TxPwDiff = ant_pwr_diff;
663
664 ant_pwr_diff &= 0xf;
665
666 priv->AntennaTxPwDiff[2] = 0;
667 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
668 priv->AntennaTxPwDiff[0] = 0;
669
670 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
671 priv->AntennaTxPwDiff[1]<<4 |
672 priv->AntennaTxPwDiff[0]);
673
674 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
675 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
676 }
677 }
678 switch (priv->rf_chip) {
679 case RF_8225:
680 break;
681 case RF_8256:
682 PHY_SetRF8256CCKTxPower(dev, powerlevel);
683 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
684 break;
685 case RF_8258:
686 break;
687 default:
688 RT_TRACE(COMP_ERR, "unknown rf chip in function %s()\n",
689 __func__);
690 break;
691 }
692 }
693
694 bool rtl8192_phy_RFConfig(struct net_device *dev)
695 {
696 struct r8192_priv *priv = rtllib_priv(dev);
697 bool rtStatus = true;
698
699 switch (priv->rf_chip) {
700 case RF_8225:
701 break;
702 case RF_8256:
703 rtStatus = PHY_RF8256_Config(dev);
704 break;
705
706 case RF_8258:
707 break;
708 case RF_PSEUDO_11N:
709 break;
710
711 default:
712 RT_TRACE(COMP_ERR, "error chip id\n");
713 break;
714 }
715 return rtStatus;
716 }
717
718 void rtl8192_phy_updateInitGain(struct net_device *dev)
719 {
720 }
721
722 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
723 enum rf90_radio_path eRFPath)
724 {
725
726 int i;
727
728 switch (eRFPath) {
729 case RF90_PATH_A:
730 for (i = 0; i < RadioA_ArrayLength; i += 2) {
731 if (Rtl819XRadioA_Array[i] == 0xfe) {
732 msleep(100);
733 continue;
734 }
735 rtl8192_phy_SetRFReg(dev, eRFPath,
736 Rtl819XRadioA_Array[i],
737 bMask12Bits,
738 Rtl819XRadioA_Array[i+1]);
739
740 }
741 break;
742 case RF90_PATH_B:
743 for (i = 0; i < RadioB_ArrayLength; i += 2) {
744 if (Rtl819XRadioB_Array[i] == 0xfe) {
745 msleep(100);
746 continue;
747 }
748 rtl8192_phy_SetRFReg(dev, eRFPath,
749 Rtl819XRadioB_Array[i],
750 bMask12Bits,
751 Rtl819XRadioB_Array[i+1]);
752
753 }
754 break;
755 case RF90_PATH_C:
756 for (i = 0; i < RadioC_ArrayLength; i += 2) {
757 if (Rtl819XRadioC_Array[i] == 0xfe) {
758 msleep(100);
759 continue;
760 }
761 rtl8192_phy_SetRFReg(dev, eRFPath,
762 Rtl819XRadioC_Array[i],
763 bMask12Bits,
764 Rtl819XRadioC_Array[i+1]);
765
766 }
767 break;
768 case RF90_PATH_D:
769 for (i = 0; i < RadioD_ArrayLength; i += 2) {
770 if (Rtl819XRadioD_Array[i] == 0xfe) {
771 msleep(100);
772 continue;
773 }
774 rtl8192_phy_SetRFReg(dev, eRFPath,
775 Rtl819XRadioD_Array[i], bMask12Bits,
776 Rtl819XRadioD_Array[i+1]);
777
778 }
779 break;
780 default:
781 break;
782 }
783
784 return 0;
785
786 }
787 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
788 {
789 struct r8192_priv *priv = rtllib_priv(dev);
790 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
791 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
792
793 switch (priv->rf_chip) {
794 case RF_8225:
795 break;
796
797 case RF_8256:
798 PHY_SetRF8256CCKTxPower(dev, powerlevel);
799 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
800 break;
801
802 case RF_8258:
803 break;
804 default:
805 RT_TRACE(COMP_ERR,
806 "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
807 break;
808 }
809 }
810
811 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
812 u32 CmdTableIdx, u32 CmdTableSz,
813 enum sw_chnl_cmd_id CmdID,
814 u32 Para1, u32 Para2, u32 msDelay)
815 {
816 struct sw_chnl_cmd *pCmd;
817
818 if (CmdTable == NULL) {
819 RT_TRACE(COMP_ERR,
820 "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
821 return false;
822 }
823 if (CmdTableIdx >= CmdTableSz) {
824 RT_TRACE(COMP_ERR,
825 "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
826 CmdTableIdx, CmdTableSz);
827 return false;
828 }
829
830 pCmd = CmdTable + CmdTableIdx;
831 pCmd->CmdID = CmdID;
832 pCmd->Para1 = Para1;
833 pCmd->Para2 = Para2;
834 pCmd->msDelay = msDelay;
835
836 return true;
837 }
838
839 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
840 u8 *stage, u8 *step, u32 *delay)
841 {
842 struct r8192_priv *priv = rtllib_priv(dev);
843 struct rtllib_device *ieee = priv->rtllib;
844 u32 PreCommonCmdCnt;
845 u32 PostCommonCmdCnt;
846 u32 RfDependCmdCnt;
847 struct sw_chnl_cmd *CurrentCmd = NULL;
848 u8 eRFPath;
849
850 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
851 __func__, *stage, *step, channel);
852
853 if (!rtllib_legal_channel(priv->rtllib, channel)) {
854 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
855 channel);
856 return true;
857 }
858
859 {
860 PreCommonCmdCnt = 0;
861 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
862 PreCommonCmdCnt++,
863 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
864 0, 0, 0);
865 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
866 PreCommonCmdCnt++,
867 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
868
869 PostCommonCmdCnt = 0;
870
871 rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd,
872 PostCommonCmdCnt++,
873 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
874
875 RfDependCmdCnt = 0;
876 switch (priv->rf_chip) {
877 case RF_8225:
878 if (!(channel >= 1 && channel <= 14)) {
879 RT_TRACE(COMP_ERR,
880 "illegal channel for Zebra 8225: %d\n",
881 channel);
882 return false;
883 }
884 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
885 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
886 CmdID_RF_WriteReg, rZebra1_Channel,
887 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
888 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
889 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
890 CmdID_End, 0, 0, 0);
891 break;
892
893 case RF_8256:
894 if (!(channel >= 1 && channel <= 14)) {
895 RT_TRACE(COMP_ERR,
896 "illegal channel for Zebra 8256: %d\n",
897 channel);
898 return false;
899 }
900 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
901 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
902 CmdID_RF_WriteReg, rZebra1_Channel, channel,
903 10);
904 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
905
906 RfDependCmdCnt++,
907 MAX_RFDEPENDCMD_CNT,
908 CmdID_End, 0, 0, 0);
909 break;
910
911 case RF_8258:
912 break;
913
914 default:
915 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
916 priv->rf_chip);
917 return false;
918 }
919
920
921 do {
922 switch (*stage) {
923 case 0:
924 CurrentCmd = &ieee->PreCommonCmd[*step];
925 break;
926 case 1:
927 CurrentCmd = &ieee->RfDependCmd[*step];
928 break;
929 case 2:
930 CurrentCmd = &ieee->PostCommonCmd[*step];
931 break;
932 }
933
934 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
935 if ((*stage) == 2)
936 return true;
937 (*stage)++;
938 (*step) = 0;
939 continue;
940 }
941
942 if (!CurrentCmd)
943 continue;
944 switch (CurrentCmd->CmdID) {
945 case CmdID_SetTxPowerLevel:
946 if (priv->IC_Cut > (u8)VERSION_8190_BD)
947 rtl8192_SetTxPowerLevel(dev, channel);
948 break;
949 case CmdID_WritePortUlong:
950 write_nic_dword(dev, CurrentCmd->Para1,
951 CurrentCmd->Para2);
952 break;
953 case CmdID_WritePortUshort:
954 write_nic_word(dev, CurrentCmd->Para1,
955 (u16)CurrentCmd->Para2);
956 break;
957 case CmdID_WritePortUchar:
958 write_nic_byte(dev, CurrentCmd->Para1,
959 (u8)CurrentCmd->Para2);
960 break;
961 case CmdID_RF_WriteReg:
962 for (eRFPath = 0; eRFPath <
963 priv->NumTotalRFPath; eRFPath++)
964 rtl8192_phy_SetRFReg(dev,
965 (enum rf90_radio_path)eRFPath,
966 CurrentCmd->Para1, bMask12Bits,
967 CurrentCmd->Para2<<7);
968 break;
969 default:
970 break;
971 }
972
973 break;
974 } while (true);
975 } /*for (Number of RF paths)*/
976
977 (*delay) = CurrentCmd->msDelay;
978 (*step)++;
979 return false;
980 }
981
982 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
983 {
984 struct r8192_priv *priv = rtllib_priv(dev);
985 u32 delay = 0;
986
987 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
988 &priv->SwChnlStep, &delay)) {
989 if (delay > 0)
990 msleep(delay);
991 if (!priv->up)
992 break;
993 }
994 }
995 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
996 {
997
998 struct r8192_priv *priv = rtllib_priv(dev);
999
1000 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1001
1002 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
1003 priv->chan, priv);
1004
1005 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1006
1007 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1008 }
1009
1010 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1011 {
1012 struct r8192_priv *priv = rtllib_priv(dev);
1013
1014 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1015 if (!priv->up) {
1016 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
1017 return false;
1018 }
1019 if (priv->SwChnlInProgress)
1020 return false;
1021
1022
1023 switch (priv->rtllib->mode) {
1024 case WIRELESS_MODE_A:
1025 case WIRELESS_MODE_N_5G:
1026 if (channel <= 14) {
1027 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1028 return false;
1029 }
1030 break;
1031 case WIRELESS_MODE_B:
1032 if (channel > 14) {
1033 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1034 return false;
1035 }
1036 break;
1037 case WIRELESS_MODE_G:
1038 case WIRELESS_MODE_N_24G:
1039 if (channel > 14) {
1040 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1041 return false;
1042 }
1043 break;
1044 }
1045
1046 priv->SwChnlInProgress = true;
1047 if (channel == 0)
1048 channel = 1;
1049
1050 priv->chan = channel;
1051
1052 priv->SwChnlStage = 0;
1053 priv->SwChnlStep = 0;
1054
1055 if (priv->up)
1056 rtl8192_SwChnl_WorkItem(dev);
1057 priv->SwChnlInProgress = false;
1058 return true;
1059 }
1060
1061 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1062 {
1063 struct r8192_priv *priv = rtllib_priv(dev);
1064
1065 switch (priv->CurrentChannelBW) {
1066 case HT_CHANNEL_WIDTH_20:
1067 priv->CCKPresentAttentuation =
1068 priv->CCKPresentAttentuation_20Mdefault +
1069 priv->CCKPresentAttentuation_difference;
1070
1071 if (priv->CCKPresentAttentuation >
1072 (CCKTxBBGainTableLength-1))
1073 priv->CCKPresentAttentuation =
1074 CCKTxBBGainTableLength-1;
1075 if (priv->CCKPresentAttentuation < 0)
1076 priv->CCKPresentAttentuation = 0;
1077
1078 RT_TRACE(COMP_POWER_TRACKING,
1079 "20M, priv->CCKPresentAttentuation = %d\n",
1080 priv->CCKPresentAttentuation);
1081
1082 if (priv->rtllib->current_network.channel == 14 &&
1083 !priv->bcck_in_ch14) {
1084 priv->bcck_in_ch14 = true;
1085 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1086 } else if (priv->rtllib->current_network.channel !=
1087 14 && priv->bcck_in_ch14) {
1088 priv->bcck_in_ch14 = false;
1089 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1090 } else {
1091 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1092 }
1093 break;
1094
1095 case HT_CHANNEL_WIDTH_20_40:
1096 priv->CCKPresentAttentuation =
1097 priv->CCKPresentAttentuation_40Mdefault +
1098 priv->CCKPresentAttentuation_difference;
1099
1100 RT_TRACE(COMP_POWER_TRACKING,
1101 "40M, priv->CCKPresentAttentuation = %d\n",
1102 priv->CCKPresentAttentuation);
1103 if (priv->CCKPresentAttentuation >
1104 (CCKTxBBGainTableLength - 1))
1105 priv->CCKPresentAttentuation =
1106 CCKTxBBGainTableLength-1;
1107 if (priv->CCKPresentAttentuation < 0)
1108 priv->CCKPresentAttentuation = 0;
1109
1110 if (priv->rtllib->current_network.channel == 14 &&
1111 !priv->bcck_in_ch14) {
1112 priv->bcck_in_ch14 = true;
1113 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1114 } else if (priv->rtllib->current_network.channel != 14
1115 && priv->bcck_in_ch14) {
1116 priv->bcck_in_ch14 = false;
1117 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1118 } else {
1119 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1120 }
1121 break;
1122 }
1123 }
1124
1125 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1126 {
1127 struct r8192_priv *priv = rtllib_priv(dev);
1128
1129 if (priv->rtllib->current_network.channel == 14 &&
1130 !priv->bcck_in_ch14)
1131 priv->bcck_in_ch14 = true;
1132 else if (priv->rtllib->current_network.channel != 14 &&
1133 priv->bcck_in_ch14)
1134 priv->bcck_in_ch14 = false;
1135
1136 switch (priv->CurrentChannelBW) {
1137 case HT_CHANNEL_WIDTH_20:
1138 if (priv->Record_CCK_20Mindex == 0)
1139 priv->Record_CCK_20Mindex = 6;
1140 priv->CCK_index = priv->Record_CCK_20Mindex;
1141 RT_TRACE(COMP_POWER_TRACKING,
1142 "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n",
1143 priv->CCK_index);
1144 break;
1145
1146 case HT_CHANNEL_WIDTH_20_40:
1147 priv->CCK_index = priv->Record_CCK_40Mindex;
1148 RT_TRACE(COMP_POWER_TRACKING,
1149 "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n",
1150 priv->CCK_index);
1151 break;
1152 }
1153 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1154 }
1155
1156 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1157 {
1158 struct r8192_priv *priv = rtllib_priv(dev);
1159
1160 if (priv->IC_Cut >= IC_VersionCut_D)
1161 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1162 else
1163 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1164 }
1165
1166 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1167 {
1168
1169 struct r8192_priv *priv = rtllib_priv(dev);
1170 u8 regBwOpMode;
1171
1172 RT_TRACE(COMP_SWBW,
1173 "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
1174 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1175 "20MHz" : "40MHz");
1176
1177
1178 if (priv->rf_chip == RF_PSEUDO_11N) {
1179 priv->SetBWModeInProgress = false;
1180 return;
1181 }
1182 if (!priv->up) {
1183 RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
1184 return;
1185 }
1186 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1187
1188 switch (priv->CurrentChannelBW) {
1189 case HT_CHANNEL_WIDTH_20:
1190 regBwOpMode |= BW_OPMODE_20MHZ;
1191 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1192 break;
1193
1194 case HT_CHANNEL_WIDTH_20_40:
1195 regBwOpMode &= ~BW_OPMODE_20MHZ;
1196 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1197 break;
1198
1199 default:
1200 RT_TRACE(COMP_ERR,
1201 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1202 priv->CurrentChannelBW);
1203 break;
1204 }
1205
1206 switch (priv->CurrentChannelBW) {
1207 case HT_CHANNEL_WIDTH_20:
1208 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1209 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1210
1211 if (!priv->btxpower_tracking) {
1212 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1213 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1214 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1215 } else {
1216 CCK_Tx_Power_Track_BW_Switch(dev);
1217 }
1218
1219 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1220
1221 break;
1222 case HT_CHANNEL_WIDTH_20_40:
1223 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1224 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1225
1226 if (!priv->btxpower_tracking) {
1227 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1228 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1229 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1230 } else {
1231 CCK_Tx_Power_Track_BW_Switch(dev);
1232 }
1233
1234 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1235 (priv->nCur40MhzPrimeSC>>1));
1236 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1237 priv->nCur40MhzPrimeSC);
1238
1239 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1240 break;
1241 default:
1242 RT_TRACE(COMP_ERR,
1243 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1244 priv->CurrentChannelBW);
1245 break;
1246
1247 }
1248
1249 switch (priv->rf_chip) {
1250 case RF_8225:
1251 break;
1252
1253 case RF_8256:
1254 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1255 break;
1256
1257 case RF_8258:
1258 break;
1259
1260 case RF_PSEUDO_11N:
1261 break;
1262
1263 default:
1264 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1265 break;
1266 }
1267
1268 atomic_dec(&(priv->rtllib->atm_swbw));
1269 priv->SetBWModeInProgress = false;
1270
1271 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1272 }
1273
1274 void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
1275 enum ht_extchnl_offset Offset)
1276 {
1277 struct r8192_priv *priv = rtllib_priv(dev);
1278
1279
1280 if (priv->SetBWModeInProgress)
1281 return;
1282
1283 atomic_inc(&(priv->rtllib->atm_swbw));
1284 priv->SetBWModeInProgress = true;
1285
1286 priv->CurrentChannelBW = Bandwidth;
1287
1288 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1289 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1290 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1291 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1292 else
1293 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1294
1295 rtl8192_SetBWModeWorkItem(dev);
1296
1297 }
1298
1299 void InitialGain819xPci(struct net_device *dev, u8 Operation)
1300 {
1301 #define SCAN_RX_INITIAL_GAIN 0x17
1302 #define POWER_DETECTION_TH 0x08
1303 struct r8192_priv *priv = rtllib_priv(dev);
1304 u32 BitMask;
1305 u8 initial_gain;
1306
1307 if (priv->up) {
1308 switch (Operation) {
1309 case IG_Backup:
1310 RT_TRACE(COMP_SCAN,
1311 "IG_Backup, backup the initial gain.\n");
1312 initial_gain = SCAN_RX_INITIAL_GAIN;
1313 BitMask = bMaskByte0;
1314 if (dm_digtable.dig_algorithm ==
1315 DIG_ALGO_BY_FALSE_ALARM)
1316 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1317 priv->initgain_backup.xaagccore1 =
1318 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
1319 BitMask);
1320 priv->initgain_backup.xbagccore1 =
1321 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
1322 BitMask);
1323 priv->initgain_backup.xcagccore1 =
1324 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
1325 BitMask);
1326 priv->initgain_backup.xdagccore1 =
1327 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1328 BitMask);
1329 BitMask = bMaskByte2;
1330 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
1331 rCCK0_CCA, BitMask);
1332
1333 RT_TRACE(COMP_SCAN,
1334 "Scan InitialGainBackup 0xc50 is %x\n",
1335 priv->initgain_backup.xaagccore1);
1336 RT_TRACE(COMP_SCAN,
1337 "Scan InitialGainBackup 0xc58 is %x\n",
1338 priv->initgain_backup.xbagccore1);
1339 RT_TRACE(COMP_SCAN,
1340 "Scan InitialGainBackup 0xc60 is %x\n",
1341 priv->initgain_backup.xcagccore1);
1342 RT_TRACE(COMP_SCAN,
1343 "Scan InitialGainBackup 0xc68 is %x\n",
1344 priv->initgain_backup.xdagccore1);
1345 RT_TRACE(COMP_SCAN,
1346 "Scan InitialGainBackup 0xa0a is %x\n",
1347 priv->initgain_backup.cca);
1348
1349 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1350 initial_gain);
1351 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1352 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1353 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1354 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1355 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1356 POWER_DETECTION_TH);
1357 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1358 break;
1359 case IG_Restore:
1360 RT_TRACE(COMP_SCAN,
1361 "IG_Restore, restore the initial gain.\n");
1362 BitMask = 0x7f;
1363 if (dm_digtable.dig_algorithm ==
1364 DIG_ALGO_BY_FALSE_ALARM)
1365 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1366
1367 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
1368 (u32)priv->initgain_backup.xaagccore1);
1369 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
1370 (u32)priv->initgain_backup.xbagccore1);
1371 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
1372 (u32)priv->initgain_backup.xcagccore1);
1373 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
1374 (u32)priv->initgain_backup.xdagccore1);
1375 BitMask = bMaskByte2;
1376 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
1377 (u32)priv->initgain_backup.cca);
1378
1379 RT_TRACE(COMP_SCAN,
1380 "Scan BBInitialGainRestore 0xc50 is %x\n",
1381 priv->initgain_backup.xaagccore1);
1382 RT_TRACE(COMP_SCAN,
1383 "Scan BBInitialGainRestore 0xc58 is %x\n",
1384 priv->initgain_backup.xbagccore1);
1385 RT_TRACE(COMP_SCAN,
1386 "Scan BBInitialGainRestore 0xc60 is %x\n",
1387 priv->initgain_backup.xcagccore1);
1388 RT_TRACE(COMP_SCAN,
1389 "Scan BBInitialGainRestore 0xc68 is %x\n",
1390 priv->initgain_backup.xdagccore1);
1391 RT_TRACE(COMP_SCAN,
1392 "Scan BBInitialGainRestore 0xa0a is %x\n",
1393 priv->initgain_backup.cca);
1394
1395 rtl8192_phy_setTxPower(dev,
1396 priv->rtllib->current_network.channel);
1397
1398 if (dm_digtable.dig_algorithm ==
1399 DIG_ALGO_BY_FALSE_ALARM)
1400 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1401 break;
1402 default:
1403 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1404 break;
1405 }
1406 }
1407 }
1408
1409 void PHY_SetRtl8192eRfOff(struct net_device *dev)
1410 {
1411
1412 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1413 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1414 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1415 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1416 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1417 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1418 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1419 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1420
1421 }
1422
1423 static bool SetRFPowerState8190(struct net_device *dev,
1424 enum rt_rf_power_state eRFPowerState)
1425 {
1426 struct r8192_priv *priv = rtllib_priv(dev);
1427 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1428 (&(priv->rtllib->PowerSaveControl));
1429 bool bResult = true;
1430 u8 i = 0, QueueID = 0;
1431 struct rtl8192_tx_ring *ring = NULL;
1432
1433 if (priv->SetRFPowerStateInProgress)
1434 return false;
1435 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1436 priv->SetRFPowerStateInProgress = true;
1437
1438 switch (priv->rf_chip) {
1439 case RF_8256:
1440 switch (eRFPowerState) {
1441 case eRfOn:
1442 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1443 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1444 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1445 bool rtstatus = true;
1446 u32 InitilizeCount = 3;
1447
1448 do {
1449 InitilizeCount--;
1450 priv->RegRfOff = false;
1451 rtstatus = NicIFEnableNIC(dev);
1452 } while (!rtstatus && (InitilizeCount > 0));
1453
1454 if (!rtstatus) {
1455 RT_TRACE(COMP_ERR,
1456 "%s():Initialize Adapter fail,return\n",
1457 __func__);
1458 priv->SetRFPowerStateInProgress = false;
1459 return false;
1460 }
1461
1462 RT_CLEAR_PS_LEVEL(pPSC,
1463 RT_RF_OFF_LEVL_HALT_NIC);
1464 } else {
1465 write_nic_byte(dev, ANAPAR, 0x37);
1466 mdelay(1);
1467 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1468 0x4, 0x1);
1469 priv->bHwRfOffAction = 0;
1470
1471 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
1472 BIT4, 0x1);
1473 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
1474 0x300, 0x3);
1475 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1476 0x18, 0x3);
1477 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
1478 0x3);
1479 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
1480 0x3);
1481 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1482 0x60, 0x3);
1483
1484 }
1485
1486 break;
1487
1488 case eRfSleep:
1489 if (priv->rtllib->eRFPowerState == eRfOff)
1490 break;
1491
1492
1493 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1494 ring = &priv->tx_ring[QueueID];
1495
1496 if (skb_queue_len(&ring->queue) == 0) {
1497 QueueID++;
1498 continue;
1499 } else {
1500 RT_TRACE((COMP_POWER|COMP_RF),
1501 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1502 (i+1), QueueID);
1503 udelay(10);
1504 i++;
1505 }
1506
1507 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1508 RT_TRACE(COMP_POWER,
1509 "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1510 MAX_DOZE_WAITING_TIMES_9x,
1511 QueueID);
1512 break;
1513 }
1514 }
1515 PHY_SetRtl8192eRfOff(dev);
1516 break;
1517
1518 case eRfOff:
1519 RT_TRACE(COMP_PS,
1520 "SetRFPowerState8190() eRfOff/Sleep !\n");
1521
1522 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1523 ring = &priv->tx_ring[QueueID];
1524
1525 if (skb_queue_len(&ring->queue) == 0) {
1526 QueueID++;
1527 continue;
1528 } else {
1529 RT_TRACE(COMP_POWER,
1530 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1531 (i+1), QueueID);
1532 udelay(10);
1533 i++;
1534 }
1535
1536 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1537 RT_TRACE(COMP_POWER,
1538 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1539 MAX_DOZE_WAITING_TIMES_9x,
1540 QueueID);
1541 break;
1542 }
1543 }
1544
1545 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1546 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1547 NicIFDisableNIC(dev);
1548 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1549 } else if (!(pPSC->RegRfPsLevel &
1550 RT_RF_OFF_LEVL_HALT_NIC)) {
1551 PHY_SetRtl8192eRfOff(dev);
1552 }
1553
1554 break;
1555
1556 default:
1557 bResult = false;
1558 RT_TRACE(COMP_ERR,
1559 "SetRFPowerState8190(): unknown state to set: 0x%X!!!\n",
1560 eRFPowerState);
1561 break;
1562 }
1563
1564 break;
1565
1566 default:
1567 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1568 break;
1569 }
1570
1571 if (bResult) {
1572 priv->rtllib->eRFPowerState = eRFPowerState;
1573
1574 switch (priv->rf_chip) {
1575 case RF_8256:
1576 break;
1577
1578 default:
1579 RT_TRACE(COMP_ERR,
1580 "SetRFPowerState8190(): Unknown RF type\n");
1581 break;
1582 }
1583 }
1584
1585 priv->SetRFPowerStateInProgress = false;
1586 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1587 bResult);
1588 return bResult;
1589 }
1590
1591 bool SetRFPowerState(struct net_device *dev,
1592 enum rt_rf_power_state eRFPowerState)
1593 {
1594 struct r8192_priv *priv = rtllib_priv(dev);
1595
1596 bool bResult = false;
1597
1598 RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
1599 eRFPowerState);
1600 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1601 priv->bHwRfOffAction == 0) {
1602 RT_TRACE(COMP_PS,
1603 "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n",
1604 eRFPowerState);
1605 return bResult;
1606 }
1607
1608 bResult = SetRFPowerState8190(dev, eRFPowerState);
1609
1610 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
1611 bResult);
1612
1613 return bResult;
1614 }
1615
1616 void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
1617 {
1618 struct r8192_priv *priv = rtllib_priv(dev);
1619
1620 if (priv->up) {
1621 switch (Operation) {
1622 case SCAN_OPT_BACKUP:
1623 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1624 break;
1625
1626 case SCAN_OPT_RESTORE:
1627 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1628 break;
1629
1630 default:
1631 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1632 break;
1633 }
1634 }
1635
1636 }
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