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spi: fsl-espi: introduce struct fsl_espi
[linux-2.6/btrfs-unstable.git] / drivers / spi / spi-fsl-espi.c
blob8539f0584a8ae1fa69896e3e2297e103ff06a751
1 /*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/fsl_devices.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/mm.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <sysdev/fsl_soc.h>
25
26 #include "spi-fsl-lib.h"
27
28 /* eSPI Controller registers */
29 #define ESPI_SPMODE 0x00 /* eSPI mode register */
30 #define ESPI_SPIE 0x04 /* eSPI event register */
31 #define ESPI_SPIM 0x08 /* eSPI mask register */
32 #define ESPI_SPCOM 0x0c /* eSPI command register */
33 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
34 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
35 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
36
37 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
38
39 /* eSPI Controller mode register definitions */
40 #define SPMODE_ENABLE BIT(31)
41 #define SPMODE_LOOP BIT(30)
42 #define SPMODE_TXTHR(x) ((x) << 8)
43 #define SPMODE_RXTHR(x) ((x) << 0)
44
45 /* eSPI Controller CS mode register definitions */
46 #define CSMODE_CI_INACTIVEHIGH BIT(31)
47 #define CSMODE_CP_BEGIN_EDGECLK BIT(30)
48 #define CSMODE_REV BIT(29)
49 #define CSMODE_DIV16 BIT(28)
50 #define CSMODE_PM(x) ((x) << 24)
51 #define CSMODE_POL_1 BIT(20)
52 #define CSMODE_LEN(x) ((x) << 16)
53 #define CSMODE_BEF(x) ((x) << 12)
54 #define CSMODE_AFT(x) ((x) << 8)
55 #define CSMODE_CG(x) ((x) << 3)
56
57 #define FSL_ESPI_FIFO_SIZE 32
58 #define FSL_ESPI_RXTHR 15
59
60 /* Default mode/csmode for eSPI controller */
61 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
62 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
63 | CSMODE_AFT(0) | CSMODE_CG(1))
64
65 /* SPIE register values */
66 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
67 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
68 #define SPIE_TXE BIT(15) /* TX FIFO empty */
69 #define SPIE_DON BIT(14) /* TX done */
70 #define SPIE_RXT BIT(13) /* RX FIFO threshold */
71 #define SPIE_RXF BIT(12) /* RX FIFO full */
72 #define SPIE_TXT BIT(11) /* TX FIFO threshold*/
73 #define SPIE_RNE BIT(9) /* RX FIFO not empty */
74 #define SPIE_TNF BIT(8) /* TX FIFO not full */
75
76 /* SPIM register values */
77 #define SPIM_TXE BIT(15) /* TX FIFO empty */
78 #define SPIM_DON BIT(14) /* TX done */
79 #define SPIM_RXT BIT(13) /* RX FIFO threshold */
80 #define SPIM_RXF BIT(12) /* RX FIFO full */
81 #define SPIM_TXT BIT(11) /* TX FIFO threshold*/
82 #define SPIM_RNE BIT(9) /* RX FIFO not empty */
83 #define SPIM_TNF BIT(8) /* TX FIFO not full */
84
85 /* SPCOM register values */
86 #define SPCOM_CS(x) ((x) << 30)
87 #define SPCOM_DO BIT(28) /* Dual output */
88 #define SPCOM_TO BIT(27) /* TX only */
89 #define SPCOM_RXSKIP(x) ((x) << 16)
90 #define SPCOM_TRANLEN(x) ((x) << 0)
91
92 #define SPCOM_TRANLEN_MAX 0x10000 /* Max transaction length */
93
94 #define AUTOSUSPEND_TIMEOUT 2000
95
96 struct fsl_espi {
97 struct device *dev;
98 void __iomem *reg_base;
99
100 const void *tx;
101 void *rx;
102
103 unsigned int rx_len;
104 unsigned int tx_len;
105 unsigned int rxskip;
106
107 u8 *local_buf;
108 spinlock_t lock;
109
110 u32 spibrg; /* SPIBRG input clock */
111
112 struct completion done;
113 };
114
115 struct fsl_espi_cs {
116 u32 hw_mode;
117 };
118
119 static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
120 {
121 return ioread32be(espi->reg_base + offset);
122 }
123
124 static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
125 {
126 return ioread8(espi->reg_base + offset);
127 }
128
129 static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
130 u32 val)
131 {
132 iowrite32be(val, espi->reg_base + offset);
133 }
134
135 static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
136 u8 val)
137 {
138 iowrite8(val, espi->reg_base + offset);
139 }
140
141 static void fsl_espi_memcpy_swab(void *to, const void *from,
142 struct spi_message *m,
143 struct spi_transfer *t)
144 {
145 unsigned int len = t->len;
146
147 if (!(m->spi->mode & SPI_LSB_FIRST) || t->bits_per_word <= 8) {
148 memcpy(to, from, len);
149 return;
150 }
151
152 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
153 while (len)
154 if (len >= 4) {
155 *(u32 *)to = swahb32p(from);
156 to += 4;
157 from += 4;
158 len -= 4;
159 } else {
160 *(u16 *)to = swab16p(from);
161 to += 2;
162 from += 2;
163 len -= 2;
164 }
165 }
166
167 static void fsl_espi_copy_to_buf(struct spi_message *m,
168 struct fsl_espi *espi)
169 {
170 struct spi_transfer *t;
171 u8 *buf = espi->local_buf;
172
173 list_for_each_entry(t, &m->transfers, transfer_list) {
174 if (t->tx_buf)
175 fsl_espi_memcpy_swab(buf, t->tx_buf, m, t);
176 /* In RXSKIP mode controller shifts out zeros internally */
177 else if (!espi->rxskip)
178 memset(buf, 0, t->len);
179 buf += t->len;
180 }
181 }
182
183 static void fsl_espi_copy_from_buf(struct spi_message *m,
184 struct fsl_espi *espi)
185 {
186 struct spi_transfer *t;
187 u8 *buf = espi->local_buf;
188
189 list_for_each_entry(t, &m->transfers, transfer_list) {
190 if (t->rx_buf)
191 fsl_espi_memcpy_swab(t->rx_buf, buf, m, t);
192 buf += t->len;
193 }
194 }
195
196 static int fsl_espi_check_message(struct spi_message *m)
197 {
198 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
199 struct spi_transfer *t, *first;
200
201 if (m->frame_length > SPCOM_TRANLEN_MAX) {
202 dev_err(espi->dev, "message too long, size is %u bytes\n",
203 m->frame_length);
204 return -EMSGSIZE;
205 }
206
207 first = list_first_entry(&m->transfers, struct spi_transfer,
208 transfer_list);
209
210 list_for_each_entry(t, &m->transfers, transfer_list) {
211 if (first->bits_per_word != t->bits_per_word ||
212 first->speed_hz != t->speed_hz) {
213 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
214 return -EINVAL;
215 }
216 }
217
218 /* ESPI supports MSB-first transfers for word size 8 / 16 only */
219 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
220 first->bits_per_word != 16) {
221 dev_err(espi->dev,
222 "MSB-first transfer not supported for wordsize %u\n",
223 first->bits_per_word);
224 return -EINVAL;
225 }
226
227 return 0;
228 }
229
230 static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
231 {
232 struct spi_transfer *t;
233 unsigned int i = 0, rxskip = 0;
234
235 /*
236 * prerequisites for ESPI rxskip mode:
237 * - message has two transfers
238 * - first transfer is a write and second is a read
239 *
240 * In addition the current low-level transfer mechanism requires
241 * that the rxskip bytes fit into the TX FIFO. Else the transfer
242 * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
243 * the TX FIFO isn't re-filled.
244 */
245 list_for_each_entry(t, &m->transfers, transfer_list) {
246 if (i == 0) {
247 if (!t->tx_buf || t->rx_buf ||
248 t->len > FSL_ESPI_FIFO_SIZE)
249 return 0;
250 rxskip = t->len;
251 } else if (i == 1) {
252 if (t->tx_buf || !t->rx_buf)
253 return 0;
254 }
255 i++;
256 }
257
258 return i == 2 ? rxskip : 0;
259 }
260
261 static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
262 {
263 u32 tx_fifo_avail;
264
265 /* if events is zero transfer has not started and tx fifo is empty */
266 tx_fifo_avail = events ? SPIE_TXCNT(events) : FSL_ESPI_FIFO_SIZE;
267
268 while (tx_fifo_avail >= min(4U, espi->tx_len) && espi->tx_len)
269 if (espi->tx_len >= 4) {
270 fsl_espi_write_reg(espi, ESPI_SPITF, *(u32 *)espi->tx);
271 espi->tx += 4;
272 espi->tx_len -= 4;
273 tx_fifo_avail -= 4;
274 } else {
275 fsl_espi_write_reg8(espi, ESPI_SPITF, *(u8 *)espi->tx);
276 espi->tx += 1;
277 espi->tx_len -= 1;
278 tx_fifo_avail -= 1;
279 }
280 }
281
282 static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
283 {
284 u32 rx_fifo_avail = SPIE_RXCNT(events);
285
286 while (rx_fifo_avail >= min(4U, espi->rx_len) && espi->rx_len)
287 if (espi->rx_len >= 4) {
288 *(u32 *)espi->rx = fsl_espi_read_reg(espi, ESPI_SPIRF);
289 espi->rx += 4;
290 espi->rx_len -= 4;
291 rx_fifo_avail -= 4;
292 } else {
293 *(u8 *)espi->rx = fsl_espi_read_reg8(espi, ESPI_SPIRF);
294 espi->rx += 1;
295 espi->rx_len -= 1;
296 rx_fifo_avail -= 1;
297 }
298 }
299
300 static void fsl_espi_setup_transfer(struct spi_device *spi,
301 struct spi_transfer *t)
302 {
303 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
304 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
305 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
306 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
307 u32 hw_mode_old = cs->hw_mode;
308
309 /* mask out bits we are going to set */
310 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
311
312 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
313
314 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
315
316 if (pm > 15) {
317 cs->hw_mode |= CSMODE_DIV16;
318 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
319
320 WARN_ONCE(pm > 15,
321 "%s: Requested speed is too low: %u Hz. Will use %u Hz instead.\n",
322 dev_name(&spi->dev), hz,
323 espi->spibrg / (4 * 16 * (15 + 1)));
324 if (pm > 15)
325 pm = 15;
326 }
327
328 cs->hw_mode |= CSMODE_PM(pm);
329
330 /* don't write the mode register if the mode doesn't change */
331 if (cs->hw_mode != hw_mode_old)
332 fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
333 cs->hw_mode);
334 }
335
336 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
337 {
338 struct fsl_espi *espi = spi_master_get_devdata(spi->master);
339 u32 mask, spcom;
340 int ret;
341
342 espi->rx_len = t->len;
343 espi->tx_len = t->len;
344
345 espi->tx = t->tx_buf;
346 espi->rx = t->rx_buf;
347
348 reinit_completion(&espi->done);
349
350 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
351 spcom = SPCOM_CS(spi->chip_select);
352 spcom |= SPCOM_TRANLEN(t->len - 1);
353
354 /* configure RXSKIP mode */
355 if (espi->rxskip) {
356 spcom |= SPCOM_RXSKIP(espi->rxskip);
357 espi->tx_len = espi->rxskip;
358 espi->rx_len = t->len - espi->rxskip;
359 espi->rx = t->rx_buf + espi->rxskip;
360 if (t->rx_nbits == SPI_NBITS_DUAL)
361 spcom |= SPCOM_DO;
362 }
363
364 fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
365
366 /* enable interrupts */
367 mask = SPIM_DON;
368 if (espi->rx_len > FSL_ESPI_FIFO_SIZE)
369 mask |= SPIM_RXT;
370 fsl_espi_write_reg(espi, ESPI_SPIM, mask);
371
372 /* Prevent filling the fifo from getting interrupted */
373 spin_lock_irq(&espi->lock);
374 fsl_espi_fill_tx_fifo(espi, 0);
375 spin_unlock_irq(&espi->lock);
376
377 /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
378 ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
379 if (ret == 0)
380 dev_err(espi->dev,
381 "Transaction hanging up (left %u tx bytes, %u rx bytes)\n",
382 espi->tx_len, espi->rx_len);
383
384 /* disable rx ints */
385 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
386
387 return ret == 0 ? -ETIMEDOUT : 0;
388 }
389
390 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
391 {
392 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
393 struct spi_device *spi = m->spi;
394 int ret;
395
396 espi->rxskip = fsl_espi_check_rxskip_mode(m);
397 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
398 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
399 return -EINVAL;
400 }
401
402 fsl_espi_copy_to_buf(m, espi);
403 fsl_espi_setup_transfer(spi, trans);
404
405 ret = fsl_espi_bufs(spi, trans);
406
407 if (trans->delay_usecs)
408 udelay(trans->delay_usecs);
409
410 if (!ret)
411 fsl_espi_copy_from_buf(m, espi);
412
413 return ret;
414 }
415
416 static int fsl_espi_do_one_msg(struct spi_master *master,
417 struct spi_message *m)
418 {
419 struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
420 unsigned int delay_usecs = 0, rx_nbits = 0;
421 struct spi_transfer *t, trans = {};
422 int ret;
423
424 ret = fsl_espi_check_message(m);
425 if (ret)
426 goto out;
427
428 list_for_each_entry(t, &m->transfers, transfer_list) {
429 if (t->delay_usecs > delay_usecs)
430 delay_usecs = t->delay_usecs;
431 if (t->rx_nbits > rx_nbits)
432 rx_nbits = t->rx_nbits;
433 }
434
435 t = list_first_entry(&m->transfers, struct spi_transfer,
436 transfer_list);
437
438 trans.len = m->frame_length;
439 trans.speed_hz = t->speed_hz;
440 trans.bits_per_word = t->bits_per_word;
441 trans.delay_usecs = delay_usecs;
442 trans.tx_buf = espi->local_buf;
443 trans.rx_buf = espi->local_buf;
444 trans.rx_nbits = rx_nbits;
445
446 if (trans.len)
447 ret = fsl_espi_trans(m, &trans);
448
449 m->actual_length = ret ? 0 : trans.len;
450 out:
451 if (m->status == -EINPROGRESS)
452 m->status = ret;
453
454 spi_finalize_current_message(master);
455
456 return ret;
457 }
458
459 static int fsl_espi_setup(struct spi_device *spi)
460 {
461 struct fsl_espi *espi;
462 u32 loop_mode;
463 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
464
465 if (!spi->max_speed_hz)
466 return -EINVAL;
467
468 if (!cs) {
469 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
470 if (!cs)
471 return -ENOMEM;
472 spi_set_ctldata(spi, cs);
473 }
474
475 espi = spi_master_get_devdata(spi->master);
476
477 pm_runtime_get_sync(espi->dev);
478
479 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
480 /* mask out bits we are going to set */
481 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
482 | CSMODE_REV);
483
484 if (spi->mode & SPI_CPHA)
485 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
486 if (spi->mode & SPI_CPOL)
487 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
488 if (!(spi->mode & SPI_LSB_FIRST))
489 cs->hw_mode |= CSMODE_REV;
490
491 /* Handle the loop mode */
492 loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
493 loop_mode &= ~SPMODE_LOOP;
494 if (spi->mode & SPI_LOOP)
495 loop_mode |= SPMODE_LOOP;
496 fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
497
498 fsl_espi_setup_transfer(spi, NULL);
499
500 pm_runtime_mark_last_busy(espi->dev);
501 pm_runtime_put_autosuspend(espi->dev);
502
503 return 0;
504 }
505
506 static void fsl_espi_cleanup(struct spi_device *spi)
507 {
508 struct fsl_espi_cs *cs = spi_get_ctldata(spi);
509
510 kfree(cs);
511 spi_set_ctldata(spi, NULL);
512 }
513
514 static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
515 {
516 if (espi->rx_len)
517 fsl_espi_read_rx_fifo(espi, events);
518
519 if (espi->tx_len)
520 fsl_espi_fill_tx_fifo(espi, events);
521
522 if (espi->tx_len || espi->rx_len)
523 return;
524
525 /* we're done, but check for errors before returning */
526 events = fsl_espi_read_reg(espi, ESPI_SPIE);
527
528 if (!(events & SPIE_DON))
529 dev_err(espi->dev,
530 "Transfer done but SPIE_DON isn't set!\n");
531
532 if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE)
533 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
534
535 complete(&espi->done);
536 }
537
538 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
539 {
540 struct fsl_espi *espi = context_data;
541 u32 events;
542
543 spin_lock(&espi->lock);
544
545 /* Get interrupt events(tx/rx) */
546 events = fsl_espi_read_reg(espi, ESPI_SPIE);
547 if (!events) {
548 spin_unlock(&espi->lock);
549 return IRQ_NONE;
550 }
551
552 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
553
554 fsl_espi_cpu_irq(espi, events);
555
556 /* Clear the events */
557 fsl_espi_write_reg(espi, ESPI_SPIE, events);
558
559 spin_unlock(&espi->lock);
560
561 return IRQ_HANDLED;
562 }
563
564 #ifdef CONFIG_PM
565 static int fsl_espi_runtime_suspend(struct device *dev)
566 {
567 struct spi_master *master = dev_get_drvdata(dev);
568 struct fsl_espi *espi = spi_master_get_devdata(master);
569 u32 regval;
570
571 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
572 regval &= ~SPMODE_ENABLE;
573 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
574
575 return 0;
576 }
577
578 static int fsl_espi_runtime_resume(struct device *dev)
579 {
580 struct spi_master *master = dev_get_drvdata(dev);
581 struct fsl_espi *espi = spi_master_get_devdata(master);
582 u32 regval;
583
584 regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
585 regval |= SPMODE_ENABLE;
586 fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
587
588 return 0;
589 }
590 #endif
591
592 static size_t fsl_espi_max_message_size(struct spi_device *spi)
593 {
594 return SPCOM_TRANLEN_MAX;
595 }
596
597 static void fsl_espi_init_regs(struct device *dev, bool initial)
598 {
599 struct spi_master *master = dev_get_drvdata(dev);
600 struct fsl_espi *espi = spi_master_get_devdata(master);
601 struct device_node *nc;
602 u32 csmode, cs, prop;
603 int ret;
604
605 /* SPI controller initializations */
606 fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
607 fsl_espi_write_reg(espi, ESPI_SPIM, 0);
608 fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
609 fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
610
611 /* Init eSPI CS mode register */
612 for_each_available_child_of_node(master->dev.of_node, nc) {
613 /* get chip select */
614 ret = of_property_read_u32(nc, "reg", &cs);
615 if (ret || cs >= master->num_chipselect)
616 continue;
617
618 csmode = CSMODE_INIT_VAL;
619
620 /* check if CSBEF is set in device tree */
621 ret = of_property_read_u32(nc, "fsl,csbef", &prop);
622 if (!ret) {
623 csmode &= ~(CSMODE_BEF(0xf));
624 csmode |= CSMODE_BEF(prop);
625 }
626
627 /* check if CSAFT is set in device tree */
628 ret = of_property_read_u32(nc, "fsl,csaft", &prop);
629 if (!ret) {
630 csmode &= ~(CSMODE_AFT(0xf));
631 csmode |= CSMODE_AFT(prop);
632 }
633
634 fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
635
636 if (initial)
637 dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
638 }
639
640 /* Enable SPI interface */
641 fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
642 }
643
644 static int fsl_espi_probe(struct device *dev, struct resource *mem,
645 unsigned int irq, unsigned int num_cs)
646 {
647 struct spi_master *master;
648 struct fsl_espi *espi;
649 int ret;
650
651 master = spi_alloc_master(dev, sizeof(struct fsl_espi));
652 if (!master)
653 return -ENOMEM;
654
655 dev_set_drvdata(dev, master);
656
657 master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
658 SPI_LSB_FIRST | SPI_LOOP;
659 master->dev.of_node = dev->of_node;
660 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
661 master->setup = fsl_espi_setup;
662 master->cleanup = fsl_espi_cleanup;
663 master->transfer_one_message = fsl_espi_do_one_msg;
664 master->auto_runtime_pm = true;
665 master->max_message_size = fsl_espi_max_message_size;
666 master->num_chipselect = num_cs;
667
668 espi = spi_master_get_devdata(master);
669 spin_lock_init(&espi->lock);
670
671 espi->dev = dev;
672 espi->spibrg = fsl_get_sys_freq();
673 if (espi->spibrg == -1) {
674 dev_err(dev, "Can't get sys frequency!\n");
675 ret = -EINVAL;
676 goto err_probe;
677 }
678
679 init_completion(&espi->done);
680
681 espi->local_buf = devm_kmalloc(dev, SPCOM_TRANLEN_MAX, GFP_KERNEL);
682 if (!espi->local_buf) {
683 ret = -ENOMEM;
684 goto err_probe;
685 }
686
687 espi->reg_base = devm_ioremap_resource(dev, mem);
688 if (IS_ERR(espi->reg_base)) {
689 ret = PTR_ERR(espi->reg_base);
690 goto err_probe;
691 }
692
693 /* Register for SPI Interrupt */
694 ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
695 if (ret)
696 goto err_probe;
697
698 fsl_espi_init_regs(dev, true);
699
700 pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
701 pm_runtime_use_autosuspend(dev);
702 pm_runtime_set_active(dev);
703 pm_runtime_enable(dev);
704 pm_runtime_get_sync(dev);
705
706 ret = devm_spi_register_master(dev, master);
707 if (ret < 0)
708 goto err_pm;
709
710 dev_info(dev, "at 0x%p (irq = %u)\n", espi->reg_base, irq);
711
712 pm_runtime_mark_last_busy(dev);
713 pm_runtime_put_autosuspend(dev);
714
715 return 0;
716
717 err_pm:
718 pm_runtime_put_noidle(dev);
719 pm_runtime_disable(dev);
720 pm_runtime_set_suspended(dev);
721 err_probe:
722 spi_master_put(master);
723 return ret;
724 }
725
726 static int of_fsl_espi_get_chipselects(struct device *dev)
727 {
728 struct device_node *np = dev->of_node;
729 u32 num_cs;
730 int ret;
731
732 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
733 if (ret) {
734 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
735 return 0;
736 }
737
738 return num_cs;
739 }
740
741 static int of_fsl_espi_probe(struct platform_device *ofdev)
742 {
743 struct device *dev = &ofdev->dev;
744 struct device_node *np = ofdev->dev.of_node;
745 struct resource mem;
746 unsigned int irq, num_cs;
747 int ret;
748
749 if (of_property_read_bool(np, "mode")) {
750 dev_err(dev, "mode property is not supported on ESPI!\n");
751 return -EINVAL;
752 }
753
754 num_cs = of_fsl_espi_get_chipselects(dev);
755 if (!num_cs)
756 return -EINVAL;
757
758 ret = of_address_to_resource(np, 0, &mem);
759 if (ret)
760 return ret;
761
762 irq = irq_of_parse_and_map(np, 0);
763 if (!irq)
764 return -EINVAL;
765
766 return fsl_espi_probe(dev, &mem, irq, num_cs);
767 }
768
769 static int of_fsl_espi_remove(struct platform_device *dev)
770 {
771 pm_runtime_disable(&dev->dev);
772
773 return 0;
774 }
775
776 #ifdef CONFIG_PM_SLEEP
777 static int of_fsl_espi_suspend(struct device *dev)
778 {
779 struct spi_master *master = dev_get_drvdata(dev);
780 int ret;
781
782 ret = spi_master_suspend(master);
783 if (ret) {
784 dev_warn(dev, "cannot suspend master\n");
785 return ret;
786 }
787
788 ret = pm_runtime_force_suspend(dev);
789 if (ret < 0)
790 return ret;
791
792 return 0;
793 }
794
795 static int of_fsl_espi_resume(struct device *dev)
796 {
797 struct spi_master *master = dev_get_drvdata(dev);
798 int ret;
799
800 fsl_espi_init_regs(dev, false);
801
802 ret = pm_runtime_force_resume(dev);
803 if (ret < 0)
804 return ret;
805
806 return spi_master_resume(master);
807 }
808 #endif /* CONFIG_PM_SLEEP */
809
810 static const struct dev_pm_ops espi_pm = {
811 SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
812 fsl_espi_runtime_resume, NULL)
813 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
814 };
815
816 static const struct of_device_id of_fsl_espi_match[] = {
817 { .compatible = "fsl,mpc8536-espi" },
818 {}
819 };
820 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
821
822 static struct platform_driver fsl_espi_driver = {
823 .driver = {
824 .name = "fsl_espi",
825 .of_match_table = of_fsl_espi_match,
826 .pm = &espi_pm,
827 },
828 .probe = of_fsl_espi_probe,
829 .remove = of_fsl_espi_remove,
830 };
831 module_platform_driver(fsl_espi_driver);
832
833 MODULE_AUTHOR("Mingkai Hu");
834 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
835 MODULE_LICENSE("GPL");
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