drivers/gpio/gpio-mt7621.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   4  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
   5  */
   6
   7 #include <linux/err.h>
   8 #include <linux/gpio/driver.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spinlock.h>
  15
  16 #define MTK_BANK_CNT    3
  17 #define MTK_BANK_WIDTH  32
  18
  19 #define GPIO_BANK_STRIDE        0x04
  20 #define GPIO_REG_CTRL           0x00
  21 #define GPIO_REG_POL            0x10
  22 #define GPIO_REG_DATA           0x20
  23 #define GPIO_REG_DSET           0x30
  24 #define GPIO_REG_DCLR           0x40
  25 #define GPIO_REG_REDGE          0x50
  26 #define GPIO_REG_FEDGE          0x60
  27 #define GPIO_REG_HLVL           0x70
  28 #define GPIO_REG_LLVL           0x80
  29 #define GPIO_REG_STAT           0x90
  30 #define GPIO_REG_EDGE           0xA0
  31
  32 struct mtk_gc {
  33         struct gpio_chip chip;
  34         spinlock_t lock;
  35         int bank;
  36         u32 rising;
  37         u32 falling;
  38         u32 hlevel;
  39         u32 llevel;
  40 };
  41
  42 /**
  43  * struct mtk - state container for
  44  * data of the platform driver. It is 3
  45  * separate gpio-chip each one with its
  46  * own irq_chip.
  47  * @dev: device instance
  48  * @base: memory base address
  49  * @gpio_irq: irq number from the device tree
  50  * @gc_map: array of the gpio chips
  51  */
  52 struct mtk {
  53         struct device *dev;
  54         void __iomem *base;
  55         int gpio_irq;
  56         struct mtk_gc gc_map[MTK_BANK_CNT];
  57 };
  58
  59 static inline struct mtk_gc *
  60 to_mediatek_gpio(struct gpio_chip *chip)
  61 {
  62         return container_of(chip, struct mtk_gc, chip);
  63 }
  64
  65 static inline void
  66 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
  67 {
  68         struct gpio_chip *gc = &rg->chip;
  69         struct mtk *mtk = gpiochip_get_data(gc);
  70
  71         offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  72         gc->write_reg(mtk->base + offset, val);
  73 }
  74
  75 static inline u32
  76 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
  77 {
  78         struct gpio_chip *gc = &rg->chip;
  79         struct mtk *mtk = gpiochip_get_data(gc);
  80
  81         offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  82         return gc->read_reg(mtk->base + offset);
  83 }
  84
  85 static irqreturn_t
  86 mediatek_gpio_irq_handler(int irq, void *data)
  87 {
  88         struct gpio_chip *gc = data;
  89         struct mtk_gc *rg = to_mediatek_gpio(gc);
  90         irqreturn_t ret = IRQ_NONE;
  91         unsigned long pending;
  92         int bit;
  93
  94         pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
  95
  96         for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
  97                 u32 map = irq_find_mapping(gc->irq.domain, bit);
  98
  99                 generic_handle_irq(map);
 100                 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
 101                 ret |= IRQ_HANDLED;
 102         }
 103
 104         return ret;
 105 }
 106
 107 static void
 108 mediatek_gpio_irq_unmask(struct irq_data *d)
 109 {
 110         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 111         struct mtk_gc *rg = to_mediatek_gpio(gc);
 112         int pin = d->hwirq;
 113         unsigned long flags;
 114         u32 rise, fall, high, low;
 115
 116         spin_lock_irqsave(&rg->lock, flags);
 117         rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 118         fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 119         high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
 120         low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
 121         mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
 122         mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
 123         mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
 124         mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
 125         spin_unlock_irqrestore(&rg->lock, flags);
 126 }
 127
 128 static void
 129 mediatek_gpio_irq_mask(struct irq_data *d)
 130 {
 131         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 132         struct mtk_gc *rg = to_mediatek_gpio(gc);
 133         int pin = d->hwirq;
 134         unsigned long flags;
 135         u32 rise, fall, high, low;
 136
 137         spin_lock_irqsave(&rg->lock, flags);
 138         rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
 139         fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
 140         high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
 141         low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
 142         mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
 143         mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
 144         mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
 145         mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
 146         spin_unlock_irqrestore(&rg->lock, flags);
 147 }
 148
 149 static int
 150 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
 151 {
 152         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 153         struct mtk_gc *rg = to_mediatek_gpio(gc);
 154         int pin = d->hwirq;
 155         u32 mask = BIT(pin);
 156
 157         if (type == IRQ_TYPE_PROBE) {
 158                 if ((rg->rising | rg->falling |
 159                      rg->hlevel | rg->llevel) & mask)
 160                         return 0;
 161
 162                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 163         }
 164
 165         rg->rising &= ~mask;
 166         rg->falling &= ~mask;
 167         rg->hlevel &= ~mask;
 168         rg->llevel &= ~mask;
 169
 170         switch (type & IRQ_TYPE_SENSE_MASK) {
 171         case IRQ_TYPE_EDGE_BOTH:
 172                 rg->rising |= mask;
 173                 rg->falling |= mask;
 174                 break;
 175         case IRQ_TYPE_EDGE_RISING:
 176                 rg->rising |= mask;
 177                 break;
 178         case IRQ_TYPE_EDGE_FALLING:
 179                 rg->falling |= mask;
 180                 break;
 181         case IRQ_TYPE_LEVEL_HIGH:
 182                 rg->hlevel |= mask;
 183                 break;
 184         case IRQ_TYPE_LEVEL_LOW:
 185                 rg->llevel |= mask;
 186                 break;
 187         }
 188
 189         return 0;
 190 }
 191
 192 static struct irq_chip mediatek_gpio_irq_chip = {
 193         .irq_unmask             = mediatek_gpio_irq_unmask,
 194         .irq_mask               = mediatek_gpio_irq_mask,
 195         .irq_mask_ack           = mediatek_gpio_irq_mask,
 196         .irq_set_type           = mediatek_gpio_irq_type,
 197 };
 198
 199 static int
 200 mediatek_gpio_xlate(struct gpio_chip *chip,
 201                     const struct of_phandle_args *spec, u32 *flags)
 202 {
 203         int gpio = spec->args[0];
 204         struct mtk_gc *rg = to_mediatek_gpio(chip);
 205
 206         if (rg->bank != gpio / MTK_BANK_WIDTH)
 207                 return -EINVAL;
 208
 209         if (flags)
 210                 *flags = spec->args[1];
 211
 212         return gpio % MTK_BANK_WIDTH;
 213 }
 214
 215 static int
 216 mediatek_gpio_bank_probe(struct device *dev,
 217                          struct device_node *node, int bank)
 218 {
 219         struct mtk *mtk = dev_get_drvdata(dev);
 220         struct mtk_gc *rg;
 221         void __iomem *dat, *set, *ctrl, *diro;
 222         int ret;
 223
 224         rg = &mtk->gc_map[bank];
 225         memset(rg, 0, sizeof(*rg));
 226
 227         spin_lock_init(&rg->lock);
 228         rg->chip.of_node = node;
 229         rg->bank = bank;
 230
 231         dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
 232         set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
 233         ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
 234         diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
 235
 236         ret = bgpio_init(&rg->chip, dev, 4,
 237                          dat, set, ctrl, diro, NULL, 0);
 238         if (ret) {
 239                 dev_err(dev, "bgpio_init() failed\n");
 240                 return ret;
 241         }
 242
 243         rg->chip.of_gpio_n_cells = 2;
 244         rg->chip.of_xlate = mediatek_gpio_xlate;
 245         rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
 246                                         dev_name(dev), bank);
 247
 248         ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
 249         if (ret < 0) {
 250                 dev_err(dev, "Could not register gpio %d, ret=%d\n",
 251                         rg->chip.ngpio, ret);
 252                 return ret;
 253         }
 254
 255         if (mtk->gpio_irq) {
 256                 /*
 257                  * Manually request the irq here instead of passing
 258                  * a flow-handler to gpiochip_set_chained_irqchip,
 259                  * because the irq is shared.
 260                  */
 261                 ret = devm_request_irq(dev, mtk->gpio_irq,
 262                                        mediatek_gpio_irq_handler, IRQF_SHARED,
 263                                        rg->chip.label, &rg->chip);
 264
 265                 if (ret) {
 266                         dev_err(dev, "Error requesting IRQ %d: %d\n",
 267                                 mtk->gpio_irq, ret);
 268                         return ret;
 269                 }
 270
 271                 ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip,
 272                                            0, handle_simple_irq, IRQ_TYPE_NONE);
 273                 if (ret) {
 274                         dev_err(dev, "failed to add gpiochip_irqchip\n");
 275                         return ret;
 276                 }
 277
 278                 gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip,
 279                                              mtk->gpio_irq, NULL);
 280         }
 281
 282         /* set polarity to low for all gpios */
 283         mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 284
 285         dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
 286
 287         return 0;
 288 }
 289
 290 static int
 291 mediatek_gpio_probe(struct platform_device *pdev)
 292 {
 293         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 294         struct device *dev = &pdev->dev;
 295         struct device_node *np = dev->of_node;
 296         struct mtk *mtk;
 297         int i;
 298
 299         mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
 300         if (!mtk)
 301                 return -ENOMEM;
 302
 303         mtk->base = devm_ioremap_resource(dev, res);
 304         if (IS_ERR(mtk->base))
 305                 return PTR_ERR(mtk->base);
 306
 307         mtk->gpio_irq = irq_of_parse_and_map(np, 0);
 308         mtk->dev = dev;
 309         platform_set_drvdata(pdev, mtk);
 310         mediatek_gpio_irq_chip.name = dev_name(dev);
 311
 312         for (i = 0; i < MTK_BANK_CNT; i++)
 313                 mediatek_gpio_bank_probe(dev, np, i);
 314
 315         return 0;
 316 }
 317
 318 static const struct of_device_id mediatek_gpio_match[] = {
 319         { .compatible = "mediatek,mt7621-gpio" },
 320         {},
 321 };
 322 MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 323
 324 static struct platform_driver mediatek_gpio_driver = {
 325         .probe = mediatek_gpio_probe,
 326         .driver = {
 327                 .name = "mt7621_gpio",
 328                 .of_match_table = mediatek_gpio_match,
 329         },
 330 };
 331
 332 builtin_platform_driver(mediatek_gpio_driver);