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ARM: OMAP4: remove duplicated include from omap_hwmod_44xx_data.c
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c
blobb5efe58c0be09cb4953dfcb70e0e93f21524a721
1 /*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
14 */
15
16 #include <linux/i2c-omap.h>
17 #include <linux/platform_data/spi-omap2-mcspi.h>
18 #include <linux/omap-dma.h>
19 #include <plat/dmtimer.h>
20
21 #include "omap_hwmod.h"
22 #include "l3_2xxx.h"
23 #include "l4_2xxx.h"
24
25 #include "omap_hwmod_common_data.h"
26
27 #include "cm-regbits-24xx.h"
28 #include "prm-regbits-24xx.h"
29 #include "i2c.h"
30 #include "mmc.h"
31 #include "serial.h"
32 #include "wd_timer.h"
33
34 /*
35 * OMAP2420 hardware module integration data
36 *
37 * All of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
40 * elsewhere.
41 */
42
43 /*
44 * IP blocks
45 */
46
47 /* IVA1 (IVA1) */
48 static struct omap_hwmod_class iva1_hwmod_class = {
49 .name = "iva1",
50 };
51
52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
53 { .name = "iva", .rst_shift = 8 },
54 };
55
56 static struct omap_hwmod omap2420_iva_hwmod = {
57 .name = "iva",
58 .class = &iva1_hwmod_class,
59 .clkdm_name = "iva1_clkdm",
60 .rst_lines = omap2420_iva_resets,
61 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
62 .main_clk = "iva1_ifck",
63 };
64
65 /* DSP */
66 static struct omap_hwmod_class dsp_hwmod_class = {
67 .name = "dsp",
68 };
69
70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
71 { .name = "logic", .rst_shift = 0 },
72 { .name = "mmu", .rst_shift = 1 },
73 };
74
75 static struct omap_hwmod omap2420_dsp_hwmod = {
76 .name = "dsp",
77 .class = &dsp_hwmod_class,
78 .clkdm_name = "dsp_clkdm",
79 .rst_lines = omap2420_dsp_resets,
80 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
81 .main_clk = "dsp_fck",
82 };
83
84 /* I2C common */
85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
86 .rev_offs = 0x00,
87 .sysc_offs = 0x20,
88 .syss_offs = 0x10,
89 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
90 .sysc_fields = &omap_hwmod_sysc_type1,
91 };
92
93 static struct omap_hwmod_class i2c_class = {
94 .name = "i2c",
95 .sysc = &i2c_sysc,
96 .rev = OMAP_I2C_IP_VERSION_1,
97 .reset = &omap_i2c_reset,
98 };
99
100 static struct omap_i2c_dev_attr i2c_dev_attr = {
101 .flags = OMAP_I2C_FLAG_NO_FIFO |
102 OMAP_I2C_FLAG_SIMPLE_CLOCK |
103 OMAP_I2C_FLAG_16BIT_DATA_REG |
104 OMAP_I2C_FLAG_BUS_SHIFT_2,
105 };
106
107 /* I2C1 */
108 static struct omap_hwmod omap2420_i2c1_hwmod = {
109 .name = "i2c1",
110 .mpu_irqs = omap2_i2c1_mpu_irqs,
111 .sdma_reqs = omap2_i2c1_sdma_reqs,
112 .main_clk = "i2c1_fck",
113 .prcm = {
114 .omap2 = {
115 .module_offs = CORE_MOD,
116 .prcm_reg_id = 1,
117 .module_bit = OMAP2420_EN_I2C1_SHIFT,
118 .idlest_reg_id = 1,
119 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
120 },
121 },
122 .class = &i2c_class,
123 .dev_attr = &i2c_dev_attr,
124 .flags = HWMOD_16BIT_REG,
125 };
126
127 /* I2C2 */
128 static struct omap_hwmod omap2420_i2c2_hwmod = {
129 .name = "i2c2",
130 .mpu_irqs = omap2_i2c2_mpu_irqs,
131 .sdma_reqs = omap2_i2c2_sdma_reqs,
132 .main_clk = "i2c2_fck",
133 .prcm = {
134 .omap2 = {
135 .module_offs = CORE_MOD,
136 .prcm_reg_id = 1,
137 .module_bit = OMAP2420_EN_I2C2_SHIFT,
138 .idlest_reg_id = 1,
139 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
140 },
141 },
142 .class = &i2c_class,
143 .dev_attr = &i2c_dev_attr,
144 .flags = HWMOD_16BIT_REG,
145 };
146
147 /* dma attributes */
148 static struct omap_dma_dev_attr dma_dev_attr = {
149 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
150 IS_CSSA_32 | IS_CDSA_32,
151 .lch_count = 32,
152 };
153
154 static struct omap_hwmod omap2420_dma_system_hwmod = {
155 .name = "dma",
156 .class = &omap2xxx_dma_hwmod_class,
157 .mpu_irqs = omap2_dma_system_irqs,
158 .main_clk = "core_l3_ck",
159 .dev_attr = &dma_dev_attr,
160 .flags = HWMOD_NO_IDLEST,
161 };
162
163 /* mailbox */
164 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
165 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
166 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
167 { .irq = -1 },
168 };
169
170 static struct omap_hwmod omap2420_mailbox_hwmod = {
171 .name = "mailbox",
172 .class = &omap2xxx_mailbox_hwmod_class,
173 .mpu_irqs = omap2420_mailbox_irqs,
174 .main_clk = "mailboxes_ick",
175 .prcm = {
176 .omap2 = {
177 .prcm_reg_id = 1,
178 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
179 .module_offs = CORE_MOD,
180 .idlest_reg_id = 1,
181 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
182 },
183 },
184 };
185
186 /*
187 * 'mcbsp' class
188 * multi channel buffered serial port controller
189 */
190
191 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
192 .name = "mcbsp",
193 };
194
195 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
196 { .role = "pad_fck", .clk = "mcbsp_clks" },
197 { .role = "prcm_fck", .clk = "func_96m_ck" },
198 };
199
200 /* mcbsp1 */
201 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
202 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
203 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
204 { .irq = -1 },
205 };
206
207 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
208 .name = "mcbsp1",
209 .class = &omap2420_mcbsp_hwmod_class,
210 .mpu_irqs = omap2420_mcbsp1_irqs,
211 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
212 .main_clk = "mcbsp1_fck",
213 .prcm = {
214 .omap2 = {
215 .prcm_reg_id = 1,
216 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
217 .module_offs = CORE_MOD,
218 .idlest_reg_id = 1,
219 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
220 },
221 },
222 .opt_clks = mcbsp_opt_clks,
223 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
224 };
225
226 /* mcbsp2 */
227 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
228 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
229 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
230 { .irq = -1 },
231 };
232
233 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
234 .name = "mcbsp2",
235 .class = &omap2420_mcbsp_hwmod_class,
236 .mpu_irqs = omap2420_mcbsp2_irqs,
237 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
238 .main_clk = "mcbsp2_fck",
239 .prcm = {
240 .omap2 = {
241 .prcm_reg_id = 1,
242 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
243 .module_offs = CORE_MOD,
244 .idlest_reg_id = 1,
245 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
246 },
247 },
248 .opt_clks = mcbsp_opt_clks,
249 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
250 };
251
252 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
253 .rev_offs = 0x3c,
254 .sysc_offs = 0x64,
255 .syss_offs = 0x68,
256 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
257 .sysc_fields = &omap_hwmod_sysc_type1,
258 };
259
260 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
261 .name = "msdi",
262 .sysc = &omap2420_msdi_sysc,
263 .reset = &omap_msdi_reset,
264 };
265
266 /* msdi1 */
267 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
268 { .irq = 83 + OMAP_INTC_START, },
269 { .irq = -1 },
270 };
271
272 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
273 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
274 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
275 { .dma_req = -1 }
276 };
277
278 static struct omap_hwmod omap2420_msdi1_hwmod = {
279 .name = "msdi1",
280 .class = &omap2420_msdi_hwmod_class,
281 .mpu_irqs = omap2420_msdi1_irqs,
282 .sdma_reqs = omap2420_msdi1_sdma_reqs,
283 .main_clk = "mmc_fck",
284 .prcm = {
285 .omap2 = {
286 .prcm_reg_id = 1,
287 .module_bit = OMAP2420_EN_MMC_SHIFT,
288 .module_offs = CORE_MOD,
289 .idlest_reg_id = 1,
290 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
291 },
292 },
293 .flags = HWMOD_16BIT_REG,
294 };
295
296 /* HDQ1W/1-wire */
297 static struct omap_hwmod omap2420_hdq1w_hwmod = {
298 .name = "hdq1w",
299 .mpu_irqs = omap2_hdq1w_mpu_irqs,
300 .main_clk = "hdq_fck",
301 .prcm = {
302 .omap2 = {
303 .module_offs = CORE_MOD,
304 .prcm_reg_id = 1,
305 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
306 .idlest_reg_id = 1,
307 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
308 },
309 },
310 .class = &omap2_hdq1w_class,
311 };
312
313 /*
314 * interfaces
315 */
316
317 /* L4 CORE -> I2C1 interface */
318 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
319 .master = &omap2xxx_l4_core_hwmod,
320 .slave = &omap2420_i2c1_hwmod,
321 .clk = "i2c1_ick",
322 .addr = omap2_i2c1_addr_space,
323 .user = OCP_USER_MPU | OCP_USER_SDMA,
324 };
325
326 /* L4 CORE -> I2C2 interface */
327 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
328 .master = &omap2xxx_l4_core_hwmod,
329 .slave = &omap2420_i2c2_hwmod,
330 .clk = "i2c2_ick",
331 .addr = omap2_i2c2_addr_space,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333 };
334
335 /* IVA <- L3 interface */
336 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
337 .master = &omap2xxx_l3_main_hwmod,
338 .slave = &omap2420_iva_hwmod,
339 .clk = "core_l3_ck",
340 .user = OCP_USER_MPU | OCP_USER_SDMA,
341 };
342
343 /* DSP <- L3 interface */
344 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
345 .master = &omap2xxx_l3_main_hwmod,
346 .slave = &omap2420_dsp_hwmod,
347 .clk = "dsp_ick",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349 };
350
351 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
352 {
353 .pa_start = 0x48028000,
354 .pa_end = 0x48028000 + SZ_1K - 1,
355 .flags = ADDR_TYPE_RT
356 },
357 { }
358 };
359
360 /* l4_wkup -> timer1 */
361 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
362 .master = &omap2xxx_l4_wkup_hwmod,
363 .slave = &omap2xxx_timer1_hwmod,
364 .clk = "gpt1_ick",
365 .addr = omap2420_timer1_addrs,
366 .user = OCP_USER_MPU | OCP_USER_SDMA,
367 };
368
369 /* l4_wkup -> wd_timer2 */
370 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
371 {
372 .pa_start = 0x48022000,
373 .pa_end = 0x4802207f,
374 .flags = ADDR_TYPE_RT
375 },
376 { }
377 };
378
379 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
380 .master = &omap2xxx_l4_wkup_hwmod,
381 .slave = &omap2xxx_wd_timer2_hwmod,
382 .clk = "mpu_wdt_ick",
383 .addr = omap2420_wd_timer2_addrs,
384 .user = OCP_USER_MPU | OCP_USER_SDMA,
385 };
386
387 /* l4_wkup -> gpio1 */
388 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
389 {
390 .pa_start = 0x48018000,
391 .pa_end = 0x480181ff,
392 .flags = ADDR_TYPE_RT
393 },
394 { }
395 };
396
397 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
398 .master = &omap2xxx_l4_wkup_hwmod,
399 .slave = &omap2xxx_gpio1_hwmod,
400 .clk = "gpios_ick",
401 .addr = omap2420_gpio1_addr_space,
402 .user = OCP_USER_MPU | OCP_USER_SDMA,
403 };
404
405 /* l4_wkup -> gpio2 */
406 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
407 {
408 .pa_start = 0x4801a000,
409 .pa_end = 0x4801a1ff,
410 .flags = ADDR_TYPE_RT
411 },
412 { }
413 };
414
415 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
416 .master = &omap2xxx_l4_wkup_hwmod,
417 .slave = &omap2xxx_gpio2_hwmod,
418 .clk = "gpios_ick",
419 .addr = omap2420_gpio2_addr_space,
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
421 };
422
423 /* l4_wkup -> gpio3 */
424 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
425 {
426 .pa_start = 0x4801c000,
427 .pa_end = 0x4801c1ff,
428 .flags = ADDR_TYPE_RT
429 },
430 { }
431 };
432
433 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
434 .master = &omap2xxx_l4_wkup_hwmod,
435 .slave = &omap2xxx_gpio3_hwmod,
436 .clk = "gpios_ick",
437 .addr = omap2420_gpio3_addr_space,
438 .user = OCP_USER_MPU | OCP_USER_SDMA,
439 };
440
441 /* l4_wkup -> gpio4 */
442 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
443 {
444 .pa_start = 0x4801e000,
445 .pa_end = 0x4801e1ff,
446 .flags = ADDR_TYPE_RT
447 },
448 { }
449 };
450
451 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
452 .master = &omap2xxx_l4_wkup_hwmod,
453 .slave = &omap2xxx_gpio4_hwmod,
454 .clk = "gpios_ick",
455 .addr = omap2420_gpio4_addr_space,
456 .user = OCP_USER_MPU | OCP_USER_SDMA,
457 };
458
459 /* dma_system -> L3 */
460 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
461 .master = &omap2420_dma_system_hwmod,
462 .slave = &omap2xxx_l3_main_hwmod,
463 .clk = "core_l3_ck",
464 .user = OCP_USER_MPU | OCP_USER_SDMA,
465 };
466
467 /* l4_core -> dma_system */
468 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
469 .master = &omap2xxx_l4_core_hwmod,
470 .slave = &omap2420_dma_system_hwmod,
471 .clk = "sdma_ick",
472 .addr = omap2_dma_system_addrs,
473 .user = OCP_USER_MPU | OCP_USER_SDMA,
474 };
475
476 /* l4_core -> mailbox */
477 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
478 .master = &omap2xxx_l4_core_hwmod,
479 .slave = &omap2420_mailbox_hwmod,
480 .addr = omap2_mailbox_addrs,
481 .user = OCP_USER_MPU | OCP_USER_SDMA,
482 };
483
484 /* l4_core -> mcbsp1 */
485 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
486 .master = &omap2xxx_l4_core_hwmod,
487 .slave = &omap2420_mcbsp1_hwmod,
488 .clk = "mcbsp1_ick",
489 .addr = omap2_mcbsp1_addrs,
490 .user = OCP_USER_MPU | OCP_USER_SDMA,
491 };
492
493 /* l4_core -> mcbsp2 */
494 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
495 .master = &omap2xxx_l4_core_hwmod,
496 .slave = &omap2420_mcbsp2_hwmod,
497 .clk = "mcbsp2_ick",
498 .addr = omap2xxx_mcbsp2_addrs,
499 .user = OCP_USER_MPU | OCP_USER_SDMA,
500 };
501
502 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
503 {
504 .pa_start = 0x4809c000,
505 .pa_end = 0x4809c000 + SZ_128 - 1,
506 .flags = ADDR_TYPE_RT,
507 },
508 { }
509 };
510
511 /* l4_core -> msdi1 */
512 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
513 .master = &omap2xxx_l4_core_hwmod,
514 .slave = &omap2420_msdi1_hwmod,
515 .clk = "mmc_ick",
516 .addr = omap2420_msdi1_addrs,
517 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 };
519
520 /* l4_core -> hdq1w interface */
521 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
522 .master = &omap2xxx_l4_core_hwmod,
523 .slave = &omap2420_hdq1w_hwmod,
524 .clk = "hdq_ick",
525 .addr = omap2_hdq1w_addr_space,
526 .user = OCP_USER_MPU | OCP_USER_SDMA,
527 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
528 };
529
530
531 /* l4_wkup -> 32ksync_counter */
532 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
533 {
534 .pa_start = 0x48004000,
535 .pa_end = 0x4800401f,
536 .flags = ADDR_TYPE_RT
537 },
538 { }
539 };
540
541 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
542 {
543 .pa_start = 0x6800a000,
544 .pa_end = 0x6800afff,
545 .flags = ADDR_TYPE_RT
546 },
547 { }
548 };
549
550 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
551 .master = &omap2xxx_l4_wkup_hwmod,
552 .slave = &omap2xxx_counter_32k_hwmod,
553 .clk = "sync_32k_ick",
554 .addr = omap2420_counter_32k_addrs,
555 .user = OCP_USER_MPU | OCP_USER_SDMA,
556 };
557
558 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
559 .master = &omap2xxx_l3_main_hwmod,
560 .slave = &omap2xxx_gpmc_hwmod,
561 .clk = "core_l3_ck",
562 .addr = omap2420_gpmc_addrs,
563 .user = OCP_USER_MPU | OCP_USER_SDMA,
564 };
565
566 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
567 &omap2xxx_l3_main__l4_core,
568 &omap2xxx_mpu__l3_main,
569 &omap2xxx_dss__l3,
570 &omap2xxx_l4_core__mcspi1,
571 &omap2xxx_l4_core__mcspi2,
572 &omap2xxx_l4_core__l4_wkup,
573 &omap2_l4_core__uart1,
574 &omap2_l4_core__uart2,
575 &omap2_l4_core__uart3,
576 &omap2420_l4_core__i2c1,
577 &omap2420_l4_core__i2c2,
578 &omap2420_l3__iva,
579 &omap2420_l3__dsp,
580 &omap2420_l4_wkup__timer1,
581 &omap2xxx_l4_core__timer2,
582 &omap2xxx_l4_core__timer3,
583 &omap2xxx_l4_core__timer4,
584 &omap2xxx_l4_core__timer5,
585 &omap2xxx_l4_core__timer6,
586 &omap2xxx_l4_core__timer7,
587 &omap2xxx_l4_core__timer8,
588 &omap2xxx_l4_core__timer9,
589 &omap2xxx_l4_core__timer10,
590 &omap2xxx_l4_core__timer11,
591 &omap2xxx_l4_core__timer12,
592 &omap2420_l4_wkup__wd_timer2,
593 &omap2xxx_l4_core__dss,
594 &omap2xxx_l4_core__dss_dispc,
595 &omap2xxx_l4_core__dss_rfbi,
596 &omap2xxx_l4_core__dss_venc,
597 &omap2420_l4_wkup__gpio1,
598 &omap2420_l4_wkup__gpio2,
599 &omap2420_l4_wkup__gpio3,
600 &omap2420_l4_wkup__gpio4,
601 &omap2420_dma_system__l3,
602 &omap2420_l4_core__dma_system,
603 &omap2420_l4_core__mailbox,
604 &omap2420_l4_core__mcbsp1,
605 &omap2420_l4_core__mcbsp2,
606 &omap2420_l4_core__msdi1,
607 &omap2xxx_l4_core__rng,
608 &omap2420_l4_core__hdq1w,
609 &omap2420_l4_wkup__counter_32k,
610 &omap2420_l3__gpmc,
611 NULL,
612 };
613
614 int __init omap2420_hwmod_init(void)
615 {
616 omap_hwmod_init();
617 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
618 }
(deprecated) Btrfs devel tree