arch/arm/mach-omap2/clock36xx.c

   1 /*
   2  * OMAP36xx-specific clkops
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  *
   7  * Mike Turquette
   8  * Vijaykumar GN
   9  * Paul Walmsley
  10  *
  11  * Parts of this code are based on code written by
  12  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
  13  * Russell King
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #undef DEBUG
  20
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24
  25 #include "clock.h"
  26 #include "clock36xx.h"
  27
  28
  29 /**
  30  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
  31  *         from HSDivider PWRDN problem Implements Errata ID: i556.
  32  * @clk: DPLL output struct clk
  33  *
  34  * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
  35  * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
  36  * valueafter their respective PWRDN bits are set.  Any dummy write
  37  * (Any other value different from the Read value) to the
  38  * corresponding CM_CLKSEL register will refresh the dividers.
  39  */
  40 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
  41 {
  42         struct clk_hw_omap *parent;
  43         struct clk_hw *parent_hw;
  44         u32 dummy_v, orig_v, clksel_shift;
  45         int ret;
  46
  47         /* Clear PWRDN bit of HSDIVIDER */
  48         ret = omap2_dflt_clk_enable(clk);
  49
  50         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
  51         parent = to_clk_hw_omap(parent_hw);
  52
  53         /* Restore the dividers */
  54         if (!ret) {
  55                 clksel_shift = __ffs(parent->clksel_mask);
  56                 orig_v = __raw_readl(parent->clksel_reg);
  57                 dummy_v = orig_v;
  58
  59                 /* Write any other value different from the Read value */
  60                 dummy_v ^= (1 << clksel_shift);
  61                 __raw_writel(dummy_v, parent->clksel_reg);
  62
  63                 /* Write the original divider */
  64                 __raw_writel(orig_v, parent->clksel_reg);
  65         }
  66
  67         return ret;
  68 }