1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 I915_MAX_PIPES
= _PIPE_EDP
64 #define pipe_name(p) ((p) + 'A')
73 #define transcoder_name(t) ((t) + 'A')
80 #define plane_name(p) ((p) + 'A')
82 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
92 #define port_name(p) ((p) + 'A')
94 #define I915_NUM_PHYS_VLV 1
106 enum intel_display_power_domain
{
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
113 POWER_DOMAIN_TRANSCODER_A
,
114 POWER_DOMAIN_TRANSCODER_B
,
115 POWER_DOMAIN_TRANSCODER_C
,
116 POWER_DOMAIN_TRANSCODER_EDP
,
117 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
118 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
119 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
120 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
121 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
122 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
123 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
124 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
125 POWER_DOMAIN_PORT_DSI
,
126 POWER_DOMAIN_PORT_CRT
,
127 POWER_DOMAIN_PORT_OTHER
,
135 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
136 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
138 #define POWER_DOMAIN_TRANSCODER(tran) \
139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
140 (tran) + POWER_DOMAIN_TRANSCODER_A)
144 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
145 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
155 #define I915_GEM_GPU_DOMAINS \
156 (I915_GEM_DOMAIN_RENDER | \
157 I915_GEM_DOMAIN_SAMPLER | \
158 I915_GEM_DOMAIN_COMMAND | \
159 I915_GEM_DOMAIN_INSTRUCTION | \
160 I915_GEM_DOMAIN_VERTEX)
162 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
165 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
166 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
167 if ((intel_encoder)->base.crtc == (__crtc))
169 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
170 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
171 if ((intel_connector)->base.encoder == (__encoder))
173 struct drm_i915_private
;
176 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
177 /* real shared dpll ids must be >= 0 */
181 #define I915_NUM_PLLS 2
183 struct intel_dpll_hw_state
{
190 struct intel_shared_dpll
{
191 int refcount
; /* count of number of CRTCs sharing this PLL */
192 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
193 bool on
; /* is the PLL actually active? Disabled during modeset */
195 /* should match the index in the dev_priv->shared_dplls array */
196 enum intel_dpll_id id
;
197 struct intel_dpll_hw_state hw_state
;
198 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
199 struct intel_shared_dpll
*pll
);
200 void (*enable
)(struct drm_i915_private
*dev_priv
,
201 struct intel_shared_dpll
*pll
);
202 void (*disable
)(struct drm_i915_private
*dev_priv
,
203 struct intel_shared_dpll
*pll
);
204 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
205 struct intel_shared_dpll
*pll
,
206 struct intel_dpll_hw_state
*hw_state
);
209 /* Used by dp and fdi links */
210 struct intel_link_m_n
{
218 void intel_link_compute_m_n(int bpp
, int nlanes
,
219 int pixel_clock
, int link_clock
,
220 struct intel_link_m_n
*m_n
);
222 struct intel_ddi_plls
{
228 /* Interface history:
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
238 #define DRIVER_MAJOR 1
239 #define DRIVER_MINOR 6
240 #define DRIVER_PATCHLEVEL 0
242 #define WATCH_LISTS 0
245 #define I915_GEM_PHYS_CURSOR_0 1
246 #define I915_GEM_PHYS_CURSOR_1 2
247 #define I915_GEM_PHYS_OVERLAY_REGS 3
248 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250 struct drm_i915_gem_phys_object
{
252 struct page
**page_list
;
253 drm_dma_handle_t
*handle
;
254 struct drm_i915_gem_object
*cur_obj
;
257 struct opregion_header
;
258 struct opregion_acpi
;
259 struct opregion_swsci
;
260 struct opregion_asle
;
262 struct intel_opregion
{
263 struct opregion_header __iomem
*header
;
264 struct opregion_acpi __iomem
*acpi
;
265 struct opregion_swsci __iomem
*swsci
;
266 u32 swsci_gbda_sub_functions
;
267 u32 swsci_sbcb_sub_functions
;
268 struct opregion_asle __iomem
*asle
;
270 u32 __iomem
*lid_state
;
271 struct work_struct asle_work
;
273 #define OPREGION_SIZE (8*1024)
275 struct intel_overlay
;
276 struct intel_overlay_error_state
;
278 struct drm_i915_master_private
{
279 drm_local_map_t
*sarea
;
280 struct _drm_i915_sarea
*sarea_priv
;
282 #define I915_FENCE_REG_NONE -1
283 #define I915_MAX_NUM_FENCES 32
284 /* 32 fences + sign bit for FENCE_REG_NONE */
285 #define I915_MAX_NUM_FENCE_BITS 6
287 struct drm_i915_fence_reg
{
288 struct list_head lru_list
;
289 struct drm_i915_gem_object
*obj
;
293 struct sdvo_device_mapping
{
302 struct intel_display_error_state
;
304 struct drm_i915_error_state
{
312 /* Generic register state */
319 u32 error
; /* gen6+ */
320 u32 err_int
; /* gen7 */
326 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
327 u32 pipestat
[I915_MAX_PIPES
];
328 u64 fence
[I915_MAX_NUM_FENCES
];
329 struct intel_overlay_error_state
*overlay
;
330 struct intel_display_error_state
*display
;
332 struct drm_i915_error_ring
{
334 /* Software tracked state */
337 enum intel_ring_hangcheck_action hangcheck_action
;
340 /* our own tracking of ring head and tail */
344 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
362 u32 rc_psmi
; /* sleep state */
363 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
365 struct drm_i915_error_object
{
369 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
371 struct drm_i915_error_request
{
386 char comm
[TASK_COMM_LEN
];
387 } ring
[I915_NUM_RINGS
];
388 struct drm_i915_error_buffer
{
395 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
402 } **active_bo
, **pinned_bo
;
404 u32
*active_bo_count
, *pinned_bo_count
;
407 struct intel_connector
;
408 struct intel_crtc_config
;
413 struct drm_i915_display_funcs
{
414 bool (*fbc_enabled
)(struct drm_device
*dev
);
415 void (*enable_fbc
)(struct drm_crtc
*crtc
);
416 void (*disable_fbc
)(struct drm_device
*dev
);
417 int (*get_display_clock_speed
)(struct drm_device
*dev
);
418 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
420 * find_dpll() - Find the best values for the PLL
421 * @limit: limits for the PLL
422 * @crtc: current CRTC
423 * @target: target frequency in kHz
424 * @refclk: reference clock frequency in kHz
425 * @match_clock: if provided, @best_clock P divider must
426 * match the P divider from @match_clock
427 * used for LVDS downclocking
428 * @best_clock: best PLL values found
430 * Returns true on success, false on failure.
432 bool (*find_dpll
)(const struct intel_limit
*limit
,
433 struct drm_crtc
*crtc
,
434 int target
, int refclk
,
435 struct dpll
*match_clock
,
436 struct dpll
*best_clock
);
437 void (*update_wm
)(struct drm_crtc
*crtc
);
438 void (*update_sprite_wm
)(struct drm_plane
*plane
,
439 struct drm_crtc
*crtc
,
440 uint32_t sprite_width
, int pixel_size
,
441 bool enable
, bool scaled
);
442 void (*modeset_global_resources
)(struct drm_device
*dev
);
443 /* Returns the active state of the crtc, and if the crtc is active,
444 * fills out the pipe-config with the hw state. */
445 bool (*get_pipe_config
)(struct intel_crtc
*,
446 struct intel_crtc_config
*);
447 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
449 struct drm_framebuffer
*old_fb
);
450 void (*crtc_enable
)(struct drm_crtc
*crtc
);
451 void (*crtc_disable
)(struct drm_crtc
*crtc
);
452 void (*off
)(struct drm_crtc
*crtc
);
453 void (*write_eld
)(struct drm_connector
*connector
,
454 struct drm_crtc
*crtc
,
455 struct drm_display_mode
*mode
);
456 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
457 void (*init_clock_gating
)(struct drm_device
*dev
);
458 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
459 struct drm_framebuffer
*fb
,
460 struct drm_i915_gem_object
*obj
,
462 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
464 void (*hpd_irq_setup
)(struct drm_device
*dev
);
465 /* clock updates for mode set */
467 /* render clock increase/decrease */
468 /* display clock increase/decrease */
469 /* pll clock increase/decrease */
471 int (*setup_backlight
)(struct intel_connector
*connector
);
472 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
473 void (*set_backlight
)(struct intel_connector
*connector
,
475 void (*disable_backlight
)(struct intel_connector
*connector
);
476 void (*enable_backlight
)(struct intel_connector
*connector
);
479 struct intel_uncore_funcs
{
480 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
482 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
485 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
486 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
487 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
488 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
490 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
491 uint8_t val
, bool trace
);
492 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
493 uint16_t val
, bool trace
);
494 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
495 uint32_t val
, bool trace
);
496 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
497 uint64_t val
, bool trace
);
500 struct intel_uncore
{
501 spinlock_t lock
; /** lock is also taken in irq contexts. */
503 struct intel_uncore_funcs funcs
;
506 unsigned forcewake_count
;
508 unsigned fw_rendercount
;
509 unsigned fw_mediacount
;
511 struct timer_list force_wake_timer
;
514 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
515 func(is_mobile) sep \
518 func(is_i945gm) sep \
520 func(need_gfx_hws) sep \
522 func(is_pineview) sep \
523 func(is_broadwater) sep \
524 func(is_crestline) sep \
525 func(is_ivybridge) sep \
526 func(is_valleyview) sep \
527 func(is_haswell) sep \
528 func(is_preliminary) sep \
530 func(has_pipe_cxsr) sep \
531 func(has_hotplug) sep \
532 func(cursor_needs_physical) sep \
533 func(has_overlay) sep \
534 func(overlay_needs_physical) sep \
535 func(supports_tv) sep \
540 #define DEFINE_FLAG(name) u8 name:1
541 #define SEP_SEMICOLON ;
543 struct intel_device_info
{
544 u32 display_mmio_offset
;
546 u8 num_sprites
[I915_MAX_PIPES
];
548 u8 ring_mask
; /* Rings supported by the HW */
549 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
550 /* Register offsets for the various display pipes and transcoders */
551 int pipe_offsets
[I915_MAX_TRANSCODERS
];
552 int trans_offsets
[I915_MAX_TRANSCODERS
];
553 int dpll_offsets
[I915_MAX_PIPES
];
554 int dpll_md_offsets
[I915_MAX_PIPES
];
555 int palette_offsets
[I915_MAX_PIPES
];
561 enum i915_cache_level
{
563 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
564 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
565 caches, eg sampler/render caches, and the
566 large Last-Level-Cache. LLC is coherent with
567 the CPU, but L3 is only visible to the GPU. */
568 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
571 typedef uint32_t gen6_gtt_pte_t
;
574 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
575 * VMA's presence cannot be guaranteed before binding, or after unbinding the
576 * object into/from the address space.
578 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
579 * will always be <= an objects lifetime. So object refcounting should cover us.
582 struct drm_mm_node node
;
583 struct drm_i915_gem_object
*obj
;
584 struct i915_address_space
*vm
;
586 /** This object's place on the active/inactive lists */
587 struct list_head mm_list
;
589 struct list_head vma_link
; /* Link in the object's VMA list */
591 /** This vma's place in the batchbuffer or on the eviction list */
592 struct list_head exec_list
;
595 * Used for performing relocations during execbuffer insertion.
597 struct hlist_node exec_node
;
598 unsigned long exec_handle
;
599 struct drm_i915_gem_exec_object2
*exec_entry
;
602 * How many users have pinned this object in GTT space. The following
603 * users can each hold at most one reference: pwrite/pread, pin_ioctl
604 * (via user_pin_count), execbuffer (objects are not allowed multiple
605 * times for the same batchbuffer), and the framebuffer code. When
606 * switching/pageflipping, the framebuffer code has at most two buffers
609 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
610 * bits with absolutely no headroom. So use 4 bits. */
611 unsigned int pin_count
:4;
612 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
614 /** Unmap an object from an address space. This usually consists of
615 * setting the valid PTE entries to a reserved scratch page. */
616 void (*unbind_vma
)(struct i915_vma
*vma
);
617 /* Map an object into an address space with the given cache flags. */
618 #define GLOBAL_BIND (1<<0)
619 void (*bind_vma
)(struct i915_vma
*vma
,
620 enum i915_cache_level cache_level
,
624 struct i915_address_space
{
626 struct drm_device
*dev
;
627 struct list_head global_link
;
628 unsigned long start
; /* Start offset always 0 for dri2 */
629 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
637 * List of objects currently involved in rendering.
639 * Includes buffers having the contents of their GPU caches
640 * flushed, not necessarily primitives. last_rendering_seqno
641 * represents when the rendering involved will be completed.
643 * A reference is held on the buffer while on this list.
645 struct list_head active_list
;
648 * LRU list of objects which are not in the ringbuffer and
649 * are ready to unbind, but are still in the GTT.
651 * last_rendering_seqno is 0 while an object is in this list.
653 * A reference is not held on the buffer while on this list,
654 * as merely being GTT-bound shouldn't prevent its being
655 * freed, and we'll pull it off the list in the free path.
657 struct list_head inactive_list
;
659 /* FIXME: Need a more generic return type */
660 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
661 enum i915_cache_level level
,
662 bool valid
); /* Create a valid PTE */
663 void (*clear_range
)(struct i915_address_space
*vm
,
667 void (*insert_entries
)(struct i915_address_space
*vm
,
670 enum i915_cache_level cache_level
);
671 void (*cleanup
)(struct i915_address_space
*vm
);
674 /* The Graphics Translation Table is the way in which GEN hardware translates a
675 * Graphics Virtual Address into a Physical Address. In addition to the normal
676 * collateral associated with any va->pa translations GEN hardware also has a
677 * portion of the GTT which can be mapped by the CPU and remain both coherent
678 * and correct (in cases like swizzling). That region is referred to as GMADR in
682 struct i915_address_space base
;
683 size_t stolen_size
; /* Total size of stolen memory */
685 unsigned long mappable_end
; /* End offset that we can CPU map */
686 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
687 phys_addr_t mappable_base
; /* PA of our GMADR */
689 /** "Graphics Stolen Memory" holds the global PTEs */
697 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
698 size_t *stolen
, phys_addr_t
*mappable_base
,
699 unsigned long *mappable_end
);
701 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
703 #define GEN8_LEGACY_PDPS 4
704 struct i915_hw_ppgtt
{
705 struct i915_address_space base
;
707 struct drm_mm_node node
;
708 unsigned num_pd_entries
;
709 unsigned num_pd_pages
; /* gen8+ */
711 struct page
**pt_pages
;
712 struct page
**gen8_pt_pages
[GEN8_LEGACY_PDPS
];
714 struct page
*pd_pages
;
717 dma_addr_t pd_dma_addr
[GEN8_LEGACY_PDPS
];
720 dma_addr_t
*pt_dma_addr
;
721 dma_addr_t
*gen8_pt_dma_addr
[4];
724 int (*enable
)(struct i915_hw_ppgtt
*ppgtt
);
725 int (*switch_mm
)(struct i915_hw_ppgtt
*ppgtt
,
726 struct intel_ring_buffer
*ring
,
728 void (*debug_dump
)(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
);
731 struct i915_ctx_hang_stats
{
732 /* This context had batch pending when hang was declared */
733 unsigned batch_pending
;
735 /* This context had batch active when hang was declared */
736 unsigned batch_active
;
738 /* Time when this context was last blamed for a GPU reset */
739 unsigned long guilty_ts
;
741 /* This context is banned to submit more work */
745 /* This must match up with the value previously used for execbuf2.rsvd1. */
746 #define DEFAULT_CONTEXT_ID 0
747 struct i915_hw_context
{
752 struct drm_i915_file_private
*file_priv
;
753 struct intel_ring_buffer
*last_ring
;
754 struct drm_i915_gem_object
*obj
;
755 struct i915_ctx_hang_stats hang_stats
;
756 struct i915_address_space
*vm
;
758 struct list_head link
;
767 struct drm_mm_node
*compressed_fb
;
768 struct drm_mm_node
*compressed_llb
;
770 struct intel_fbc_work
{
771 struct delayed_work work
;
772 struct drm_crtc
*crtc
;
773 struct drm_framebuffer
*fb
;
777 FBC_OK
, /* FBC is enabled */
778 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
779 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
780 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
781 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
782 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
783 FBC_BAD_PLANE
, /* fbc not supported on plane */
784 FBC_NOT_TILED
, /* buffer not tiled */
785 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
787 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
797 PCH_NONE
= 0, /* No PCH present */
798 PCH_IBX
, /* Ibexpeak PCH */
799 PCH_CPT
, /* Cougarpoint PCH */
800 PCH_LPT
, /* Lynxpoint PCH */
804 enum intel_sbi_destination
{
809 #define QUIRK_PIPEA_FORCE (1<<0)
810 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
811 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
814 struct intel_fbc_work
;
817 struct i2c_adapter adapter
;
821 struct i2c_algo_bit_data bit_algo
;
822 struct drm_i915_private
*dev_priv
;
825 struct i915_suspend_saved_registers
{
846 u32 saveTRANS_HTOTAL_A
;
847 u32 saveTRANS_HBLANK_A
;
848 u32 saveTRANS_HSYNC_A
;
849 u32 saveTRANS_VTOTAL_A
;
850 u32 saveTRANS_VBLANK_A
;
851 u32 saveTRANS_VSYNC_A
;
859 u32 savePFIT_PGM_RATIOS
;
860 u32 saveBLC_HIST_CTL
;
862 u32 saveBLC_PWM_CTL2
;
863 u32 saveBLC_HIST_CTL_B
;
864 u32 saveBLC_CPU_PWM_CTL
;
865 u32 saveBLC_CPU_PWM_CTL2
;
878 u32 saveTRANS_HTOTAL_B
;
879 u32 saveTRANS_HBLANK_B
;
880 u32 saveTRANS_HSYNC_B
;
881 u32 saveTRANS_VTOTAL_B
;
882 u32 saveTRANS_VBLANK_B
;
883 u32 saveTRANS_VSYNC_B
;
897 u32 savePP_ON_DELAYS
;
898 u32 savePP_OFF_DELAYS
;
906 u32 savePFIT_CONTROL
;
907 u32 save_palette_a
[256];
908 u32 save_palette_b
[256];
919 u32 saveCACHE_MODE_0
;
920 u32 saveMI_ARB_STATE
;
931 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
942 u32 savePIPEA_GMCH_DATA_M
;
943 u32 savePIPEB_GMCH_DATA_M
;
944 u32 savePIPEA_GMCH_DATA_N
;
945 u32 savePIPEB_GMCH_DATA_N
;
946 u32 savePIPEA_DP_LINK_M
;
947 u32 savePIPEB_DP_LINK_M
;
948 u32 savePIPEA_DP_LINK_N
;
949 u32 savePIPEB_DP_LINK_N
;
960 u32 savePCH_DREF_CONTROL
;
961 u32 saveDISP_ARB_CTL
;
962 u32 savePIPEA_DATA_M1
;
963 u32 savePIPEA_DATA_N1
;
964 u32 savePIPEA_LINK_M1
;
965 u32 savePIPEA_LINK_N1
;
966 u32 savePIPEB_DATA_M1
;
967 u32 savePIPEB_DATA_N1
;
968 u32 savePIPEB_LINK_M1
;
969 u32 savePIPEB_LINK_N1
;
970 u32 saveMCHBAR_RENDER_STANDBY
;
971 u32 savePCH_PORT_HOTPLUG
;
974 struct intel_gen6_power_mgmt
{
975 /* work and pm_iir are protected by dev_priv->irq_lock */
976 struct work_struct work
;
991 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
994 struct delayed_work delayed_resume_work
;
997 * Protects RPS/RC6 register access and PCU communication.
998 * Must be taken after struct_mutex if nested.
1000 struct mutex hw_lock
;
1003 /* defined intel_pm.c */
1004 extern spinlock_t mchdev_lock
;
1006 struct intel_ilk_power_mgmt
{
1014 unsigned long last_time1
;
1015 unsigned long chipset_power
;
1017 struct timespec last_time2
;
1018 unsigned long gfx_power
;
1024 struct drm_i915_gem_object
*pwrctx
;
1025 struct drm_i915_gem_object
*renderctx
;
1028 struct drm_i915_private
;
1029 struct i915_power_well
;
1031 struct i915_power_well_ops
{
1033 * Synchronize the well's hw state to match the current sw state, for
1034 * example enable/disable it based on the current refcount. Called
1035 * during driver init and resume time, possibly after first calling
1036 * the enable/disable handlers.
1038 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1039 struct i915_power_well
*power_well
);
1041 * Enable the well and resources that depend on it (for example
1042 * interrupts located on the well). Called after the 0->1 refcount
1045 void (*enable
)(struct drm_i915_private
*dev_priv
,
1046 struct i915_power_well
*power_well
);
1048 * Disable the well and resources that depend on it. Called after
1049 * the 1->0 refcount transition.
1051 void (*disable
)(struct drm_i915_private
*dev_priv
,
1052 struct i915_power_well
*power_well
);
1053 /* Returns the hw enabled state. */
1054 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1055 struct i915_power_well
*power_well
);
1058 /* Power well structure for haswell */
1059 struct i915_power_well
{
1062 /* power well enable/disable usage count */
1064 unsigned long domains
;
1066 const struct i915_power_well_ops
*ops
;
1069 struct i915_power_domains
{
1071 * Power wells needed for initialization at driver init and suspend
1072 * time are on. They are kept on until after the first modeset.
1075 int power_well_count
;
1078 int domain_use_count
[POWER_DOMAIN_NUM
];
1079 struct i915_power_well
*power_wells
;
1082 struct i915_dri1_state
{
1083 unsigned allow_batchbuffer
: 1;
1084 u32 __iomem
*gfx_hws_cpu_addr
;
1095 struct i915_ums_state
{
1097 * Flag if the X Server, and thus DRM, is not currently in
1098 * control of the device.
1100 * This is set between LeaveVT and EnterVT. It needs to be
1101 * replaced with a semaphore. It also needs to be
1102 * transitioned away from for kernel modesetting.
1107 #define MAX_L3_SLICES 2
1108 struct intel_l3_parity
{
1109 u32
*remap_info
[MAX_L3_SLICES
];
1110 struct work_struct error_work
;
1114 struct i915_gem_mm
{
1115 /** Memory allocator for GTT stolen memory */
1116 struct drm_mm stolen
;
1117 /** List of all objects in gtt_space. Used to restore gtt
1118 * mappings on resume */
1119 struct list_head bound_list
;
1121 * List of objects which are not bound to the GTT (thus
1122 * are idle and not used by the GPU) but still have
1123 * (presumably uncached) pages still attached.
1125 struct list_head unbound_list
;
1127 /** Usable portion of the GTT for GEM */
1128 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1130 /** PPGTT used for aliasing the PPGTT with the GTT */
1131 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1133 struct shrinker inactive_shrinker
;
1134 bool shrinker_no_lock_stealing
;
1136 /** LRU list of objects with fence regs on them. */
1137 struct list_head fence_list
;
1140 * We leave the user IRQ off as much as possible,
1141 * but this means that requests will finish and never
1142 * be retired once the system goes idle. Set a timer to
1143 * fire periodically while the ring is running. When it
1144 * fires, go retire requests.
1146 struct delayed_work retire_work
;
1149 * When we detect an idle GPU, we want to turn on
1150 * powersaving features. So once we see that there
1151 * are no more requests outstanding and no more
1152 * arrive within a small period of time, we fire
1153 * off the idle_work.
1155 struct delayed_work idle_work
;
1158 * Are we in a non-interruptible section of code like
1164 * Is the GPU currently considered idle, or busy executing userspace
1165 * requests? Whilst idle, we attempt to power down the hardware and
1166 * display clocks. In order to reduce the effect on performance, there
1167 * is a slight delay before we do so.
1171 /** Bit 6 swizzling required for X tiling */
1172 uint32_t bit_6_swizzle_x
;
1173 /** Bit 6 swizzling required for Y tiling */
1174 uint32_t bit_6_swizzle_y
;
1176 /* storage for physical objects */
1177 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
1179 /* accounting, useful for userland debugging */
1180 spinlock_t object_stat_lock
;
1181 size_t object_memory
;
1185 struct drm_i915_error_state_buf
{
1194 struct i915_error_state_file_priv
{
1195 struct drm_device
*dev
;
1196 struct drm_i915_error_state
*error
;
1199 struct i915_gpu_error
{
1200 /* For hangcheck timer */
1201 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1202 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1203 /* Hang gpu twice in this window and your context gets banned */
1204 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1206 struct timer_list hangcheck_timer
;
1208 /* For reset and error_state handling. */
1210 /* Protected by the above dev->gpu_error.lock. */
1211 struct drm_i915_error_state
*first_error
;
1212 struct work_struct work
;
1215 unsigned long missed_irq_rings
;
1218 * State variable controlling the reset flow and count
1220 * This is a counter which gets incremented when reset is triggered,
1221 * and again when reset has been handled. So odd values (lowest bit set)
1222 * means that reset is in progress and even values that
1223 * (reset_counter >> 1):th reset was successfully completed.
1225 * If reset is not completed succesfully, the I915_WEDGE bit is
1226 * set meaning that hardware is terminally sour and there is no
1227 * recovery. All waiters on the reset_queue will be woken when
1230 * This counter is used by the wait_seqno code to notice that reset
1231 * event happened and it needs to restart the entire ioctl (since most
1232 * likely the seqno it waited for won't ever signal anytime soon).
1234 * This is important for lock-free wait paths, where no contended lock
1235 * naturally enforces the correct ordering between the bail-out of the
1236 * waiter and the gpu reset work code.
1238 atomic_t reset_counter
;
1240 #define I915_RESET_IN_PROGRESS_FLAG 1
1241 #define I915_WEDGED (1 << 31)
1244 * Waitqueue to signal when the reset has completed. Used by clients
1245 * that wait for dev_priv->mm.wedged to settle.
1247 wait_queue_head_t reset_queue
;
1249 /* For gpu hang simulation. */
1250 unsigned int stop_rings
;
1252 /* For missed irq/seqno simulation. */
1253 unsigned int test_irq_rings
;
1256 enum modeset_restore
{
1257 MODESET_ON_LID_OPEN
,
1262 struct ddi_vbt_port_info
{
1263 uint8_t hdmi_level_shift
;
1265 uint8_t supports_dvi
:1;
1266 uint8_t supports_hdmi
:1;
1267 uint8_t supports_dp
:1;
1270 struct intel_vbt_data
{
1271 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1272 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1275 unsigned int int_tv_support
:1;
1276 unsigned int lvds_dither
:1;
1277 unsigned int lvds_vbt
:1;
1278 unsigned int int_crt_support
:1;
1279 unsigned int lvds_use_ssc
:1;
1280 unsigned int display_clock_mode
:1;
1281 unsigned int fdi_rx_polarity_inverted
:1;
1283 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1288 int edp_preemphasis
;
1290 bool edp_initialized
;
1293 struct edp_power_seq edp_pps
;
1297 bool active_low_pwm
;
1308 union child_device_config
*child_dev
;
1310 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1313 enum intel_ddb_partitioning
{
1315 INTEL_DDB_PART_5_6
, /* IVB+ */
1318 struct intel_wm_level
{
1326 struct ilk_wm_values
{
1327 uint32_t wm_pipe
[3];
1329 uint32_t wm_lp_spr
[3];
1330 uint32_t wm_linetime
[3];
1332 enum intel_ddb_partitioning partitioning
;
1336 * This struct tracks the state needed for the Package C8+ feature.
1338 * Package states C8 and deeper are really deep PC states that can only be
1339 * reached when all the devices on the system allow it, so even if the graphics
1340 * device allows PC8+, it doesn't mean the system will actually get to these
1343 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1344 * is disabled and the GPU is idle. When these conditions are met, we manually
1345 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1348 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1349 * the state of some registers, so when we come back from PC8+ we need to
1350 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1351 * need to take care of the registers kept by RC6.
1353 * The interrupt disabling is part of the requirements. We can only leave the
1354 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1355 * can lock the machine.
1357 * Ideally every piece of our code that needs PC8+ disabled would call
1358 * hsw_disable_package_c8, which would increment disable_count and prevent the
1359 * system from reaching PC8+. But we don't have a symmetric way to do this for
1360 * everything, so we have the requirements_met variable. When we switch
1361 * requirements_met to true we decrease disable_count, and increase it in the
1362 * opposite case. The requirements_met variable is true when all the CRTCs,
1363 * encoders and the power well are disabled.
1365 * In addition to everything, we only actually enable PC8+ if disable_count
1366 * stays at zero for at least some seconds. This is implemented with the
1367 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1368 * consecutive times when all screens are disabled and some background app
1369 * queries the state of our connectors, or we have some application constantly
1370 * waking up to use the GPU. Only after the enable_work function actually
1371 * enables PC8+ the "enable" variable will become true, which means that it can
1372 * be false even if disable_count is 0.
1374 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1375 * goes back to false exactly before we reenable the IRQs. We use this variable
1376 * to check if someone is trying to enable/disable IRQs while they're supposed
1377 * to be disabled. This shouldn't happen and we'll print some error messages in
1378 * case it happens, but if it actually happens we'll also update the variables
1379 * inside struct regsave so when we restore the IRQs they will contain the
1380 * latest expected values.
1382 * For more, read "Display Sequences for Package C8" on our documentation.
1384 struct i915_package_c8
{
1385 bool requirements_met
;
1387 /* Only true after the delayed work task actually enables it. */
1391 struct delayed_work enable_work
;
1398 uint32_t gen6_pmimr
;
1402 struct i915_runtime_pm
{
1406 enum intel_pipe_crc_source
{
1407 INTEL_PIPE_CRC_SOURCE_NONE
,
1408 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1409 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1410 INTEL_PIPE_CRC_SOURCE_PF
,
1411 INTEL_PIPE_CRC_SOURCE_PIPE
,
1412 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1413 INTEL_PIPE_CRC_SOURCE_TV
,
1414 INTEL_PIPE_CRC_SOURCE_DP_B
,
1415 INTEL_PIPE_CRC_SOURCE_DP_C
,
1416 INTEL_PIPE_CRC_SOURCE_DP_D
,
1417 INTEL_PIPE_CRC_SOURCE_AUTO
,
1418 INTEL_PIPE_CRC_SOURCE_MAX
,
1421 struct intel_pipe_crc_entry
{
1426 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1427 struct intel_pipe_crc
{
1429 bool opened
; /* exclusive access to the result file */
1430 struct intel_pipe_crc_entry
*entries
;
1431 enum intel_pipe_crc_source source
;
1433 wait_queue_head_t wq
;
1436 typedef struct drm_i915_private
{
1437 struct drm_device
*dev
;
1438 struct kmem_cache
*slab
;
1440 const struct intel_device_info info
;
1442 int relative_constants_mode
;
1446 struct intel_uncore uncore
;
1448 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1451 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1452 * controller on different i2c buses. */
1453 struct mutex gmbus_mutex
;
1456 * Base address of the gmbus and gpio block.
1458 uint32_t gpio_mmio_base
;
1460 wait_queue_head_t gmbus_wait_queue
;
1462 struct pci_dev
*bridge_dev
;
1463 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1464 uint32_t last_seqno
, next_seqno
;
1466 drm_dma_handle_t
*status_page_dmah
;
1467 struct resource mch_res
;
1469 /* protects the irq masks */
1470 spinlock_t irq_lock
;
1472 bool display_irqs_enabled
;
1474 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1475 struct pm_qos_request pm_qos
;
1477 /* DPIO indirect register protection */
1478 struct mutex dpio_lock
;
1480 /** Cached value of IMR to avoid reads in updating the bitfield */
1483 u32 de_irq_mask
[I915_MAX_PIPES
];
1487 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1489 struct work_struct hotplug_work
;
1490 bool enable_hotplug_processing
;
1492 unsigned long hpd_last_jiffies
;
1497 HPD_MARK_DISABLED
= 2
1499 } hpd_stats
[HPD_NUM_PINS
];
1501 struct timer_list hotplug_reenable_timer
;
1503 struct i915_fbc fbc
;
1504 struct intel_opregion opregion
;
1505 struct intel_vbt_data vbt
;
1508 struct intel_overlay
*overlay
;
1510 /* backlight registers and fields in struct intel_panel */
1511 spinlock_t backlight_lock
;
1514 bool no_aux_handshake
;
1516 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1517 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1518 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1520 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1523 * wq - Driver workqueue for GEM.
1525 * NOTE: Work items scheduled here are not allowed to grab any modeset
1526 * locks, for otherwise the flushing done in the pageflip code will
1527 * result in deadlocks.
1529 struct workqueue_struct
*wq
;
1531 /* Display functions */
1532 struct drm_i915_display_funcs display
;
1534 /* PCH chipset type */
1535 enum intel_pch pch_type
;
1536 unsigned short pch_id
;
1538 unsigned long quirks
;
1540 enum modeset_restore modeset_restore
;
1541 struct mutex modeset_restore_lock
;
1543 struct list_head vm_list
; /* Global list of all address spaces */
1544 struct i915_gtt gtt
; /* VMA representing the global address space */
1546 struct i915_gem_mm mm
;
1548 /* Kernel Modesetting */
1550 struct sdvo_device_mapping sdvo_mappings
[2];
1552 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1553 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1554 wait_queue_head_t pending_flip_queue
;
1556 #ifdef CONFIG_DEBUG_FS
1557 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1560 int num_shared_dpll
;
1561 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1562 struct intel_ddi_plls ddi_plls
;
1563 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1565 /* Reclocking support */
1566 bool render_reclock_avail
;
1567 bool lvds_downclock_avail
;
1568 /* indicates the reduced downclock for LVDS*/
1572 bool mchbar_need_disable
;
1574 struct intel_l3_parity l3_parity
;
1576 /* Cannot be determined by PCIID. You must always read a register. */
1579 /* gen6+ rps state */
1580 struct intel_gen6_power_mgmt rps
;
1582 /* ilk-only ips/rps state. Everything in here is protected by the global
1583 * mchdev_lock in intel_pm.c */
1584 struct intel_ilk_power_mgmt ips
;
1586 struct i915_power_domains power_domains
;
1588 struct i915_psr psr
;
1590 struct i915_gpu_error gpu_error
;
1592 struct drm_i915_gem_object
*vlv_pctx
;
1594 #ifdef CONFIG_DRM_I915_FBDEV
1595 /* list of fbdev register on this device */
1596 struct intel_fbdev
*fbdev
;
1600 * The console may be contended at resume, but we don't
1601 * want it to block on it.
1603 struct work_struct console_resume_work
;
1605 struct drm_property
*broadcast_rgb_property
;
1606 struct drm_property
*force_audio_property
;
1608 uint32_t hw_context_size
;
1609 struct list_head context_list
;
1613 struct i915_suspend_saved_registers regfile
;
1617 * Raw watermark latency values:
1618 * in 0.1us units for WM0,
1619 * in 0.5us units for WM1+.
1622 uint16_t pri_latency
[5];
1624 uint16_t spr_latency
[5];
1626 uint16_t cur_latency
[5];
1628 /* current hardware state */
1629 struct ilk_wm_values hw
;
1632 struct i915_package_c8 pc8
;
1634 struct i915_runtime_pm pm
;
1636 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1638 struct i915_dri1_state dri1
;
1639 /* Old ums support infrastructure, same warning applies. */
1640 struct i915_ums_state ums
;
1643 } drm_i915_private_t
;
1645 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1647 return dev
->dev_private
;
1650 /* Iterate over initialised rings */
1651 #define for_each_ring(ring__, dev_priv__, i__) \
1652 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1653 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1655 enum hdmi_force_audio
{
1656 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1657 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1658 HDMI_AUDIO_AUTO
, /* trust EDID */
1659 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1662 #define I915_GTT_OFFSET_NONE ((u32)-1)
1664 struct drm_i915_gem_object_ops
{
1665 /* Interface between the GEM object and its backing storage.
1666 * get_pages() is called once prior to the use of the associated set
1667 * of pages before to binding them into the GTT, and put_pages() is
1668 * called after we no longer need them. As we expect there to be
1669 * associated cost with migrating pages between the backing storage
1670 * and making them available for the GPU (e.g. clflush), we may hold
1671 * onto the pages after they are no longer referenced by the GPU
1672 * in case they may be used again shortly (for example migrating the
1673 * pages to a different memory domain within the GTT). put_pages()
1674 * will therefore most likely be called when the object itself is
1675 * being released or under memory pressure (where we attempt to
1676 * reap pages for the shrinker).
1678 int (*get_pages
)(struct drm_i915_gem_object
*);
1679 void (*put_pages
)(struct drm_i915_gem_object
*);
1682 struct drm_i915_gem_object
{
1683 struct drm_gem_object base
;
1685 const struct drm_i915_gem_object_ops
*ops
;
1687 /** List of VMAs backed by this object */
1688 struct list_head vma_list
;
1690 /** Stolen memory for this object, instead of being backed by shmem. */
1691 struct drm_mm_node
*stolen
;
1692 struct list_head global_list
;
1694 struct list_head ring_list
;
1695 /** Used in execbuf to temporarily hold a ref */
1696 struct list_head obj_exec_link
;
1699 * This is set if the object is on the active lists (has pending
1700 * rendering and so a non-zero seqno), and is not set if it i s on
1701 * inactive (ready to be unbound) list.
1703 unsigned int active
:1;
1706 * This is set if the object has been written to since last bound
1709 unsigned int dirty
:1;
1712 * Fence register bits (if any) for this object. Will be set
1713 * as needed when mapped into the GTT.
1714 * Protected by dev->struct_mutex.
1716 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1719 * Advice: are the backing pages purgeable?
1721 unsigned int madv
:2;
1724 * Current tiling mode for the object.
1726 unsigned int tiling_mode
:2;
1728 * Whether the tiling parameters for the currently associated fence
1729 * register have changed. Note that for the purposes of tracking
1730 * tiling changes we also treat the unfenced register, the register
1731 * slot that the object occupies whilst it executes a fenced
1732 * command (such as BLT on gen2/3), as a "fence".
1734 unsigned int fence_dirty
:1;
1737 * Is the object at the current location in the gtt mappable and
1738 * fenceable? Used to avoid costly recalculations.
1740 unsigned int map_and_fenceable
:1;
1743 * Whether the current gtt mapping needs to be mappable (and isn't just
1744 * mappable by accident). Track pin and fault separate for a more
1745 * accurate mappable working set.
1747 unsigned int fault_mappable
:1;
1748 unsigned int pin_mappable
:1;
1749 unsigned int pin_display
:1;
1752 * Is the GPU currently using a fence to access this buffer,
1754 unsigned int pending_fenced_gpu_access
:1;
1755 unsigned int fenced_gpu_access
:1;
1757 unsigned int cache_level
:3;
1759 unsigned int has_aliasing_ppgtt_mapping
:1;
1760 unsigned int has_global_gtt_mapping
:1;
1761 unsigned int has_dma_mapping
:1;
1763 struct sg_table
*pages
;
1764 int pages_pin_count
;
1766 /* prime dma-buf support */
1767 void *dma_buf_vmapping
;
1770 struct intel_ring_buffer
*ring
;
1772 /** Breadcrumb of last rendering to the buffer. */
1773 uint32_t last_read_seqno
;
1774 uint32_t last_write_seqno
;
1775 /** Breadcrumb of last fenced GPU access to the buffer. */
1776 uint32_t last_fenced_seqno
;
1778 /** Current tiling stride for the object, if it's tiled. */
1781 /** References from framebuffers, locks out tiling changes. */
1782 unsigned long framebuffer_references
;
1784 /** Record of address bit 17 of each page at last unbind. */
1785 unsigned long *bit_17
;
1787 /** User space pin count and filp owning the pin */
1788 unsigned long user_pin_count
;
1789 struct drm_file
*pin_filp
;
1791 /** for phy allocated objects */
1792 struct drm_i915_gem_phys_object
*phys_obj
;
1795 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1798 * Request queue structure.
1800 * The request queue allows us to note sequence numbers that have been emitted
1801 * and may be associated with active buffers to be retired.
1803 * By keeping this list, we can avoid having to do questionable
1804 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1805 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1807 struct drm_i915_gem_request
{
1808 /** On Which ring this request was generated */
1809 struct intel_ring_buffer
*ring
;
1811 /** GEM sequence number associated with this request. */
1814 /** Position in the ringbuffer of the start of the request */
1817 /** Position in the ringbuffer of the end of the request */
1820 /** Context related to this request */
1821 struct i915_hw_context
*ctx
;
1823 /** Batch buffer related to this request if any */
1824 struct drm_i915_gem_object
*batch_obj
;
1826 /** Time at which this request was emitted, in jiffies. */
1827 unsigned long emitted_jiffies
;
1829 /** global list entry for this request */
1830 struct list_head list
;
1832 struct drm_i915_file_private
*file_priv
;
1833 /** file_priv list entry for this request */
1834 struct list_head client_list
;
1837 struct drm_i915_file_private
{
1838 struct drm_i915_private
*dev_priv
;
1839 struct drm_file
*file
;
1843 struct list_head request_list
;
1844 struct delayed_work idle_work
;
1846 struct idr context_idr
;
1848 struct i915_hw_context
*private_default_ctx
;
1849 atomic_t rps_wait_boost
;
1853 * A command that requires special handling by the command parser.
1855 struct drm_i915_cmd_descriptor
{
1857 * Flags describing how the command parser processes the command.
1859 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1860 * a length mask if not set
1861 * CMD_DESC_SKIP: The command is allowed but does not follow the
1862 * standard length encoding for the opcode range in
1864 * CMD_DESC_REJECT: The command is never allowed
1865 * CMD_DESC_REGISTER: The command should be checked against the
1866 * register whitelist for the appropriate ring
1867 * CMD_DESC_MASTER: The command is allowed if the submitting process
1871 #define CMD_DESC_FIXED (1<<0)
1872 #define CMD_DESC_SKIP (1<<1)
1873 #define CMD_DESC_REJECT (1<<2)
1874 #define CMD_DESC_REGISTER (1<<3)
1875 #define CMD_DESC_BITMASK (1<<4)
1876 #define CMD_DESC_MASTER (1<<5)
1879 * The command's unique identification bits and the bitmask to get them.
1880 * This isn't strictly the opcode field as defined in the spec and may
1881 * also include type, subtype, and/or subop fields.
1889 * The command's length. The command is either fixed length (i.e. does
1890 * not include a length field) or has a length field mask. The flag
1891 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1892 * a length mask. All command entries in a command table must include
1893 * length information.
1901 * Describes where to find a register address in the command to check
1902 * against the ring's register whitelist. Only valid if flags has the
1903 * CMD_DESC_REGISTER bit set.
1910 #define MAX_CMD_DESC_BITMASKS 3
1912 * Describes command checks where a particular dword is masked and
1913 * compared against an expected value. If the command does not match
1914 * the expected value, the parser rejects it. Only valid if flags has
1915 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1922 } bits
[MAX_CMD_DESC_BITMASKS
];
1926 * A table of commands requiring special handling by the command parser.
1928 * Each ring has an array of tables. Each table consists of an array of command
1929 * descriptors, which must be sorted with command opcodes in ascending order.
1931 struct drm_i915_cmd_table
{
1932 const struct drm_i915_cmd_descriptor
*table
;
1936 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1938 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1939 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1940 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1941 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1942 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1943 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1944 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1945 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1946 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1947 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1948 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1949 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1950 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1951 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1952 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1953 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1954 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1955 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1956 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1957 (dev)->pdev->device == 0x0152 || \
1958 (dev)->pdev->device == 0x015a)
1959 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1960 (dev)->pdev->device == 0x0106 || \
1961 (dev)->pdev->device == 0x010A)
1962 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1963 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1964 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1965 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1966 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1967 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1968 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1969 (((dev)->pdev->device & 0xf) == 0x2 || \
1970 ((dev)->pdev->device & 0xf) == 0x6 || \
1971 ((dev)->pdev->device & 0xf) == 0xe))
1972 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1973 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1974 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1975 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1976 ((dev)->pdev->device & 0x00F0) == 0x0020)
1977 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1980 * The genX designation typically refers to the render engine, so render
1981 * capability related checks should use IS_GEN, while display and other checks
1982 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1985 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1986 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1987 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1988 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1989 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1990 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1991 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1993 #define RENDER_RING (1<<RCS)
1994 #define BSD_RING (1<<VCS)
1995 #define BLT_RING (1<<BCS)
1996 #define VEBOX_RING (1<<VECS)
1997 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1998 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1999 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2000 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2001 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
2002 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2004 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2005 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
2006 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
2007 && !IS_BROADWELL(dev))
2008 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
2009 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
2011 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2012 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2014 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2015 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2017 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2018 * rows, which changed the alignment requirements and fence programming.
2020 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2022 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2023 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2024 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2025 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2026 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2028 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2029 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2030 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2032 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2034 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2035 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2036 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2037 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
2038 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
2040 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2041 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2042 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2043 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2044 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2045 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2047 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2048 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2049 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2050 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2051 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2052 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2054 /* DPF == dynamic parity feature */
2055 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2056 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2058 #define GT_FREQUENCY_MULTIPLIER 50
2060 #include "i915_trace.h"
2062 extern const struct drm_ioctl_desc i915_ioctls
[];
2063 extern int i915_max_ioctl
;
2065 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2066 extern int i915_resume(struct drm_device
*dev
);
2067 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2068 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2071 struct i915_params
{
2073 int panel_ignore_lid
;
2074 unsigned int powersave
;
2076 unsigned int lvds_downclock
;
2077 int lvds_channel_mode
;
2079 int vbt_sdvo_panel_type
;
2084 unsigned int preliminary_hw_support
;
2085 int disable_power_well
;
2089 int invert_brightness
;
2090 int enable_cmd_parser
;
2091 /* leave bools at the end to not create holes */
2092 bool enable_hangcheck
;
2094 bool prefault_disable
;
2096 bool disable_display
;
2098 extern struct i915_params i915 __read_mostly
;
2101 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2102 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2103 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2104 extern int i915_driver_unload(struct drm_device
*);
2105 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
2106 extern void i915_driver_lastclose(struct drm_device
* dev
);
2107 extern void i915_driver_preclose(struct drm_device
*dev
,
2108 struct drm_file
*file_priv
);
2109 extern void i915_driver_postclose(struct drm_device
*dev
,
2110 struct drm_file
*file_priv
);
2111 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2112 #ifdef CONFIG_COMPAT
2113 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2116 extern int i915_emit_box(struct drm_device
*dev
,
2117 struct drm_clip_rect
*box
,
2119 extern int intel_gpu_reset(struct drm_device
*dev
);
2120 extern int i915_reset(struct drm_device
*dev
);
2121 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2122 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2123 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2124 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2126 extern void intel_console_resume(struct work_struct
*work
);
2129 void i915_queue_hangcheck(struct drm_device
*dev
);
2131 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2132 const char *fmt
, ...);
2134 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2136 extern void intel_irq_init(struct drm_device
*dev
);
2137 extern void intel_hpd_init(struct drm_device
*dev
);
2139 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2140 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
2141 extern void intel_uncore_init(struct drm_device
*dev
);
2142 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2143 extern void intel_uncore_fini(struct drm_device
*dev
);
2146 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
,
2150 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
,
2153 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2154 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2157 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2158 struct drm_file
*file_priv
);
2159 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2160 struct drm_file
*file_priv
);
2161 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2162 struct drm_file
*file_priv
);
2163 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2164 struct drm_file
*file_priv
);
2165 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2166 struct drm_file
*file_priv
);
2167 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2168 struct drm_file
*file_priv
);
2169 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2170 struct drm_file
*file_priv
);
2171 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2172 struct drm_file
*file_priv
);
2173 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2174 struct drm_file
*file_priv
);
2175 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2176 struct drm_file
*file_priv
);
2177 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2178 struct drm_file
*file_priv
);
2179 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2180 struct drm_file
*file_priv
);
2181 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2182 struct drm_file
*file_priv
);
2183 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2184 struct drm_file
*file
);
2185 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2186 struct drm_file
*file
);
2187 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2188 struct drm_file
*file_priv
);
2189 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2190 struct drm_file
*file_priv
);
2191 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2192 struct drm_file
*file_priv
);
2193 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2194 struct drm_file
*file_priv
);
2195 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2196 struct drm_file
*file_priv
);
2197 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2198 struct drm_file
*file_priv
);
2199 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2200 struct drm_file
*file_priv
);
2201 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2202 struct drm_file
*file_priv
);
2203 void i915_gem_load(struct drm_device
*dev
);
2204 void *i915_gem_object_alloc(struct drm_device
*dev
);
2205 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2206 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2207 const struct drm_i915_gem_object_ops
*ops
);
2208 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2210 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2211 struct i915_address_space
*vm
);
2212 void i915_gem_free_object(struct drm_gem_object
*obj
);
2213 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2215 #define PIN_MAPPABLE 0x1
2216 #define PIN_NONBLOCK 0x2
2217 #define PIN_GLOBAL 0x4
2218 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2219 struct i915_address_space
*vm
,
2222 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2223 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2224 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2225 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2226 void i915_gem_lastclose(struct drm_device
*dev
);
2228 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2229 int *needs_clflush
);
2231 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2232 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2234 struct sg_page_iter sg_iter
;
2236 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2237 return sg_page_iter_page(&sg_iter
);
2241 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2243 BUG_ON(obj
->pages
== NULL
);
2244 obj
->pages_pin_count
++;
2246 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2248 BUG_ON(obj
->pages_pin_count
== 0);
2249 obj
->pages_pin_count
--;
2252 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2253 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2254 struct intel_ring_buffer
*to
);
2255 void i915_vma_move_to_active(struct i915_vma
*vma
,
2256 struct intel_ring_buffer
*ring
);
2257 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2258 struct drm_device
*dev
,
2259 struct drm_mode_create_dumb
*args
);
2260 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2261 uint32_t handle
, uint64_t *offset
);
2263 * Returns true if seq1 is later than seq2.
2266 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2268 return (int32_t)(seq1
- seq2
) >= 0;
2271 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2272 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2273 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2274 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2277 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
2279 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2280 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2281 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
2288 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
2290 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2291 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2292 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
2293 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
2297 struct drm_i915_gem_request
*
2298 i915_gem_find_active_request(struct intel_ring_buffer
*ring
);
2300 bool i915_gem_retire_requests(struct drm_device
*dev
);
2301 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2302 bool interruptible
);
2303 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2305 return unlikely(atomic_read(&error
->reset_counter
)
2306 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2309 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2311 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2314 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2316 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2319 void i915_gem_reset(struct drm_device
*dev
);
2320 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2321 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2322 int __must_check
i915_gem_init(struct drm_device
*dev
);
2323 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2324 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
);
2325 void i915_gem_init_swizzling(struct drm_device
*dev
);
2326 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2327 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2328 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2329 int __i915_add_request(struct intel_ring_buffer
*ring
,
2330 struct drm_file
*file
,
2331 struct drm_i915_gem_object
*batch_obj
,
2333 #define i915_add_request(ring, seqno) \
2334 __i915_add_request(ring, NULL, NULL, seqno)
2335 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
2337 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2339 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2342 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2344 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2346 struct intel_ring_buffer
*pipelined
);
2347 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2348 int i915_gem_attach_phys_object(struct drm_device
*dev
,
2349 struct drm_i915_gem_object
*obj
,
2352 void i915_gem_detach_phys_object(struct drm_device
*dev
,
2353 struct drm_i915_gem_object
*obj
);
2354 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
2355 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2356 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2359 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2361 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2362 int tiling_mode
, bool fenced
);
2364 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2365 enum i915_cache_level cache_level
);
2367 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2368 struct dma_buf
*dma_buf
);
2370 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2371 struct drm_gem_object
*gem_obj
, int flags
);
2373 void i915_gem_restore_fences(struct drm_device
*dev
);
2375 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2376 struct i915_address_space
*vm
);
2377 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2378 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2379 struct i915_address_space
*vm
);
2380 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2381 struct i915_address_space
*vm
);
2382 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2383 struct i915_address_space
*vm
);
2385 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2386 struct i915_address_space
*vm
);
2388 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2389 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2390 struct i915_vma
*vma
;
2391 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2392 if (vma
->pin_count
> 0)
2397 /* Some GGTT VM helpers */
2398 #define obj_to_ggtt(obj) \
2399 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2400 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2402 struct i915_address_space
*ggtt
=
2403 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2407 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2409 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2412 static inline unsigned long
2413 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2415 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2418 static inline unsigned long
2419 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2421 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2424 static inline int __must_check
2425 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2429 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
, flags
| PIN_GLOBAL
);
2433 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2435 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2438 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2440 /* i915_gem_context.c */
2441 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2442 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2443 void i915_gem_context_fini(struct drm_device
*dev
);
2444 void i915_gem_context_reset(struct drm_device
*dev
);
2445 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2446 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2447 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2448 int i915_switch_context(struct intel_ring_buffer
*ring
,
2449 struct drm_file
*file
, struct i915_hw_context
*to
);
2450 struct i915_hw_context
*
2451 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2452 void i915_gem_context_free(struct kref
*ctx_ref
);
2453 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
2455 if (ctx
->obj
&& HAS_HW_CONTEXTS(ctx
->obj
->base
.dev
))
2456 kref_get(&ctx
->ref
);
2459 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
2461 if (ctx
->obj
&& HAS_HW_CONTEXTS(ctx
->obj
->base
.dev
))
2462 kref_put(&ctx
->ref
, i915_gem_context_free
);
2465 static inline bool i915_gem_context_is_default(const struct i915_hw_context
*c
)
2467 return c
->id
== DEFAULT_CONTEXT_ID
;
2470 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2471 struct drm_file
*file
);
2472 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2473 struct drm_file
*file
);
2475 /* i915_gem_evict.c */
2476 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2477 struct i915_address_space
*vm
,
2480 unsigned cache_level
,
2482 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2483 int i915_gem_evict_everything(struct drm_device
*dev
);
2485 /* i915_gem_gtt.c */
2486 void i915_check_and_clear_faults(struct drm_device
*dev
);
2487 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
);
2488 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
2489 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
2490 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
2491 void i915_gem_init_global_gtt(struct drm_device
*dev
);
2492 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
2493 unsigned long mappable_end
, unsigned long end
);
2494 int i915_gem_gtt_init(struct drm_device
*dev
);
2495 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2497 if (INTEL_INFO(dev
)->gen
< 6)
2498 intel_gtt_chipset_flush();
2500 int i915_gem_init_ppgtt(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
);
2501 bool intel_enable_ppgtt(struct drm_device
*dev
, bool full
);
2503 /* i915_gem_stolen.c */
2504 int i915_gem_init_stolen(struct drm_device
*dev
);
2505 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2506 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2507 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2508 struct drm_i915_gem_object
*
2509 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2510 struct drm_i915_gem_object
*
2511 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2515 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2517 /* i915_gem_tiling.c */
2518 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2520 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2522 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2523 obj
->tiling_mode
!= I915_TILING_NONE
;
2526 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2527 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2528 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2530 /* i915_gem_debug.c */
2532 int i915_verify_lists(struct drm_device
*dev
);
2534 #define i915_verify_lists(dev) 0
2537 /* i915_debugfs.c */
2538 int i915_debugfs_init(struct drm_minor
*minor
);
2539 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2540 #ifdef CONFIG_DEBUG_FS
2541 void intel_display_crc_init(struct drm_device
*dev
);
2543 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2546 /* i915_gpu_error.c */
2548 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2549 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2550 const struct i915_error_state_file_priv
*error
);
2551 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2552 size_t count
, loff_t pos
);
2553 static inline void i915_error_state_buf_release(
2554 struct drm_i915_error_state_buf
*eb
)
2558 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2559 const char *error_msg
);
2560 void i915_error_state_get(struct drm_device
*dev
,
2561 struct i915_error_state_file_priv
*error_priv
);
2562 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2563 void i915_destroy_error_state(struct drm_device
*dev
);
2565 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2566 const char *i915_cache_level_str(int type
);
2568 /* i915_cmd_parser.c */
2569 void i915_cmd_parser_init_ring(struct intel_ring_buffer
*ring
);
2570 bool i915_needs_cmd_parser(struct intel_ring_buffer
*ring
);
2571 int i915_parse_cmds(struct intel_ring_buffer
*ring
,
2572 struct drm_i915_gem_object
*batch_obj
,
2573 u32 batch_start_offset
,
2576 /* i915_suspend.c */
2577 extern int i915_save_state(struct drm_device
*dev
);
2578 extern int i915_restore_state(struct drm_device
*dev
);
2581 void i915_save_display_reg(struct drm_device
*dev
);
2582 void i915_restore_display_reg(struct drm_device
*dev
);
2585 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2586 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2589 extern int intel_setup_gmbus(struct drm_device
*dev
);
2590 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2591 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2593 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2596 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2597 struct drm_i915_private
*dev_priv
, unsigned port
);
2598 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2599 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2600 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2602 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2604 extern void intel_i2c_reset(struct drm_device
*dev
);
2606 /* intel_opregion.c */
2607 struct intel_encoder
;
2608 extern int intel_opregion_setup(struct drm_device
*dev
);
2610 extern void intel_opregion_init(struct drm_device
*dev
);
2611 extern void intel_opregion_fini(struct drm_device
*dev
);
2612 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2613 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2615 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2618 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2619 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2620 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2622 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2627 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2635 extern void intel_register_dsm_handler(void);
2636 extern void intel_unregister_dsm_handler(void);
2638 static inline void intel_register_dsm_handler(void) { return; }
2639 static inline void intel_unregister_dsm_handler(void) { return; }
2640 #endif /* CONFIG_ACPI */
2643 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2644 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2645 extern void intel_modeset_init(struct drm_device
*dev
);
2646 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2647 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2648 extern void intel_connector_unregister(struct intel_connector
*);
2649 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2650 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2651 bool force_restore
);
2652 extern void i915_redisable_vga(struct drm_device
*dev
);
2653 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2654 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2655 extern void intel_disable_fbc(struct drm_device
*dev
);
2656 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2657 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2658 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2659 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2660 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2661 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2662 extern void intel_detect_pch(struct drm_device
*dev
);
2663 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2664 extern int intel_enable_rc6(const struct drm_device
*dev
);
2666 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2667 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2668 struct drm_file
*file
);
2669 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2670 struct drm_file
*file
);
2673 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2674 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2675 struct intel_overlay_error_state
*error
);
2677 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2678 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2679 struct drm_device
*dev
,
2680 struct intel_display_error_state
*error
);
2682 /* On SNB platform, before reading ring registers forcewake bit
2683 * must be set to prevent GT core from power down and stale values being
2686 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2687 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2688 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2690 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2691 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2693 /* intel_sideband.c */
2694 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2695 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2696 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2697 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2698 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2699 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2700 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2701 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2702 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2703 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2704 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2705 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2706 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2707 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2708 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2709 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2710 enum intel_sbi_destination destination
);
2711 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2712 enum intel_sbi_destination destination
);
2713 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2714 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2716 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2717 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2719 void vlv_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2720 void vlv_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2722 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2723 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2724 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2725 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2726 ((reg) >= 0x2E000 && (reg) < 0x30000))
2728 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2729 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2730 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2731 ((reg) >= 0x30000 && (reg) < 0x40000))
2733 #define FORCEWAKE_RENDER (1 << 0)
2734 #define FORCEWAKE_MEDIA (1 << 1)
2735 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2738 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2739 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2741 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2742 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2743 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2744 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2746 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2747 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2748 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2749 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2751 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2752 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2754 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2755 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2757 /* "Broadcast RGB" property */
2758 #define INTEL_BROADCAST_RGB_AUTO 0
2759 #define INTEL_BROADCAST_RGB_FULL 1
2760 #define INTEL_BROADCAST_RGB_LIMITED 2
2762 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2764 if (HAS_PCH_SPLIT(dev
))
2765 return CPU_VGACNTRL
;
2766 else if (IS_VALLEYVIEW(dev
))
2767 return VLV_VGACNTRL
;
2772 static inline void __user
*to_user_ptr(u64 address
)
2774 return (void __user
*)(uintptr_t)address
;
2777 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2779 unsigned long j
= msecs_to_jiffies(m
);
2781 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2784 static inline unsigned long
2785 timespec_to_jiffies_timeout(const struct timespec
*value
)
2787 unsigned long j
= timespec_to_jiffies(value
);
2789 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2793 * If you need to wait X milliseconds between events A and B, but event B
2794 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2795 * when event A happened, then just before event B you call this function and
2796 * pass the timestamp as the first argument, and X as the second argument.
2799 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2801 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2804 * Don't re-read the value of "jiffies" every time since it may change
2805 * behind our back and break the math.
2807 tmp_jiffies
= jiffies
;
2808 target_jiffies
= timestamp_jiffies
+
2809 msecs_to_jiffies_timeout(to_wait_ms
);
2811 if (time_after(target_jiffies
, tmp_jiffies
)) {
2812 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2813 while (remaining_jiffies
)
2815 schedule_timeout_uninterruptible(remaining_jiffies
);