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net: pass info struct via netdevice notifier
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / marvell / skge.c
blobc896079728e1312893fdf03f0b0e111f2a6676cc
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
45 #include <linux/slab.h>
46 #include <linux/dmi.h>
47 #include <linux/prefetch.h>
48 #include <asm/irq.h>
49
50 #include "skge.h"
51
52 #define DRV_NAME "skge"
53 #define DRV_VERSION "1.14"
54
55 #define DEFAULT_TX_RING_SIZE 128
56 #define DEFAULT_RX_RING_SIZE 512
57 #define MAX_TX_RING_SIZE 1024
58 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
59 #define MAX_RX_RING_SIZE 4096
60 #define RX_COPY_THRESHOLD 128
61 #define RX_BUF_SIZE 1536
62 #define PHY_RETRIES 1000
63 #define ETH_JUMBO_MTU 9000
64 #define TX_WATCHDOG (5 * HZ)
65 #define NAPI_WEIGHT 64
66 #define BLINK_MS 250
67 #define LINK_HZ HZ
68
69 #define SKGE_EEPROM_MAGIC 0x9933aabb
70
71
72 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
73 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_VERSION);
76
77 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
79 NETIF_MSG_IFDOWN);
80
81 static int debug = -1; /* defaults above */
82 module_param(debug, int, 0);
83 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
85 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
88 #ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90 #endif
91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
100 { 0 }
101 };
102 MODULE_DEVICE_TABLE(pci, skge_id_table);
103
104 static int skge_up(struct net_device *dev);
105 static int skge_down(struct net_device *dev);
106 static void skge_phy_reset(struct skge_port *skge);
107 static void skge_tx_clean(struct net_device *dev);
108 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
110 static void genesis_get_stats(struct skge_port *skge, u64 *data);
111 static void yukon_get_stats(struct skge_port *skge, u64 *data);
112 static void yukon_init(struct skge_hw *hw, int port);
113 static void genesis_mac_init(struct skge_hw *hw, int port);
114 static void genesis_link_up(struct skge_port *skge);
115 static void skge_set_multicast(struct net_device *dev);
116 static irqreturn_t skge_intr(int irq, void *dev_id);
117
118 /* Avoid conditionals by using array */
119 static const int txqaddr[] = { Q_XA1, Q_XA2 };
120 static const int rxqaddr[] = { Q_R1, Q_R2 };
121 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
122 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
123 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
124 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
125
126 static inline bool is_genesis(const struct skge_hw *hw)
127 {
128 #ifdef CONFIG_SKGE_GENESIS
129 return hw->chip_id == CHIP_ID_GENESIS;
130 #else
131 return false;
132 #endif
133 }
134
135 static int skge_get_regs_len(struct net_device *dev)
136 {
137 return 0x4000;
138 }
139
140 /*
141 * Returns copy of whole control register region
142 * Note: skip RAM address register because accessing it will
143 * cause bus hangs!
144 */
145 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
146 void *p)
147 {
148 const struct skge_port *skge = netdev_priv(dev);
149 const void __iomem *io = skge->hw->regs;
150
151 regs->version = 1;
152 memset(p, 0, regs->len);
153 memcpy_fromio(p, io, B3_RAM_ADDR);
154
155 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
156 regs->len - B3_RI_WTO_R1);
157 }
158
159 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
160 static u32 wol_supported(const struct skge_hw *hw)
161 {
162 if (is_genesis(hw))
163 return 0;
164
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
166 return 0;
167
168 return WAKE_MAGIC | WAKE_PHY;
169 }
170
171 static void skge_wol_init(struct skge_port *skge)
172 {
173 struct skge_hw *hw = skge->hw;
174 int port = skge->port;
175 u16 ctrl;
176
177 skge_write16(hw, B0_CTST, CS_RST_CLR);
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
179
180 /* Turn on Vaux */
181 skge_write8(hw, B0_POWER_CTRL,
182 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
183
184 /* WA code for COMA mode -- clear PHY reset */
185 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
187 u32 reg = skge_read32(hw, B2_GP_IO);
188 reg |= GP_DIR_9;
189 reg &= ~GP_IO_9;
190 skge_write32(hw, B2_GP_IO, reg);
191 }
192
193 skge_write32(hw, SK_REG(port, GPHY_CTRL),
194 GPC_DIS_SLEEP |
195 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
196 GPC_ANEG_1 | GPC_RST_SET);
197
198 skge_write32(hw, SK_REG(port, GPHY_CTRL),
199 GPC_DIS_SLEEP |
200 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
201 GPC_ANEG_1 | GPC_RST_CLR);
202
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
204
205 /* Force to 10/100 skge_reset will re-enable on resume */
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
207 (PHY_AN_100FULL | PHY_AN_100HALF |
208 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
209 /* no 1000 HD/FD */
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
211 gm_phy_write(hw, port, PHY_MARV_CTRL,
212 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
213 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
214
215
216 /* Set GMAC to no flow control and auto update for speed/duplex */
217 gma_write16(hw, port, GM_GP_CTRL,
218 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
219 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
220
221 /* Set WOL address */
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
223 skge->netdev->dev_addr, ETH_ALEN);
224
225 /* Turn on appropriate WOL control bits */
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
227 ctrl = 0;
228 if (skge->wol & WAKE_PHY)
229 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
230 else
231 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
232
233 if (skge->wol & WAKE_MAGIC)
234 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
235 else
236 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
237
238 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
240
241 /* block receiver */
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
243 }
244
245 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
246 {
247 struct skge_port *skge = netdev_priv(dev);
248
249 wol->supported = wol_supported(skge->hw);
250 wol->wolopts = skge->wol;
251 }
252
253 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
254 {
255 struct skge_port *skge = netdev_priv(dev);
256 struct skge_hw *hw = skge->hw;
257
258 if ((wol->wolopts & ~wol_supported(hw)) ||
259 !device_can_wakeup(&hw->pdev->dev))
260 return -EOPNOTSUPP;
261
262 skge->wol = wol->wolopts;
263
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
265
266 return 0;
267 }
268
269 /* Determine supported/advertised modes based on hardware.
270 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
271 */
272 static u32 skge_supported_modes(const struct skge_hw *hw)
273 {
274 u32 supported;
275
276 if (hw->copper) {
277 supported = (SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full |
281 SUPPORTED_1000baseT_Half |
282 SUPPORTED_1000baseT_Full |
283 SUPPORTED_Autoneg |
284 SUPPORTED_TP);
285
286 if (is_genesis(hw))
287 supported &= ~(SUPPORTED_10baseT_Half |
288 SUPPORTED_10baseT_Full |
289 SUPPORTED_100baseT_Half |
290 SUPPORTED_100baseT_Full);
291
292 else if (hw->chip_id == CHIP_ID_YUKON)
293 supported &= ~SUPPORTED_1000baseT_Half;
294 } else
295 supported = (SUPPORTED_1000baseT_Full |
296 SUPPORTED_1000baseT_Half |
297 SUPPORTED_FIBRE |
298 SUPPORTED_Autoneg);
299
300 return supported;
301 }
302
303 static int skge_get_settings(struct net_device *dev,
304 struct ethtool_cmd *ecmd)
305 {
306 struct skge_port *skge = netdev_priv(dev);
307 struct skge_hw *hw = skge->hw;
308
309 ecmd->transceiver = XCVR_INTERNAL;
310 ecmd->supported = skge_supported_modes(hw);
311
312 if (hw->copper) {
313 ecmd->port = PORT_TP;
314 ecmd->phy_address = hw->phy_addr;
315 } else
316 ecmd->port = PORT_FIBRE;
317
318 ecmd->advertising = skge->advertising;
319 ecmd->autoneg = skge->autoneg;
320 ethtool_cmd_speed_set(ecmd, skge->speed);
321 ecmd->duplex = skge->duplex;
322 return 0;
323 }
324
325 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
326 {
327 struct skge_port *skge = netdev_priv(dev);
328 const struct skge_hw *hw = skge->hw;
329 u32 supported = skge_supported_modes(hw);
330 int err = 0;
331
332 if (ecmd->autoneg == AUTONEG_ENABLE) {
333 ecmd->advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = ethtool_cmd_speed(ecmd);
339
340 switch (speed) {
341 case SPEED_1000:
342 if (ecmd->duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (ecmd->duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (ecmd->duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (ecmd->duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (ecmd->duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (ecmd->duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = ecmd->duplex;
375 }
376
377 skge->autoneg = ecmd->autoneg;
378 skge->advertising = ecmd->advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390 }
391
392 static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394 {
395 struct skge_port *skge = netdev_priv(dev);
396
397 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
401 }
402
403 static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407 } skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432 };
433
434 static int skge_get_sset_count(struct net_device *dev, int sset)
435 {
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442 }
443
444 static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446 {
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453 }
454
455 /* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
459 static struct net_device_stats *skge_get_stats(struct net_device *dev)
460 {
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478 }
479
480 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481 {
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
489 break;
490 }
491 }
492
493 static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495 {
496 struct skge_port *skge = netdev_priv(dev);
497
498 p->rx_max_pending = MAX_RX_RING_SIZE;
499 p->tx_max_pending = MAX_TX_RING_SIZE;
500
501 p->rx_pending = skge->rx_ring.count;
502 p->tx_pending = skge->tx_ring.count;
503 }
504
505 static int skge_set_ring_param(struct net_device *dev,
506 struct ethtool_ringparam *p)
507 {
508 struct skge_port *skge = netdev_priv(dev);
509 int err = 0;
510
511 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
512 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
513 return -EINVAL;
514
515 skge->rx_ring.count = p->rx_pending;
516 skge->tx_ring.count = p->tx_pending;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 err = skge_up(dev);
521 if (err)
522 dev_close(dev);
523 }
524
525 return err;
526 }
527
528 static u32 skge_get_msglevel(struct net_device *netdev)
529 {
530 struct skge_port *skge = netdev_priv(netdev);
531 return skge->msg_enable;
532 }
533
534 static void skge_set_msglevel(struct net_device *netdev, u32 value)
535 {
536 struct skge_port *skge = netdev_priv(netdev);
537 skge->msg_enable = value;
538 }
539
540 static int skge_nway_reset(struct net_device *dev)
541 {
542 struct skge_port *skge = netdev_priv(dev);
543
544 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
545 return -EINVAL;
546
547 skge_phy_reset(skge);
548 return 0;
549 }
550
551 static void skge_get_pauseparam(struct net_device *dev,
552 struct ethtool_pauseparam *ecmd)
553 {
554 struct skge_port *skge = netdev_priv(dev);
555
556 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
557 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
558 ecmd->tx_pause = (ecmd->rx_pause ||
559 (skge->flow_control == FLOW_MODE_LOC_SEND));
560
561 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
562 }
563
564 static int skge_set_pauseparam(struct net_device *dev,
565 struct ethtool_pauseparam *ecmd)
566 {
567 struct skge_port *skge = netdev_priv(dev);
568 struct ethtool_pauseparam old;
569 int err = 0;
570
571 skge_get_pauseparam(dev, &old);
572
573 if (ecmd->autoneg != old.autoneg)
574 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
575 else {
576 if (ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_SYMMETRIC;
578 else if (ecmd->rx_pause && !ecmd->tx_pause)
579 skge->flow_control = FLOW_MODE_SYM_OR_REM;
580 else if (!ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_LOC_SEND;
582 else
583 skge->flow_control = FLOW_MODE_NONE;
584 }
585
586 if (netif_running(dev)) {
587 skge_down(dev);
588 err = skge_up(dev);
589 if (err) {
590 dev_close(dev);
591 return err;
592 }
593 }
594
595 return 0;
596 }
597
598 /* Chip internal frequency for clock calculations */
599 static inline u32 hwkhz(const struct skge_hw *hw)
600 {
601 return is_genesis(hw) ? 53125 : 78125;
602 }
603
604 /* Chip HZ to microseconds */
605 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
606 {
607 return (ticks * 1000) / hwkhz(hw);
608 }
609
610 /* Microseconds to chip HZ */
611 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
612 {
613 return hwkhz(hw) * usec / 1000;
614 }
615
616 static int skge_get_coalesce(struct net_device *dev,
617 struct ethtool_coalesce *ecmd)
618 {
619 struct skge_port *skge = netdev_priv(dev);
620 struct skge_hw *hw = skge->hw;
621 int port = skge->port;
622
623 ecmd->rx_coalesce_usecs = 0;
624 ecmd->tx_coalesce_usecs = 0;
625
626 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
627 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
628 u32 msk = skge_read32(hw, B2_IRQM_MSK);
629
630 if (msk & rxirqmask[port])
631 ecmd->rx_coalesce_usecs = delay;
632 if (msk & txirqmask[port])
633 ecmd->tx_coalesce_usecs = delay;
634 }
635
636 return 0;
637 }
638
639 /* Note: interrupt timer is per board, but can turn on/off per port */
640 static int skge_set_coalesce(struct net_device *dev,
641 struct ethtool_coalesce *ecmd)
642 {
643 struct skge_port *skge = netdev_priv(dev);
644 struct skge_hw *hw = skge->hw;
645 int port = skge->port;
646 u32 msk = skge_read32(hw, B2_IRQM_MSK);
647 u32 delay = 25;
648
649 if (ecmd->rx_coalesce_usecs == 0)
650 msk &= ~rxirqmask[port];
651 else if (ecmd->rx_coalesce_usecs < 25 ||
652 ecmd->rx_coalesce_usecs > 33333)
653 return -EINVAL;
654 else {
655 msk |= rxirqmask[port];
656 delay = ecmd->rx_coalesce_usecs;
657 }
658
659 if (ecmd->tx_coalesce_usecs == 0)
660 msk &= ~txirqmask[port];
661 else if (ecmd->tx_coalesce_usecs < 25 ||
662 ecmd->tx_coalesce_usecs > 33333)
663 return -EINVAL;
664 else {
665 msk |= txirqmask[port];
666 delay = min(delay, ecmd->rx_coalesce_usecs);
667 }
668
669 skge_write32(hw, B2_IRQM_MSK, msk);
670 if (msk == 0)
671 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
672 else {
673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
674 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
675 }
676 return 0;
677 }
678
679 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
680 static void skge_led(struct skge_port *skge, enum led_mode mode)
681 {
682 struct skge_hw *hw = skge->hw;
683 int port = skge->port;
684
685 spin_lock_bh(&hw->phy_lock);
686 if (is_genesis(hw)) {
687 switch (mode) {
688 case LED_MODE_OFF:
689 if (hw->phy_type == SK_PHY_BCOM)
690 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
691 else {
692 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
693 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
694 }
695 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
696 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
697 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
698 break;
699
700 case LED_MODE_ON:
701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
703
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
705 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
706
707 break;
708
709 case LED_MODE_TST:
710 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
713
714 if (hw->phy_type == SK_PHY_BCOM)
715 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
716 else {
717 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
718 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
719 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
720 }
721
722 }
723 } else {
724 switch (mode) {
725 case LED_MODE_OFF:
726 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
727 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
728 PHY_M_LED_MO_DUP(MO_LED_OFF) |
729 PHY_M_LED_MO_10(MO_LED_OFF) |
730 PHY_M_LED_MO_100(MO_LED_OFF) |
731 PHY_M_LED_MO_1000(MO_LED_OFF) |
732 PHY_M_LED_MO_RX(MO_LED_OFF));
733 break;
734 case LED_MODE_ON:
735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
736 PHY_M_LED_PULS_DUR(PULS_170MS) |
737 PHY_M_LED_BLINK_RT(BLINK_84MS) |
738 PHY_M_LEDC_TX_CTRL |
739 PHY_M_LEDC_DP_CTRL);
740
741 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
742 PHY_M_LED_MO_RX(MO_LED_OFF) |
743 (skge->speed == SPEED_100 ?
744 PHY_M_LED_MO_100(MO_LED_ON) : 0));
745 break;
746 case LED_MODE_TST:
747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
749 PHY_M_LED_MO_DUP(MO_LED_ON) |
750 PHY_M_LED_MO_10(MO_LED_ON) |
751 PHY_M_LED_MO_100(MO_LED_ON) |
752 PHY_M_LED_MO_1000(MO_LED_ON) |
753 PHY_M_LED_MO_RX(MO_LED_ON));
754 }
755 }
756 spin_unlock_bh(&hw->phy_lock);
757 }
758
759 /* blink LED's for finding board */
760 static int skge_set_phys_id(struct net_device *dev,
761 enum ethtool_phys_id_state state)
762 {
763 struct skge_port *skge = netdev_priv(dev);
764
765 switch (state) {
766 case ETHTOOL_ID_ACTIVE:
767 return 2; /* cycle on/off twice per second */
768
769 case ETHTOOL_ID_ON:
770 skge_led(skge, LED_MODE_TST);
771 break;
772
773 case ETHTOOL_ID_OFF:
774 skge_led(skge, LED_MODE_OFF);
775 break;
776
777 case ETHTOOL_ID_INACTIVE:
778 /* back to regular LED state */
779 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
780 }
781
782 return 0;
783 }
784
785 static int skge_get_eeprom_len(struct net_device *dev)
786 {
787 struct skge_port *skge = netdev_priv(dev);
788 u32 reg2;
789
790 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
791 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
792 }
793
794 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
795 {
796 u32 val;
797
798 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
799
800 do {
801 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
802 } while (!(offset & PCI_VPD_ADDR_F));
803
804 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
805 return val;
806 }
807
808 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
809 {
810 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
811 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
812 offset | PCI_VPD_ADDR_F);
813
814 do {
815 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
816 } while (offset & PCI_VPD_ADDR_F);
817 }
818
819 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
820 u8 *data)
821 {
822 struct skge_port *skge = netdev_priv(dev);
823 struct pci_dev *pdev = skge->hw->pdev;
824 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
825 int length = eeprom->len;
826 u16 offset = eeprom->offset;
827
828 if (!cap)
829 return -EINVAL;
830
831 eeprom->magic = SKGE_EEPROM_MAGIC;
832
833 while (length > 0) {
834 u32 val = skge_vpd_read(pdev, cap, offset);
835 int n = min_t(int, length, sizeof(val));
836
837 memcpy(data, &val, n);
838 length -= n;
839 data += n;
840 offset += n;
841 }
842 return 0;
843 }
844
845 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
846 u8 *data)
847 {
848 struct skge_port *skge = netdev_priv(dev);
849 struct pci_dev *pdev = skge->hw->pdev;
850 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
851 int length = eeprom->len;
852 u16 offset = eeprom->offset;
853
854 if (!cap)
855 return -EINVAL;
856
857 if (eeprom->magic != SKGE_EEPROM_MAGIC)
858 return -EINVAL;
859
860 while (length > 0) {
861 u32 val;
862 int n = min_t(int, length, sizeof(val));
863
864 if (n < sizeof(val))
865 val = skge_vpd_read(pdev, cap, offset);
866 memcpy(&val, data, n);
867
868 skge_vpd_write(pdev, cap, offset, val);
869
870 length -= n;
871 data += n;
872 offset += n;
873 }
874 return 0;
875 }
876
877 static const struct ethtool_ops skge_ethtool_ops = {
878 .get_settings = skge_get_settings,
879 .set_settings = skge_set_settings,
880 .get_drvinfo = skge_get_drvinfo,
881 .get_regs_len = skge_get_regs_len,
882 .get_regs = skge_get_regs,
883 .get_wol = skge_get_wol,
884 .set_wol = skge_set_wol,
885 .get_msglevel = skge_get_msglevel,
886 .set_msglevel = skge_set_msglevel,
887 .nway_reset = skge_nway_reset,
888 .get_link = ethtool_op_get_link,
889 .get_eeprom_len = skge_get_eeprom_len,
890 .get_eeprom = skge_get_eeprom,
891 .set_eeprom = skge_set_eeprom,
892 .get_ringparam = skge_get_ring_param,
893 .set_ringparam = skge_set_ring_param,
894 .get_pauseparam = skge_get_pauseparam,
895 .set_pauseparam = skge_set_pauseparam,
896 .get_coalesce = skge_get_coalesce,
897 .set_coalesce = skge_set_coalesce,
898 .get_strings = skge_get_strings,
899 .set_phys_id = skge_set_phys_id,
900 .get_sset_count = skge_get_sset_count,
901 .get_ethtool_stats = skge_get_ethtool_stats,
902 };
903
904 /*
905 * Allocate ring elements and chain them together
906 * One-to-one association of board descriptors with ring elements
907 */
908 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
909 {
910 struct skge_tx_desc *d;
911 struct skge_element *e;
912 int i;
913
914 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
915 if (!ring->start)
916 return -ENOMEM;
917
918 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
919 e->desc = d;
920 if (i == ring->count - 1) {
921 e->next = ring->start;
922 d->next_offset = base;
923 } else {
924 e->next = e + 1;
925 d->next_offset = base + (i+1) * sizeof(*d);
926 }
927 }
928 ring->to_use = ring->to_clean = ring->start;
929
930 return 0;
931 }
932
933 /* Allocate and setup a new buffer for receiving */
934 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
935 struct sk_buff *skb, unsigned int bufsize)
936 {
937 struct skge_rx_desc *rd = e->desc;
938 u64 map;
939
940 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
941 PCI_DMA_FROMDEVICE);
942
943 rd->dma_lo = map;
944 rd->dma_hi = map >> 32;
945 e->skb = skb;
946 rd->csum1_start = ETH_HLEN;
947 rd->csum2_start = ETH_HLEN;
948 rd->csum1 = 0;
949 rd->csum2 = 0;
950
951 wmb();
952
953 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
954 dma_unmap_addr_set(e, mapaddr, map);
955 dma_unmap_len_set(e, maplen, bufsize);
956 }
957
958 /* Resume receiving using existing skb,
959 * Note: DMA address is not changed by chip.
960 * MTU not changed while receiver active.
961 */
962 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
963 {
964 struct skge_rx_desc *rd = e->desc;
965
966 rd->csum2 = 0;
967 rd->csum2_start = ETH_HLEN;
968
969 wmb();
970
971 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
972 }
973
974
975 /* Free all buffers in receive ring, assumes receiver stopped */
976 static void skge_rx_clean(struct skge_port *skge)
977 {
978 struct skge_hw *hw = skge->hw;
979 struct skge_ring *ring = &skge->rx_ring;
980 struct skge_element *e;
981
982 e = ring->start;
983 do {
984 struct skge_rx_desc *rd = e->desc;
985 rd->control = 0;
986 if (e->skb) {
987 pci_unmap_single(hw->pdev,
988 dma_unmap_addr(e, mapaddr),
989 dma_unmap_len(e, maplen),
990 PCI_DMA_FROMDEVICE);
991 dev_kfree_skb(e->skb);
992 e->skb = NULL;
993 }
994 } while ((e = e->next) != ring->start);
995 }
996
997
998 /* Allocate buffers for receive ring
999 * For receive: to_clean is next received frame.
1000 */
1001 static int skge_rx_fill(struct net_device *dev)
1002 {
1003 struct skge_port *skge = netdev_priv(dev);
1004 struct skge_ring *ring = &skge->rx_ring;
1005 struct skge_element *e;
1006
1007 e = ring->start;
1008 do {
1009 struct sk_buff *skb;
1010
1011 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1012 GFP_KERNEL);
1013 if (!skb)
1014 return -ENOMEM;
1015
1016 skb_reserve(skb, NET_IP_ALIGN);
1017 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1018 } while ((e = e->next) != ring->start);
1019
1020 ring->to_clean = ring->start;
1021 return 0;
1022 }
1023
1024 static const char *skge_pause(enum pause_status status)
1025 {
1026 switch (status) {
1027 case FLOW_STAT_NONE:
1028 return "none";
1029 case FLOW_STAT_REM_SEND:
1030 return "rx only";
1031 case FLOW_STAT_LOC_SEND:
1032 return "tx_only";
1033 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1034 return "both";
1035 default:
1036 return "indeterminated";
1037 }
1038 }
1039
1040
1041 static void skge_link_up(struct skge_port *skge)
1042 {
1043 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1044 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1045
1046 netif_carrier_on(skge->netdev);
1047 netif_wake_queue(skge->netdev);
1048
1049 netif_info(skge, link, skge->netdev,
1050 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1051 skge->speed,
1052 skge->duplex == DUPLEX_FULL ? "full" : "half",
1053 skge_pause(skge->flow_status));
1054 }
1055
1056 static void skge_link_down(struct skge_port *skge)
1057 {
1058 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1059 netif_carrier_off(skge->netdev);
1060 netif_stop_queue(skge->netdev);
1061
1062 netif_info(skge, link, skge->netdev, "Link is down\n");
1063 }
1064
1065 static void xm_link_down(struct skge_hw *hw, int port)
1066 {
1067 struct net_device *dev = hw->dev[port];
1068 struct skge_port *skge = netdev_priv(dev);
1069
1070 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1071
1072 if (netif_carrier_ok(dev))
1073 skge_link_down(skge);
1074 }
1075
1076 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1077 {
1078 int i;
1079
1080 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1081 *val = xm_read16(hw, port, XM_PHY_DATA);
1082
1083 if (hw->phy_type == SK_PHY_XMAC)
1084 goto ready;
1085
1086 for (i = 0; i < PHY_RETRIES; i++) {
1087 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1088 goto ready;
1089 udelay(1);
1090 }
1091
1092 return -ETIMEDOUT;
1093 ready:
1094 *val = xm_read16(hw, port, XM_PHY_DATA);
1095
1096 return 0;
1097 }
1098
1099 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1100 {
1101 u16 v = 0;
1102 if (__xm_phy_read(hw, port, reg, &v))
1103 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1104 return v;
1105 }
1106
1107 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1108 {
1109 int i;
1110
1111 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1112 for (i = 0; i < PHY_RETRIES; i++) {
1113 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1114 goto ready;
1115 udelay(1);
1116 }
1117 return -EIO;
1118
1119 ready:
1120 xm_write16(hw, port, XM_PHY_DATA, val);
1121 for (i = 0; i < PHY_RETRIES; i++) {
1122 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1123 return 0;
1124 udelay(1);
1125 }
1126 return -ETIMEDOUT;
1127 }
1128
1129 static void genesis_init(struct skge_hw *hw)
1130 {
1131 /* set blink source counter */
1132 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1133 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1134
1135 /* configure mac arbiter */
1136 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1137
1138 /* configure mac arbiter timeout values */
1139 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1140 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1141 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1142 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1143
1144 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1145 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1146 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1147 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1148
1149 /* configure packet arbiter timeout */
1150 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1151 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1152 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1153 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1154 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1155 }
1156
1157 static void genesis_reset(struct skge_hw *hw, int port)
1158 {
1159 static const u8 zero[8] = { 0 };
1160 u32 reg;
1161
1162 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1163
1164 /* reset the statistics module */
1165 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1166 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1167 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1168 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1169 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1170
1171 /* disable Broadcom PHY IRQ */
1172 if (hw->phy_type == SK_PHY_BCOM)
1173 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1174
1175 xm_outhash(hw, port, XM_HSM, zero);
1176
1177 /* Flush TX and RX fifo */
1178 reg = xm_read32(hw, port, XM_MODE);
1179 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1180 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1181 }
1182
1183 /* Convert mode to MII values */
1184 static const u16 phy_pause_map[] = {
1185 [FLOW_MODE_NONE] = 0,
1186 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1187 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1188 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1189 };
1190
1191 /* special defines for FIBER (88E1011S only) */
1192 static const u16 fiber_pause_map[] = {
1193 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1194 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1195 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1196 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1197 };
1198
1199
1200 /* Check status of Broadcom phy link */
1201 static void bcom_check_link(struct skge_hw *hw, int port)
1202 {
1203 struct net_device *dev = hw->dev[port];
1204 struct skge_port *skge = netdev_priv(dev);
1205 u16 status;
1206
1207 /* read twice because of latch */
1208 xm_phy_read(hw, port, PHY_BCOM_STAT);
1209 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1210
1211 if ((status & PHY_ST_LSYNC) == 0) {
1212 xm_link_down(hw, port);
1213 return;
1214 }
1215
1216 if (skge->autoneg == AUTONEG_ENABLE) {
1217 u16 lpa, aux;
1218
1219 if (!(status & PHY_ST_AN_OVER))
1220 return;
1221
1222 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1223 if (lpa & PHY_B_AN_RF) {
1224 netdev_notice(dev, "remote fault\n");
1225 return;
1226 }
1227
1228 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1229
1230 /* Check Duplex mismatch */
1231 switch (aux & PHY_B_AS_AN_RES_MSK) {
1232 case PHY_B_RES_1000FD:
1233 skge->duplex = DUPLEX_FULL;
1234 break;
1235 case PHY_B_RES_1000HD:
1236 skge->duplex = DUPLEX_HALF;
1237 break;
1238 default:
1239 netdev_notice(dev, "duplex mismatch\n");
1240 return;
1241 }
1242
1243 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1244 switch (aux & PHY_B_AS_PAUSE_MSK) {
1245 case PHY_B_AS_PAUSE_MSK:
1246 skge->flow_status = FLOW_STAT_SYMMETRIC;
1247 break;
1248 case PHY_B_AS_PRR:
1249 skge->flow_status = FLOW_STAT_REM_SEND;
1250 break;
1251 case PHY_B_AS_PRT:
1252 skge->flow_status = FLOW_STAT_LOC_SEND;
1253 break;
1254 default:
1255 skge->flow_status = FLOW_STAT_NONE;
1256 }
1257 skge->speed = SPEED_1000;
1258 }
1259
1260 if (!netif_carrier_ok(dev))
1261 genesis_link_up(skge);
1262 }
1263
1264 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1265 * Phy on for 100 or 10Mbit operation
1266 */
1267 static void bcom_phy_init(struct skge_port *skge)
1268 {
1269 struct skge_hw *hw = skge->hw;
1270 int port = skge->port;
1271 int i;
1272 u16 id1, r, ext, ctl;
1273
1274 /* magic workaround patterns for Broadcom */
1275 static const struct {
1276 u16 reg;
1277 u16 val;
1278 } A1hack[] = {
1279 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1280 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1281 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1282 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1283 }, C0hack[] = {
1284 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1285 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1286 };
1287
1288 /* read Id from external PHY (all have the same address) */
1289 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1290
1291 /* Optimize MDIO transfer by suppressing preamble. */
1292 r = xm_read16(hw, port, XM_MMU_CMD);
1293 r |= XM_MMU_NO_PRE;
1294 xm_write16(hw, port, XM_MMU_CMD, r);
1295
1296 switch (id1) {
1297 case PHY_BCOM_ID1_C0:
1298 /*
1299 * Workaround BCOM Errata for the C0 type.
1300 * Write magic patterns to reserved registers.
1301 */
1302 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1303 xm_phy_write(hw, port,
1304 C0hack[i].reg, C0hack[i].val);
1305
1306 break;
1307 case PHY_BCOM_ID1_A1:
1308 /*
1309 * Workaround BCOM Errata for the A1 type.
1310 * Write magic patterns to reserved registers.
1311 */
1312 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1313 xm_phy_write(hw, port,
1314 A1hack[i].reg, A1hack[i].val);
1315 break;
1316 }
1317
1318 /*
1319 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1320 * Disable Power Management after reset.
1321 */
1322 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1323 r |= PHY_B_AC_DIS_PM;
1324 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1325
1326 /* Dummy read */
1327 xm_read16(hw, port, XM_ISRC);
1328
1329 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1330 ctl = PHY_CT_SP1000; /* always 1000mbit */
1331
1332 if (skge->autoneg == AUTONEG_ENABLE) {
1333 /*
1334 * Workaround BCOM Errata #1 for the C5 type.
1335 * 1000Base-T Link Acquisition Failure in Slave Mode
1336 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1337 */
1338 u16 adv = PHY_B_1000C_RD;
1339 if (skge->advertising & ADVERTISED_1000baseT_Half)
1340 adv |= PHY_B_1000C_AHD;
1341 if (skge->advertising & ADVERTISED_1000baseT_Full)
1342 adv |= PHY_B_1000C_AFD;
1343 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1344
1345 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1346 } else {
1347 if (skge->duplex == DUPLEX_FULL)
1348 ctl |= PHY_CT_DUP_MD;
1349 /* Force to slave */
1350 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1351 }
1352
1353 /* Set autonegotiation pause parameters */
1354 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1355 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1356
1357 /* Handle Jumbo frames */
1358 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1359 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1360 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1361
1362 ext |= PHY_B_PEC_HIGH_LA;
1363
1364 }
1365
1366 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1367 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1368
1369 /* Use link status change interrupt */
1370 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1371 }
1372
1373 static void xm_phy_init(struct skge_port *skge)
1374 {
1375 struct skge_hw *hw = skge->hw;
1376 int port = skge->port;
1377 u16 ctrl = 0;
1378
1379 if (skge->autoneg == AUTONEG_ENABLE) {
1380 if (skge->advertising & ADVERTISED_1000baseT_Half)
1381 ctrl |= PHY_X_AN_HD;
1382 if (skge->advertising & ADVERTISED_1000baseT_Full)
1383 ctrl |= PHY_X_AN_FD;
1384
1385 ctrl |= fiber_pause_map[skge->flow_control];
1386
1387 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1388
1389 /* Restart Auto-negotiation */
1390 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1391 } else {
1392 /* Set DuplexMode in Config register */
1393 if (skge->duplex == DUPLEX_FULL)
1394 ctrl |= PHY_CT_DUP_MD;
1395 /*
1396 * Do NOT enable Auto-negotiation here. This would hold
1397 * the link down because no IDLEs are transmitted
1398 */
1399 }
1400
1401 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1402
1403 /* Poll PHY for status changes */
1404 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1405 }
1406
1407 static int xm_check_link(struct net_device *dev)
1408 {
1409 struct skge_port *skge = netdev_priv(dev);
1410 struct skge_hw *hw = skge->hw;
1411 int port = skge->port;
1412 u16 status;
1413
1414 /* read twice because of latch */
1415 xm_phy_read(hw, port, PHY_XMAC_STAT);
1416 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1417
1418 if ((status & PHY_ST_LSYNC) == 0) {
1419 xm_link_down(hw, port);
1420 return 0;
1421 }
1422
1423 if (skge->autoneg == AUTONEG_ENABLE) {
1424 u16 lpa, res;
1425
1426 if (!(status & PHY_ST_AN_OVER))
1427 return 0;
1428
1429 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1430 if (lpa & PHY_B_AN_RF) {
1431 netdev_notice(dev, "remote fault\n");
1432 return 0;
1433 }
1434
1435 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1436
1437 /* Check Duplex mismatch */
1438 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1439 case PHY_X_RS_FD:
1440 skge->duplex = DUPLEX_FULL;
1441 break;
1442 case PHY_X_RS_HD:
1443 skge->duplex = DUPLEX_HALF;
1444 break;
1445 default:
1446 netdev_notice(dev, "duplex mismatch\n");
1447 return 0;
1448 }
1449
1450 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1451 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1452 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1453 (lpa & PHY_X_P_SYM_MD))
1454 skge->flow_status = FLOW_STAT_SYMMETRIC;
1455 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1456 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1457 /* Enable PAUSE receive, disable PAUSE transmit */
1458 skge->flow_status = FLOW_STAT_REM_SEND;
1459 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1460 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1461 /* Disable PAUSE receive, enable PAUSE transmit */
1462 skge->flow_status = FLOW_STAT_LOC_SEND;
1463 else
1464 skge->flow_status = FLOW_STAT_NONE;
1465
1466 skge->speed = SPEED_1000;
1467 }
1468
1469 if (!netif_carrier_ok(dev))
1470 genesis_link_up(skge);
1471 return 1;
1472 }
1473
1474 /* Poll to check for link coming up.
1475 *
1476 * Since internal PHY is wired to a level triggered pin, can't
1477 * get an interrupt when carrier is detected, need to poll for
1478 * link coming up.
1479 */
1480 static void xm_link_timer(unsigned long arg)
1481 {
1482 struct skge_port *skge = (struct skge_port *) arg;
1483 struct net_device *dev = skge->netdev;
1484 struct skge_hw *hw = skge->hw;
1485 int port = skge->port;
1486 int i;
1487 unsigned long flags;
1488
1489 if (!netif_running(dev))
1490 return;
1491
1492 spin_lock_irqsave(&hw->phy_lock, flags);
1493
1494 /*
1495 * Verify that the link by checking GPIO register three times.
1496 * This pin has the signal from the link_sync pin connected to it.
1497 */
1498 for (i = 0; i < 3; i++) {
1499 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1500 goto link_down;
1501 }
1502
1503 /* Re-enable interrupt to detect link down */
1504 if (xm_check_link(dev)) {
1505 u16 msk = xm_read16(hw, port, XM_IMSK);
1506 msk &= ~XM_IS_INP_ASS;
1507 xm_write16(hw, port, XM_IMSK, msk);
1508 xm_read16(hw, port, XM_ISRC);
1509 } else {
1510 link_down:
1511 mod_timer(&skge->link_timer,
1512 round_jiffies(jiffies + LINK_HZ));
1513 }
1514 spin_unlock_irqrestore(&hw->phy_lock, flags);
1515 }
1516
1517 static void genesis_mac_init(struct skge_hw *hw, int port)
1518 {
1519 struct net_device *dev = hw->dev[port];
1520 struct skge_port *skge = netdev_priv(dev);
1521 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1522 int i;
1523 u32 r;
1524 static const u8 zero[6] = { 0 };
1525
1526 for (i = 0; i < 10; i++) {
1527 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1528 MFF_SET_MAC_RST);
1529 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1530 goto reset_ok;
1531 udelay(1);
1532 }
1533
1534 netdev_warn(dev, "genesis reset failed\n");
1535
1536 reset_ok:
1537 /* Unreset the XMAC. */
1538 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1539
1540 /*
1541 * Perform additional initialization for external PHYs,
1542 * namely for the 1000baseTX cards that use the XMAC's
1543 * GMII mode.
1544 */
1545 if (hw->phy_type != SK_PHY_XMAC) {
1546 /* Take external Phy out of reset */
1547 r = skge_read32(hw, B2_GP_IO);
1548 if (port == 0)
1549 r |= GP_DIR_0|GP_IO_0;
1550 else
1551 r |= GP_DIR_2|GP_IO_2;
1552
1553 skge_write32(hw, B2_GP_IO, r);
1554
1555 /* Enable GMII interface */
1556 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1557 }
1558
1559
1560 switch (hw->phy_type) {
1561 case SK_PHY_XMAC:
1562 xm_phy_init(skge);
1563 break;
1564 case SK_PHY_BCOM:
1565 bcom_phy_init(skge);
1566 bcom_check_link(hw, port);
1567 }
1568
1569 /* Set Station Address */
1570 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1571
1572 /* We don't use match addresses so clear */
1573 for (i = 1; i < 16; i++)
1574 xm_outaddr(hw, port, XM_EXM(i), zero);
1575
1576 /* Clear MIB counters */
1577 xm_write16(hw, port, XM_STAT_CMD,
1578 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1579 /* Clear two times according to Errata #3 */
1580 xm_write16(hw, port, XM_STAT_CMD,
1581 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1582
1583 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1584 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1585
1586 /* We don't need the FCS appended to the packet. */
1587 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1588 if (jumbo)
1589 r |= XM_RX_BIG_PK_OK;
1590
1591 if (skge->duplex == DUPLEX_HALF) {
1592 /*
1593 * If in manual half duplex mode the other side might be in
1594 * full duplex mode, so ignore if a carrier extension is not seen
1595 * on frames received
1596 */
1597 r |= XM_RX_DIS_CEXT;
1598 }
1599 xm_write16(hw, port, XM_RX_CMD, r);
1600
1601 /* We want short frames padded to 60 bytes. */
1602 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1603
1604 /* Increase threshold for jumbo frames on dual port */
1605 if (hw->ports > 1 && jumbo)
1606 xm_write16(hw, port, XM_TX_THR, 1020);
1607 else
1608 xm_write16(hw, port, XM_TX_THR, 512);
1609
1610 /*
1611 * Enable the reception of all error frames. This is is
1612 * a necessary evil due to the design of the XMAC. The
1613 * XMAC's receive FIFO is only 8K in size, however jumbo
1614 * frames can be up to 9000 bytes in length. When bad
1615 * frame filtering is enabled, the XMAC's RX FIFO operates
1616 * in 'store and forward' mode. For this to work, the
1617 * entire frame has to fit into the FIFO, but that means
1618 * that jumbo frames larger than 8192 bytes will be
1619 * truncated. Disabling all bad frame filtering causes
1620 * the RX FIFO to operate in streaming mode, in which
1621 * case the XMAC will start transferring frames out of the
1622 * RX FIFO as soon as the FIFO threshold is reached.
1623 */
1624 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1625
1626
1627 /*
1628 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1629 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1630 * and 'Octets Rx OK Hi Cnt Ov'.
1631 */
1632 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1633
1634 /*
1635 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1636 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1637 * and 'Octets Tx OK Hi Cnt Ov'.
1638 */
1639 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1640
1641 /* Configure MAC arbiter */
1642 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1643
1644 /* configure timeout values */
1645 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1646 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1647 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1648 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1649
1650 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1651 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1652 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1653 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1654
1655 /* Configure Rx MAC FIFO */
1656 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1657 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1658 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1659
1660 /* Configure Tx MAC FIFO */
1661 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1662 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1663 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1664
1665 if (jumbo) {
1666 /* Enable frame flushing if jumbo frames used */
1667 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1668 } else {
1669 /* enable timeout timers if normal frames */
1670 skge_write16(hw, B3_PA_CTRL,
1671 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1672 }
1673 }
1674
1675 static void genesis_stop(struct skge_port *skge)
1676 {
1677 struct skge_hw *hw = skge->hw;
1678 int port = skge->port;
1679 unsigned retries = 1000;
1680 u16 cmd;
1681
1682 /* Disable Tx and Rx */
1683 cmd = xm_read16(hw, port, XM_MMU_CMD);
1684 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1685 xm_write16(hw, port, XM_MMU_CMD, cmd);
1686
1687 genesis_reset(hw, port);
1688
1689 /* Clear Tx packet arbiter timeout IRQ */
1690 skge_write16(hw, B3_PA_CTRL,
1691 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1692
1693 /* Reset the MAC */
1694 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1695 do {
1696 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1697 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1698 break;
1699 } while (--retries > 0);
1700
1701 /* For external PHYs there must be special handling */
1702 if (hw->phy_type != SK_PHY_XMAC) {
1703 u32 reg = skge_read32(hw, B2_GP_IO);
1704 if (port == 0) {
1705 reg |= GP_DIR_0;
1706 reg &= ~GP_IO_0;
1707 } else {
1708 reg |= GP_DIR_2;
1709 reg &= ~GP_IO_2;
1710 }
1711 skge_write32(hw, B2_GP_IO, reg);
1712 skge_read32(hw, B2_GP_IO);
1713 }
1714
1715 xm_write16(hw, port, XM_MMU_CMD,
1716 xm_read16(hw, port, XM_MMU_CMD)
1717 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1718
1719 xm_read16(hw, port, XM_MMU_CMD);
1720 }
1721
1722
1723 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1724 {
1725 struct skge_hw *hw = skge->hw;
1726 int port = skge->port;
1727 int i;
1728 unsigned long timeout = jiffies + HZ;
1729
1730 xm_write16(hw, port,
1731 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1732
1733 /* wait for update to complete */
1734 while (xm_read16(hw, port, XM_STAT_CMD)
1735 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1736 if (time_after(jiffies, timeout))
1737 break;
1738 udelay(10);
1739 }
1740
1741 /* special case for 64 bit octet counter */
1742 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1743 | xm_read32(hw, port, XM_TXO_OK_LO);
1744 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1745 | xm_read32(hw, port, XM_RXO_OK_LO);
1746
1747 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1748 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1749 }
1750
1751 static void genesis_mac_intr(struct skge_hw *hw, int port)
1752 {
1753 struct net_device *dev = hw->dev[port];
1754 struct skge_port *skge = netdev_priv(dev);
1755 u16 status = xm_read16(hw, port, XM_ISRC);
1756
1757 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1758 "mac interrupt status 0x%x\n", status);
1759
1760 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1761 xm_link_down(hw, port);
1762 mod_timer(&skge->link_timer, jiffies + 1);
1763 }
1764
1765 if (status & XM_IS_TXF_UR) {
1766 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1767 ++dev->stats.tx_fifo_errors;
1768 }
1769 }
1770
1771 static void genesis_link_up(struct skge_port *skge)
1772 {
1773 struct skge_hw *hw = skge->hw;
1774 int port = skge->port;
1775 u16 cmd, msk;
1776 u32 mode;
1777
1778 cmd = xm_read16(hw, port, XM_MMU_CMD);
1779
1780 /*
1781 * enabling pause frame reception is required for 1000BT
1782 * because the XMAC is not reset if the link is going down
1783 */
1784 if (skge->flow_status == FLOW_STAT_NONE ||
1785 skge->flow_status == FLOW_STAT_LOC_SEND)
1786 /* Disable Pause Frame Reception */
1787 cmd |= XM_MMU_IGN_PF;
1788 else
1789 /* Enable Pause Frame Reception */
1790 cmd &= ~XM_MMU_IGN_PF;
1791
1792 xm_write16(hw, port, XM_MMU_CMD, cmd);
1793
1794 mode = xm_read32(hw, port, XM_MODE);
1795 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1796 skge->flow_status == FLOW_STAT_LOC_SEND) {
1797 /*
1798 * Configure Pause Frame Generation
1799 * Use internal and external Pause Frame Generation.
1800 * Sending pause frames is edge triggered.
1801 * Send a Pause frame with the maximum pause time if
1802 * internal oder external FIFO full condition occurs.
1803 * Send a zero pause time frame to re-start transmission.
1804 */
1805 /* XM_PAUSE_DA = '010000C28001' (default) */
1806 /* XM_MAC_PTIME = 0xffff (maximum) */
1807 /* remember this value is defined in big endian (!) */
1808 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1809
1810 mode |= XM_PAUSE_MODE;
1811 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1812 } else {
1813 /*
1814 * disable pause frame generation is required for 1000BT
1815 * because the XMAC is not reset if the link is going down
1816 */
1817 /* Disable Pause Mode in Mode Register */
1818 mode &= ~XM_PAUSE_MODE;
1819
1820 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1821 }
1822
1823 xm_write32(hw, port, XM_MODE, mode);
1824
1825 /* Turn on detection of Tx underrun */
1826 msk = xm_read16(hw, port, XM_IMSK);
1827 msk &= ~XM_IS_TXF_UR;
1828 xm_write16(hw, port, XM_IMSK, msk);
1829
1830 xm_read16(hw, port, XM_ISRC);
1831
1832 /* get MMU Command Reg. */
1833 cmd = xm_read16(hw, port, XM_MMU_CMD);
1834 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1835 cmd |= XM_MMU_GMII_FD;
1836
1837 /*
1838 * Workaround BCOM Errata (#10523) for all BCom Phys
1839 * Enable Power Management after link up
1840 */
1841 if (hw->phy_type == SK_PHY_BCOM) {
1842 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1843 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1844 & ~PHY_B_AC_DIS_PM);
1845 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1846 }
1847
1848 /* enable Rx/Tx */
1849 xm_write16(hw, port, XM_MMU_CMD,
1850 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1851 skge_link_up(skge);
1852 }
1853
1854
1855 static inline void bcom_phy_intr(struct skge_port *skge)
1856 {
1857 struct skge_hw *hw = skge->hw;
1858 int port = skge->port;
1859 u16 isrc;
1860
1861 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1862 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1863 "phy interrupt status 0x%x\n", isrc);
1864
1865 if (isrc & PHY_B_IS_PSE)
1866 pr_err("%s: uncorrectable pair swap error\n",
1867 hw->dev[port]->name);
1868
1869 /* Workaround BCom Errata:
1870 * enable and disable loopback mode if "NO HCD" occurs.
1871 */
1872 if (isrc & PHY_B_IS_NO_HDCL) {
1873 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1874 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1875 ctrl | PHY_CT_LOOP);
1876 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1877 ctrl & ~PHY_CT_LOOP);
1878 }
1879
1880 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1881 bcom_check_link(hw, port);
1882
1883 }
1884
1885 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1886 {
1887 int i;
1888
1889 gma_write16(hw, port, GM_SMI_DATA, val);
1890 gma_write16(hw, port, GM_SMI_CTRL,
1891 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1892 for (i = 0; i < PHY_RETRIES; i++) {
1893 udelay(1);
1894
1895 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1896 return 0;
1897 }
1898
1899 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1900 return -EIO;
1901 }
1902
1903 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1904 {
1905 int i;
1906
1907 gma_write16(hw, port, GM_SMI_CTRL,
1908 GM_SMI_CT_PHY_AD(hw->phy_addr)
1909 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1910
1911 for (i = 0; i < PHY_RETRIES; i++) {
1912 udelay(1);
1913 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1914 goto ready;
1915 }
1916
1917 return -ETIMEDOUT;
1918 ready:
1919 *val = gma_read16(hw, port, GM_SMI_DATA);
1920 return 0;
1921 }
1922
1923 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1924 {
1925 u16 v = 0;
1926 if (__gm_phy_read(hw, port, reg, &v))
1927 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1928 return v;
1929 }
1930
1931 /* Marvell Phy Initialization */
1932 static void yukon_init(struct skge_hw *hw, int port)
1933 {
1934 struct skge_port *skge = netdev_priv(hw->dev[port]);
1935 u16 ctrl, ct1000, adv;
1936
1937 if (skge->autoneg == AUTONEG_ENABLE) {
1938 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1939
1940 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1941 PHY_M_EC_MAC_S_MSK);
1942 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1943
1944 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1945
1946 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1947 }
1948
1949 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1950 if (skge->autoneg == AUTONEG_DISABLE)
1951 ctrl &= ~PHY_CT_ANE;
1952
1953 ctrl |= PHY_CT_RESET;
1954 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1955
1956 ctrl = 0;
1957 ct1000 = 0;
1958 adv = PHY_AN_CSMA;
1959
1960 if (skge->autoneg == AUTONEG_ENABLE) {
1961 if (hw->copper) {
1962 if (skge->advertising & ADVERTISED_1000baseT_Full)
1963 ct1000 |= PHY_M_1000C_AFD;
1964 if (skge->advertising & ADVERTISED_1000baseT_Half)
1965 ct1000 |= PHY_M_1000C_AHD;
1966 if (skge->advertising & ADVERTISED_100baseT_Full)
1967 adv |= PHY_M_AN_100_FD;
1968 if (skge->advertising & ADVERTISED_100baseT_Half)
1969 adv |= PHY_M_AN_100_HD;
1970 if (skge->advertising & ADVERTISED_10baseT_Full)
1971 adv |= PHY_M_AN_10_FD;
1972 if (skge->advertising & ADVERTISED_10baseT_Half)
1973 adv |= PHY_M_AN_10_HD;
1974
1975 /* Set Flow-control capabilities */
1976 adv |= phy_pause_map[skge->flow_control];
1977 } else {
1978 if (skge->advertising & ADVERTISED_1000baseT_Full)
1979 adv |= PHY_M_AN_1000X_AFD;
1980 if (skge->advertising & ADVERTISED_1000baseT_Half)
1981 adv |= PHY_M_AN_1000X_AHD;
1982
1983 adv |= fiber_pause_map[skge->flow_control];
1984 }
1985
1986 /* Restart Auto-negotiation */
1987 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1988 } else {
1989 /* forced speed/duplex settings */
1990 ct1000 = PHY_M_1000C_MSE;
1991
1992 if (skge->duplex == DUPLEX_FULL)
1993 ctrl |= PHY_CT_DUP_MD;
1994
1995 switch (skge->speed) {
1996 case SPEED_1000:
1997 ctrl |= PHY_CT_SP1000;
1998 break;
1999 case SPEED_100:
2000 ctrl |= PHY_CT_SP100;
2001 break;
2002 }
2003
2004 ctrl |= PHY_CT_RESET;
2005 }
2006
2007 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2008
2009 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2010 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2011
2012 /* Enable phy interrupt on autonegotiation complete (or link up) */
2013 if (skge->autoneg == AUTONEG_ENABLE)
2014 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2015 else
2016 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2017 }
2018
2019 static void yukon_reset(struct skge_hw *hw, int port)
2020 {
2021 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2022 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2023 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2024 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2025 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2026
2027 gma_write16(hw, port, GM_RX_CTRL,
2028 gma_read16(hw, port, GM_RX_CTRL)
2029 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2030 }
2031
2032 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2033 static int is_yukon_lite_a0(struct skge_hw *hw)
2034 {
2035 u32 reg;
2036 int ret;
2037
2038 if (hw->chip_id != CHIP_ID_YUKON)
2039 return 0;
2040
2041 reg = skge_read32(hw, B2_FAR);
2042 skge_write8(hw, B2_FAR + 3, 0xff);
2043 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2044 skge_write32(hw, B2_FAR, reg);
2045 return ret;
2046 }
2047
2048 static void yukon_mac_init(struct skge_hw *hw, int port)
2049 {
2050 struct skge_port *skge = netdev_priv(hw->dev[port]);
2051 int i;
2052 u32 reg;
2053 const u8 *addr = hw->dev[port]->dev_addr;
2054
2055 /* WA code for COMA mode -- set PHY reset */
2056 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2057 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2058 reg = skge_read32(hw, B2_GP_IO);
2059 reg |= GP_DIR_9 | GP_IO_9;
2060 skge_write32(hw, B2_GP_IO, reg);
2061 }
2062
2063 /* hard reset */
2064 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2065 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2066
2067 /* WA code for COMA mode -- clear PHY reset */
2068 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2069 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2070 reg = skge_read32(hw, B2_GP_IO);
2071 reg |= GP_DIR_9;
2072 reg &= ~GP_IO_9;
2073 skge_write32(hw, B2_GP_IO, reg);
2074 }
2075
2076 /* Set hardware config mode */
2077 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2078 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2079 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2080
2081 /* Clear GMC reset */
2082 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2083 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2084 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2085
2086 if (skge->autoneg == AUTONEG_DISABLE) {
2087 reg = GM_GPCR_AU_ALL_DIS;
2088 gma_write16(hw, port, GM_GP_CTRL,
2089 gma_read16(hw, port, GM_GP_CTRL) | reg);
2090
2091 switch (skge->speed) {
2092 case SPEED_1000:
2093 reg &= ~GM_GPCR_SPEED_100;
2094 reg |= GM_GPCR_SPEED_1000;
2095 break;
2096 case SPEED_100:
2097 reg &= ~GM_GPCR_SPEED_1000;
2098 reg |= GM_GPCR_SPEED_100;
2099 break;
2100 case SPEED_10:
2101 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2102 break;
2103 }
2104
2105 if (skge->duplex == DUPLEX_FULL)
2106 reg |= GM_GPCR_DUP_FULL;
2107 } else
2108 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2109
2110 switch (skge->flow_control) {
2111 case FLOW_MODE_NONE:
2112 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2113 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2114 break;
2115 case FLOW_MODE_LOC_SEND:
2116 /* disable Rx flow-control */
2117 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2118 break;
2119 case FLOW_MODE_SYMMETRIC:
2120 case FLOW_MODE_SYM_OR_REM:
2121 /* enable Tx & Rx flow-control */
2122 break;
2123 }
2124
2125 gma_write16(hw, port, GM_GP_CTRL, reg);
2126 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2127
2128 yukon_init(hw, port);
2129
2130 /* MIB clear */
2131 reg = gma_read16(hw, port, GM_PHY_ADDR);
2132 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2133
2134 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2135 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2136 gma_write16(hw, port, GM_PHY_ADDR, reg);
2137
2138 /* transmit control */
2139 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2140
2141 /* receive control reg: unicast + multicast + no FCS */
2142 gma_write16(hw, port, GM_RX_CTRL,
2143 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2144
2145 /* transmit flow control */
2146 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2147
2148 /* transmit parameter */
2149 gma_write16(hw, port, GM_TX_PARAM,
2150 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2151 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2152 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2153
2154 /* configure the Serial Mode Register */
2155 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2156 | GM_SMOD_VLAN_ENA
2157 | IPG_DATA_VAL(IPG_DATA_DEF);
2158
2159 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2160 reg |= GM_SMOD_JUMBO_ENA;
2161
2162 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2163
2164 /* physical address: used for pause frames */
2165 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2166 /* virtual address for data */
2167 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2168
2169 /* enable interrupt mask for counter overflows */
2170 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2171 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2172 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2173
2174 /* Initialize Mac Fifo */
2175
2176 /* Configure Rx MAC FIFO */
2177 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2178 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2179
2180 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2181 if (is_yukon_lite_a0(hw))
2182 reg &= ~GMF_RX_F_FL_ON;
2183
2184 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2185 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2186 /*
2187 * because Pause Packet Truncation in GMAC is not working
2188 * we have to increase the Flush Threshold to 64 bytes
2189 * in order to flush pause packets in Rx FIFO on Yukon-1
2190 */
2191 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2192
2193 /* Configure Tx MAC FIFO */
2194 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2195 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2196 }
2197
2198 /* Go into power down mode */
2199 static void yukon_suspend(struct skge_hw *hw, int port)
2200 {
2201 u16 ctrl;
2202
2203 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2204 ctrl |= PHY_M_PC_POL_R_DIS;
2205 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2206
2207 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2208 ctrl |= PHY_CT_RESET;
2209 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2210
2211 /* switch IEEE compatible power down mode on */
2212 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2213 ctrl |= PHY_CT_PDOWN;
2214 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2215 }
2216
2217 static void yukon_stop(struct skge_port *skge)
2218 {
2219 struct skge_hw *hw = skge->hw;
2220 int port = skge->port;
2221
2222 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2223 yukon_reset(hw, port);
2224
2225 gma_write16(hw, port, GM_GP_CTRL,
2226 gma_read16(hw, port, GM_GP_CTRL)
2227 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2228 gma_read16(hw, port, GM_GP_CTRL);
2229
2230 yukon_suspend(hw, port);
2231
2232 /* set GPHY Control reset */
2233 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2234 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2235 }
2236
2237 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2238 {
2239 struct skge_hw *hw = skge->hw;
2240 int port = skge->port;
2241 int i;
2242
2243 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2244 | gma_read32(hw, port, GM_TXO_OK_LO);
2245 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2246 | gma_read32(hw, port, GM_RXO_OK_LO);
2247
2248 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2249 data[i] = gma_read32(hw, port,
2250 skge_stats[i].gma_offset);
2251 }
2252
2253 static void yukon_mac_intr(struct skge_hw *hw, int port)
2254 {
2255 struct net_device *dev = hw->dev[port];
2256 struct skge_port *skge = netdev_priv(dev);
2257 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2258
2259 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2260 "mac interrupt status 0x%x\n", status);
2261
2262 if (status & GM_IS_RX_FF_OR) {
2263 ++dev->stats.rx_fifo_errors;
2264 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2265 }
2266
2267 if (status & GM_IS_TX_FF_UR) {
2268 ++dev->stats.tx_fifo_errors;
2269 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2270 }
2271
2272 }
2273
2274 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2275 {
2276 switch (aux & PHY_M_PS_SPEED_MSK) {
2277 case PHY_M_PS_SPEED_1000:
2278 return SPEED_1000;
2279 case PHY_M_PS_SPEED_100:
2280 return SPEED_100;
2281 default:
2282 return SPEED_10;
2283 }
2284 }
2285
2286 static void yukon_link_up(struct skge_port *skge)
2287 {
2288 struct skge_hw *hw = skge->hw;
2289 int port = skge->port;
2290 u16 reg;
2291
2292 /* Enable Transmit FIFO Underrun */
2293 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2294
2295 reg = gma_read16(hw, port, GM_GP_CTRL);
2296 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2297 reg |= GM_GPCR_DUP_FULL;
2298
2299 /* enable Rx/Tx */
2300 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2301 gma_write16(hw, port, GM_GP_CTRL, reg);
2302
2303 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2304 skge_link_up(skge);
2305 }
2306
2307 static void yukon_link_down(struct skge_port *skge)
2308 {
2309 struct skge_hw *hw = skge->hw;
2310 int port = skge->port;
2311 u16 ctrl;
2312
2313 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2314 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2315 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2316
2317 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2318 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2319 ctrl |= PHY_M_AN_ASP;
2320 /* restore Asymmetric Pause bit */
2321 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2322 }
2323
2324 skge_link_down(skge);
2325
2326 yukon_init(hw, port);
2327 }
2328
2329 static void yukon_phy_intr(struct skge_port *skge)
2330 {
2331 struct skge_hw *hw = skge->hw;
2332 int port = skge->port;
2333 const char *reason = NULL;
2334 u16 istatus, phystat;
2335
2336 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2337 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2338
2339 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2340 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2341
2342 if (istatus & PHY_M_IS_AN_COMPL) {
2343 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2344 & PHY_M_AN_RF) {
2345 reason = "remote fault";
2346 goto failed;
2347 }
2348
2349 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2350 reason = "master/slave fault";
2351 goto failed;
2352 }
2353
2354 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2355 reason = "speed/duplex";
2356 goto failed;
2357 }
2358
2359 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2360 ? DUPLEX_FULL : DUPLEX_HALF;
2361 skge->speed = yukon_speed(hw, phystat);
2362
2363 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2364 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2365 case PHY_M_PS_PAUSE_MSK:
2366 skge->flow_status = FLOW_STAT_SYMMETRIC;
2367 break;
2368 case PHY_M_PS_RX_P_EN:
2369 skge->flow_status = FLOW_STAT_REM_SEND;
2370 break;
2371 case PHY_M_PS_TX_P_EN:
2372 skge->flow_status = FLOW_STAT_LOC_SEND;
2373 break;
2374 default:
2375 skge->flow_status = FLOW_STAT_NONE;
2376 }
2377
2378 if (skge->flow_status == FLOW_STAT_NONE ||
2379 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2380 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2381 else
2382 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2383 yukon_link_up(skge);
2384 return;
2385 }
2386
2387 if (istatus & PHY_M_IS_LSP_CHANGE)
2388 skge->speed = yukon_speed(hw, phystat);
2389
2390 if (istatus & PHY_M_IS_DUP_CHANGE)
2391 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2392 if (istatus & PHY_M_IS_LST_CHANGE) {
2393 if (phystat & PHY_M_PS_LINK_UP)
2394 yukon_link_up(skge);
2395 else
2396 yukon_link_down(skge);
2397 }
2398 return;
2399 failed:
2400 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2401
2402 /* XXX restart autonegotiation? */
2403 }
2404
2405 static void skge_phy_reset(struct skge_port *skge)
2406 {
2407 struct skge_hw *hw = skge->hw;
2408 int port = skge->port;
2409 struct net_device *dev = hw->dev[port];
2410
2411 netif_stop_queue(skge->netdev);
2412 netif_carrier_off(skge->netdev);
2413
2414 spin_lock_bh(&hw->phy_lock);
2415 if (is_genesis(hw)) {
2416 genesis_reset(hw, port);
2417 genesis_mac_init(hw, port);
2418 } else {
2419 yukon_reset(hw, port);
2420 yukon_init(hw, port);
2421 }
2422 spin_unlock_bh(&hw->phy_lock);
2423
2424 skge_set_multicast(dev);
2425 }
2426
2427 /* Basic MII support */
2428 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2429 {
2430 struct mii_ioctl_data *data = if_mii(ifr);
2431 struct skge_port *skge = netdev_priv(dev);
2432 struct skge_hw *hw = skge->hw;
2433 int err = -EOPNOTSUPP;
2434
2435 if (!netif_running(dev))
2436 return -ENODEV; /* Phy still in reset */
2437
2438 switch (cmd) {
2439 case SIOCGMIIPHY:
2440 data->phy_id = hw->phy_addr;
2441
2442 /* fallthru */
2443 case SIOCGMIIREG: {
2444 u16 val = 0;
2445 spin_lock_bh(&hw->phy_lock);
2446
2447 if (is_genesis(hw))
2448 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2449 else
2450 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2451 spin_unlock_bh(&hw->phy_lock);
2452 data->val_out = val;
2453 break;
2454 }
2455
2456 case SIOCSMIIREG:
2457 spin_lock_bh(&hw->phy_lock);
2458 if (is_genesis(hw))
2459 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2460 data->val_in);
2461 else
2462 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2463 data->val_in);
2464 spin_unlock_bh(&hw->phy_lock);
2465 break;
2466 }
2467 return err;
2468 }
2469
2470 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2471 {
2472 u32 end;
2473
2474 start /= 8;
2475 len /= 8;
2476 end = start + len - 1;
2477
2478 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2479 skge_write32(hw, RB_ADDR(q, RB_START), start);
2480 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2481 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2482 skge_write32(hw, RB_ADDR(q, RB_END), end);
2483
2484 if (q == Q_R1 || q == Q_R2) {
2485 /* Set thresholds on receive queue's */
2486 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2487 start + (2*len)/3);
2488 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2489 start + (len/3));
2490 } else {
2491 /* Enable store & forward on Tx queue's because
2492 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2493 */
2494 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2495 }
2496
2497 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2498 }
2499
2500 /* Setup Bus Memory Interface */
2501 static void skge_qset(struct skge_port *skge, u16 q,
2502 const struct skge_element *e)
2503 {
2504 struct skge_hw *hw = skge->hw;
2505 u32 watermark = 0x600;
2506 u64 base = skge->dma + (e->desc - skge->mem);
2507
2508 /* optimization to reduce window on 32bit/33mhz */
2509 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2510 watermark /= 2;
2511
2512 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2513 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2514 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2515 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2516 }
2517
2518 static int skge_up(struct net_device *dev)
2519 {
2520 struct skge_port *skge = netdev_priv(dev);
2521 struct skge_hw *hw = skge->hw;
2522 int port = skge->port;
2523 u32 chunk, ram_addr;
2524 size_t rx_size, tx_size;
2525 int err;
2526
2527 if (!is_valid_ether_addr(dev->dev_addr))
2528 return -EINVAL;
2529
2530 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2531
2532 if (dev->mtu > RX_BUF_SIZE)
2533 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2534 else
2535 skge->rx_buf_size = RX_BUF_SIZE;
2536
2537
2538 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2539 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2540 skge->mem_size = tx_size + rx_size;
2541 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2542 if (!skge->mem)
2543 return -ENOMEM;
2544
2545 BUG_ON(skge->dma & 7);
2546
2547 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2548 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2549 err = -EINVAL;
2550 goto free_pci_mem;
2551 }
2552
2553 memset(skge->mem, 0, skge->mem_size);
2554
2555 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2556 if (err)
2557 goto free_pci_mem;
2558
2559 err = skge_rx_fill(dev);
2560 if (err)
2561 goto free_rx_ring;
2562
2563 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2564 skge->dma + rx_size);
2565 if (err)
2566 goto free_rx_ring;
2567
2568 if (hw->ports == 1) {
2569 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2570 dev->name, hw);
2571 if (err) {
2572 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2573 hw->pdev->irq, err);
2574 goto free_tx_ring;
2575 }
2576 }
2577
2578 /* Initialize MAC */
2579 netif_carrier_off(dev);
2580 spin_lock_bh(&hw->phy_lock);
2581 if (is_genesis(hw))
2582 genesis_mac_init(hw, port);
2583 else
2584 yukon_mac_init(hw, port);
2585 spin_unlock_bh(&hw->phy_lock);
2586
2587 /* Configure RAMbuffers - equally between ports and tx/rx */
2588 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2589 ram_addr = hw->ram_offset + 2 * chunk * port;
2590
2591 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2592 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2593
2594 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2595 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2596 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2597
2598 /* Start receiver BMU */
2599 wmb();
2600 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2601 skge_led(skge, LED_MODE_ON);
2602
2603 spin_lock_irq(&hw->hw_lock);
2604 hw->intr_mask |= portmask[port];
2605 skge_write32(hw, B0_IMSK, hw->intr_mask);
2606 skge_read32(hw, B0_IMSK);
2607 spin_unlock_irq(&hw->hw_lock);
2608
2609 napi_enable(&skge->napi);
2610
2611 skge_set_multicast(dev);
2612
2613 return 0;
2614
2615 free_tx_ring:
2616 kfree(skge->tx_ring.start);
2617 free_rx_ring:
2618 skge_rx_clean(skge);
2619 kfree(skge->rx_ring.start);
2620 free_pci_mem:
2621 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2622 skge->mem = NULL;
2623
2624 return err;
2625 }
2626
2627 /* stop receiver */
2628 static void skge_rx_stop(struct skge_hw *hw, int port)
2629 {
2630 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2631 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2632 RB_RST_SET|RB_DIS_OP_MD);
2633 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2634 }
2635
2636 static int skge_down(struct net_device *dev)
2637 {
2638 struct skge_port *skge = netdev_priv(dev);
2639 struct skge_hw *hw = skge->hw;
2640 int port = skge->port;
2641
2642 if (skge->mem == NULL)
2643 return 0;
2644
2645 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2646
2647 netif_tx_disable(dev);
2648
2649 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2650 del_timer_sync(&skge->link_timer);
2651
2652 napi_disable(&skge->napi);
2653 netif_carrier_off(dev);
2654
2655 spin_lock_irq(&hw->hw_lock);
2656 hw->intr_mask &= ~portmask[port];
2657 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2658 skge_read32(hw, B0_IMSK);
2659 spin_unlock_irq(&hw->hw_lock);
2660
2661 if (hw->ports == 1)
2662 free_irq(hw->pdev->irq, hw);
2663
2664 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2665 if (is_genesis(hw))
2666 genesis_stop(skge);
2667 else
2668 yukon_stop(skge);
2669
2670 /* Stop transmitter */
2671 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2672 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2673 RB_RST_SET|RB_DIS_OP_MD);
2674
2675
2676 /* Disable Force Sync bit and Enable Alloc bit */
2677 skge_write8(hw, SK_REG(port, TXA_CTRL),
2678 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2679
2680 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2681 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2682 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2683
2684 /* Reset PCI FIFO */
2685 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2687
2688 /* Reset the RAM Buffer async Tx queue */
2689 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2690
2691 skge_rx_stop(hw, port);
2692
2693 if (is_genesis(hw)) {
2694 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2695 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2696 } else {
2697 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2698 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2699 }
2700
2701 skge_led(skge, LED_MODE_OFF);
2702
2703 netif_tx_lock_bh(dev);
2704 skge_tx_clean(dev);
2705 netif_tx_unlock_bh(dev);
2706
2707 skge_rx_clean(skge);
2708
2709 kfree(skge->rx_ring.start);
2710 kfree(skge->tx_ring.start);
2711 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2712 skge->mem = NULL;
2713 return 0;
2714 }
2715
2716 static inline int skge_avail(const struct skge_ring *ring)
2717 {
2718 smp_mb();
2719 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2720 + (ring->to_clean - ring->to_use) - 1;
2721 }
2722
2723 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2724 struct net_device *dev)
2725 {
2726 struct skge_port *skge = netdev_priv(dev);
2727 struct skge_hw *hw = skge->hw;
2728 struct skge_element *e;
2729 struct skge_tx_desc *td;
2730 int i;
2731 u32 control, len;
2732 u64 map;
2733
2734 if (skb_padto(skb, ETH_ZLEN))
2735 return NETDEV_TX_OK;
2736
2737 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2738 return NETDEV_TX_BUSY;
2739
2740 e = skge->tx_ring.to_use;
2741 td = e->desc;
2742 BUG_ON(td->control & BMU_OWN);
2743 e->skb = skb;
2744 len = skb_headlen(skb);
2745 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2746 dma_unmap_addr_set(e, mapaddr, map);
2747 dma_unmap_len_set(e, maplen, len);
2748
2749 td->dma_lo = map;
2750 td->dma_hi = map >> 32;
2751
2752 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2753 const int offset = skb_checksum_start_offset(skb);
2754
2755 /* This seems backwards, but it is what the sk98lin
2756 * does. Looks like hardware is wrong?
2757 */
2758 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2759 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2760 control = BMU_TCP_CHECK;
2761 else
2762 control = BMU_UDP_CHECK;
2763
2764 td->csum_offs = 0;
2765 td->csum_start = offset;
2766 td->csum_write = offset + skb->csum_offset;
2767 } else
2768 control = BMU_CHECK;
2769
2770 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2771 control |= BMU_EOF | BMU_IRQ_EOF;
2772 else {
2773 struct skge_tx_desc *tf = td;
2774
2775 control |= BMU_STFWD;
2776 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2777 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2778
2779 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2780 skb_frag_size(frag), DMA_TO_DEVICE);
2781
2782 e = e->next;
2783 e->skb = skb;
2784 tf = e->desc;
2785 BUG_ON(tf->control & BMU_OWN);
2786
2787 tf->dma_lo = map;
2788 tf->dma_hi = (u64) map >> 32;
2789 dma_unmap_addr_set(e, mapaddr, map);
2790 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2791
2792 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2793 }
2794 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2795 }
2796 /* Make sure all the descriptors written */
2797 wmb();
2798 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2799 wmb();
2800
2801 netdev_sent_queue(dev, skb->len);
2802
2803 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2804
2805 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2806 "tx queued, slot %td, len %d\n",
2807 e - skge->tx_ring.start, skb->len);
2808
2809 skge->tx_ring.to_use = e->next;
2810 smp_wmb();
2811
2812 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2813 netdev_dbg(dev, "transmit queue full\n");
2814 netif_stop_queue(dev);
2815 }
2816
2817 return NETDEV_TX_OK;
2818 }
2819
2820
2821 /* Free resources associated with this reing element */
2822 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2823 u32 control)
2824 {
2825 /* skb header vs. fragment */
2826 if (control & BMU_STF)
2827 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2828 dma_unmap_len(e, maplen),
2829 PCI_DMA_TODEVICE);
2830 else
2831 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2832 dma_unmap_len(e, maplen),
2833 PCI_DMA_TODEVICE);
2834 }
2835
2836 /* Free all buffers in transmit ring */
2837 static void skge_tx_clean(struct net_device *dev)
2838 {
2839 struct skge_port *skge = netdev_priv(dev);
2840 struct skge_element *e;
2841
2842 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2843 struct skge_tx_desc *td = e->desc;
2844
2845 skge_tx_unmap(skge->hw->pdev, e, td->control);
2846
2847 if (td->control & BMU_EOF)
2848 dev_kfree_skb(e->skb);
2849 td->control = 0;
2850 }
2851
2852 netdev_reset_queue(dev);
2853 skge->tx_ring.to_clean = e;
2854 }
2855
2856 static void skge_tx_timeout(struct net_device *dev)
2857 {
2858 struct skge_port *skge = netdev_priv(dev);
2859
2860 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2861
2862 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2863 skge_tx_clean(dev);
2864 netif_wake_queue(dev);
2865 }
2866
2867 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2868 {
2869 int err;
2870
2871 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2872 return -EINVAL;
2873
2874 if (!netif_running(dev)) {
2875 dev->mtu = new_mtu;
2876 return 0;
2877 }
2878
2879 skge_down(dev);
2880
2881 dev->mtu = new_mtu;
2882
2883 err = skge_up(dev);
2884 if (err)
2885 dev_close(dev);
2886
2887 return err;
2888 }
2889
2890 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2891
2892 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2893 {
2894 u32 crc, bit;
2895
2896 crc = ether_crc_le(ETH_ALEN, addr);
2897 bit = ~crc & 0x3f;
2898 filter[bit/8] |= 1 << (bit%8);
2899 }
2900
2901 static void genesis_set_multicast(struct net_device *dev)
2902 {
2903 struct skge_port *skge = netdev_priv(dev);
2904 struct skge_hw *hw = skge->hw;
2905 int port = skge->port;
2906 struct netdev_hw_addr *ha;
2907 u32 mode;
2908 u8 filter[8];
2909
2910 mode = xm_read32(hw, port, XM_MODE);
2911 mode |= XM_MD_ENA_HASH;
2912 if (dev->flags & IFF_PROMISC)
2913 mode |= XM_MD_ENA_PROM;
2914 else
2915 mode &= ~XM_MD_ENA_PROM;
2916
2917 if (dev->flags & IFF_ALLMULTI)
2918 memset(filter, 0xff, sizeof(filter));
2919 else {
2920 memset(filter, 0, sizeof(filter));
2921
2922 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2923 skge->flow_status == FLOW_STAT_SYMMETRIC)
2924 genesis_add_filter(filter, pause_mc_addr);
2925
2926 netdev_for_each_mc_addr(ha, dev)
2927 genesis_add_filter(filter, ha->addr);
2928 }
2929
2930 xm_write32(hw, port, XM_MODE, mode);
2931 xm_outhash(hw, port, XM_HSM, filter);
2932 }
2933
2934 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2935 {
2936 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2937 filter[bit/8] |= 1 << (bit%8);
2938 }
2939
2940 static void yukon_set_multicast(struct net_device *dev)
2941 {
2942 struct skge_port *skge = netdev_priv(dev);
2943 struct skge_hw *hw = skge->hw;
2944 int port = skge->port;
2945 struct netdev_hw_addr *ha;
2946 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2947 skge->flow_status == FLOW_STAT_SYMMETRIC);
2948 u16 reg;
2949 u8 filter[8];
2950
2951 memset(filter, 0, sizeof(filter));
2952
2953 reg = gma_read16(hw, port, GM_RX_CTRL);
2954 reg |= GM_RXCR_UCF_ENA;
2955
2956 if (dev->flags & IFF_PROMISC) /* promiscuous */
2957 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2958 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2959 memset(filter, 0xff, sizeof(filter));
2960 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2961 reg &= ~GM_RXCR_MCF_ENA;
2962 else {
2963 reg |= GM_RXCR_MCF_ENA;
2964
2965 if (rx_pause)
2966 yukon_add_filter(filter, pause_mc_addr);
2967
2968 netdev_for_each_mc_addr(ha, dev)
2969 yukon_add_filter(filter, ha->addr);
2970 }
2971
2972
2973 gma_write16(hw, port, GM_MC_ADDR_H1,
2974 (u16)filter[0] | ((u16)filter[1] << 8));
2975 gma_write16(hw, port, GM_MC_ADDR_H2,
2976 (u16)filter[2] | ((u16)filter[3] << 8));
2977 gma_write16(hw, port, GM_MC_ADDR_H3,
2978 (u16)filter[4] | ((u16)filter[5] << 8));
2979 gma_write16(hw, port, GM_MC_ADDR_H4,
2980 (u16)filter[6] | ((u16)filter[7] << 8));
2981
2982 gma_write16(hw, port, GM_RX_CTRL, reg);
2983 }
2984
2985 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2986 {
2987 if (is_genesis(hw))
2988 return status >> XMR_FS_LEN_SHIFT;
2989 else
2990 return status >> GMR_FS_LEN_SHIFT;
2991 }
2992
2993 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2994 {
2995 if (is_genesis(hw))
2996 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2997 else
2998 return (status & GMR_FS_ANY_ERR) ||
2999 (status & GMR_FS_RX_OK) == 0;
3000 }
3001
3002 static void skge_set_multicast(struct net_device *dev)
3003 {
3004 struct skge_port *skge = netdev_priv(dev);
3005
3006 if (is_genesis(skge->hw))
3007 genesis_set_multicast(dev);
3008 else
3009 yukon_set_multicast(dev);
3010
3011 }
3012
3013
3014 /* Get receive buffer from descriptor.
3015 * Handles copy of small buffers and reallocation failures
3016 */
3017 static struct sk_buff *skge_rx_get(struct net_device *dev,
3018 struct skge_element *e,
3019 u32 control, u32 status, u16 csum)
3020 {
3021 struct skge_port *skge = netdev_priv(dev);
3022 struct sk_buff *skb;
3023 u16 len = control & BMU_BBC;
3024
3025 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3026 "rx slot %td status 0x%x len %d\n",
3027 e - skge->rx_ring.start, status, len);
3028
3029 if (len > skge->rx_buf_size)
3030 goto error;
3031
3032 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3033 goto error;
3034
3035 if (bad_phy_status(skge->hw, status))
3036 goto error;
3037
3038 if (phy_length(skge->hw, status) != len)
3039 goto error;
3040
3041 if (len < RX_COPY_THRESHOLD) {
3042 skb = netdev_alloc_skb_ip_align(dev, len);
3043 if (!skb)
3044 goto resubmit;
3045
3046 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3047 dma_unmap_addr(e, mapaddr),
3048 len, PCI_DMA_FROMDEVICE);
3049 skb_copy_from_linear_data(e->skb, skb->data, len);
3050 pci_dma_sync_single_for_device(skge->hw->pdev,
3051 dma_unmap_addr(e, mapaddr),
3052 len, PCI_DMA_FROMDEVICE);
3053 skge_rx_reuse(e, skge->rx_buf_size);
3054 } else {
3055 struct sk_buff *nskb;
3056
3057 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3058 if (!nskb)
3059 goto resubmit;
3060
3061 pci_unmap_single(skge->hw->pdev,
3062 dma_unmap_addr(e, mapaddr),
3063 dma_unmap_len(e, maplen),
3064 PCI_DMA_FROMDEVICE);
3065 skb = e->skb;
3066 prefetch(skb->data);
3067 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3068 }
3069
3070 skb_put(skb, len);
3071
3072 if (dev->features & NETIF_F_RXCSUM) {
3073 skb->csum = csum;
3074 skb->ip_summed = CHECKSUM_COMPLETE;
3075 }
3076
3077 skb->protocol = eth_type_trans(skb, dev);
3078
3079 return skb;
3080 error:
3081
3082 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3083 "rx err, slot %td control 0x%x status 0x%x\n",
3084 e - skge->rx_ring.start, control, status);
3085
3086 if (is_genesis(skge->hw)) {
3087 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3088 dev->stats.rx_length_errors++;
3089 if (status & XMR_FS_FRA_ERR)
3090 dev->stats.rx_frame_errors++;
3091 if (status & XMR_FS_FCS_ERR)
3092 dev->stats.rx_crc_errors++;
3093 } else {
3094 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3095 dev->stats.rx_length_errors++;
3096 if (status & GMR_FS_FRAGMENT)
3097 dev->stats.rx_frame_errors++;
3098 if (status & GMR_FS_CRC_ERR)
3099 dev->stats.rx_crc_errors++;
3100 }
3101
3102 resubmit:
3103 skge_rx_reuse(e, skge->rx_buf_size);
3104 return NULL;
3105 }
3106
3107 /* Free all buffers in Tx ring which are no longer owned by device */
3108 static void skge_tx_done(struct net_device *dev)
3109 {
3110 struct skge_port *skge = netdev_priv(dev);
3111 struct skge_ring *ring = &skge->tx_ring;
3112 struct skge_element *e;
3113 unsigned int bytes_compl = 0, pkts_compl = 0;
3114
3115 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3116
3117 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3118 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3119
3120 if (control & BMU_OWN)
3121 break;
3122
3123 skge_tx_unmap(skge->hw->pdev, e, control);
3124
3125 if (control & BMU_EOF) {
3126 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3127 "tx done slot %td\n",
3128 e - skge->tx_ring.start);
3129
3130 pkts_compl++;
3131 bytes_compl += e->skb->len;
3132
3133 dev_kfree_skb(e->skb);
3134 }
3135 }
3136 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3137 skge->tx_ring.to_clean = e;
3138
3139 /* Can run lockless until we need to synchronize to restart queue. */
3140 smp_mb();
3141
3142 if (unlikely(netif_queue_stopped(dev) &&
3143 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3144 netif_tx_lock(dev);
3145 if (unlikely(netif_queue_stopped(dev) &&
3146 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3147 netif_wake_queue(dev);
3148
3149 }
3150 netif_tx_unlock(dev);
3151 }
3152 }
3153
3154 static int skge_poll(struct napi_struct *napi, int to_do)
3155 {
3156 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3157 struct net_device *dev = skge->netdev;
3158 struct skge_hw *hw = skge->hw;
3159 struct skge_ring *ring = &skge->rx_ring;
3160 struct skge_element *e;
3161 int work_done = 0;
3162
3163 skge_tx_done(dev);
3164
3165 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3166
3167 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3168 struct skge_rx_desc *rd = e->desc;
3169 struct sk_buff *skb;
3170 u32 control;
3171
3172 rmb();
3173 control = rd->control;
3174 if (control & BMU_OWN)
3175 break;
3176
3177 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3178 if (likely(skb)) {
3179 napi_gro_receive(napi, skb);
3180 ++work_done;
3181 }
3182 }
3183 ring->to_clean = e;
3184
3185 /* restart receiver */
3186 wmb();
3187 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3188
3189 if (work_done < to_do) {
3190 unsigned long flags;
3191
3192 napi_gro_flush(napi, false);
3193 spin_lock_irqsave(&hw->hw_lock, flags);
3194 __napi_complete(napi);
3195 hw->intr_mask |= napimask[skge->port];
3196 skge_write32(hw, B0_IMSK, hw->intr_mask);
3197 skge_read32(hw, B0_IMSK);
3198 spin_unlock_irqrestore(&hw->hw_lock, flags);
3199 }
3200
3201 return work_done;
3202 }
3203
3204 /* Parity errors seem to happen when Genesis is connected to a switch
3205 * with no other ports present. Heartbeat error??
3206 */
3207 static void skge_mac_parity(struct skge_hw *hw, int port)
3208 {
3209 struct net_device *dev = hw->dev[port];
3210
3211 ++dev->stats.tx_heartbeat_errors;
3212
3213 if (is_genesis(hw))
3214 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3215 MFF_CLR_PERR);
3216 else
3217 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3218 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3219 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3220 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3221 }
3222
3223 static void skge_mac_intr(struct skge_hw *hw, int port)
3224 {
3225 if (is_genesis(hw))
3226 genesis_mac_intr(hw, port);
3227 else
3228 yukon_mac_intr(hw, port);
3229 }
3230
3231 /* Handle device specific framing and timeout interrupts */
3232 static void skge_error_irq(struct skge_hw *hw)
3233 {
3234 struct pci_dev *pdev = hw->pdev;
3235 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3236
3237 if (is_genesis(hw)) {
3238 /* clear xmac errors */
3239 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3240 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3241 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3242 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3243 } else {
3244 /* Timestamp (unused) overflow */
3245 if (hwstatus & IS_IRQ_TIST_OV)
3246 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3247 }
3248
3249 if (hwstatus & IS_RAM_RD_PAR) {
3250 dev_err(&pdev->dev, "Ram read data parity error\n");
3251 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3252 }
3253
3254 if (hwstatus & IS_RAM_WR_PAR) {
3255 dev_err(&pdev->dev, "Ram write data parity error\n");
3256 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3257 }
3258
3259 if (hwstatus & IS_M1_PAR_ERR)
3260 skge_mac_parity(hw, 0);
3261
3262 if (hwstatus & IS_M2_PAR_ERR)
3263 skge_mac_parity(hw, 1);
3264
3265 if (hwstatus & IS_R1_PAR_ERR) {
3266 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3267 hw->dev[0]->name);
3268 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3269 }
3270
3271 if (hwstatus & IS_R2_PAR_ERR) {
3272 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3273 hw->dev[1]->name);
3274 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3275 }
3276
3277 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3278 u16 pci_status, pci_cmd;
3279
3280 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3281 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3282
3283 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3284 pci_cmd, pci_status);
3285
3286 /* Write the error bits back to clear them. */
3287 pci_status &= PCI_STATUS_ERROR_BITS;
3288 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3289 pci_write_config_word(pdev, PCI_COMMAND,
3290 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3291 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3292 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3293
3294 /* if error still set then just ignore it */
3295 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3296 if (hwstatus & IS_IRQ_STAT) {
3297 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3298 hw->intr_mask &= ~IS_HW_ERR;
3299 }
3300 }
3301 }
3302
3303 /*
3304 * Interrupt from PHY are handled in tasklet (softirq)
3305 * because accessing phy registers requires spin wait which might
3306 * cause excess interrupt latency.
3307 */
3308 static void skge_extirq(unsigned long arg)
3309 {
3310 struct skge_hw *hw = (struct skge_hw *) arg;
3311 int port;
3312
3313 for (port = 0; port < hw->ports; port++) {
3314 struct net_device *dev = hw->dev[port];
3315
3316 if (netif_running(dev)) {
3317 struct skge_port *skge = netdev_priv(dev);
3318
3319 spin_lock(&hw->phy_lock);
3320 if (!is_genesis(hw))
3321 yukon_phy_intr(skge);
3322 else if (hw->phy_type == SK_PHY_BCOM)
3323 bcom_phy_intr(skge);
3324 spin_unlock(&hw->phy_lock);
3325 }
3326 }
3327
3328 spin_lock_irq(&hw->hw_lock);
3329 hw->intr_mask |= IS_EXT_REG;
3330 skge_write32(hw, B0_IMSK, hw->intr_mask);
3331 skge_read32(hw, B0_IMSK);
3332 spin_unlock_irq(&hw->hw_lock);
3333 }
3334
3335 static irqreturn_t skge_intr(int irq, void *dev_id)
3336 {
3337 struct skge_hw *hw = dev_id;
3338 u32 status;
3339 int handled = 0;
3340
3341 spin_lock(&hw->hw_lock);
3342 /* Reading this register masks IRQ */
3343 status = skge_read32(hw, B0_SP_ISRC);
3344 if (status == 0 || status == ~0)
3345 goto out;
3346
3347 handled = 1;
3348 status &= hw->intr_mask;
3349 if (status & IS_EXT_REG) {
3350 hw->intr_mask &= ~IS_EXT_REG;
3351 tasklet_schedule(&hw->phy_task);
3352 }
3353
3354 if (status & (IS_XA1_F|IS_R1_F)) {
3355 struct skge_port *skge = netdev_priv(hw->dev[0]);
3356 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3357 napi_schedule(&skge->napi);
3358 }
3359
3360 if (status & IS_PA_TO_TX1)
3361 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3362
3363 if (status & IS_PA_TO_RX1) {
3364 ++hw->dev[0]->stats.rx_over_errors;
3365 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3366 }
3367
3368
3369 if (status & IS_MAC1)
3370 skge_mac_intr(hw, 0);
3371
3372 if (hw->dev[1]) {
3373 struct skge_port *skge = netdev_priv(hw->dev[1]);
3374
3375 if (status & (IS_XA2_F|IS_R2_F)) {
3376 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3377 napi_schedule(&skge->napi);
3378 }
3379
3380 if (status & IS_PA_TO_RX2) {
3381 ++hw->dev[1]->stats.rx_over_errors;
3382 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3383 }
3384
3385 if (status & IS_PA_TO_TX2)
3386 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3387
3388 if (status & IS_MAC2)
3389 skge_mac_intr(hw, 1);
3390 }
3391
3392 if (status & IS_HW_ERR)
3393 skge_error_irq(hw);
3394
3395 skge_write32(hw, B0_IMSK, hw->intr_mask);
3396 skge_read32(hw, B0_IMSK);
3397 out:
3398 spin_unlock(&hw->hw_lock);
3399
3400 return IRQ_RETVAL(handled);
3401 }
3402
3403 #ifdef CONFIG_NET_POLL_CONTROLLER
3404 static void skge_netpoll(struct net_device *dev)
3405 {
3406 struct skge_port *skge = netdev_priv(dev);
3407
3408 disable_irq(dev->irq);
3409 skge_intr(dev->irq, skge->hw);
3410 enable_irq(dev->irq);
3411 }
3412 #endif
3413
3414 static int skge_set_mac_address(struct net_device *dev, void *p)
3415 {
3416 struct skge_port *skge = netdev_priv(dev);
3417 struct skge_hw *hw = skge->hw;
3418 unsigned port = skge->port;
3419 const struct sockaddr *addr = p;
3420 u16 ctrl;
3421
3422 if (!is_valid_ether_addr(addr->sa_data))
3423 return -EADDRNOTAVAIL;
3424
3425 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3426
3427 if (!netif_running(dev)) {
3428 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3429 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3430 } else {
3431 /* disable Rx */
3432 spin_lock_bh(&hw->phy_lock);
3433 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3434 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3435
3436 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3437 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3438
3439 if (is_genesis(hw))
3440 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3441 else {
3442 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3443 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3444 }
3445
3446 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3447 spin_unlock_bh(&hw->phy_lock);
3448 }
3449
3450 return 0;
3451 }
3452
3453 static const struct {
3454 u8 id;
3455 const char *name;
3456 } skge_chips[] = {
3457 { CHIP_ID_GENESIS, "Genesis" },
3458 { CHIP_ID_YUKON, "Yukon" },
3459 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3460 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3461 };
3462
3463 static const char *skge_board_name(const struct skge_hw *hw)
3464 {
3465 int i;
3466 static char buf[16];
3467
3468 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3469 if (skge_chips[i].id == hw->chip_id)
3470 return skge_chips[i].name;
3471
3472 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3473 return buf;
3474 }
3475
3476
3477 /*
3478 * Setup the board data structure, but don't bring up
3479 * the port(s)
3480 */
3481 static int skge_reset(struct skge_hw *hw)
3482 {
3483 u32 reg;
3484 u16 ctst, pci_status;
3485 u8 t8, mac_cfg, pmd_type;
3486 int i;
3487
3488 ctst = skge_read16(hw, B0_CTST);
3489
3490 /* do a SW reset */
3491 skge_write8(hw, B0_CTST, CS_RST_SET);
3492 skge_write8(hw, B0_CTST, CS_RST_CLR);
3493
3494 /* clear PCI errors, if any */
3495 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3496 skge_write8(hw, B2_TST_CTRL2, 0);
3497
3498 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3499 pci_write_config_word(hw->pdev, PCI_STATUS,
3500 pci_status | PCI_STATUS_ERROR_BITS);
3501 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3502 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3503
3504 /* restore CLK_RUN bits (for Yukon-Lite) */
3505 skge_write16(hw, B0_CTST,
3506 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3507
3508 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3509 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3510 pmd_type = skge_read8(hw, B2_PMD_TYP);
3511 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3512
3513 switch (hw->chip_id) {
3514 case CHIP_ID_GENESIS:
3515 #ifdef CONFIG_SKGE_GENESIS
3516 switch (hw->phy_type) {
3517 case SK_PHY_XMAC:
3518 hw->phy_addr = PHY_ADDR_XMAC;
3519 break;
3520 case SK_PHY_BCOM:
3521 hw->phy_addr = PHY_ADDR_BCOM;
3522 break;
3523 default:
3524 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3525 hw->phy_type);
3526 return -EOPNOTSUPP;
3527 }
3528 break;
3529 #else
3530 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3531 return -EOPNOTSUPP;
3532 #endif
3533
3534 case CHIP_ID_YUKON:
3535 case CHIP_ID_YUKON_LITE:
3536 case CHIP_ID_YUKON_LP:
3537 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3538 hw->copper = 1;
3539
3540 hw->phy_addr = PHY_ADDR_MARV;
3541 break;
3542
3543 default:
3544 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3545 hw->chip_id);
3546 return -EOPNOTSUPP;
3547 }
3548
3549 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3550 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3551 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3552
3553 /* read the adapters RAM size */
3554 t8 = skge_read8(hw, B2_E_0);
3555 if (is_genesis(hw)) {
3556 if (t8 == 3) {
3557 /* special case: 4 x 64k x 36, offset = 0x80000 */
3558 hw->ram_size = 0x100000;
3559 hw->ram_offset = 0x80000;
3560 } else
3561 hw->ram_size = t8 * 512;
3562 } else if (t8 == 0)
3563 hw->ram_size = 0x20000;
3564 else
3565 hw->ram_size = t8 * 4096;
3566
3567 hw->intr_mask = IS_HW_ERR;
3568
3569 /* Use PHY IRQ for all but fiber based Genesis board */
3570 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3571 hw->intr_mask |= IS_EXT_REG;
3572
3573 if (is_genesis(hw))
3574 genesis_init(hw);
3575 else {
3576 /* switch power to VCC (WA for VAUX problem) */
3577 skge_write8(hw, B0_POWER_CTRL,
3578 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3579
3580 /* avoid boards with stuck Hardware error bits */
3581 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3582 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3583 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3584 hw->intr_mask &= ~IS_HW_ERR;
3585 }
3586
3587 /* Clear PHY COMA */
3588 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3589 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3590 reg &= ~PCI_PHY_COMA;
3591 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3592 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3593
3594
3595 for (i = 0; i < hw->ports; i++) {
3596 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3597 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3598 }
3599 }
3600
3601 /* turn off hardware timer (unused) */
3602 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3603 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3604 skge_write8(hw, B0_LED, LED_STAT_ON);
3605
3606 /* enable the Tx Arbiters */
3607 for (i = 0; i < hw->ports; i++)
3608 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3609
3610 /* Initialize ram interface */
3611 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3612
3613 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3614 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3615 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3616 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3617 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3618 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3621 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3622 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3623 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3624 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3625
3626 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3627
3628 /* Set interrupt moderation for Transmit only
3629 * Receive interrupts avoided by NAPI
3630 */
3631 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3632 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3633 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3634
3635 /* Leave irq disabled until first port is brought up. */
3636 skge_write32(hw, B0_IMSK, 0);
3637
3638 for (i = 0; i < hw->ports; i++) {
3639 if (is_genesis(hw))
3640 genesis_reset(hw, i);
3641 else
3642 yukon_reset(hw, i);
3643 }
3644
3645 return 0;
3646 }
3647
3648
3649 #ifdef CONFIG_SKGE_DEBUG
3650
3651 static struct dentry *skge_debug;
3652
3653 static int skge_debug_show(struct seq_file *seq, void *v)
3654 {
3655 struct net_device *dev = seq->private;
3656 const struct skge_port *skge = netdev_priv(dev);
3657 const struct skge_hw *hw = skge->hw;
3658 const struct skge_element *e;
3659
3660 if (!netif_running(dev))
3661 return -ENETDOWN;
3662
3663 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3664 skge_read32(hw, B0_IMSK));
3665
3666 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3667 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3668 const struct skge_tx_desc *t = e->desc;
3669 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3670 t->control, t->dma_hi, t->dma_lo, t->status,
3671 t->csum_offs, t->csum_write, t->csum_start);
3672 }
3673
3674 seq_printf(seq, "\nRx Ring:\n");
3675 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3676 const struct skge_rx_desc *r = e->desc;
3677
3678 if (r->control & BMU_OWN)
3679 break;
3680
3681 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3682 r->control, r->dma_hi, r->dma_lo, r->status,
3683 r->timestamp, r->csum1, r->csum1_start);
3684 }
3685
3686 return 0;
3687 }
3688
3689 static int skge_debug_open(struct inode *inode, struct file *file)
3690 {
3691 return single_open(file, skge_debug_show, inode->i_private);
3692 }
3693
3694 static const struct file_operations skge_debug_fops = {
3695 .owner = THIS_MODULE,
3696 .open = skge_debug_open,
3697 .read = seq_read,
3698 .llseek = seq_lseek,
3699 .release = single_release,
3700 };
3701
3702 /*
3703 * Use network device events to create/remove/rename
3704 * debugfs file entries
3705 */
3706 static int skge_device_event(struct notifier_block *unused,
3707 unsigned long event, void *ptr)
3708 {
3709 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3710 struct skge_port *skge;
3711 struct dentry *d;
3712
3713 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3714 goto done;
3715
3716 skge = netdev_priv(dev);
3717 switch (event) {
3718 case NETDEV_CHANGENAME:
3719 if (skge->debugfs) {
3720 d = debugfs_rename(skge_debug, skge->debugfs,
3721 skge_debug, dev->name);
3722 if (d)
3723 skge->debugfs = d;
3724 else {
3725 netdev_info(dev, "rename failed\n");
3726 debugfs_remove(skge->debugfs);
3727 }
3728 }
3729 break;
3730
3731 case NETDEV_GOING_DOWN:
3732 if (skge->debugfs) {
3733 debugfs_remove(skge->debugfs);
3734 skge->debugfs = NULL;
3735 }
3736 break;
3737
3738 case NETDEV_UP:
3739 d = debugfs_create_file(dev->name, S_IRUGO,
3740 skge_debug, dev,
3741 &skge_debug_fops);
3742 if (!d || IS_ERR(d))
3743 netdev_info(dev, "debugfs create failed\n");
3744 else
3745 skge->debugfs = d;
3746 break;
3747 }
3748
3749 done:
3750 return NOTIFY_DONE;
3751 }
3752
3753 static struct notifier_block skge_notifier = {
3754 .notifier_call = skge_device_event,
3755 };
3756
3757
3758 static __init void skge_debug_init(void)
3759 {
3760 struct dentry *ent;
3761
3762 ent = debugfs_create_dir("skge", NULL);
3763 if (!ent || IS_ERR(ent)) {
3764 pr_info("debugfs create directory failed\n");
3765 return;
3766 }
3767
3768 skge_debug = ent;
3769 register_netdevice_notifier(&skge_notifier);
3770 }
3771
3772 static __exit void skge_debug_cleanup(void)
3773 {
3774 if (skge_debug) {
3775 unregister_netdevice_notifier(&skge_notifier);
3776 debugfs_remove(skge_debug);
3777 skge_debug = NULL;
3778 }
3779 }
3780
3781 #else
3782 #define skge_debug_init()
3783 #define skge_debug_cleanup()
3784 #endif
3785
3786 static const struct net_device_ops skge_netdev_ops = {
3787 .ndo_open = skge_up,
3788 .ndo_stop = skge_down,
3789 .ndo_start_xmit = skge_xmit_frame,
3790 .ndo_do_ioctl = skge_ioctl,
3791 .ndo_get_stats = skge_get_stats,
3792 .ndo_tx_timeout = skge_tx_timeout,
3793 .ndo_change_mtu = skge_change_mtu,
3794 .ndo_validate_addr = eth_validate_addr,
3795 .ndo_set_rx_mode = skge_set_multicast,
3796 .ndo_set_mac_address = skge_set_mac_address,
3797 #ifdef CONFIG_NET_POLL_CONTROLLER
3798 .ndo_poll_controller = skge_netpoll,
3799 #endif
3800 };
3801
3802
3803 /* Initialize network device */
3804 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3805 int highmem)
3806 {
3807 struct skge_port *skge;
3808 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3809
3810 if (!dev)
3811 return NULL;
3812
3813 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3814 dev->netdev_ops = &skge_netdev_ops;
3815 dev->ethtool_ops = &skge_ethtool_ops;
3816 dev->watchdog_timeo = TX_WATCHDOG;
3817 dev->irq = hw->pdev->irq;
3818
3819 if (highmem)
3820 dev->features |= NETIF_F_HIGHDMA;
3821
3822 skge = netdev_priv(dev);
3823 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3824 skge->netdev = dev;
3825 skge->hw = hw;
3826 skge->msg_enable = netif_msg_init(debug, default_msg);
3827
3828 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3829 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3830
3831 /* Auto speed and flow control */
3832 skge->autoneg = AUTONEG_ENABLE;
3833 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3834 skge->duplex = -1;
3835 skge->speed = -1;
3836 skge->advertising = skge_supported_modes(hw);
3837
3838 if (device_can_wakeup(&hw->pdev->dev)) {
3839 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3840 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3841 }
3842
3843 hw->dev[port] = dev;
3844
3845 skge->port = port;
3846
3847 /* Only used for Genesis XMAC */
3848 if (is_genesis(hw))
3849 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3850 else {
3851 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3852 NETIF_F_RXCSUM;
3853 dev->features |= dev->hw_features;
3854 }
3855
3856 /* read the mac address */
3857 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3858
3859 return dev;
3860 }
3861
3862 static void skge_show_addr(struct net_device *dev)
3863 {
3864 const struct skge_port *skge = netdev_priv(dev);
3865
3866 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3867 }
3868
3869 static int only_32bit_dma;
3870
3871 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3872 {
3873 struct net_device *dev, *dev1;
3874 struct skge_hw *hw;
3875 int err, using_dac = 0;
3876
3877 err = pci_enable_device(pdev);
3878 if (err) {
3879 dev_err(&pdev->dev, "cannot enable PCI device\n");
3880 goto err_out;
3881 }
3882
3883 err = pci_request_regions(pdev, DRV_NAME);
3884 if (err) {
3885 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3886 goto err_out_disable_pdev;
3887 }
3888
3889 pci_set_master(pdev);
3890
3891 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3892 using_dac = 1;
3893 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3894 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3895 using_dac = 0;
3896 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3897 }
3898
3899 if (err) {
3900 dev_err(&pdev->dev, "no usable DMA configuration\n");
3901 goto err_out_free_regions;
3902 }
3903
3904 #ifdef __BIG_ENDIAN
3905 /* byte swap descriptors in hardware */
3906 {
3907 u32 reg;
3908
3909 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3910 reg |= PCI_REV_DESC;
3911 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3912 }
3913 #endif
3914
3915 err = -ENOMEM;
3916 /* space for skge@pci:0000:04:00.0 */
3917 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3918 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3919 if (!hw)
3920 goto err_out_free_regions;
3921
3922 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3923
3924 hw->pdev = pdev;
3925 spin_lock_init(&hw->hw_lock);
3926 spin_lock_init(&hw->phy_lock);
3927 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3928
3929 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3930 if (!hw->regs) {
3931 dev_err(&pdev->dev, "cannot map device registers\n");
3932 goto err_out_free_hw;
3933 }
3934
3935 err = skge_reset(hw);
3936 if (err)
3937 goto err_out_iounmap;
3938
3939 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3940 DRV_VERSION,
3941 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3942 skge_board_name(hw), hw->chip_rev);
3943
3944 dev = skge_devinit(hw, 0, using_dac);
3945 if (!dev) {
3946 err = -ENOMEM;
3947 goto err_out_led_off;
3948 }
3949
3950 /* Some motherboards are broken and has zero in ROM. */
3951 if (!is_valid_ether_addr(dev->dev_addr))
3952 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3953
3954 err = register_netdev(dev);
3955 if (err) {
3956 dev_err(&pdev->dev, "cannot register net device\n");
3957 goto err_out_free_netdev;
3958 }
3959
3960 skge_show_addr(dev);
3961
3962 if (hw->ports > 1) {
3963 dev1 = skge_devinit(hw, 1, using_dac);
3964 if (!dev1) {
3965 err = -ENOMEM;
3966 goto err_out_unregister;
3967 }
3968
3969 err = register_netdev(dev1);
3970 if (err) {
3971 dev_err(&pdev->dev, "cannot register second net device\n");
3972 goto err_out_free_dev1;
3973 }
3974
3975 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3976 hw->irq_name, hw);
3977 if (err) {
3978 dev_err(&pdev->dev, "cannot assign irq %d\n",
3979 pdev->irq);
3980 goto err_out_unregister_dev1;
3981 }
3982
3983 skge_show_addr(dev1);
3984 }
3985 pci_set_drvdata(pdev, hw);
3986
3987 return 0;
3988
3989 err_out_unregister_dev1:
3990 unregister_netdev(dev1);
3991 err_out_free_dev1:
3992 free_netdev(dev1);
3993 err_out_unregister:
3994 unregister_netdev(dev);
3995 err_out_free_netdev:
3996 free_netdev(dev);
3997 err_out_led_off:
3998 skge_write16(hw, B0_LED, LED_STAT_OFF);
3999 err_out_iounmap:
4000 iounmap(hw->regs);
4001 err_out_free_hw:
4002 kfree(hw);
4003 err_out_free_regions:
4004 pci_release_regions(pdev);
4005 err_out_disable_pdev:
4006 pci_disable_device(pdev);
4007 pci_set_drvdata(pdev, NULL);
4008 err_out:
4009 return err;
4010 }
4011
4012 static void skge_remove(struct pci_dev *pdev)
4013 {
4014 struct skge_hw *hw = pci_get_drvdata(pdev);
4015 struct net_device *dev0, *dev1;
4016
4017 if (!hw)
4018 return;
4019
4020 dev1 = hw->dev[1];
4021 if (dev1)
4022 unregister_netdev(dev1);
4023 dev0 = hw->dev[0];
4024 unregister_netdev(dev0);
4025
4026 tasklet_kill(&hw->phy_task);
4027
4028 spin_lock_irq(&hw->hw_lock);
4029 hw->intr_mask = 0;
4030
4031 if (hw->ports > 1) {
4032 skge_write32(hw, B0_IMSK, 0);
4033 skge_read32(hw, B0_IMSK);
4034 free_irq(pdev->irq, hw);
4035 }
4036 spin_unlock_irq(&hw->hw_lock);
4037
4038 skge_write16(hw, B0_LED, LED_STAT_OFF);
4039 skge_write8(hw, B0_CTST, CS_RST_SET);
4040
4041 if (hw->ports > 1)
4042 free_irq(pdev->irq, hw);
4043 pci_release_regions(pdev);
4044 pci_disable_device(pdev);
4045 if (dev1)
4046 free_netdev(dev1);
4047 free_netdev(dev0);
4048
4049 iounmap(hw->regs);
4050 kfree(hw);
4051 pci_set_drvdata(pdev, NULL);
4052 }
4053
4054 #ifdef CONFIG_PM_SLEEP
4055 static int skge_suspend(struct device *dev)
4056 {
4057 struct pci_dev *pdev = to_pci_dev(dev);
4058 struct skge_hw *hw = pci_get_drvdata(pdev);
4059 int i;
4060
4061 if (!hw)
4062 return 0;
4063
4064 for (i = 0; i < hw->ports; i++) {
4065 struct net_device *dev = hw->dev[i];
4066 struct skge_port *skge = netdev_priv(dev);
4067
4068 if (netif_running(dev))
4069 skge_down(dev);
4070
4071 if (skge->wol)
4072 skge_wol_init(skge);
4073 }
4074
4075 skge_write32(hw, B0_IMSK, 0);
4076
4077 return 0;
4078 }
4079
4080 static int skge_resume(struct device *dev)
4081 {
4082 struct pci_dev *pdev = to_pci_dev(dev);
4083 struct skge_hw *hw = pci_get_drvdata(pdev);
4084 int i, err;
4085
4086 if (!hw)
4087 return 0;
4088
4089 err = skge_reset(hw);
4090 if (err)
4091 goto out;
4092
4093 for (i = 0; i < hw->ports; i++) {
4094 struct net_device *dev = hw->dev[i];
4095
4096 if (netif_running(dev)) {
4097 err = skge_up(dev);
4098
4099 if (err) {
4100 netdev_err(dev, "could not up: %d\n", err);
4101 dev_close(dev);
4102 goto out;
4103 }
4104 }
4105 }
4106 out:
4107 return err;
4108 }
4109
4110 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4111 #define SKGE_PM_OPS (&skge_pm_ops)
4112
4113 #else
4114
4115 #define SKGE_PM_OPS NULL
4116 #endif /* CONFIG_PM_SLEEP */
4117
4118 static void skge_shutdown(struct pci_dev *pdev)
4119 {
4120 struct skge_hw *hw = pci_get_drvdata(pdev);
4121 int i;
4122
4123 if (!hw)
4124 return;
4125
4126 for (i = 0; i < hw->ports; i++) {
4127 struct net_device *dev = hw->dev[i];
4128 struct skge_port *skge = netdev_priv(dev);
4129
4130 if (skge->wol)
4131 skge_wol_init(skge);
4132 }
4133
4134 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4135 pci_set_power_state(pdev, PCI_D3hot);
4136 }
4137
4138 static struct pci_driver skge_driver = {
4139 .name = DRV_NAME,
4140 .id_table = skge_id_table,
4141 .probe = skge_probe,
4142 .remove = skge_remove,
4143 .shutdown = skge_shutdown,
4144 .driver.pm = SKGE_PM_OPS,
4145 };
4146
4147 static struct dmi_system_id skge_32bit_dma_boards[] = {
4148 {
4149 .ident = "Gigabyte nForce boards",
4150 .matches = {
4151 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4152 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4153 },
4154 },
4155 {
4156 .ident = "ASUS P5NSLI",
4157 .matches = {
4158 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4159 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4160 },
4161 },
4162 {}
4163 };
4164
4165 static int __init skge_init_module(void)
4166 {
4167 if (dmi_check_system(skge_32bit_dma_boards))
4168 only_32bit_dma = 1;
4169 skge_debug_init();
4170 return pci_register_driver(&skge_driver);
4171 }
4172
4173 static void __exit skge_cleanup_module(void)
4174 {
4175 pci_unregister_driver(&skge_driver);
4176 skge_debug_cleanup();
4177 }
4178
4179 module_init(skge_init_module);
4180 module_exit(skge_cleanup_module);
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