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[media] coda: add coda_bit_stream_set_flag helper
[linux-2.6/btrfs-unstable.git] / drivers / media / platform / coda / coda-common.c
blob3e232441549bc23715043d08498a32d9297151af
1 /*
2 * Coda multi-standard codec IP
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/genalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/irq.h>
22 #include <linux/kfifo.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/slab.h>
28 #include <linux/videodev2.h>
29 #include <linux/of.h>
30 #include <linux/platform_data/coda.h>
31 #include <linux/reset.h>
32
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-event.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/v4l2-mem2mem.h>
38 #include <media/videobuf2-core.h>
39 #include <media/videobuf2-dma-contig.h>
40
41 #include "coda.h"
42 #include "coda_regs.h"
43
44 #define CODA_NAME "coda"
45
46 #define CODADX6_MAX_INSTANCES 4
47
48 #define CODA_PARA_BUF_SIZE (10 * 1024)
49 #define CODA_ISRAM_SIZE (2048 * 2)
50
51 #define CODA7_PS_BUF_SIZE 0x28000
52 #define CODA9_PS_SAVE_SIZE (512 * 1024)
53
54 #define CODA_DEFAULT_GAMMA 4096
55 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
56
57 #define MIN_W 176
58 #define MIN_H 144
59
60 #define S_ALIGN 1 /* multiple of 2 */
61 #define W_ALIGN 1 /* multiple of 2 */
62 #define H_ALIGN 1 /* multiple of 2 */
63
64 #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
65
66 static int coda_debug;
67 module_param(coda_debug, int, 0644);
68 MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
69
70 struct coda_fmt {
71 char *name;
72 u32 fourcc;
73 };
74
75 static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
76 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80 };
77 static const u8 coda_filler_size[8] = { 0, 7, 14, 13, 12, 11, 10, 9 };
78
79 void coda_write(struct coda_dev *dev, u32 data, u32 reg)
80 {
81 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
82 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
83 writel(data, dev->regs_base + reg);
84 }
85
86 unsigned int coda_read(struct coda_dev *dev, u32 reg)
87 {
88 u32 data;
89 data = readl(dev->regs_base + reg);
90 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
91 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
92 return data;
93 }
94
95 static inline unsigned long coda_isbusy(struct coda_dev *dev)
96 {
97 return coda_read(dev, CODA_REG_BIT_BUSY);
98 }
99
100 static inline int coda_is_initialized(struct coda_dev *dev)
101 {
102 return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
103 }
104
105 static int coda_wait_timeout(struct coda_dev *dev)
106 {
107 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
108
109 while (coda_isbusy(dev)) {
110 if (time_after(jiffies, timeout))
111 return -ETIMEDOUT;
112 }
113 return 0;
114 }
115
116 static void coda_command_async(struct coda_ctx *ctx, int cmd)
117 {
118 struct coda_dev *dev = ctx->dev;
119
120 if (dev->devtype->product == CODA_960 ||
121 dev->devtype->product == CODA_7541) {
122 /* Restore context related registers to CODA */
123 coda_write(dev, ctx->bit_stream_param,
124 CODA_REG_BIT_BIT_STREAM_PARAM);
125 coda_write(dev, ctx->frm_dis_flg,
126 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
127 coda_write(dev, ctx->frame_mem_ctrl,
128 CODA_REG_BIT_FRAME_MEM_CTRL);
129 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
130 }
131
132 if (dev->devtype->product == CODA_960) {
133 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
134 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
135 }
136
137 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
138
139 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
140 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
141 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
142
143 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
144 }
145
146 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
147 {
148 struct coda_dev *dev = ctx->dev;
149
150 coda_command_async(ctx, cmd);
151 return coda_wait_timeout(dev);
152 }
153
154 static int coda_hw_reset(struct coda_ctx *ctx)
155 {
156 struct coda_dev *dev = ctx->dev;
157 unsigned long timeout;
158 unsigned int idx;
159 int ret;
160
161 if (!dev->rstc)
162 return -ENOENT;
163
164 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
165
166 if (dev->devtype->product == CODA_960) {
167 timeout = jiffies + msecs_to_jiffies(100);
168 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
169 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
170 if (time_after(jiffies, timeout))
171 return -ETIME;
172 cpu_relax();
173 }
174 }
175
176 ret = reset_control_reset(dev->rstc);
177 if (ret < 0)
178 return ret;
179
180 if (dev->devtype->product == CODA_960)
181 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
182 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
183 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
184 ret = coda_wait_timeout(dev);
185 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
186
187 return ret;
188 }
189
190 static void coda_bit_stream_end_flag(struct coda_ctx *ctx)
191 {
192 struct coda_dev *dev = ctx->dev;
193
194 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
195
196 if ((dev->devtype->product == CODA_960) &&
197 coda_isbusy(dev) &&
198 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
199 /* If this context is currently running, update the hardware flag */
200 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
201 }
202 }
203
204 static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
205 enum v4l2_buf_type type)
206 {
207 switch (type) {
208 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
209 return &(ctx->q_data[V4L2_M2M_SRC]);
210 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
211 return &(ctx->q_data[V4L2_M2M_DST]);
212 default:
213 return NULL;
214 }
215 }
216
217 /*
218 * Array of all formats supported by any version of Coda:
219 */
220 static const struct coda_fmt coda_formats[] = {
221 {
222 .name = "YUV 4:2:0 Planar, YCbCr",
223 .fourcc = V4L2_PIX_FMT_YUV420,
224 },
225 {
226 .name = "YUV 4:2:0 Planar, YCrCb",
227 .fourcc = V4L2_PIX_FMT_YVU420,
228 },
229 {
230 .name = "H264 Encoded Stream",
231 .fourcc = V4L2_PIX_FMT_H264,
232 },
233 {
234 .name = "MPEG4 Encoded Stream",
235 .fourcc = V4L2_PIX_FMT_MPEG4,
236 },
237 };
238
239 #define CODA_CODEC(mode, src_fourcc, dst_fourcc, max_w, max_h) \
240 { mode, src_fourcc, dst_fourcc, max_w, max_h }
241
242 /*
243 * Arrays of codecs supported by each given version of Coda:
244 * i.MX27 -> codadx6
245 * i.MX5x -> coda7
246 * i.MX6 -> coda960
247 * Use V4L2_PIX_FMT_YUV420 as placeholder for all supported YUV 4:2:0 variants
248 */
249 static const struct coda_codec codadx6_codecs[] = {
250 CODA_CODEC(CODADX6_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 720, 576),
251 CODA_CODEC(CODADX6_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 720, 576),
252 };
253
254 static const struct coda_codec coda7_codecs[] = {
255 CODA_CODEC(CODA7_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 1280, 720),
256 CODA_CODEC(CODA7_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 1280, 720),
257 CODA_CODEC(CODA7_MODE_DECODE_H264, V4L2_PIX_FMT_H264, V4L2_PIX_FMT_YUV420, 1920, 1080),
258 CODA_CODEC(CODA7_MODE_DECODE_MP4, V4L2_PIX_FMT_MPEG4, V4L2_PIX_FMT_YUV420, 1920, 1080),
259 };
260
261 static const struct coda_codec coda9_codecs[] = {
262 CODA_CODEC(CODA9_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 1920, 1080),
263 CODA_CODEC(CODA9_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 1920, 1080),
264 CODA_CODEC(CODA9_MODE_DECODE_H264, V4L2_PIX_FMT_H264, V4L2_PIX_FMT_YUV420, 1920, 1080),
265 CODA_CODEC(CODA9_MODE_DECODE_MP4, V4L2_PIX_FMT_MPEG4, V4L2_PIX_FMT_YUV420, 1920, 1080),
266 };
267
268 static bool coda_format_is_yuv(u32 fourcc)
269 {
270 switch (fourcc) {
271 case V4L2_PIX_FMT_YUV420:
272 case V4L2_PIX_FMT_YVU420:
273 return true;
274 default:
275 return false;
276 }
277 }
278
279 /*
280 * Normalize all supported YUV 4:2:0 formats to the value used in the codec
281 * tables.
282 */
283 static u32 coda_format_normalize_yuv(u32 fourcc)
284 {
285 return coda_format_is_yuv(fourcc) ? V4L2_PIX_FMT_YUV420 : fourcc;
286 }
287
288 static const struct coda_codec *coda_find_codec(struct coda_dev *dev,
289 int src_fourcc, int dst_fourcc)
290 {
291 const struct coda_codec *codecs = dev->devtype->codecs;
292 int num_codecs = dev->devtype->num_codecs;
293 int k;
294
295 src_fourcc = coda_format_normalize_yuv(src_fourcc);
296 dst_fourcc = coda_format_normalize_yuv(dst_fourcc);
297 if (src_fourcc == dst_fourcc)
298 return NULL;
299
300 for (k = 0; k < num_codecs; k++) {
301 if (codecs[k].src_fourcc == src_fourcc &&
302 codecs[k].dst_fourcc == dst_fourcc)
303 break;
304 }
305
306 if (k == num_codecs)
307 return NULL;
308
309 return &codecs[k];
310 }
311
312 static void coda_get_max_dimensions(struct coda_dev *dev,
313 const struct coda_codec *codec,
314 int *max_w, int *max_h)
315 {
316 const struct coda_codec *codecs = dev->devtype->codecs;
317 int num_codecs = dev->devtype->num_codecs;
318 unsigned int w, h;
319 int k;
320
321 if (codec) {
322 w = codec->max_w;
323 h = codec->max_h;
324 } else {
325 for (k = 0, w = 0, h = 0; k < num_codecs; k++) {
326 w = max(w, codecs[k].max_w);
327 h = max(h, codecs[k].max_h);
328 }
329 }
330
331 if (max_w)
332 *max_w = w;
333 if (max_h)
334 *max_h = h;
335 }
336
337 static char *coda_product_name(int product)
338 {
339 static char buf[9];
340
341 switch (product) {
342 case CODA_DX6:
343 return "CodaDx6";
344 case CODA_7541:
345 return "CODA7541";
346 case CODA_960:
347 return "CODA960";
348 default:
349 snprintf(buf, sizeof(buf), "(0x%04x)", product);
350 return buf;
351 }
352 }
353
354 /*
355 * V4L2 ioctl() operations.
356 */
357 static int coda_querycap(struct file *file, void *priv,
358 struct v4l2_capability *cap)
359 {
360 struct coda_ctx *ctx = fh_to_ctx(priv);
361
362 strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
363 strlcpy(cap->card, coda_product_name(ctx->dev->devtype->product),
364 sizeof(cap->card));
365 strlcpy(cap->bus_info, "platform:" CODA_NAME, sizeof(cap->bus_info));
366 cap->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
367 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
368
369 return 0;
370 }
371
372 static int coda_enum_fmt(struct file *file, void *priv,
373 struct v4l2_fmtdesc *f)
374 {
375 struct coda_ctx *ctx = fh_to_ctx(priv);
376 const struct coda_codec *codecs = ctx->dev->devtype->codecs;
377 const struct coda_fmt *formats = coda_formats;
378 const struct coda_fmt *fmt;
379 int num_codecs = ctx->dev->devtype->num_codecs;
380 int num_formats = ARRAY_SIZE(coda_formats);
381 int i, k, num = 0;
382 bool yuv;
383
384 if (ctx->inst_type == CODA_INST_ENCODER)
385 yuv = (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT);
386 else
387 yuv = (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE);
388
389 for (i = 0; i < num_formats; i++) {
390 /* Skip either raw or compressed formats */
391 if (yuv != coda_format_is_yuv(formats[i].fourcc))
392 continue;
393 /* All uncompressed formats are always supported */
394 if (yuv) {
395 if (num == f->index)
396 break;
397 ++num;
398 continue;
399 }
400 /* Compressed formats may be supported, check the codec list */
401 for (k = 0; k < num_codecs; k++) {
402 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE &&
403 formats[i].fourcc == codecs[k].dst_fourcc)
404 break;
405 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT &&
406 formats[i].fourcc == codecs[k].src_fourcc)
407 break;
408 }
409 if (k < num_codecs) {
410 if (num == f->index)
411 break;
412 ++num;
413 }
414 }
415
416 if (i < num_formats) {
417 fmt = &formats[i];
418 strlcpy(f->description, fmt->name, sizeof(f->description));
419 f->pixelformat = fmt->fourcc;
420 if (!yuv)
421 f->flags |= V4L2_FMT_FLAG_COMPRESSED;
422 return 0;
423 }
424
425 /* Format not found */
426 return -EINVAL;
427 }
428
429 static int coda_g_fmt(struct file *file, void *priv,
430 struct v4l2_format *f)
431 {
432 struct coda_q_data *q_data;
433 struct coda_ctx *ctx = fh_to_ctx(priv);
434
435 q_data = get_q_data(ctx, f->type);
436 if (!q_data)
437 return -EINVAL;
438
439 f->fmt.pix.field = V4L2_FIELD_NONE;
440 f->fmt.pix.pixelformat = q_data->fourcc;
441 f->fmt.pix.width = q_data->width;
442 f->fmt.pix.height = q_data->height;
443 f->fmt.pix.bytesperline = q_data->bytesperline;
444
445 f->fmt.pix.sizeimage = q_data->sizeimage;
446 f->fmt.pix.colorspace = ctx->colorspace;
447
448 return 0;
449 }
450
451 static int coda_try_fmt(struct coda_ctx *ctx, const struct coda_codec *codec,
452 struct v4l2_format *f)
453 {
454 struct coda_dev *dev = ctx->dev;
455 struct coda_q_data *q_data;
456 unsigned int max_w, max_h;
457 enum v4l2_field field;
458
459 field = f->fmt.pix.field;
460 if (field == V4L2_FIELD_ANY)
461 field = V4L2_FIELD_NONE;
462 else if (V4L2_FIELD_NONE != field)
463 return -EINVAL;
464
465 /* V4L2 specification suggests the driver corrects the format struct
466 * if any of the dimensions is unsupported */
467 f->fmt.pix.field = field;
468
469 coda_get_max_dimensions(dev, codec, &max_w, &max_h);
470 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, max_w, W_ALIGN,
471 &f->fmt.pix.height, MIN_H, max_h, H_ALIGN,
472 S_ALIGN);
473
474 switch (f->fmt.pix.pixelformat) {
475 case V4L2_PIX_FMT_YUV420:
476 case V4L2_PIX_FMT_YVU420:
477 case V4L2_PIX_FMT_H264:
478 case V4L2_PIX_FMT_MPEG4:
479 case V4L2_PIX_FMT_JPEG:
480 break;
481 default:
482 q_data = get_q_data(ctx, f->type);
483 if (!q_data)
484 return -EINVAL;
485 f->fmt.pix.pixelformat = q_data->fourcc;
486 }
487
488 switch (f->fmt.pix.pixelformat) {
489 case V4L2_PIX_FMT_YUV420:
490 case V4L2_PIX_FMT_YVU420:
491 /* Frame stride must be multiple of 8, but 16 for h.264 */
492 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 16);
493 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline *
494 f->fmt.pix.height * 3 / 2;
495 break;
496 case V4L2_PIX_FMT_H264:
497 case V4L2_PIX_FMT_MPEG4:
498 case V4L2_PIX_FMT_JPEG:
499 f->fmt.pix.bytesperline = 0;
500 f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
501 break;
502 default:
503 BUG();
504 }
505
506 return 0;
507 }
508
509 static int coda_try_fmt_vid_cap(struct file *file, void *priv,
510 struct v4l2_format *f)
511 {
512 struct coda_ctx *ctx = fh_to_ctx(priv);
513 const struct coda_codec *codec = NULL;
514 struct vb2_queue *src_vq;
515 int ret;
516
517 /*
518 * If the source format is already fixed, try to find a codec that
519 * converts to the given destination format
520 */
521 src_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
522 if (vb2_is_streaming(src_vq)) {
523 struct coda_q_data *q_data_src;
524
525 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
526 codec = coda_find_codec(ctx->dev, q_data_src->fourcc,
527 f->fmt.pix.pixelformat);
528 if (!codec)
529 return -EINVAL;
530
531 f->fmt.pix.width = q_data_src->width;
532 f->fmt.pix.height = q_data_src->height;
533 } else {
534 /* Otherwise determine codec by encoded format, if possible */
535 codec = coda_find_codec(ctx->dev, V4L2_PIX_FMT_YUV420,
536 f->fmt.pix.pixelformat);
537 }
538
539 f->fmt.pix.colorspace = ctx->colorspace;
540
541 ret = coda_try_fmt(ctx, codec, f);
542 if (ret < 0)
543 return ret;
544
545 /* The h.264 decoder only returns complete 16x16 macroblocks */
546 if (codec && codec->src_fourcc == V4L2_PIX_FMT_H264) {
547 f->fmt.pix.width = f->fmt.pix.width;
548 f->fmt.pix.height = round_up(f->fmt.pix.height, 16);
549 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 16);
550 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline *
551 f->fmt.pix.height * 3 / 2;
552 }
553
554 return 0;
555 }
556
557 static int coda_try_fmt_vid_out(struct file *file, void *priv,
558 struct v4l2_format *f)
559 {
560 struct coda_ctx *ctx = fh_to_ctx(priv);
561 const struct coda_codec *codec;
562
563 /* Determine codec by encoded format, returns NULL if raw or invalid */
564 codec = coda_find_codec(ctx->dev, f->fmt.pix.pixelformat,
565 V4L2_PIX_FMT_YUV420);
566 if (!codec && ctx->inst_type == CODA_INST_DECODER) {
567 codec = coda_find_codec(ctx->dev, V4L2_PIX_FMT_H264,
568 V4L2_PIX_FMT_YUV420);
569 if (!codec)
570 return -EINVAL;
571 }
572
573 if (!f->fmt.pix.colorspace)
574 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
575
576 return coda_try_fmt(ctx, codec, f);
577 }
578
579 static int coda_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
580 {
581 struct coda_q_data *q_data;
582 struct vb2_queue *vq;
583
584 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
585 if (!vq)
586 return -EINVAL;
587
588 q_data = get_q_data(ctx, f->type);
589 if (!q_data)
590 return -EINVAL;
591
592 if (vb2_is_busy(vq)) {
593 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
594 return -EBUSY;
595 }
596
597 q_data->fourcc = f->fmt.pix.pixelformat;
598 q_data->width = f->fmt.pix.width;
599 q_data->height = f->fmt.pix.height;
600 q_data->bytesperline = f->fmt.pix.bytesperline;
601 q_data->sizeimage = f->fmt.pix.sizeimage;
602 q_data->rect.left = 0;
603 q_data->rect.top = 0;
604 q_data->rect.width = f->fmt.pix.width;
605 q_data->rect.height = f->fmt.pix.height;
606
607 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
608 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
609 f->type, q_data->width, q_data->height, q_data->fourcc);
610
611 return 0;
612 }
613
614 static int coda_s_fmt_vid_cap(struct file *file, void *priv,
615 struct v4l2_format *f)
616 {
617 struct coda_ctx *ctx = fh_to_ctx(priv);
618 int ret;
619
620 ret = coda_try_fmt_vid_cap(file, priv, f);
621 if (ret)
622 return ret;
623
624 return coda_s_fmt(ctx, f);
625 }
626
627 static int coda_s_fmt_vid_out(struct file *file, void *priv,
628 struct v4l2_format *f)
629 {
630 struct coda_ctx *ctx = fh_to_ctx(priv);
631 int ret;
632
633 ret = coda_try_fmt_vid_out(file, priv, f);
634 if (ret)
635 return ret;
636
637 ret = coda_s_fmt(ctx, f);
638 if (ret)
639 ctx->colorspace = f->fmt.pix.colorspace;
640
641 return ret;
642 }
643
644 static int coda_qbuf(struct file *file, void *priv,
645 struct v4l2_buffer *buf)
646 {
647 struct coda_ctx *ctx = fh_to_ctx(priv);
648
649 return v4l2_m2m_qbuf(file, ctx->fh.m2m_ctx, buf);
650 }
651
652 static bool coda_buf_is_end_of_stream(struct coda_ctx *ctx,
653 struct v4l2_buffer *buf)
654 {
655 struct vb2_queue *src_vq;
656
657 src_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
658
659 return ((ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) &&
660 (buf->sequence == (ctx->qsequence - 1)));
661 }
662
663 static int coda_dqbuf(struct file *file, void *priv,
664 struct v4l2_buffer *buf)
665 {
666 struct coda_ctx *ctx = fh_to_ctx(priv);
667 int ret;
668
669 ret = v4l2_m2m_dqbuf(file, ctx->fh.m2m_ctx, buf);
670
671 /* If this is the last capture buffer, emit an end-of-stream event */
672 if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE &&
673 coda_buf_is_end_of_stream(ctx, buf)) {
674 const struct v4l2_event eos_event = {
675 .type = V4L2_EVENT_EOS
676 };
677
678 v4l2_event_queue_fh(&ctx->fh, &eos_event);
679 }
680
681 return ret;
682 }
683
684 static int coda_g_selection(struct file *file, void *fh,
685 struct v4l2_selection *s)
686 {
687 struct coda_ctx *ctx = fh_to_ctx(fh);
688 struct coda_q_data *q_data;
689 struct v4l2_rect r, *rsel;
690
691 q_data = get_q_data(ctx, s->type);
692 if (!q_data)
693 return -EINVAL;
694
695 r.left = 0;
696 r.top = 0;
697 r.width = q_data->width;
698 r.height = q_data->height;
699 rsel = &q_data->rect;
700
701 switch (s->target) {
702 case V4L2_SEL_TGT_CROP_DEFAULT:
703 case V4L2_SEL_TGT_CROP_BOUNDS:
704 rsel = &r;
705 /* fallthrough */
706 case V4L2_SEL_TGT_CROP:
707 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
708 return -EINVAL;
709 break;
710 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
711 case V4L2_SEL_TGT_COMPOSE_PADDED:
712 rsel = &r;
713 /* fallthrough */
714 case V4L2_SEL_TGT_COMPOSE:
715 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
716 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
717 return -EINVAL;
718 break;
719 default:
720 return -EINVAL;
721 }
722
723 s->r = *rsel;
724
725 return 0;
726 }
727
728 static int coda_try_decoder_cmd(struct file *file, void *fh,
729 struct v4l2_decoder_cmd *dc)
730 {
731 if (dc->cmd != V4L2_DEC_CMD_STOP)
732 return -EINVAL;
733
734 if (dc->flags & V4L2_DEC_CMD_STOP_TO_BLACK)
735 return -EINVAL;
736
737 if (!(dc->flags & V4L2_DEC_CMD_STOP_IMMEDIATELY) && (dc->stop.pts != 0))
738 return -EINVAL;
739
740 return 0;
741 }
742
743 static int coda_decoder_cmd(struct file *file, void *fh,
744 struct v4l2_decoder_cmd *dc)
745 {
746 struct coda_ctx *ctx = fh_to_ctx(fh);
747 int ret;
748
749 ret = coda_try_decoder_cmd(file, fh, dc);
750 if (ret < 0)
751 return ret;
752
753 /* Ignore decoder stop command silently in encoder context */
754 if (ctx->inst_type != CODA_INST_DECODER)
755 return 0;
756
757 /* Set the stream-end flag on this context */
758 coda_bit_stream_end_flag(ctx);
759 ctx->hold = false;
760 v4l2_m2m_try_schedule(ctx->fh.m2m_ctx);
761
762 return 0;
763 }
764
765 static int coda_subscribe_event(struct v4l2_fh *fh,
766 const struct v4l2_event_subscription *sub)
767 {
768 switch (sub->type) {
769 case V4L2_EVENT_EOS:
770 return v4l2_event_subscribe(fh, sub, 0, NULL);
771 default:
772 return v4l2_ctrl_subscribe_event(fh, sub);
773 }
774 }
775
776 static const struct v4l2_ioctl_ops coda_ioctl_ops = {
777 .vidioc_querycap = coda_querycap,
778
779 .vidioc_enum_fmt_vid_cap = coda_enum_fmt,
780 .vidioc_g_fmt_vid_cap = coda_g_fmt,
781 .vidioc_try_fmt_vid_cap = coda_try_fmt_vid_cap,
782 .vidioc_s_fmt_vid_cap = coda_s_fmt_vid_cap,
783
784 .vidioc_enum_fmt_vid_out = coda_enum_fmt,
785 .vidioc_g_fmt_vid_out = coda_g_fmt,
786 .vidioc_try_fmt_vid_out = coda_try_fmt_vid_out,
787 .vidioc_s_fmt_vid_out = coda_s_fmt_vid_out,
788
789 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
790 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
791
792 .vidioc_qbuf = coda_qbuf,
793 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
794 .vidioc_dqbuf = coda_dqbuf,
795 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
796
797 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
798 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
799
800 .vidioc_g_selection = coda_g_selection,
801
802 .vidioc_try_decoder_cmd = coda_try_decoder_cmd,
803 .vidioc_decoder_cmd = coda_decoder_cmd,
804
805 .vidioc_subscribe_event = coda_subscribe_event,
806 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
807 };
808
809 static int __coda_start_decoding(struct coda_ctx *ctx);
810
811 static inline int coda_get_bitstream_payload(struct coda_ctx *ctx)
812 {
813 return kfifo_len(&ctx->bitstream_fifo);
814 }
815
816 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
817 {
818 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
819 struct coda_dev *dev = ctx->dev;
820 u32 rd_ptr;
821
822 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
823 kfifo->out = (kfifo->in & ~kfifo->mask) |
824 (rd_ptr - ctx->bitstream.paddr);
825 if (kfifo->out > kfifo->in)
826 kfifo->out -= kfifo->mask + 1;
827 }
828
829 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
830 {
831 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
832 struct coda_dev *dev = ctx->dev;
833 u32 rd_ptr, wr_ptr;
834
835 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
836 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
837 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
838 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
839 }
840
841 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
842 {
843 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
844 struct coda_dev *dev = ctx->dev;
845 u32 wr_ptr;
846
847 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
848 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
849 }
850
851 static int coda_bitstream_queue(struct coda_ctx *ctx, struct vb2_buffer *src_buf)
852 {
853 u32 src_size = vb2_get_plane_payload(src_buf, 0);
854 u32 n;
855
856 n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0), src_size);
857 if (n < src_size)
858 return -ENOSPC;
859
860 dma_sync_single_for_device(&ctx->dev->plat_dev->dev, ctx->bitstream.paddr,
861 ctx->bitstream.size, DMA_TO_DEVICE);
862
863 src_buf->v4l2_buf.sequence = ctx->qsequence++;
864
865 return 0;
866 }
867
868 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
869 struct vb2_buffer *src_buf)
870 {
871 int ret;
872
873 if (coda_get_bitstream_payload(ctx) +
874 vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
875 return false;
876
877 if (vb2_plane_vaddr(src_buf, 0) == NULL) {
878 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
879 return true;
880 }
881
882 ret = coda_bitstream_queue(ctx, src_buf);
883 if (ret < 0) {
884 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
885 return false;
886 }
887 /* Sync read pointer to device */
888 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
889 coda_kfifo_sync_to_device_write(ctx);
890
891 ctx->hold = false;
892
893 return true;
894 }
895
896 static void coda_fill_bitstream(struct coda_ctx *ctx)
897 {
898 struct vb2_buffer *src_buf;
899 struct coda_timestamp *ts;
900
901 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
902 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
903
904 if (coda_bitstream_try_queue(ctx, src_buf)) {
905 /*
906 * Source buffer is queued in the bitstream ringbuffer;
907 * queue the timestamp and mark source buffer as done
908 */
909 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
910
911 ts = kmalloc(sizeof(*ts), GFP_KERNEL);
912 if (ts) {
913 ts->sequence = src_buf->v4l2_buf.sequence;
914 ts->timecode = src_buf->v4l2_buf.timecode;
915 ts->timestamp = src_buf->v4l2_buf.timestamp;
916 list_add_tail(&ts->list, &ctx->timestamp_list);
917 }
918
919 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
920 } else {
921 break;
922 }
923 }
924 }
925
926 static void coda_set_gdi_regs(struct coda_ctx *ctx)
927 {
928 struct gdi_tiled_map *tiled_map = &ctx->tiled_map;
929 struct coda_dev *dev = ctx->dev;
930 int i;
931
932 for (i = 0; i < 16; i++)
933 coda_write(dev, tiled_map->xy2ca_map[i],
934 CODA9_GDI_XY2_CAS_0 + 4 * i);
935 for (i = 0; i < 4; i++)
936 coda_write(dev, tiled_map->xy2ba_map[i],
937 CODA9_GDI_XY2_BA_0 + 4 * i);
938 for (i = 0; i < 16; i++)
939 coda_write(dev, tiled_map->xy2ra_map[i],
940 CODA9_GDI_XY2_RAS_0 + 4 * i);
941 coda_write(dev, tiled_map->xy2rbc_config, CODA9_GDI_XY2_RBC_CONFIG);
942 for (i = 0; i < 32; i++)
943 coda_write(dev, tiled_map->rbc2axi_map[i],
944 CODA9_GDI_RBC2_AXI_0 + 4 * i);
945 }
946
947 /*
948 * Mem-to-mem operations.
949 */
950 static int coda_prepare_decode(struct coda_ctx *ctx)
951 {
952 struct vb2_buffer *dst_buf;
953 struct coda_dev *dev = ctx->dev;
954 struct coda_q_data *q_data_dst;
955 u32 stridey, height;
956 u32 picture_y, picture_cb, picture_cr;
957
958 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
959 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
960
961 if (ctx->params.rot_mode & CODA_ROT_90) {
962 stridey = q_data_dst->height;
963 height = q_data_dst->width;
964 } else {
965 stridey = q_data_dst->width;
966 height = q_data_dst->height;
967 }
968
969 /* Try to copy source buffer contents into the bitstream ringbuffer */
970 mutex_lock(&ctx->bitstream_mutex);
971 coda_fill_bitstream(ctx);
972 mutex_unlock(&ctx->bitstream_mutex);
973
974 if (coda_get_bitstream_payload(ctx) < 512 &&
975 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
976 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
977 "bitstream payload: %d, skipping\n",
978 coda_get_bitstream_payload(ctx));
979 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
980 return -EAGAIN;
981 }
982
983 /* Run coda_start_decoding (again) if not yet initialized */
984 if (!ctx->initialized) {
985 int ret = __coda_start_decoding(ctx);
986 if (ret < 0) {
987 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
988 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
989 return -EAGAIN;
990 } else {
991 ctx->initialized = 1;
992 }
993 }
994
995 if (dev->devtype->product == CODA_960)
996 coda_set_gdi_regs(ctx);
997
998 /* Set rotator output */
999 picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1000 if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) {
1001 /* Switch Cr and Cb for YVU420 format */
1002 picture_cr = picture_y + stridey * height;
1003 picture_cb = picture_cr + stridey / 2 * height / 2;
1004 } else {
1005 picture_cb = picture_y + stridey * height;
1006 picture_cr = picture_cb + stridey / 2 * height / 2;
1007 }
1008
1009 if (dev->devtype->product == CODA_960) {
1010 /*
1011 * The CODA960 seems to have an internal list of buffers with
1012 * 64 entries that includes the registered frame buffers as
1013 * well as the rotator buffer output.
1014 * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1015 */
1016 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1017 CODA9_CMD_DEC_PIC_ROT_INDEX);
1018 coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y);
1019 coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB);
1020 coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR);
1021 coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE);
1022 } else {
1023 coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y);
1024 coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB);
1025 coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR);
1026 coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE);
1027 }
1028 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1029 CODA_CMD_DEC_PIC_ROT_MODE);
1030
1031 switch (dev->devtype->product) {
1032 case CODA_DX6:
1033 /* TBD */
1034 case CODA_7541:
1035 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1036 break;
1037 case CODA_960:
1038 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION); /* 'hardcode to use interrupt disable mode'? */
1039 break;
1040 }
1041
1042 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1043
1044 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1045 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1046
1047 if (dev->devtype->product != CODA_DX6)
1048 coda_write(dev, ctx->iram_info.axi_sram_use,
1049 CODA7_REG_BIT_AXI_SRAM_USE);
1050
1051 coda_kfifo_sync_to_device_full(ctx);
1052 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1053
1054 return 0;
1055 }
1056
1057 static int coda_prepare_encode(struct coda_ctx *ctx)
1058 {
1059 struct coda_q_data *q_data_src, *q_data_dst;
1060 struct vb2_buffer *src_buf, *dst_buf;
1061 struct coda_dev *dev = ctx->dev;
1062 int force_ipicture;
1063 int quant_param = 0;
1064 u32 picture_y, picture_cb, picture_cr;
1065 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1066 u32 dst_fourcc;
1067
1068 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1069 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1070 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1071 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1072 dst_fourcc = q_data_dst->fourcc;
1073
1074 src_buf->v4l2_buf.sequence = ctx->osequence;
1075 dst_buf->v4l2_buf.sequence = ctx->osequence;
1076 ctx->osequence++;
1077
1078 /*
1079 * Workaround coda firmware BUG that only marks the first
1080 * frame as IDR. This is a problem for some decoders that can't
1081 * recover when a frame is lost.
1082 */
1083 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1084 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1085 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1086 } else {
1087 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1088 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1089 }
1090
1091 if (dev->devtype->product == CODA_960)
1092 coda_set_gdi_regs(ctx);
1093
1094 /*
1095 * Copy headers at the beginning of the first frame for H.264 only.
1096 * In MPEG4 they are already copied by the coda.
1097 */
1098 if (src_buf->v4l2_buf.sequence == 0) {
1099 pic_stream_buffer_addr =
1100 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1101 ctx->vpu_header_size[0] +
1102 ctx->vpu_header_size[1] +
1103 ctx->vpu_header_size[2];
1104 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
1105 ctx->vpu_header_size[0] -
1106 ctx->vpu_header_size[1] -
1107 ctx->vpu_header_size[2];
1108 memcpy(vb2_plane_vaddr(dst_buf, 0),
1109 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1110 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1111 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1112 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1113 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1114 ctx->vpu_header_size[2]);
1115 } else {
1116 pic_stream_buffer_addr =
1117 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1118 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
1119 }
1120
1121 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1122 force_ipicture = 1;
1123 switch (dst_fourcc) {
1124 case V4L2_PIX_FMT_H264:
1125 quant_param = ctx->params.h264_intra_qp;
1126 break;
1127 case V4L2_PIX_FMT_MPEG4:
1128 quant_param = ctx->params.mpeg4_intra_qp;
1129 break;
1130 default:
1131 v4l2_warn(&ctx->dev->v4l2_dev,
1132 "cannot set intra qp, fmt not supported\n");
1133 break;
1134 }
1135 } else {
1136 force_ipicture = 0;
1137 switch (dst_fourcc) {
1138 case V4L2_PIX_FMT_H264:
1139 quant_param = ctx->params.h264_inter_qp;
1140 break;
1141 case V4L2_PIX_FMT_MPEG4:
1142 quant_param = ctx->params.mpeg4_inter_qp;
1143 break;
1144 default:
1145 v4l2_warn(&ctx->dev->v4l2_dev,
1146 "cannot set inter qp, fmt not supported\n");
1147 break;
1148 }
1149 }
1150
1151 /* submit */
1152 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1153 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1154
1155
1156 picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
1157 switch (q_data_src->fourcc) {
1158 case V4L2_PIX_FMT_YVU420:
1159 /* Switch Cb and Cr for YVU420 format */
1160 picture_cr = picture_y + q_data_src->bytesperline *
1161 q_data_src->height;
1162 picture_cb = picture_cr + q_data_src->bytesperline / 2 *
1163 q_data_src->height / 2;
1164 break;
1165 case V4L2_PIX_FMT_YUV420:
1166 default:
1167 picture_cb = picture_y + q_data_src->bytesperline *
1168 q_data_src->height;
1169 picture_cr = picture_cb + q_data_src->bytesperline / 2 *
1170 q_data_src->height / 2;
1171 break;
1172 }
1173
1174 if (dev->devtype->product == CODA_960) {
1175 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1176 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1177 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1178
1179 coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y);
1180 coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB);
1181 coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR);
1182 } else {
1183 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
1184 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
1185 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
1186 }
1187 coda_write(dev, force_ipicture << 1 & 0x2,
1188 CODA_CMD_ENC_PIC_OPTION);
1189
1190 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1191 coda_write(dev, pic_stream_buffer_size / 1024,
1192 CODA_CMD_ENC_PIC_BB_SIZE);
1193
1194 if (!ctx->streamon_out) {
1195 /* After streamoff on the output side, set the stream end flag */
1196 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1197 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
1198 }
1199
1200 if (dev->devtype->product != CODA_DX6)
1201 coda_write(dev, ctx->iram_info.axi_sram_use,
1202 CODA7_REG_BIT_AXI_SRAM_USE);
1203
1204 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1205
1206 return 0;
1207 }
1208
1209 static void coda_device_run(void *m2m_priv)
1210 {
1211 struct coda_ctx *ctx = m2m_priv;
1212 struct coda_dev *dev = ctx->dev;
1213
1214 queue_work(dev->workqueue, &ctx->pic_run_work);
1215 }
1216
1217 static void coda_free_framebuffers(struct coda_ctx *ctx);
1218 static void coda_free_context_buffers(struct coda_ctx *ctx);
1219
1220 static void coda_seq_end_work(struct work_struct *work)
1221 {
1222 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1223 struct coda_dev *dev = ctx->dev;
1224
1225 mutex_lock(&ctx->buffer_mutex);
1226 mutex_lock(&dev->coda_mutex);
1227
1228 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1229 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx, __func__);
1230 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1231 v4l2_err(&dev->v4l2_dev,
1232 "CODA_COMMAND_SEQ_END failed\n");
1233 }
1234
1235 kfifo_init(&ctx->bitstream_fifo,
1236 ctx->bitstream.vaddr, ctx->bitstream.size);
1237
1238 coda_free_framebuffers(ctx);
1239 coda_free_context_buffers(ctx);
1240
1241 mutex_unlock(&dev->coda_mutex);
1242 mutex_unlock(&ctx->buffer_mutex);
1243 }
1244
1245 static void coda_finish_decode(struct coda_ctx *ctx);
1246 static void coda_finish_encode(struct coda_ctx *ctx);
1247
1248 static void coda_pic_run_work(struct work_struct *work)
1249 {
1250 struct coda_ctx *ctx = container_of(work, struct coda_ctx, pic_run_work);
1251 struct coda_dev *dev = ctx->dev;
1252 int ret;
1253
1254 mutex_lock(&ctx->buffer_mutex);
1255 mutex_lock(&dev->coda_mutex);
1256
1257 ret = ctx->ops->prepare_run(ctx);
1258 if (ret < 0 && ctx->inst_type == CODA_INST_DECODER) {
1259 mutex_unlock(&dev->coda_mutex);
1260 mutex_unlock(&ctx->buffer_mutex);
1261 /* job_finish scheduled by prepare_decode */
1262 return;
1263 }
1264
1265 if (!wait_for_completion_timeout(&ctx->completion, msecs_to_jiffies(1000))) {
1266 dev_err(&dev->plat_dev->dev, "CODA PIC_RUN timeout\n");
1267
1268 ctx->hold = true;
1269
1270 coda_hw_reset(ctx);
1271 } else if (!ctx->aborting) {
1272 ctx->ops->finish_run(ctx);
1273 }
1274
1275 if (ctx->aborting || (!ctx->streamon_cap && !ctx->streamon_out))
1276 queue_work(dev->workqueue, &ctx->seq_end_work);
1277
1278 mutex_unlock(&dev->coda_mutex);
1279 mutex_unlock(&ctx->buffer_mutex);
1280
1281 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1282 }
1283
1284 static int coda_job_ready(void *m2m_priv)
1285 {
1286 struct coda_ctx *ctx = m2m_priv;
1287
1288 /*
1289 * For both 'P' and 'key' frame cases 1 picture
1290 * and 1 frame are needed. In the decoder case,
1291 * the compressed frame can be in the bitstream.
1292 */
1293 if (!v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) &&
1294 ctx->inst_type != CODA_INST_DECODER) {
1295 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1296 "not ready: not enough video buffers.\n");
1297 return 0;
1298 }
1299
1300 if (!v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)) {
1301 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1302 "not ready: not enough video capture buffers.\n");
1303 return 0;
1304 }
1305
1306 if (ctx->hold ||
1307 ((ctx->inst_type == CODA_INST_DECODER) &&
1308 (coda_get_bitstream_payload(ctx) < 512) &&
1309 !(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1310 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1311 "%d: not ready: not enough bitstream data.\n",
1312 ctx->idx);
1313 return 0;
1314 }
1315
1316 if (ctx->aborting) {
1317 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1318 "not ready: aborting\n");
1319 return 0;
1320 }
1321
1322 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1323 "job ready\n");
1324 return 1;
1325 }
1326
1327 static void coda_job_abort(void *priv)
1328 {
1329 struct coda_ctx *ctx = priv;
1330
1331 ctx->aborting = 1;
1332
1333 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1334 "Aborting task\n");
1335 }
1336
1337 static void coda_lock(void *m2m_priv)
1338 {
1339 struct coda_ctx *ctx = m2m_priv;
1340 struct coda_dev *pcdev = ctx->dev;
1341 mutex_lock(&pcdev->dev_mutex);
1342 }
1343
1344 static void coda_unlock(void *m2m_priv)
1345 {
1346 struct coda_ctx *ctx = m2m_priv;
1347 struct coda_dev *pcdev = ctx->dev;
1348 mutex_unlock(&pcdev->dev_mutex);
1349 }
1350
1351 static const struct v4l2_m2m_ops coda_m2m_ops = {
1352 .device_run = coda_device_run,
1353 .job_ready = coda_job_ready,
1354 .job_abort = coda_job_abort,
1355 .lock = coda_lock,
1356 .unlock = coda_unlock,
1357 };
1358
1359 static void coda_set_tiled_map_type(struct coda_ctx *ctx, int tiled_map_type)
1360 {
1361 struct gdi_tiled_map *tiled_map = &ctx->tiled_map;
1362 int luma_map, chro_map, i;
1363
1364 memset(tiled_map, 0, sizeof(*tiled_map));
1365
1366 luma_map = 64;
1367 chro_map = 64;
1368 tiled_map->map_type = tiled_map_type;
1369 for (i = 0; i < 16; i++)
1370 tiled_map->xy2ca_map[i] = luma_map << 8 | chro_map;
1371 for (i = 0; i < 4; i++)
1372 tiled_map->xy2ba_map[i] = luma_map << 8 | chro_map;
1373 for (i = 0; i < 16; i++)
1374 tiled_map->xy2ra_map[i] = luma_map << 8 | chro_map;
1375
1376 if (tiled_map_type == GDI_LINEAR_FRAME_MAP) {
1377 tiled_map->xy2rbc_config = 0;
1378 } else {
1379 dev_err(&ctx->dev->plat_dev->dev, "invalid map type: %d\n",
1380 tiled_map_type);
1381 return;
1382 }
1383 }
1384
1385 static void set_default_params(struct coda_ctx *ctx)
1386 {
1387 u32 src_fourcc, dst_fourcc;
1388 int max_w;
1389 int max_h;
1390
1391 if (ctx->inst_type == CODA_INST_ENCODER) {
1392 src_fourcc = V4L2_PIX_FMT_YUV420;
1393 dst_fourcc = V4L2_PIX_FMT_H264;
1394 } else {
1395 src_fourcc = V4L2_PIX_FMT_H264;
1396 dst_fourcc = V4L2_PIX_FMT_YUV420;
1397 }
1398 ctx->codec = coda_find_codec(ctx->dev, src_fourcc, dst_fourcc);
1399 max_w = ctx->codec->max_w;
1400 max_h = ctx->codec->max_h;
1401
1402 ctx->params.codec_mode = ctx->codec->mode;
1403 ctx->colorspace = V4L2_COLORSPACE_REC709;
1404 ctx->params.framerate = 30;
1405 ctx->aborting = 0;
1406
1407 /* Default formats for output and input queues */
1408 ctx->q_data[V4L2_M2M_SRC].fourcc = ctx->codec->src_fourcc;
1409 ctx->q_data[V4L2_M2M_DST].fourcc = ctx->codec->dst_fourcc;
1410 ctx->q_data[V4L2_M2M_SRC].width = max_w;
1411 ctx->q_data[V4L2_M2M_SRC].height = max_h;
1412 ctx->q_data[V4L2_M2M_DST].width = max_w;
1413 ctx->q_data[V4L2_M2M_DST].height = max_h;
1414 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_YUV420) {
1415 ctx->q_data[V4L2_M2M_SRC].bytesperline = max_w;
1416 ctx->q_data[V4L2_M2M_SRC].sizeimage = (max_w * max_h * 3) / 2;
1417 ctx->q_data[V4L2_M2M_DST].bytesperline = 0;
1418 ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
1419 } else {
1420 ctx->q_data[V4L2_M2M_SRC].bytesperline = 0;
1421 ctx->q_data[V4L2_M2M_SRC].sizeimage = CODA_MAX_FRAME_SIZE;
1422 ctx->q_data[V4L2_M2M_DST].bytesperline = max_w;
1423 ctx->q_data[V4L2_M2M_DST].sizeimage = (max_w * max_h * 3) / 2;
1424 }
1425 ctx->q_data[V4L2_M2M_SRC].rect.width = max_w;
1426 ctx->q_data[V4L2_M2M_SRC].rect.height = max_h;
1427 ctx->q_data[V4L2_M2M_DST].rect.width = max_w;
1428 ctx->q_data[V4L2_M2M_DST].rect.height = max_h;
1429
1430 if (ctx->dev->devtype->product == CODA_960)
1431 coda_set_tiled_map_type(ctx, GDI_LINEAR_FRAME_MAP);
1432 }
1433
1434 /*
1435 * Queue operations
1436 */
1437 static int coda_queue_setup(struct vb2_queue *vq,
1438 const struct v4l2_format *fmt,
1439 unsigned int *nbuffers, unsigned int *nplanes,
1440 unsigned int sizes[], void *alloc_ctxs[])
1441 {
1442 struct coda_ctx *ctx = vb2_get_drv_priv(vq);
1443 struct coda_q_data *q_data;
1444 unsigned int size;
1445
1446 q_data = get_q_data(ctx, vq->type);
1447 size = q_data->sizeimage;
1448
1449 *nplanes = 1;
1450 sizes[0] = size;
1451
1452 alloc_ctxs[0] = ctx->dev->alloc_ctx;
1453
1454 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1455 "get %d buffer(s) of size %d each.\n", *nbuffers, size);
1456
1457 return 0;
1458 }
1459
1460 static int coda_buf_prepare(struct vb2_buffer *vb)
1461 {
1462 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1463 struct coda_q_data *q_data;
1464
1465 q_data = get_q_data(ctx, vb->vb2_queue->type);
1466
1467 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
1468 v4l2_warn(&ctx->dev->v4l2_dev,
1469 "%s data will not fit into plane (%lu < %lu)\n",
1470 __func__, vb2_plane_size(vb, 0),
1471 (long)q_data->sizeimage);
1472 return -EINVAL;
1473 }
1474
1475 return 0;
1476 }
1477
1478 static void coda_buf_queue(struct vb2_buffer *vb)
1479 {
1480 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1481 struct coda_q_data *q_data;
1482
1483 q_data = get_q_data(ctx, vb->vb2_queue->type);
1484
1485 /*
1486 * In the decoder case, immediately try to copy the buffer into the
1487 * bitstream ringbuffer and mark it as ready to be dequeued.
1488 */
1489 if (q_data->fourcc == V4L2_PIX_FMT_H264 &&
1490 vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1491 /*
1492 * For backwards compatibility, queuing an empty buffer marks
1493 * the stream end
1494 */
1495 if (vb2_get_plane_payload(vb, 0) == 0)
1496 coda_bit_stream_end_flag(ctx);
1497 mutex_lock(&ctx->bitstream_mutex);
1498 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vb);
1499 if (vb2_is_streaming(vb->vb2_queue))
1500 coda_fill_bitstream(ctx);
1501 mutex_unlock(&ctx->bitstream_mutex);
1502 } else {
1503 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vb);
1504 }
1505 }
1506
1507 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
1508 {
1509 struct coda_dev *dev = ctx->dev;
1510 u32 *p = ctx->parabuf.vaddr;
1511
1512 if (dev->devtype->product == CODA_DX6)
1513 p[index] = value;
1514 else
1515 p[index ^ 1] = value;
1516 }
1517
1518 static int coda_alloc_aux_buf(struct coda_dev *dev,
1519 struct coda_aux_buf *buf, size_t size,
1520 const char *name, struct dentry *parent)
1521 {
1522 buf->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size, &buf->paddr,
1523 GFP_KERNEL);
1524 if (!buf->vaddr)
1525 return -ENOMEM;
1526
1527 buf->size = size;
1528
1529 if (name && parent) {
1530 buf->blob.data = buf->vaddr;
1531 buf->blob.size = size;
1532 buf->dentry = debugfs_create_blob(name, 0644, parent, &buf->blob);
1533 if (!buf->dentry)
1534 dev_warn(&dev->plat_dev->dev,
1535 "failed to create debugfs entry %s\n", name);
1536 }
1537
1538 return 0;
1539 }
1540
1541 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
1542 struct coda_aux_buf *buf, size_t size,
1543 const char *name)
1544 {
1545 return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
1546 }
1547
1548 static void coda_free_aux_buf(struct coda_dev *dev,
1549 struct coda_aux_buf *buf)
1550 {
1551 if (buf->vaddr) {
1552 dma_free_coherent(&dev->plat_dev->dev, buf->size,
1553 buf->vaddr, buf->paddr);
1554 buf->vaddr = NULL;
1555 buf->size = 0;
1556 }
1557 debugfs_remove(buf->dentry);
1558 }
1559
1560 static void coda_free_framebuffers(struct coda_ctx *ctx)
1561 {
1562 int i;
1563
1564 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
1565 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
1566 }
1567
1568 static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
1569 {
1570 struct coda_dev *dev = ctx->dev;
1571 int width, height;
1572 dma_addr_t paddr;
1573 int ysize;
1574 int ret;
1575 int i;
1576
1577 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
1578 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
1579 width = round_up(q_data->width, 16);
1580 height = round_up(q_data->height, 16);
1581 } else {
1582 width = round_up(q_data->width, 8);
1583 height = q_data->height;
1584 }
1585 ysize = width * height;
1586
1587 /* Allocate frame buffers */
1588 for (i = 0; i < ctx->num_internal_frames; i++) {
1589 size_t size;
1590 char *name;
1591
1592 size = ysize + ysize / 2;
1593 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
1594 dev->devtype->product != CODA_DX6)
1595 size += ysize / 4;
1596 name = kasprintf(GFP_KERNEL, "fb%d", i);
1597 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
1598 size, name);
1599 kfree(name);
1600 if (ret < 0) {
1601 coda_free_framebuffers(ctx);
1602 return ret;
1603 }
1604 }
1605
1606 /* Register frame buffers in the parameter buffer */
1607 for (i = 0; i < ctx->num_internal_frames; i++) {
1608 paddr = ctx->internal_frames[i].paddr;
1609 coda_parabuf_write(ctx, i * 3 + 0, paddr); /* Y */
1610 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize); /* Cb */
1611 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize/4); /* Cr */
1612
1613 /* mvcol buffer for h.264 */
1614 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
1615 dev->devtype->product != CODA_DX6)
1616 coda_parabuf_write(ctx, 96 + i,
1617 ctx->internal_frames[i].paddr +
1618 ysize + ysize/4 + ysize/4);
1619 }
1620
1621 /* mvcol buffer for mpeg4 */
1622 if ((dev->devtype->product != CODA_DX6) &&
1623 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
1624 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
1625 ysize + ysize/4 + ysize/4);
1626
1627 return 0;
1628 }
1629
1630 static int coda_h264_padding(int size, char *p)
1631 {
1632 int nal_size;
1633 int diff;
1634
1635 diff = size - (size & ~0x7);
1636 if (diff == 0)
1637 return 0;
1638
1639 nal_size = coda_filler_size[diff];
1640 memcpy(p, coda_filler_nal, nal_size);
1641
1642 /* Add rbsp stop bit and trailing at the end */
1643 *(p + nal_size - 1) = 0x80;
1644
1645 return nal_size;
1646 }
1647
1648 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
1649 {
1650 phys_addr_t ret;
1651
1652 size = round_up(size, 1024);
1653 if (size > iram->remaining)
1654 return 0;
1655 iram->remaining -= size;
1656
1657 ret = iram->next_paddr;
1658 iram->next_paddr += size;
1659
1660 return ret;
1661 }
1662
1663 static void coda_setup_iram(struct coda_ctx *ctx)
1664 {
1665 struct coda_iram_info *iram_info = &ctx->iram_info;
1666 struct coda_dev *dev = ctx->dev;
1667 int mb_width;
1668 int dbk_bits;
1669 int bit_bits;
1670 int ip_bits;
1671
1672 memset(iram_info, 0, sizeof(*iram_info));
1673 iram_info->next_paddr = dev->iram.paddr;
1674 iram_info->remaining = dev->iram.size;
1675
1676 switch (dev->devtype->product) {
1677 case CODA_7541:
1678 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
1679 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
1680 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
1681 break;
1682 case CODA_960:
1683 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
1684 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
1685 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
1686 break;
1687 default: /* CODA_DX6 */
1688 return;
1689 }
1690
1691 if (ctx->inst_type == CODA_INST_ENCODER) {
1692 struct coda_q_data *q_data_src;
1693
1694 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1695 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
1696
1697 /* Prioritize in case IRAM is too small for everything */
1698 if (dev->devtype->product == CODA_7541) {
1699 iram_info->search_ram_size = round_up(mb_width * 16 *
1700 36 + 2048, 1024);
1701 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
1702 iram_info->search_ram_size);
1703 if (!iram_info->search_ram_paddr) {
1704 pr_err("IRAM is smaller than the search ram size\n");
1705 goto out;
1706 }
1707 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
1708 CODA7_USE_ME_ENABLE;
1709 }
1710
1711 /* Only H.264BP and H.263P3 are considered */
1712 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 64 * mb_width);
1713 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 64 * mb_width);
1714 if (!iram_info->buf_dbk_c_use)
1715 goto out;
1716 iram_info->axi_sram_use |= dbk_bits;
1717
1718 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
1719 if (!iram_info->buf_bit_use)
1720 goto out;
1721 iram_info->axi_sram_use |= bit_bits;
1722
1723 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
1724 if (!iram_info->buf_ip_ac_dc_use)
1725 goto out;
1726 iram_info->axi_sram_use |= ip_bits;
1727
1728 /* OVL and BTP disabled for encoder */
1729 } else if (ctx->inst_type == CODA_INST_DECODER) {
1730 struct coda_q_data *q_data_dst;
1731
1732 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1733 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
1734
1735 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 128 * mb_width);
1736 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 128 * mb_width);
1737 if (!iram_info->buf_dbk_c_use)
1738 goto out;
1739 iram_info->axi_sram_use |= dbk_bits;
1740
1741 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
1742 if (!iram_info->buf_bit_use)
1743 goto out;
1744 iram_info->axi_sram_use |= bit_bits;
1745
1746 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
1747 if (!iram_info->buf_ip_ac_dc_use)
1748 goto out;
1749 iram_info->axi_sram_use |= ip_bits;
1750
1751 /* OVL and BTP unused as there is no VC1 support yet */
1752 }
1753
1754 out:
1755 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
1756 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1757 "IRAM smaller than needed\n");
1758
1759 if (dev->devtype->product == CODA_7541) {
1760 /* TODO - Enabling these causes picture errors on CODA7541 */
1761 if (ctx->inst_type == CODA_INST_DECODER) {
1762 /* fw 1.4.50 */
1763 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
1764 CODA7_USE_IP_ENABLE);
1765 } else {
1766 /* fw 13.4.29 */
1767 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
1768 CODA7_USE_HOST_DBK_ENABLE |
1769 CODA7_USE_IP_ENABLE |
1770 CODA7_USE_DBK_ENABLE);
1771 }
1772 }
1773 }
1774
1775 static void coda_free_context_buffers(struct coda_ctx *ctx)
1776 {
1777 struct coda_dev *dev = ctx->dev;
1778
1779 coda_free_aux_buf(dev, &ctx->slicebuf);
1780 coda_free_aux_buf(dev, &ctx->psbuf);
1781 if (dev->devtype->product != CODA_DX6)
1782 coda_free_aux_buf(dev, &ctx->workbuf);
1783 }
1784
1785 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
1786 struct coda_q_data *q_data)
1787 {
1788 struct coda_dev *dev = ctx->dev;
1789 size_t size;
1790 int ret;
1791
1792 if (dev->devtype->product == CODA_DX6)
1793 return 0;
1794
1795 if (ctx->psbuf.vaddr) {
1796 v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
1797 return -EBUSY;
1798 }
1799 if (ctx->slicebuf.vaddr) {
1800 v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
1801 return -EBUSY;
1802 }
1803 if (ctx->workbuf.vaddr) {
1804 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
1805 ret = -EBUSY;
1806 return -ENOMEM;
1807 }
1808
1809 if (q_data->fourcc == V4L2_PIX_FMT_H264) {
1810 /* worst case slice size */
1811 size = (DIV_ROUND_UP(q_data->width, 16) *
1812 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
1813 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size, "slicebuf");
1814 if (ret < 0) {
1815 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte slice buffer",
1816 ctx->slicebuf.size);
1817 return ret;
1818 }
1819 }
1820
1821 if (dev->devtype->product == CODA_7541) {
1822 ret = coda_alloc_context_buf(ctx, &ctx->psbuf, CODA7_PS_BUF_SIZE, "psbuf");
1823 if (ret < 0) {
1824 v4l2_err(&dev->v4l2_dev, "failed to allocate psmem buffer");
1825 goto err;
1826 }
1827 }
1828
1829 size = dev->devtype->workbuf_size;
1830 if (dev->devtype->product == CODA_960 &&
1831 q_data->fourcc == V4L2_PIX_FMT_H264)
1832 size += CODA9_PS_SAVE_SIZE;
1833 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
1834 if (ret < 0) {
1835 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte context buffer",
1836 ctx->workbuf.size);
1837 goto err;
1838 }
1839
1840 return 0;
1841
1842 err:
1843 coda_free_context_buffers(ctx);
1844 return ret;
1845 }
1846
1847 static int __coda_start_decoding(struct coda_ctx *ctx)
1848 {
1849 struct coda_q_data *q_data_src, *q_data_dst;
1850 u32 bitstream_buf, bitstream_size;
1851 struct coda_dev *dev = ctx->dev;
1852 int width, height;
1853 u32 src_fourcc;
1854 u32 val;
1855 int ret;
1856
1857 /* Start decoding */
1858 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1859 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1860 bitstream_buf = ctx->bitstream.paddr;
1861 bitstream_size = ctx->bitstream.size;
1862 src_fourcc = q_data_src->fourcc;
1863
1864 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1865
1866 /* Update coda bitstream read and write pointers from kfifo */
1867 coda_kfifo_sync_to_device_full(ctx);
1868
1869 ctx->display_idx = -1;
1870 ctx->frm_dis_flg = 0;
1871 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1872
1873 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1874 CODA_REG_BIT_BIT_STREAM_PARAM);
1875
1876 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1877 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1878 val = 0;
1879 if ((dev->devtype->product == CODA_7541) ||
1880 (dev->devtype->product == CODA_960))
1881 val |= CODA_REORDER_ENABLE;
1882 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1883
1884 ctx->params.codec_mode = ctx->codec->mode;
1885 if (dev->devtype->product == CODA_960 &&
1886 src_fourcc == V4L2_PIX_FMT_MPEG4)
1887 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1888 else
1889 ctx->params.codec_mode_aux = 0;
1890 if (src_fourcc == V4L2_PIX_FMT_H264) {
1891 if (dev->devtype->product == CODA_7541) {
1892 coda_write(dev, ctx->psbuf.paddr,
1893 CODA_CMD_DEC_SEQ_PS_BB_START);
1894 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1895 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1896 }
1897 if (dev->devtype->product == CODA_960) {
1898 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1899 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1900 }
1901 }
1902 if (dev->devtype->product != CODA_960) {
1903 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1904 }
1905
1906 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1907 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1908 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1909 return -ETIMEDOUT;
1910 }
1911
1912 /* Update kfifo out pointer from coda bitstream read pointer */
1913 coda_kfifo_sync_from_device(ctx);
1914
1915 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1916
1917 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1918 v4l2_err(&dev->v4l2_dev,
1919 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1920 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1921 return -EAGAIN;
1922 }
1923
1924 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1925 if (dev->devtype->product == CODA_DX6) {
1926 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1927 height = val & CODADX6_PICHEIGHT_MASK;
1928 } else {
1929 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1930 height = val & CODA7_PICHEIGHT_MASK;
1931 }
1932
1933 if (width > q_data_dst->width || height > q_data_dst->height) {
1934 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1935 width, height, q_data_dst->width, q_data_dst->height);
1936 return -EINVAL;
1937 }
1938
1939 width = round_up(width, 16);
1940 height = round_up(height, 16);
1941
1942 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1943 __func__, ctx->idx, width, height);
1944
1945 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1946 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1947 v4l2_err(&dev->v4l2_dev,
1948 "not enough framebuffers to decode (%d < %d)\n",
1949 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1950 return -EINVAL;
1951 }
1952
1953 if (src_fourcc == V4L2_PIX_FMT_H264) {
1954 u32 left_right;
1955 u32 top_bottom;
1956
1957 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1958 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1959
1960 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1961 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1962 q_data_dst->rect.width = width - q_data_dst->rect.left -
1963 (left_right & 0x3ff);
1964 q_data_dst->rect.height = height - q_data_dst->rect.top -
1965 (top_bottom & 0x3ff);
1966 }
1967
1968 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1969 if (ret < 0)
1970 return ret;
1971
1972 /* Tell the decoder how many frame buffers we allocated. */
1973 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1974 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1975
1976 if (dev->devtype->product != CODA_DX6) {
1977 /* Set secondary AXI IRAM */
1978 coda_setup_iram(ctx);
1979
1980 coda_write(dev, ctx->iram_info.buf_bit_use,
1981 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1982 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1983 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1984 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1985 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1986 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1987 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1988 coda_write(dev, ctx->iram_info.buf_ovl_use,
1989 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1990 if (dev->devtype->product == CODA_960)
1991 coda_write(dev, ctx->iram_info.buf_btp_use,
1992 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1993 }
1994
1995 if (dev->devtype->product == CODA_960) {
1996 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1997
1998 coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
1999 coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
2000 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
2001 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
2002 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
2003 CODA9_CMD_SET_FRAME_CACHE_CONFIG);
2004 }
2005
2006 if (src_fourcc == V4L2_PIX_FMT_H264) {
2007 coda_write(dev, ctx->slicebuf.paddr,
2008 CODA_CMD_SET_FRAME_SLICE_BB_START);
2009 coda_write(dev, ctx->slicebuf.size / 1024,
2010 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
2011 }
2012
2013 if (dev->devtype->product == CODA_7541) {
2014 int max_mb_x = 1920 / 16;
2015 int max_mb_y = 1088 / 16;
2016 int max_mb_num = max_mb_x * max_mb_y;
2017
2018 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
2019 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
2020 } else if (dev->devtype->product == CODA_960) {
2021 int max_mb_x = 1920 / 16;
2022 int max_mb_y = 1088 / 16;
2023 int max_mb_num = max_mb_x * max_mb_y;
2024
2025 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
2026 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
2027 }
2028
2029 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
2030 v4l2_err(&ctx->dev->v4l2_dev,
2031 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
2032 return -ETIMEDOUT;
2033 }
2034
2035 return 0;
2036 }
2037
2038 static int coda_start_decoding(struct coda_ctx *ctx)
2039 {
2040 struct coda_dev *dev = ctx->dev;
2041 int ret;
2042
2043 mutex_lock(&dev->coda_mutex);
2044 ret = __coda_start_decoding(ctx);
2045 mutex_unlock(&dev->coda_mutex);
2046
2047 return ret;
2048 }
2049
2050 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
2051 int header_code, u8 *header, int *size)
2052 {
2053 struct coda_dev *dev = ctx->dev;
2054 size_t bufsize;
2055 int ret;
2056 int i;
2057
2058 if (dev->devtype->product == CODA_960)
2059 memset(vb2_plane_vaddr(buf, 0), 0, 64);
2060
2061 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
2062 CODA_CMD_ENC_HEADER_BB_START);
2063 bufsize = vb2_plane_size(buf, 0);
2064 if (dev->devtype->product == CODA_960)
2065 bufsize /= 1024;
2066 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
2067 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
2068 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
2069 if (ret < 0) {
2070 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
2071 return ret;
2072 }
2073
2074 if (dev->devtype->product == CODA_960) {
2075 for (i = 63; i > 0; i--)
2076 if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
2077 break;
2078 *size = i + 1;
2079 } else {
2080 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
2081 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
2082 }
2083 memcpy(header, vb2_plane_vaddr(buf, 0), *size);
2084
2085 return 0;
2086 }
2087
2088 static int coda_start_encoding(struct coda_ctx *ctx);
2089
2090 static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
2091 {
2092 struct coda_ctx *ctx = vb2_get_drv_priv(q);
2093 struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
2094 struct coda_q_data *q_data_src, *q_data_dst;
2095 u32 dst_fourcc;
2096 int ret = 0;
2097
2098 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2099 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
2100 if (q_data_src->fourcc == V4L2_PIX_FMT_H264) {
2101 /* copy the buffers that where queued before streamon */
2102 mutex_lock(&ctx->bitstream_mutex);
2103 coda_fill_bitstream(ctx);
2104 mutex_unlock(&ctx->bitstream_mutex);
2105
2106 if (coda_get_bitstream_payload(ctx) < 512)
2107 return -EINVAL;
2108 } else {
2109 if (count < 1)
2110 return -EINVAL;
2111 }
2112
2113 ctx->streamon_out = 1;
2114 } else {
2115 if (count < 1)
2116 return -EINVAL;
2117
2118 ctx->streamon_cap = 1;
2119 }
2120
2121 /* Don't start the coda unless both queues are on */
2122 if (!(ctx->streamon_out & ctx->streamon_cap))
2123 return 0;
2124
2125 /* Allow decoder device_run with no new buffers queued */
2126 if (ctx->inst_type == CODA_INST_DECODER)
2127 v4l2_m2m_set_src_buffered(ctx->fh.m2m_ctx, true);
2128
2129 ctx->gopcounter = ctx->params.gop_size - 1;
2130 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2131 dst_fourcc = q_data_dst->fourcc;
2132
2133 ctx->codec = coda_find_codec(ctx->dev, q_data_src->fourcc,
2134 q_data_dst->fourcc);
2135 if (!ctx->codec) {
2136 v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
2137 return -EINVAL;
2138 }
2139
2140 /* Allocate per-instance buffers */
2141 ret = coda_alloc_context_buffers(ctx, q_data_src);
2142 if (ret < 0)
2143 return ret;
2144
2145 ret = ctx->ops->start_streaming(ctx);
2146 if (ctx->inst_type == CODA_INST_DECODER) {
2147 if (ret == -EAGAIN)
2148 return 0;
2149 else if (ret < 0)
2150 return ret;
2151 }
2152
2153 ctx->initialized = 1;
2154 return ret;
2155 }
2156
2157 static int coda_start_encoding(struct coda_ctx *ctx)
2158 {
2159 struct coda_dev *dev = ctx->dev;
2160 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2161 struct coda_q_data *q_data_src, *q_data_dst;
2162 u32 bitstream_buf, bitstream_size;
2163 struct vb2_buffer *buf;
2164 int gamma, ret, value;
2165 u32 dst_fourcc;
2166
2167 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2168 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2169 dst_fourcc = q_data_dst->fourcc;
2170
2171 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
2172 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
2173 bitstream_size = q_data_dst->sizeimage;
2174
2175 if (!coda_is_initialized(dev)) {
2176 v4l2_err(v4l2_dev, "coda is not initialized.\n");
2177 return -EFAULT;
2178 }
2179
2180 mutex_lock(&dev->coda_mutex);
2181
2182 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
2183 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
2184 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
2185 switch (dev->devtype->product) {
2186 case CODA_DX6:
2187 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
2188 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
2189 break;
2190 case CODA_960:
2191 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
2192 /* fallthrough */
2193 case CODA_7541:
2194 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
2195 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
2196 break;
2197 }
2198
2199 value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL);
2200 value &= ~(1 << 2 | 0x7 << 9);
2201 ctx->frame_mem_ctrl = value;
2202 coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL);
2203
2204 if (dev->devtype->product == CODA_DX6) {
2205 /* Configure the coda */
2206 coda_write(dev, dev->iram.paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
2207 }
2208
2209 /* Could set rotation here if needed */
2210 switch (dev->devtype->product) {
2211 case CODA_DX6:
2212 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
2213 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
2214 break;
2215 case CODA_7541:
2216 if (dst_fourcc == V4L2_PIX_FMT_H264) {
2217 value = (round_up(q_data_src->width, 16) &
2218 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
2219 value |= (round_up(q_data_src->height, 16) &
2220 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
2221 break;
2222 }
2223 /* fallthrough */
2224 case CODA_960:
2225 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
2226 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
2227 }
2228 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
2229 coda_write(dev, ctx->params.framerate,
2230 CODA_CMD_ENC_SEQ_SRC_F_RATE);
2231
2232 ctx->params.codec_mode = ctx->codec->mode;
2233 switch (dst_fourcc) {
2234 case V4L2_PIX_FMT_MPEG4:
2235 if (dev->devtype->product == CODA_960)
2236 coda_write(dev, CODA9_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
2237 else
2238 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
2239 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
2240 break;
2241 case V4L2_PIX_FMT_H264:
2242 if (dev->devtype->product == CODA_960)
2243 coda_write(dev, CODA9_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
2244 else
2245 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
2246 if (ctx->params.h264_deblk_enabled) {
2247 value = ((ctx->params.h264_deblk_alpha &
2248 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
2249 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
2250 ((ctx->params.h264_deblk_beta &
2251 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
2252 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
2253 } else {
2254 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
2255 }
2256 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
2257 break;
2258 default:
2259 v4l2_err(v4l2_dev,
2260 "dst format (0x%08x) invalid.\n", dst_fourcc);
2261 ret = -EINVAL;
2262 goto out;
2263 }
2264
2265 switch (ctx->params.slice_mode) {
2266 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
2267 value = 0;
2268 break;
2269 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
2270 value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
2271 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
2272 value |= 1 & CODA_SLICING_MODE_MASK;
2273 break;
2274 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
2275 value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
2276 value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
2277 value |= 1 & CODA_SLICING_MODE_MASK;
2278 break;
2279 }
2280 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
2281 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
2282 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
2283
2284 if (ctx->params.bitrate) {
2285 /* Rate control enabled */
2286 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
2287 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
2288 if (dev->devtype->product == CODA_960)
2289 value |= BIT(31); /* disable autoskip */
2290 } else {
2291 value = 0;
2292 }
2293 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
2294
2295 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
2296 coda_write(dev, ctx->params.intra_refresh,
2297 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
2298
2299 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
2300 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
2301
2302
2303 value = 0;
2304 if (dev->devtype->product == CODA_960)
2305 gamma = CODA9_DEFAULT_GAMMA;
2306 else
2307 gamma = CODA_DEFAULT_GAMMA;
2308 if (gamma > 0) {
2309 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
2310 CODA_CMD_ENC_SEQ_RC_GAMMA);
2311 }
2312
2313 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
2314 coda_write(dev,
2315 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
2316 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
2317 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
2318 }
2319 if (dev->devtype->product == CODA_960) {
2320 if (ctx->params.h264_max_qp)
2321 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
2322 if (CODA_DEFAULT_GAMMA > 0)
2323 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
2324 } else {
2325 if (CODA_DEFAULT_GAMMA > 0) {
2326 if (dev->devtype->product == CODA_DX6)
2327 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
2328 else
2329 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
2330 }
2331 if (ctx->params.h264_min_qp)
2332 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
2333 if (ctx->params.h264_max_qp)
2334 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
2335 }
2336 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
2337
2338 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
2339
2340 coda_setup_iram(ctx);
2341
2342 if (dst_fourcc == V4L2_PIX_FMT_H264) {
2343 switch (dev->devtype->product) {
2344 case CODA_DX6:
2345 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
2346 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
2347 break;
2348 case CODA_7541:
2349 coda_write(dev, ctx->iram_info.search_ram_paddr,
2350 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
2351 coda_write(dev, ctx->iram_info.search_ram_size,
2352 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
2353 break;
2354 case CODA_960:
2355 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
2356 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
2357 }
2358 }
2359
2360 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
2361 if (ret < 0) {
2362 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
2363 goto out;
2364 }
2365
2366 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
2367 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
2368 ret = -EFAULT;
2369 goto out;
2370 }
2371
2372 if (dev->devtype->product == CODA_960)
2373 ctx->num_internal_frames = 4;
2374 else
2375 ctx->num_internal_frames = 2;
2376 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
2377 if (ret < 0) {
2378 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
2379 goto out;
2380 }
2381
2382 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
2383 coda_write(dev, q_data_src->bytesperline,
2384 CODA_CMD_SET_FRAME_BUF_STRIDE);
2385 if (dev->devtype->product == CODA_7541) {
2386 coda_write(dev, q_data_src->bytesperline,
2387 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
2388 }
2389 if (dev->devtype->product != CODA_DX6) {
2390 coda_write(dev, ctx->iram_info.buf_bit_use,
2391 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
2392 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
2393 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
2394 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
2395 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
2396 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
2397 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
2398 coda_write(dev, ctx->iram_info.buf_ovl_use,
2399 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
2400 if (dev->devtype->product == CODA_960) {
2401 coda_write(dev, ctx->iram_info.buf_btp_use,
2402 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
2403
2404 /* FIXME */
2405 coda_write(dev, ctx->internal_frames[2].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_A);
2406 coda_write(dev, ctx->internal_frames[3].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_B);
2407 }
2408 }
2409
2410 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
2411 if (ret < 0) {
2412 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
2413 goto out;
2414 }
2415
2416 /* Save stream headers */
2417 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
2418 switch (dst_fourcc) {
2419 case V4L2_PIX_FMT_H264:
2420 /*
2421 * Get SPS in the first frame and copy it to an
2422 * intermediate buffer.
2423 */
2424 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
2425 &ctx->vpu_header[0][0],
2426 &ctx->vpu_header_size[0]);
2427 if (ret < 0)
2428 goto out;
2429
2430 /*
2431 * Get PPS in the first frame and copy it to an
2432 * intermediate buffer.
2433 */
2434 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
2435 &ctx->vpu_header[1][0],
2436 &ctx->vpu_header_size[1]);
2437 if (ret < 0)
2438 goto out;
2439
2440 /*
2441 * Length of H.264 headers is variable and thus it might not be
2442 * aligned for the coda to append the encoded frame. In that is
2443 * the case a filler NAL must be added to header 2.
2444 */
2445 ctx->vpu_header_size[2] = coda_h264_padding(
2446 (ctx->vpu_header_size[0] +
2447 ctx->vpu_header_size[1]),
2448 ctx->vpu_header[2]);
2449 break;
2450 case V4L2_PIX_FMT_MPEG4:
2451 /*
2452 * Get VOS in the first frame and copy it to an
2453 * intermediate buffer
2454 */
2455 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
2456 &ctx->vpu_header[0][0],
2457 &ctx->vpu_header_size[0]);
2458 if (ret < 0)
2459 goto out;
2460
2461 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
2462 &ctx->vpu_header[1][0],
2463 &ctx->vpu_header_size[1]);
2464 if (ret < 0)
2465 goto out;
2466
2467 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
2468 &ctx->vpu_header[2][0],
2469 &ctx->vpu_header_size[2]);
2470 if (ret < 0)
2471 goto out;
2472 break;
2473 default:
2474 /* No more formats need to save headers at the moment */
2475 break;
2476 }
2477
2478 out:
2479 mutex_unlock(&dev->coda_mutex);
2480 return ret;
2481 }
2482
2483 static void coda_stop_streaming(struct vb2_queue *q)
2484 {
2485 struct coda_ctx *ctx = vb2_get_drv_priv(q);
2486 struct coda_dev *dev = ctx->dev;
2487
2488 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
2489 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2490 "%s: output\n", __func__);
2491 ctx->streamon_out = 0;
2492
2493 coda_bit_stream_end_flag(ctx);
2494 ctx->isequence = 0;
2495 } else {
2496 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2497 "%s: capture\n", __func__);
2498 ctx->streamon_cap = 0;
2499
2500 ctx->osequence = 0;
2501 ctx->sequence_offset = 0;
2502 }
2503
2504 if (!ctx->streamon_out && !ctx->streamon_cap) {
2505 struct coda_timestamp *ts;
2506
2507 while (!list_empty(&ctx->timestamp_list)) {
2508 ts = list_first_entry(&ctx->timestamp_list,
2509 struct coda_timestamp, list);
2510 list_del(&ts->list);
2511 kfree(ts);
2512 }
2513 kfifo_init(&ctx->bitstream_fifo,
2514 ctx->bitstream.vaddr, ctx->bitstream.size);
2515 ctx->runcounter = 0;
2516 }
2517 }
2518
2519 static const struct vb2_ops coda_qops = {
2520 .queue_setup = coda_queue_setup,
2521 .buf_prepare = coda_buf_prepare,
2522 .buf_queue = coda_buf_queue,
2523 .start_streaming = coda_start_streaming,
2524 .stop_streaming = coda_stop_streaming,
2525 .wait_prepare = vb2_ops_wait_prepare,
2526 .wait_finish = vb2_ops_wait_finish,
2527 };
2528
2529 static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
2530 {
2531 struct coda_ctx *ctx =
2532 container_of(ctrl->handler, struct coda_ctx, ctrls);
2533
2534 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2535 "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
2536
2537 switch (ctrl->id) {
2538 case V4L2_CID_HFLIP:
2539 if (ctrl->val)
2540 ctx->params.rot_mode |= CODA_MIR_HOR;
2541 else
2542 ctx->params.rot_mode &= ~CODA_MIR_HOR;
2543 break;
2544 case V4L2_CID_VFLIP:
2545 if (ctrl->val)
2546 ctx->params.rot_mode |= CODA_MIR_VER;
2547 else
2548 ctx->params.rot_mode &= ~CODA_MIR_VER;
2549 break;
2550 case V4L2_CID_MPEG_VIDEO_BITRATE:
2551 ctx->params.bitrate = ctrl->val / 1000;
2552 break;
2553 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
2554 ctx->params.gop_size = ctrl->val;
2555 break;
2556 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
2557 ctx->params.h264_intra_qp = ctrl->val;
2558 break;
2559 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
2560 ctx->params.h264_inter_qp = ctrl->val;
2561 break;
2562 case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
2563 ctx->params.h264_min_qp = ctrl->val;
2564 break;
2565 case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
2566 ctx->params.h264_max_qp = ctrl->val;
2567 break;
2568 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA:
2569 ctx->params.h264_deblk_alpha = ctrl->val;
2570 break;
2571 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA:
2572 ctx->params.h264_deblk_beta = ctrl->val;
2573 break;
2574 case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE:
2575 ctx->params.h264_deblk_enabled = (ctrl->val ==
2576 V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED);
2577 break;
2578 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
2579 ctx->params.mpeg4_intra_qp = ctrl->val;
2580 break;
2581 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
2582 ctx->params.mpeg4_inter_qp = ctrl->val;
2583 break;
2584 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
2585 ctx->params.slice_mode = ctrl->val;
2586 break;
2587 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
2588 ctx->params.slice_max_mb = ctrl->val;
2589 break;
2590 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
2591 ctx->params.slice_max_bits = ctrl->val * 8;
2592 break;
2593 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
2594 break;
2595 case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB:
2596 ctx->params.intra_refresh = ctrl->val;
2597 break;
2598 default:
2599 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2600 "Invalid control, id=%d, val=%d\n",
2601 ctrl->id, ctrl->val);
2602 return -EINVAL;
2603 }
2604
2605 return 0;
2606 }
2607
2608 static const struct v4l2_ctrl_ops coda_ctrl_ops = {
2609 .s_ctrl = coda_s_ctrl,
2610 };
2611
2612 static int coda_ctrls_setup(struct coda_ctx *ctx)
2613 {
2614 v4l2_ctrl_handler_init(&ctx->ctrls, 9);
2615
2616 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2617 V4L2_CID_HFLIP, 0, 1, 1, 0);
2618 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2619 V4L2_CID_VFLIP, 0, 1, 1, 0);
2620 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2621 V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
2622 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2623 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
2624 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2625 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 0, 51, 1, 25);
2626 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2627 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 0, 51, 1, 25);
2628 if (ctx->dev->devtype->product != CODA_960) {
2629 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2630 V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 0, 51, 1, 12);
2631 }
2632 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2633 V4L2_CID_MPEG_VIDEO_H264_MAX_QP, 0, 51, 1, 51);
2634 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2635 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, 0, 15, 1, 0);
2636 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2637 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, 0, 15, 1, 0);
2638 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
2639 V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE,
2640 V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED, 0x0,
2641 V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED);
2642 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2643 V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
2644 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2645 V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
2646 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
2647 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
2648 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
2649 V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
2650 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2651 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
2652 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2653 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
2654 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
2655 V4L2_CID_MPEG_VIDEO_HEADER_MODE,
2656 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
2657 (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
2658 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
2659 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
2660 V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB, 0, 1920 * 1088 / 256, 1, 0);
2661
2662 if (ctx->ctrls.error) {
2663 v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
2664 ctx->ctrls.error);
2665 return -EINVAL;
2666 }
2667
2668 return v4l2_ctrl_handler_setup(&ctx->ctrls);
2669 }
2670
2671 static int coda_queue_init(struct coda_ctx *ctx, struct vb2_queue *vq)
2672 {
2673 vq->drv_priv = ctx;
2674 vq->ops = &coda_qops;
2675 vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2676 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2677 vq->lock = &ctx->dev->dev_mutex;
2678
2679 return vb2_queue_init(vq);
2680 }
2681
2682 static int coda_encoder_queue_init(void *priv, struct vb2_queue *src_vq,
2683 struct vb2_queue *dst_vq)
2684 {
2685 int ret;
2686
2687 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2688 src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2689 src_vq->mem_ops = &vb2_dma_contig_memops;
2690
2691 ret = coda_queue_init(priv, src_vq);
2692 if (ret)
2693 return ret;
2694
2695 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2696 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2697 dst_vq->mem_ops = &vb2_dma_contig_memops;
2698
2699 return coda_queue_init(priv, dst_vq);
2700 }
2701
2702 static int coda_decoder_queue_init(void *priv, struct vb2_queue *src_vq,
2703 struct vb2_queue *dst_vq)
2704 {
2705 int ret;
2706
2707 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2708 src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2709 src_vq->mem_ops = &vb2_dma_contig_memops;
2710
2711 ret = coda_queue_init(priv, src_vq);
2712 if (ret)
2713 return ret;
2714
2715 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2716 dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2717 dst_vq->mem_ops = &vb2_dma_contig_memops;
2718
2719 return coda_queue_init(priv, dst_vq);
2720 }
2721
2722 static int coda_next_free_instance(struct coda_dev *dev)
2723 {
2724 int idx = ffz(dev->instance_mask);
2725
2726 if ((idx < 0) ||
2727 (dev->devtype->product == CODA_DX6 && idx > CODADX6_MAX_INSTANCES))
2728 return -EBUSY;
2729
2730 return idx;
2731 }
2732
2733 static int coda_open(struct file *file, enum coda_inst_type inst_type,
2734 const struct coda_context_ops *ctx_ops)
2735 {
2736 struct coda_dev *dev = video_drvdata(file);
2737 struct coda_ctx *ctx = NULL;
2738 char *name;
2739 int ret;
2740 int idx;
2741
2742 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
2743 if (!ctx)
2744 return -ENOMEM;
2745
2746 idx = coda_next_free_instance(dev);
2747 if (idx < 0) {
2748 ret = idx;
2749 goto err_coda_max;
2750 }
2751 set_bit(idx, &dev->instance_mask);
2752
2753 name = kasprintf(GFP_KERNEL, "context%d", idx);
2754 ctx->debugfs_entry = debugfs_create_dir(name, dev->debugfs_root);
2755 kfree(name);
2756
2757 ctx->inst_type = inst_type;
2758 ctx->ops = ctx_ops;
2759 init_completion(&ctx->completion);
2760 INIT_WORK(&ctx->pic_run_work, coda_pic_run_work);
2761 INIT_WORK(&ctx->seq_end_work, ctx->ops->seq_end_work);
2762 v4l2_fh_init(&ctx->fh, video_devdata(file));
2763 file->private_data = &ctx->fh;
2764 v4l2_fh_add(&ctx->fh);
2765 ctx->dev = dev;
2766 ctx->idx = idx;
2767 switch (dev->devtype->product) {
2768 case CODA_7541:
2769 case CODA_960:
2770 ctx->reg_idx = 0;
2771 break;
2772 default:
2773 ctx->reg_idx = idx;
2774 }
2775
2776 /* Power up and upload firmware if necessary */
2777 ret = pm_runtime_get_sync(&dev->plat_dev->dev);
2778 if (ret < 0) {
2779 v4l2_err(&dev->v4l2_dev, "failed to power up: %d\n", ret);
2780 goto err_pm_get;
2781 }
2782
2783 ret = clk_prepare_enable(dev->clk_per);
2784 if (ret)
2785 goto err_clk_per;
2786
2787 ret = clk_prepare_enable(dev->clk_ahb);
2788 if (ret)
2789 goto err_clk_ahb;
2790
2791 set_default_params(ctx);
2792 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
2793 ctx->ops->queue_init);
2794 if (IS_ERR(ctx->fh.m2m_ctx)) {
2795 ret = PTR_ERR(ctx->fh.m2m_ctx);
2796
2797 v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
2798 __func__, ret);
2799 goto err_ctx_init;
2800 }
2801
2802 ret = coda_ctrls_setup(ctx);
2803 if (ret) {
2804 v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
2805 goto err_ctrls_setup;
2806 }
2807
2808 ctx->fh.ctrl_handler = &ctx->ctrls;
2809
2810 ret = coda_alloc_context_buf(ctx, &ctx->parabuf, CODA_PARA_BUF_SIZE,
2811 "parabuf");
2812 if (ret < 0) {
2813 v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
2814 goto err_dma_alloc;
2815 }
2816
2817 ctx->bitstream.size = CODA_MAX_FRAME_SIZE;
2818 ctx->bitstream.vaddr = dma_alloc_writecombine(&dev->plat_dev->dev,
2819 ctx->bitstream.size, &ctx->bitstream.paddr, GFP_KERNEL);
2820 if (!ctx->bitstream.vaddr) {
2821 v4l2_err(&dev->v4l2_dev, "failed to allocate bitstream ringbuffer");
2822 ret = -ENOMEM;
2823 goto err_dma_writecombine;
2824 }
2825 kfifo_init(&ctx->bitstream_fifo,
2826 ctx->bitstream.vaddr, ctx->bitstream.size);
2827 mutex_init(&ctx->bitstream_mutex);
2828 mutex_init(&ctx->buffer_mutex);
2829 INIT_LIST_HEAD(&ctx->timestamp_list);
2830
2831 coda_lock(ctx);
2832 list_add(&ctx->list, &dev->instances);
2833 coda_unlock(ctx);
2834
2835 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
2836 ctx->idx, ctx);
2837
2838 return 0;
2839
2840 err_dma_writecombine:
2841 coda_free_context_buffers(ctx);
2842 if (ctx->dev->devtype->product == CODA_DX6)
2843 coda_free_aux_buf(dev, &ctx->workbuf);
2844 coda_free_aux_buf(dev, &ctx->parabuf);
2845 err_dma_alloc:
2846 v4l2_ctrl_handler_free(&ctx->ctrls);
2847 err_ctrls_setup:
2848 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2849 err_ctx_init:
2850 clk_disable_unprepare(dev->clk_ahb);
2851 err_clk_ahb:
2852 clk_disable_unprepare(dev->clk_per);
2853 err_clk_per:
2854 pm_runtime_put_sync(&dev->plat_dev->dev);
2855 err_pm_get:
2856 v4l2_fh_del(&ctx->fh);
2857 v4l2_fh_exit(&ctx->fh);
2858 clear_bit(ctx->idx, &dev->instance_mask);
2859 err_coda_max:
2860 kfree(ctx);
2861 return ret;
2862 }
2863
2864 struct coda_context_ops coda_encode_ops = {
2865 .queue_init = coda_encoder_queue_init,
2866 .start_streaming = coda_start_encoding,
2867 .prepare_run = coda_prepare_encode,
2868 .finish_run = coda_finish_encode,
2869 .seq_end_work = coda_seq_end_work,
2870 };
2871
2872 struct coda_context_ops coda_decode_ops = {
2873 .queue_init = coda_decoder_queue_init,
2874 .start_streaming = coda_start_decoding,
2875 .prepare_run = coda_prepare_decode,
2876 .finish_run = coda_finish_decode,
2877 .seq_end_work = coda_seq_end_work
2878 };
2879
2880 static int coda_encoder_open(struct file *file)
2881 {
2882 return coda_open(file, CODA_INST_ENCODER, &coda_encode_ops);
2883 }
2884
2885 static int coda_decoder_open(struct file *file)
2886 {
2887 return coda_open(file, CODA_INST_DECODER, &coda_decode_ops);
2888 }
2889
2890 static int coda_release(struct file *file)
2891 {
2892 struct coda_dev *dev = video_drvdata(file);
2893 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
2894
2895 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
2896 ctx);
2897
2898 debugfs_remove_recursive(ctx->debugfs_entry);
2899
2900 /* If this instance is running, call .job_abort and wait for it to end */
2901 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2902
2903 /* In case the instance was not running, we still need to call SEQ_END */
2904 if (ctx->initialized) {
2905 queue_work(dev->workqueue, &ctx->seq_end_work);
2906 flush_work(&ctx->seq_end_work);
2907 }
2908
2909 coda_free_framebuffers(ctx);
2910
2911 coda_lock(ctx);
2912 list_del(&ctx->list);
2913 coda_unlock(ctx);
2914
2915 dma_free_writecombine(&dev->plat_dev->dev, ctx->bitstream.size,
2916 ctx->bitstream.vaddr, ctx->bitstream.paddr);
2917 coda_free_context_buffers(ctx);
2918 if (ctx->dev->devtype->product == CODA_DX6)
2919 coda_free_aux_buf(dev, &ctx->workbuf);
2920
2921 coda_free_aux_buf(dev, &ctx->parabuf);
2922 v4l2_ctrl_handler_free(&ctx->ctrls);
2923 clk_disable_unprepare(dev->clk_ahb);
2924 clk_disable_unprepare(dev->clk_per);
2925 pm_runtime_put_sync(&dev->plat_dev->dev);
2926 v4l2_fh_del(&ctx->fh);
2927 v4l2_fh_exit(&ctx->fh);
2928 clear_bit(ctx->idx, &dev->instance_mask);
2929 kfree(ctx);
2930
2931 return 0;
2932 }
2933
2934 static const struct v4l2_file_operations coda_encoder_fops = {
2935 .owner = THIS_MODULE,
2936 .open = coda_encoder_open,
2937 .release = coda_release,
2938 .poll = v4l2_m2m_fop_poll,
2939 .unlocked_ioctl = video_ioctl2,
2940 .mmap = v4l2_m2m_fop_mmap,
2941 };
2942
2943 static const struct v4l2_file_operations coda_decoder_fops = {
2944 .owner = THIS_MODULE,
2945 .open = coda_decoder_open,
2946 .release = coda_release,
2947 .poll = v4l2_m2m_fop_poll,
2948 .unlocked_ioctl = video_ioctl2,
2949 .mmap = v4l2_m2m_fop_mmap,
2950 };
2951
2952 static void coda_finish_decode(struct coda_ctx *ctx)
2953 {
2954 struct coda_dev *dev = ctx->dev;
2955 struct coda_q_data *q_data_src;
2956 struct coda_q_data *q_data_dst;
2957 struct vb2_buffer *dst_buf;
2958 struct coda_timestamp *ts;
2959 int width, height;
2960 int decoded_idx;
2961 int display_idx;
2962 u32 src_fourcc;
2963 int success;
2964 u32 err_mb;
2965 u32 val;
2966
2967 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
2968
2969 /* Update kfifo out pointer from coda bitstream read pointer */
2970 coda_kfifo_sync_from_device(ctx);
2971
2972 /*
2973 * in stream-end mode, the read pointer can overshoot the write pointer
2974 * by up to 512 bytes
2975 */
2976 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
2977 if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
2978 kfifo_init(&ctx->bitstream_fifo,
2979 ctx->bitstream.vaddr, ctx->bitstream.size);
2980 }
2981
2982 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2983 src_fourcc = q_data_src->fourcc;
2984
2985 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
2986 if (val != 1)
2987 pr_err("DEC_PIC_SUCCESS = %d\n", val);
2988
2989 success = val & 0x1;
2990 if (!success)
2991 v4l2_err(&dev->v4l2_dev, "decode failed\n");
2992
2993 if (src_fourcc == V4L2_PIX_FMT_H264) {
2994 if (val & (1 << 3))
2995 v4l2_err(&dev->v4l2_dev,
2996 "insufficient PS buffer space (%d bytes)\n",
2997 ctx->psbuf.size);
2998 if (val & (1 << 2))
2999 v4l2_err(&dev->v4l2_dev,
3000 "insufficient slice buffer space (%d bytes)\n",
3001 ctx->slicebuf.size);
3002 }
3003
3004 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
3005 width = (val >> 16) & 0xffff;
3006 height = val & 0xffff;
3007
3008 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
3009
3010 /* frame crop information */
3011 if (src_fourcc == V4L2_PIX_FMT_H264) {
3012 u32 left_right;
3013 u32 top_bottom;
3014
3015 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
3016 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
3017
3018 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
3019 /* Keep current crop information */
3020 } else {
3021 struct v4l2_rect *rect = &q_data_dst->rect;
3022
3023 rect->left = left_right >> 16 & 0xffff;
3024 rect->top = top_bottom >> 16 & 0xffff;
3025 rect->width = width - rect->left -
3026 (left_right & 0xffff);
3027 rect->height = height - rect->top -
3028 (top_bottom & 0xffff);
3029 }
3030 } else {
3031 /* no cropping */
3032 }
3033
3034 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
3035 if (err_mb > 0)
3036 v4l2_err(&dev->v4l2_dev,
3037 "errors in %d macroblocks\n", err_mb);
3038
3039 if (dev->devtype->product == CODA_7541) {
3040 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
3041 if (val == 0) {
3042 /* not enough bitstream data */
3043 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
3044 "prescan failed: %d\n", val);
3045 ctx->hold = true;
3046 return;
3047 }
3048 }
3049
3050 ctx->frm_dis_flg = coda_read(dev, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
3051
3052 /*
3053 * The previous display frame was copied out by the rotator,
3054 * now it can be overwritten again
3055 */
3056 if (ctx->display_idx >= 0 &&
3057 ctx->display_idx < ctx->num_internal_frames) {
3058 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
3059 coda_write(dev, ctx->frm_dis_flg,
3060 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
3061 }
3062
3063 /*
3064 * The index of the last decoded frame, not necessarily in
3065 * display order, and the index of the next display frame.
3066 * The latter could have been decoded in a previous run.
3067 */
3068 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
3069 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
3070
3071 if (decoded_idx == -1) {
3072 /* no frame was decoded, but we might have a display frame */
3073 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
3074 ctx->sequence_offset++;
3075 else if (ctx->display_idx < 0)
3076 ctx->hold = true;
3077 } else if (decoded_idx == -2) {
3078 /* no frame was decoded, we still return the remaining buffers */
3079 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
3080 v4l2_err(&dev->v4l2_dev,
3081 "decoded frame index out of range: %d\n", decoded_idx);
3082 } else {
3083 ts = list_first_entry(&ctx->timestamp_list,
3084 struct coda_timestamp, list);
3085 list_del(&ts->list);
3086 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
3087 val -= ctx->sequence_offset;
3088 if (val != (ts->sequence & 0xffff)) {
3089 v4l2_err(&dev->v4l2_dev,
3090 "sequence number mismatch (%d(%d) != %d)\n",
3091 val, ctx->sequence_offset, ts->sequence);
3092 }
3093 ctx->frame_timestamps[decoded_idx] = *ts;
3094 kfree(ts);
3095
3096 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
3097 if (val == 0)
3098 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
3099 else if (val == 1)
3100 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
3101 else
3102 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
3103
3104 ctx->frame_errors[decoded_idx] = err_mb;
3105 }
3106
3107 if (display_idx == -1) {
3108 /*
3109 * no more frames to be decoded, but there could still
3110 * be rotator output to dequeue
3111 */
3112 ctx->hold = true;
3113 } else if (display_idx == -3) {
3114 /* possibly prescan failure */
3115 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
3116 v4l2_err(&dev->v4l2_dev,
3117 "presentation frame index out of range: %d\n",
3118 display_idx);
3119 }
3120
3121 /* If a frame was copied out, return it */
3122 if (ctx->display_idx >= 0 &&
3123 ctx->display_idx < ctx->num_internal_frames) {
3124 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
3125 dst_buf->v4l2_buf.sequence = ctx->osequence++;
3126
3127 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
3128 V4L2_BUF_FLAG_PFRAME |
3129 V4L2_BUF_FLAG_BFRAME);
3130 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
3131 ts = &ctx->frame_timestamps[ctx->display_idx];
3132 dst_buf->v4l2_buf.timecode = ts->timecode;
3133 dst_buf->v4l2_buf.timestamp = ts->timestamp;
3134
3135 vb2_set_plane_payload(dst_buf, 0, width * height * 3 / 2);
3136
3137 v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
3138 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
3139
3140 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
3141 "job finished: decoding frame (%d) (%s)\n",
3142 dst_buf->v4l2_buf.sequence,
3143 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
3144 "KEYFRAME" : "PFRAME");
3145 } else {
3146 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
3147 "job finished: no frame decoded\n");
3148 }
3149
3150 /* The rotator will copy the current display frame next time */
3151 ctx->display_idx = display_idx;
3152 }
3153
3154 static void coda_finish_encode(struct coda_ctx *ctx)
3155 {
3156 struct vb2_buffer *src_buf, *dst_buf;
3157 struct coda_dev *dev = ctx->dev;
3158 u32 wr_ptr, start_ptr;
3159
3160 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
3161 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
3162
3163 /* Get results from the coda */
3164 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
3165 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
3166
3167 /* Calculate bytesused field */
3168 if (dst_buf->v4l2_buf.sequence == 0) {
3169 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
3170 ctx->vpu_header_size[0] +
3171 ctx->vpu_header_size[1] +
3172 ctx->vpu_header_size[2]);
3173 } else {
3174 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
3175 }
3176
3177 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
3178 wr_ptr - start_ptr);
3179
3180 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
3181 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
3182
3183 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
3184 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
3185 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
3186 } else {
3187 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
3188 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
3189 }
3190
3191 dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
3192 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
3193 dst_buf->v4l2_buf.flags |=
3194 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
3195 dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
3196
3197 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
3198
3199 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
3200 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
3201
3202 ctx->gopcounter--;
3203 if (ctx->gopcounter < 0)
3204 ctx->gopcounter = ctx->params.gop_size - 1;
3205
3206 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
3207 "job finished: encoding frame (%d) (%s)\n",
3208 dst_buf->v4l2_buf.sequence,
3209 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
3210 "KEYFRAME" : "PFRAME");
3211 }
3212
3213 static irqreturn_t coda_irq_handler(int irq, void *data)
3214 {
3215 struct coda_dev *dev = data;
3216 struct coda_ctx *ctx;
3217
3218 /* read status register to attend the IRQ */
3219 coda_read(dev, CODA_REG_BIT_INT_STATUS);
3220 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
3221 CODA_REG_BIT_INT_CLEAR);
3222
3223 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
3224 if (ctx == NULL) {
3225 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
3226 mutex_unlock(&dev->coda_mutex);
3227 return IRQ_HANDLED;
3228 }
3229
3230 if (ctx->aborting) {
3231 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
3232 "task has been aborted\n");
3233 }
3234
3235 if (coda_isbusy(ctx->dev)) {
3236 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
3237 "coda is still busy!!!!\n");
3238 return IRQ_NONE;
3239 }
3240
3241 complete(&ctx->completion);
3242
3243 return IRQ_HANDLED;
3244 }
3245
3246 static u32 coda_supported_firmwares[] = {
3247 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
3248 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
3249 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
3250 };
3251
3252 static bool coda_firmware_supported(u32 vernum)
3253 {
3254 int i;
3255
3256 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
3257 if (vernum == coda_supported_firmwares[i])
3258 return true;
3259 return false;
3260 }
3261
3262 static int coda_hw_init(struct coda_dev *dev)
3263 {
3264 u32 data;
3265 u16 *p;
3266 int i, ret;
3267
3268 ret = clk_prepare_enable(dev->clk_per);
3269 if (ret)
3270 goto err_clk_per;
3271
3272 ret = clk_prepare_enable(dev->clk_ahb);
3273 if (ret)
3274 goto err_clk_ahb;
3275
3276 if (dev->rstc)
3277 reset_control_reset(dev->rstc);
3278
3279 /*
3280 * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
3281 * The 16-bit chars in the code buffer are in memory access
3282 * order, re-sort them to CODA order for register download.
3283 * Data in this SRAM survives a reboot.
3284 */
3285 p = (u16 *)dev->codebuf.vaddr;
3286 if (dev->devtype->product == CODA_DX6) {
3287 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
3288 data = CODA_DOWN_ADDRESS_SET(i) |
3289 CODA_DOWN_DATA_SET(p[i ^ 1]);
3290 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
3291 }
3292 } else {
3293 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
3294 data = CODA_DOWN_ADDRESS_SET(i) |
3295 CODA_DOWN_DATA_SET(p[round_down(i, 4) +
3296 3 - (i % 4)]);
3297 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
3298 }
3299 }
3300
3301 /* Clear registers */
3302 for (i = 0; i < 64; i++)
3303 coda_write(dev, 0, CODA_REG_BIT_CODE_BUF_ADDR + i * 4);
3304
3305 /* Tell the BIT where to find everything it needs */
3306 if (dev->devtype->product == CODA_960 ||
3307 dev->devtype->product == CODA_7541) {
3308 coda_write(dev, dev->tempbuf.paddr,
3309 CODA_REG_BIT_TEMP_BUF_ADDR);
3310 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
3311 } else {
3312 coda_write(dev, dev->workbuf.paddr,
3313 CODA_REG_BIT_WORK_BUF_ADDR);
3314 }
3315 coda_write(dev, dev->codebuf.paddr,
3316 CODA_REG_BIT_CODE_BUF_ADDR);
3317 coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
3318
3319 /* Set default values */
3320 switch (dev->devtype->product) {
3321 case CODA_DX6:
3322 coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
3323 break;
3324 default:
3325 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
3326 }
3327 if (dev->devtype->product == CODA_960)
3328 coda_write(dev, 1 << 12, CODA_REG_BIT_FRAME_MEM_CTRL);
3329 else
3330 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
3331
3332 if (dev->devtype->product != CODA_DX6)
3333 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
3334
3335 coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
3336 CODA_REG_BIT_INT_ENABLE);
3337
3338 /* Reset VPU and start processor */
3339 data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
3340 data |= CODA_REG_RESET_ENABLE;
3341 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
3342 udelay(10);
3343 data &= ~CODA_REG_RESET_ENABLE;
3344 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
3345 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
3346
3347 clk_disable_unprepare(dev->clk_ahb);
3348 clk_disable_unprepare(dev->clk_per);
3349
3350 return 0;
3351
3352 err_clk_ahb:
3353 clk_disable_unprepare(dev->clk_per);
3354 err_clk_per:
3355 return ret;
3356 }
3357
3358 static int coda_check_firmware(struct coda_dev *dev)
3359 {
3360 u16 product, major, minor, release;
3361 u32 data;
3362 int ret;
3363
3364 ret = clk_prepare_enable(dev->clk_per);
3365 if (ret)
3366 goto err_clk_per;
3367
3368 ret = clk_prepare_enable(dev->clk_ahb);
3369 if (ret)
3370 goto err_clk_ahb;
3371
3372 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
3373 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
3374 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
3375 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
3376 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
3377 if (coda_wait_timeout(dev)) {
3378 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
3379 ret = -EIO;
3380 goto err_run_cmd;
3381 }
3382
3383 if (dev->devtype->product == CODA_960) {
3384 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
3385 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
3386 data);
3387 }
3388
3389 /* Check we are compatible with the loaded firmware */
3390 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
3391 product = CODA_FIRMWARE_PRODUCT(data);
3392 major = CODA_FIRMWARE_MAJOR(data);
3393 minor = CODA_FIRMWARE_MINOR(data);
3394 release = CODA_FIRMWARE_RELEASE(data);
3395
3396 clk_disable_unprepare(dev->clk_per);
3397 clk_disable_unprepare(dev->clk_ahb);
3398
3399 if (product != dev->devtype->product) {
3400 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
3401 " Version: %u.%u.%u\n",
3402 coda_product_name(dev->devtype->product),
3403 coda_product_name(product), major, minor, release);
3404 return -EINVAL;
3405 }
3406
3407 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
3408 coda_product_name(product));
3409
3410 if (coda_firmware_supported(data)) {
3411 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
3412 major, minor, release);
3413 } else {
3414 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
3415 "%u.%u.%u\n", major, minor, release);
3416 }
3417
3418 return 0;
3419
3420 err_run_cmd:
3421 clk_disable_unprepare(dev->clk_ahb);
3422 err_clk_ahb:
3423 clk_disable_unprepare(dev->clk_per);
3424 err_clk_per:
3425 return ret;
3426 }
3427
3428 static int coda_register_device(struct coda_dev *dev, struct video_device *vfd)
3429 {
3430 vfd->release = video_device_release_empty,
3431 vfd->lock = &dev->dev_mutex;
3432 vfd->v4l2_dev = &dev->v4l2_dev;
3433 vfd->vfl_dir = VFL_DIR_M2M;
3434 video_set_drvdata(vfd, dev);
3435
3436 return video_register_device(vfd, VFL_TYPE_GRABBER, 0);
3437 }
3438
3439 static void coda_fw_callback(const struct firmware *fw, void *context)
3440 {
3441 struct coda_dev *dev = context;
3442 struct platform_device *pdev = dev->plat_dev;
3443 int ret;
3444
3445 if (!fw) {
3446 v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
3447 return;
3448 }
3449
3450 /* allocate auxiliary per-device code buffer for the BIT processor */
3451 ret = coda_alloc_aux_buf(dev, &dev->codebuf, fw->size, "codebuf",
3452 dev->debugfs_root);
3453 if (ret < 0) {
3454 dev_err(&pdev->dev, "failed to allocate code buffer\n");
3455 return;
3456 }
3457
3458 /* Copy the whole firmware image to the code buffer */
3459 memcpy(dev->codebuf.vaddr, fw->data, fw->size);
3460 release_firmware(fw);
3461
3462 if (pm_runtime_enabled(&pdev->dev) && pdev->dev.pm_domain) {
3463 /*
3464 * Enabling power temporarily will cause coda_hw_init to be
3465 * called via coda_runtime_resume by the pm domain.
3466 */
3467 ret = pm_runtime_get_sync(&dev->plat_dev->dev);
3468 if (ret < 0) {
3469 v4l2_err(&dev->v4l2_dev, "failed to power on: %d\n",
3470 ret);
3471 return;
3472 }
3473
3474 ret = coda_check_firmware(dev);
3475 if (ret < 0)
3476 return;
3477
3478 pm_runtime_put_sync(&dev->plat_dev->dev);
3479 } else {
3480 /*
3481 * If runtime pm is disabled or pm_domain is not set,
3482 * initialize once manually.
3483 */
3484 ret = coda_hw_init(dev);
3485 if (ret < 0) {
3486 v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
3487 return;
3488 }
3489
3490 ret = coda_check_firmware(dev);
3491 if (ret < 0)
3492 return;
3493 }
3494
3495 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
3496 if (IS_ERR(dev->alloc_ctx)) {
3497 v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
3498 return;
3499 }
3500
3501 dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
3502 if (IS_ERR(dev->m2m_dev)) {
3503 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
3504 goto rel_ctx;
3505 }
3506
3507 dev->vfd[0].fops = &coda_encoder_fops,
3508 dev->vfd[0].ioctl_ops = &coda_ioctl_ops;
3509 snprintf(dev->vfd[0].name, sizeof(dev->vfd[0].name), "coda-encoder");
3510 ret = coda_register_device(dev, &dev->vfd[0]);
3511 if (ret) {
3512 v4l2_err(&dev->v4l2_dev,
3513 "Failed to register encoder video device\n");
3514 goto rel_m2m;
3515 }
3516
3517 dev->vfd[1].fops = &coda_decoder_fops,
3518 dev->vfd[1].ioctl_ops = &coda_ioctl_ops;
3519 snprintf(dev->vfd[1].name, sizeof(dev->vfd[1].name), "coda-decoder");
3520 ret = coda_register_device(dev, &dev->vfd[1]);
3521 if (ret) {
3522 v4l2_err(&dev->v4l2_dev,
3523 "Failed to register decoder video device\n");
3524 goto rel_m2m;
3525 }
3526
3527 v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video[%d-%d]\n",
3528 dev->vfd[0].num, dev->vfd[1].num);
3529
3530 return;
3531
3532 rel_m2m:
3533 v4l2_m2m_release(dev->m2m_dev);
3534 rel_ctx:
3535 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
3536 }
3537
3538 static int coda_firmware_request(struct coda_dev *dev)
3539 {
3540 char *fw = dev->devtype->firmware;
3541
3542 dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
3543 coda_product_name(dev->devtype->product));
3544
3545 return request_firmware_nowait(THIS_MODULE, true,
3546 fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
3547 }
3548
3549 enum coda_platform {
3550 CODA_IMX27,
3551 CODA_IMX53,
3552 CODA_IMX6Q,
3553 CODA_IMX6DL,
3554 };
3555
3556 static const struct coda_devtype coda_devdata[] = {
3557 [CODA_IMX27] = {
3558 .firmware = "v4l-codadx6-imx27.bin",
3559 .product = CODA_DX6,
3560 .codecs = codadx6_codecs,
3561 .num_codecs = ARRAY_SIZE(codadx6_codecs),
3562 .workbuf_size = 288 * 1024 + FMO_SLICE_SAVE_BUF_SIZE * 8 * 1024,
3563 .iram_size = 0xb000,
3564 },
3565 [CODA_IMX53] = {
3566 .firmware = "v4l-coda7541-imx53.bin",
3567 .product = CODA_7541,
3568 .codecs = coda7_codecs,
3569 .num_codecs = ARRAY_SIZE(coda7_codecs),
3570 .workbuf_size = 128 * 1024,
3571 .tempbuf_size = 304 * 1024,
3572 .iram_size = 0x14000,
3573 },
3574 [CODA_IMX6Q] = {
3575 .firmware = "v4l-coda960-imx6q.bin",
3576 .product = CODA_960,
3577 .codecs = coda9_codecs,
3578 .num_codecs = ARRAY_SIZE(coda9_codecs),
3579 .workbuf_size = 80 * 1024,
3580 .tempbuf_size = 204 * 1024,
3581 .iram_size = 0x21000,
3582 },
3583 [CODA_IMX6DL] = {
3584 .firmware = "v4l-coda960-imx6dl.bin",
3585 .product = CODA_960,
3586 .codecs = coda9_codecs,
3587 .num_codecs = ARRAY_SIZE(coda9_codecs),
3588 .workbuf_size = 80 * 1024,
3589 .tempbuf_size = 204 * 1024,
3590 .iram_size = 0x20000,
3591 },
3592 };
3593
3594 static struct platform_device_id coda_platform_ids[] = {
3595 { .name = "coda-imx27", .driver_data = CODA_IMX27 },
3596 { .name = "coda-imx53", .driver_data = CODA_IMX53 },
3597 { /* sentinel */ }
3598 };
3599 MODULE_DEVICE_TABLE(platform, coda_platform_ids);
3600
3601 #ifdef CONFIG_OF
3602 static const struct of_device_id coda_dt_ids[] = {
3603 { .compatible = "fsl,imx27-vpu", .data = &coda_devdata[CODA_IMX27] },
3604 { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
3605 { .compatible = "fsl,imx6q-vpu", .data = &coda_devdata[CODA_IMX6Q] },
3606 { .compatible = "fsl,imx6dl-vpu", .data = &coda_devdata[CODA_IMX6DL] },
3607 { /* sentinel */ }
3608 };
3609 MODULE_DEVICE_TABLE(of, coda_dt_ids);
3610 #endif
3611
3612 static int coda_probe(struct platform_device *pdev)
3613 {
3614 const struct of_device_id *of_id =
3615 of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
3616 const struct platform_device_id *pdev_id;
3617 struct coda_platform_data *pdata = pdev->dev.platform_data;
3618 struct device_node *np = pdev->dev.of_node;
3619 struct gen_pool *pool;
3620 struct coda_dev *dev;
3621 struct resource *res;
3622 int ret, irq;
3623
3624 dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
3625 if (!dev) {
3626 dev_err(&pdev->dev, "Not enough memory for %s\n",
3627 CODA_NAME);
3628 return -ENOMEM;
3629 }
3630
3631 spin_lock_init(&dev->irqlock);
3632 INIT_LIST_HEAD(&dev->instances);
3633
3634 dev->plat_dev = pdev;
3635 dev->clk_per = devm_clk_get(&pdev->dev, "per");
3636 if (IS_ERR(dev->clk_per)) {
3637 dev_err(&pdev->dev, "Could not get per clock\n");
3638 return PTR_ERR(dev->clk_per);
3639 }
3640
3641 dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3642 if (IS_ERR(dev->clk_ahb)) {
3643 dev_err(&pdev->dev, "Could not get ahb clock\n");
3644 return PTR_ERR(dev->clk_ahb);
3645 }
3646
3647 /* Get memory for physical registers */
3648 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3649 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
3650 if (IS_ERR(dev->regs_base))
3651 return PTR_ERR(dev->regs_base);
3652
3653 /* IRQ */
3654 irq = platform_get_irq(pdev, 0);
3655 if (irq < 0) {
3656 dev_err(&pdev->dev, "failed to get irq resource\n");
3657 return irq;
3658 }
3659
3660 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, coda_irq_handler,
3661 IRQF_ONESHOT, dev_name(&pdev->dev), dev);
3662 if (ret < 0) {
3663 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3664 return ret;
3665 }
3666
3667 dev->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
3668 if (IS_ERR(dev->rstc)) {
3669 ret = PTR_ERR(dev->rstc);
3670 if (ret == -ENOENT || ret == -ENOSYS) {
3671 dev->rstc = NULL;
3672 } else {
3673 dev_err(&pdev->dev, "failed get reset control: %d\n", ret);
3674 return ret;
3675 }
3676 }
3677
3678 /* Get IRAM pool from device tree or platform data */
3679 pool = of_get_named_gen_pool(np, "iram", 0);
3680 if (!pool && pdata)
3681 pool = dev_get_gen_pool(pdata->iram_dev);
3682 if (!pool) {
3683 dev_err(&pdev->dev, "iram pool not available\n");
3684 return -ENOMEM;
3685 }
3686 dev->iram_pool = pool;
3687
3688 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3689 if (ret)
3690 return ret;
3691
3692 mutex_init(&dev->dev_mutex);
3693 mutex_init(&dev->coda_mutex);
3694
3695 pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
3696
3697 if (of_id) {
3698 dev->devtype = of_id->data;
3699 } else if (pdev_id) {
3700 dev->devtype = &coda_devdata[pdev_id->driver_data];
3701 } else {
3702 v4l2_device_unregister(&dev->v4l2_dev);
3703 return -EINVAL;
3704 }
3705
3706 dev->debugfs_root = debugfs_create_dir("coda", NULL);
3707 if (!dev->debugfs_root)
3708 dev_warn(&pdev->dev, "failed to create debugfs root\n");
3709
3710 /* allocate auxiliary per-device buffers for the BIT processor */
3711 if (dev->devtype->product == CODA_DX6) {
3712 ret = coda_alloc_aux_buf(dev, &dev->workbuf,
3713 dev->devtype->workbuf_size, "workbuf",
3714 dev->debugfs_root);
3715 if (ret < 0) {
3716 dev_err(&pdev->dev, "failed to allocate work buffer\n");
3717 v4l2_device_unregister(&dev->v4l2_dev);
3718 return ret;
3719 }
3720 }
3721
3722 if (dev->devtype->tempbuf_size) {
3723 ret = coda_alloc_aux_buf(dev, &dev->tempbuf,
3724 dev->devtype->tempbuf_size, "tempbuf",
3725 dev->debugfs_root);
3726 if (ret < 0) {
3727 dev_err(&pdev->dev, "failed to allocate temp buffer\n");
3728 v4l2_device_unregister(&dev->v4l2_dev);
3729 return ret;
3730 }
3731 }
3732
3733 dev->iram.size = dev->devtype->iram_size;
3734 dev->iram.vaddr = gen_pool_dma_alloc(dev->iram_pool, dev->iram.size,
3735 &dev->iram.paddr);
3736 if (!dev->iram.vaddr) {
3737 dev_err(&pdev->dev, "unable to alloc iram\n");
3738 return -ENOMEM;
3739 }
3740
3741 dev->iram.blob.data = dev->iram.vaddr;
3742 dev->iram.blob.size = dev->iram.size;
3743 dev->iram.dentry = debugfs_create_blob("iram", 0644, dev->debugfs_root,
3744 &dev->iram.blob);
3745
3746 dev->workqueue = alloc_workqueue("coda", WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
3747 if (!dev->workqueue) {
3748 dev_err(&pdev->dev, "unable to alloc workqueue\n");
3749 return -ENOMEM;
3750 }
3751
3752 platform_set_drvdata(pdev, dev);
3753
3754 pm_runtime_enable(&pdev->dev);
3755
3756 return coda_firmware_request(dev);
3757 }
3758
3759 static int coda_remove(struct platform_device *pdev)
3760 {
3761 struct coda_dev *dev = platform_get_drvdata(pdev);
3762
3763 video_unregister_device(&dev->vfd[0]);
3764 video_unregister_device(&dev->vfd[1]);
3765 if (dev->m2m_dev)
3766 v4l2_m2m_release(dev->m2m_dev);
3767 pm_runtime_disable(&pdev->dev);
3768 if (dev->alloc_ctx)
3769 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
3770 v4l2_device_unregister(&dev->v4l2_dev);
3771 destroy_workqueue(dev->workqueue);
3772 if (dev->iram.vaddr)
3773 gen_pool_free(dev->iram_pool, (unsigned long)dev->iram.vaddr,
3774 dev->iram.size);
3775 coda_free_aux_buf(dev, &dev->codebuf);
3776 coda_free_aux_buf(dev, &dev->tempbuf);
3777 coda_free_aux_buf(dev, &dev->workbuf);
3778 debugfs_remove_recursive(dev->debugfs_root);
3779 return 0;
3780 }
3781
3782 #ifdef CONFIG_PM_RUNTIME
3783 static int coda_runtime_resume(struct device *dev)
3784 {
3785 struct coda_dev *cdev = dev_get_drvdata(dev);
3786 int ret = 0;
3787
3788 if (dev->pm_domain && cdev->codebuf.vaddr) {
3789 ret = coda_hw_init(cdev);
3790 if (ret)
3791 v4l2_err(&cdev->v4l2_dev, "HW initialization failed\n");
3792 }
3793
3794 return ret;
3795 }
3796 #endif
3797
3798 static const struct dev_pm_ops coda_pm_ops = {
3799 SET_RUNTIME_PM_OPS(NULL, coda_runtime_resume, NULL)
3800 };
3801
3802 static struct platform_driver coda_driver = {
3803 .probe = coda_probe,
3804 .remove = coda_remove,
3805 .driver = {
3806 .name = CODA_NAME,
3807 .owner = THIS_MODULE,
3808 .of_match_table = of_match_ptr(coda_dt_ids),
3809 .pm = &coda_pm_ops,
3810 },
3811 .id_table = coda_platform_ids,
3812 };
3813
3814 module_platform_driver(coda_driver);
3815
3816 MODULE_LICENSE("GPL");
3817 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
3818 MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");
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