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r8169: initialize rtl8169_stats seqlock
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / realtek / r8169.c
blobe9779653cd4ce6cee899f92694b071ed5e7cd7a8
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #define RTL8169_VERSION "2.3LK-NAPI"
35 #define MODULENAME "r8169"
36 #define PFX MODULENAME ": "
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53
54 #ifdef RTL8169_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
58 #expr,__FILE__,__func__,__LINE__); \
59 }
60 #define dprintk(fmt, args...) \
61 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
62 #else
63 #define assert(expr) do {} while (0)
64 #define dprintk(fmt, args...) do {} while (0)
65 #endif /* RTL8169_DEBUG */
66
67 #define R8169_MSG_DEFAULT \
68 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
69
70 #define TX_SLOTS_AVAIL(tp) \
71 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
72
73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
75 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
76
77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
78 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
79 static const int multicast_filter_limit = 32;
80
81 #define MAX_READ_REQUEST_SHIFT 12
82 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
84
85 #define R8169_REGS_SIZE 256
86 #define R8169_NAPI_WEIGHT 64
87 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
88 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
89 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92 #define RTL8169_TX_TIMEOUT (6*HZ)
93 #define RTL8169_PHY_TIMEOUT (10*HZ)
94
95 /* write/read MMIO register */
96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
99 #define RTL_R8(reg) readb (ioaddr + (reg))
100 #define RTL_R16(reg) readw (ioaddr + (reg))
101 #define RTL_R32(reg) readl (ioaddr + (reg))
102
103 enum mac_version {
104 RTL_GIGA_MAC_VER_01 = 0,
105 RTL_GIGA_MAC_VER_02,
106 RTL_GIGA_MAC_VER_03,
107 RTL_GIGA_MAC_VER_04,
108 RTL_GIGA_MAC_VER_05,
109 RTL_GIGA_MAC_VER_06,
110 RTL_GIGA_MAC_VER_07,
111 RTL_GIGA_MAC_VER_08,
112 RTL_GIGA_MAC_VER_09,
113 RTL_GIGA_MAC_VER_10,
114 RTL_GIGA_MAC_VER_11,
115 RTL_GIGA_MAC_VER_12,
116 RTL_GIGA_MAC_VER_13,
117 RTL_GIGA_MAC_VER_14,
118 RTL_GIGA_MAC_VER_15,
119 RTL_GIGA_MAC_VER_16,
120 RTL_GIGA_MAC_VER_17,
121 RTL_GIGA_MAC_VER_18,
122 RTL_GIGA_MAC_VER_19,
123 RTL_GIGA_MAC_VER_20,
124 RTL_GIGA_MAC_VER_21,
125 RTL_GIGA_MAC_VER_22,
126 RTL_GIGA_MAC_VER_23,
127 RTL_GIGA_MAC_VER_24,
128 RTL_GIGA_MAC_VER_25,
129 RTL_GIGA_MAC_VER_26,
130 RTL_GIGA_MAC_VER_27,
131 RTL_GIGA_MAC_VER_28,
132 RTL_GIGA_MAC_VER_29,
133 RTL_GIGA_MAC_VER_30,
134 RTL_GIGA_MAC_VER_31,
135 RTL_GIGA_MAC_VER_32,
136 RTL_GIGA_MAC_VER_33,
137 RTL_GIGA_MAC_VER_34,
138 RTL_GIGA_MAC_VER_35,
139 RTL_GIGA_MAC_VER_36,
140 RTL_GIGA_MAC_VER_37,
141 RTL_GIGA_MAC_VER_38,
142 RTL_GIGA_MAC_VER_39,
143 RTL_GIGA_MAC_VER_40,
144 RTL_GIGA_MAC_VER_41,
145 RTL_GIGA_MAC_VER_42,
146 RTL_GIGA_MAC_VER_43,
147 RTL_GIGA_MAC_VER_44,
148 RTL_GIGA_MAC_NONE = 0xff,
149 };
150
151 enum rtl_tx_desc_version {
152 RTL_TD_0 = 0,
153 RTL_TD_1 = 1,
154 };
155
156 #define JUMBO_1K ETH_DATA_LEN
157 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
158 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
159 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
160 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
161
162 #define _R(NAME,TD,FW,SZ,B) { \
163 .name = NAME, \
164 .txd_version = TD, \
165 .fw_name = FW, \
166 .jumbo_max = SZ, \
167 .jumbo_tx_csum = B \
168 }
169
170 static const struct {
171 const char *name;
172 enum rtl_tx_desc_version txd_version;
173 const char *fw_name;
174 u16 jumbo_max;
175 bool jumbo_tx_csum;
176 } rtl_chip_infos[] = {
177 /* PCI devices. */
178 [RTL_GIGA_MAC_VER_01] =
179 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
180 [RTL_GIGA_MAC_VER_02] =
181 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
182 [RTL_GIGA_MAC_VER_03] =
183 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
184 [RTL_GIGA_MAC_VER_04] =
185 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
186 [RTL_GIGA_MAC_VER_05] =
187 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
188 [RTL_GIGA_MAC_VER_06] =
189 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
190 /* PCI-E devices. */
191 [RTL_GIGA_MAC_VER_07] =
192 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
193 [RTL_GIGA_MAC_VER_08] =
194 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
195 [RTL_GIGA_MAC_VER_09] =
196 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
197 [RTL_GIGA_MAC_VER_10] =
198 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
199 [RTL_GIGA_MAC_VER_11] =
200 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
201 [RTL_GIGA_MAC_VER_12] =
202 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
203 [RTL_GIGA_MAC_VER_13] =
204 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
205 [RTL_GIGA_MAC_VER_14] =
206 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
207 [RTL_GIGA_MAC_VER_15] =
208 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
209 [RTL_GIGA_MAC_VER_16] =
210 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
211 [RTL_GIGA_MAC_VER_17] =
212 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
213 [RTL_GIGA_MAC_VER_18] =
214 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
215 [RTL_GIGA_MAC_VER_19] =
216 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
217 [RTL_GIGA_MAC_VER_20] =
218 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
219 [RTL_GIGA_MAC_VER_21] =
220 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
221 [RTL_GIGA_MAC_VER_22] =
222 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
223 [RTL_GIGA_MAC_VER_23] =
224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
225 [RTL_GIGA_MAC_VER_24] =
226 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
227 [RTL_GIGA_MAC_VER_25] =
228 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
229 JUMBO_9K, false),
230 [RTL_GIGA_MAC_VER_26] =
231 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
232 JUMBO_9K, false),
233 [RTL_GIGA_MAC_VER_27] =
234 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
235 [RTL_GIGA_MAC_VER_28] =
236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
237 [RTL_GIGA_MAC_VER_29] =
238 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
239 JUMBO_1K, true),
240 [RTL_GIGA_MAC_VER_30] =
241 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
242 JUMBO_1K, true),
243 [RTL_GIGA_MAC_VER_31] =
244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
245 [RTL_GIGA_MAC_VER_32] =
246 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
247 JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_33] =
249 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
250 JUMBO_9K, false),
251 [RTL_GIGA_MAC_VER_34] =
252 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
253 JUMBO_9K, false),
254 [RTL_GIGA_MAC_VER_35] =
255 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
256 JUMBO_9K, false),
257 [RTL_GIGA_MAC_VER_36] =
258 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
259 JUMBO_9K, false),
260 [RTL_GIGA_MAC_VER_37] =
261 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
262 JUMBO_1K, true),
263 [RTL_GIGA_MAC_VER_38] =
264 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
265 JUMBO_9K, false),
266 [RTL_GIGA_MAC_VER_39] =
267 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
268 JUMBO_1K, true),
269 [RTL_GIGA_MAC_VER_40] =
270 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
271 JUMBO_9K, false),
272 [RTL_GIGA_MAC_VER_41] =
273 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
274 [RTL_GIGA_MAC_VER_42] =
275 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
276 JUMBO_9K, false),
277 [RTL_GIGA_MAC_VER_43] =
278 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
279 JUMBO_1K, true),
280 [RTL_GIGA_MAC_VER_44] =
281 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
282 JUMBO_9K, false),
283 };
284 #undef _R
285
286 enum cfg_version {
287 RTL_CFG_0 = 0x00,
288 RTL_CFG_1,
289 RTL_CFG_2
290 };
291
292 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
293 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
294 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
298 { PCI_VENDOR_ID_DLINK, 0x4300,
299 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
300 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
301 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
302 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
303 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
304 { PCI_VENDOR_ID_LINKSYS, 0x1032,
305 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
306 { 0x0001, 0x8168,
307 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
308 {0,},
309 };
310
311 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
312
313 static int rx_buf_sz = 16383;
314 static int use_dac;
315 static struct {
316 u32 msg_enable;
317 } debug = { -1 };
318
319 enum rtl_registers {
320 MAC0 = 0, /* Ethernet hardware address. */
321 MAC4 = 4,
322 MAR0 = 8, /* Multicast filter. */
323 CounterAddrLow = 0x10,
324 CounterAddrHigh = 0x14,
325 TxDescStartAddrLow = 0x20,
326 TxDescStartAddrHigh = 0x24,
327 TxHDescStartAddrLow = 0x28,
328 TxHDescStartAddrHigh = 0x2c,
329 FLASH = 0x30,
330 ERSR = 0x36,
331 ChipCmd = 0x37,
332 TxPoll = 0x38,
333 IntrMask = 0x3c,
334 IntrStatus = 0x3e,
335
336 TxConfig = 0x40,
337 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
338 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
339
340 RxConfig = 0x44,
341 #define RX128_INT_EN (1 << 15) /* 8111c and later */
342 #define RX_MULTI_EN (1 << 14) /* 8111c only */
343 #define RXCFG_FIFO_SHIFT 13
344 /* No threshold before first PCI xfer */
345 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
346 #define RX_EARLY_OFF (1 << 11)
347 #define RXCFG_DMA_SHIFT 8
348 /* Unlimited maximum PCI burst. */
349 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
350
351 RxMissed = 0x4c,
352 Cfg9346 = 0x50,
353 Config0 = 0x51,
354 Config1 = 0x52,
355 Config2 = 0x53,
356 #define PME_SIGNAL (1 << 5) /* 8168c and later */
357
358 Config3 = 0x54,
359 Config4 = 0x55,
360 Config5 = 0x56,
361 MultiIntr = 0x5c,
362 PHYAR = 0x60,
363 PHYstatus = 0x6c,
364 RxMaxSize = 0xda,
365 CPlusCmd = 0xe0,
366 IntrMitigate = 0xe2,
367 RxDescAddrLow = 0xe4,
368 RxDescAddrHigh = 0xe8,
369 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
370
371 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
372
373 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
374
375 #define TxPacketMax (8064 >> 7)
376 #define EarlySize 0x27
377
378 FuncEvent = 0xf0,
379 FuncEventMask = 0xf4,
380 FuncPresetState = 0xf8,
381 FuncForceEvent = 0xfc,
382 };
383
384 enum rtl8110_registers {
385 TBICSR = 0x64,
386 TBI_ANAR = 0x68,
387 TBI_LPAR = 0x6a,
388 };
389
390 enum rtl8168_8101_registers {
391 CSIDR = 0x64,
392 CSIAR = 0x68,
393 #define CSIAR_FLAG 0x80000000
394 #define CSIAR_WRITE_CMD 0x80000000
395 #define CSIAR_BYTE_ENABLE 0x0f
396 #define CSIAR_BYTE_ENABLE_SHIFT 12
397 #define CSIAR_ADDR_MASK 0x0fff
398 #define CSIAR_FUNC_CARD 0x00000000
399 #define CSIAR_FUNC_SDIO 0x00010000
400 #define CSIAR_FUNC_NIC 0x00020000
401 #define CSIAR_FUNC_NIC2 0x00010000
402 PMCH = 0x6f,
403 EPHYAR = 0x80,
404 #define EPHYAR_FLAG 0x80000000
405 #define EPHYAR_WRITE_CMD 0x80000000
406 #define EPHYAR_REG_MASK 0x1f
407 #define EPHYAR_REG_SHIFT 16
408 #define EPHYAR_DATA_MASK 0xffff
409 DLLPR = 0xd0,
410 #define PFM_EN (1 << 6)
411 DBG_REG = 0xd1,
412 #define FIX_NAK_1 (1 << 4)
413 #define FIX_NAK_2 (1 << 3)
414 TWSI = 0xd2,
415 MCU = 0xd3,
416 #define NOW_IS_OOB (1 << 7)
417 #define TX_EMPTY (1 << 5)
418 #define RX_EMPTY (1 << 4)
419 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
420 #define EN_NDP (1 << 3)
421 #define EN_OOB_RESET (1 << 2)
422 #define LINK_LIST_RDY (1 << 1)
423 EFUSEAR = 0xdc,
424 #define EFUSEAR_FLAG 0x80000000
425 #define EFUSEAR_WRITE_CMD 0x80000000
426 #define EFUSEAR_READ_CMD 0x00000000
427 #define EFUSEAR_REG_MASK 0x03ff
428 #define EFUSEAR_REG_SHIFT 8
429 #define EFUSEAR_DATA_MASK 0xff
430 };
431
432 enum rtl8168_registers {
433 LED_FREQ = 0x1a,
434 EEE_LED = 0x1b,
435 ERIDR = 0x70,
436 ERIAR = 0x74,
437 #define ERIAR_FLAG 0x80000000
438 #define ERIAR_WRITE_CMD 0x80000000
439 #define ERIAR_READ_CMD 0x00000000
440 #define ERIAR_ADDR_BYTE_ALIGN 4
441 #define ERIAR_TYPE_SHIFT 16
442 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
443 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
444 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
445 #define ERIAR_MASK_SHIFT 12
446 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
447 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
448 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
449 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
450 EPHY_RXER_NUM = 0x7c,
451 OCPDR = 0xb0, /* OCP GPHY access */
452 #define OCPDR_WRITE_CMD 0x80000000
453 #define OCPDR_READ_CMD 0x00000000
454 #define OCPDR_REG_MASK 0x7f
455 #define OCPDR_GPHY_REG_SHIFT 16
456 #define OCPDR_DATA_MASK 0xffff
457 OCPAR = 0xb4,
458 #define OCPAR_FLAG 0x80000000
459 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
460 #define OCPAR_GPHY_READ_CMD 0x0000f060
461 GPHY_OCP = 0xb8,
462 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
463 MISC = 0xf0, /* 8168e only. */
464 #define TXPLA_RST (1 << 29)
465 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
466 #define PWM_EN (1 << 22)
467 #define RXDV_GATED_EN (1 << 19)
468 #define EARLY_TALLY_EN (1 << 16)
469 };
470
471 enum rtl_register_content {
472 /* InterruptStatusBits */
473 SYSErr = 0x8000,
474 PCSTimeout = 0x4000,
475 SWInt = 0x0100,
476 TxDescUnavail = 0x0080,
477 RxFIFOOver = 0x0040,
478 LinkChg = 0x0020,
479 RxOverflow = 0x0010,
480 TxErr = 0x0008,
481 TxOK = 0x0004,
482 RxErr = 0x0002,
483 RxOK = 0x0001,
484
485 /* RxStatusDesc */
486 RxBOVF = (1 << 24),
487 RxFOVF = (1 << 23),
488 RxRWT = (1 << 22),
489 RxRES = (1 << 21),
490 RxRUNT = (1 << 20),
491 RxCRC = (1 << 19),
492
493 /* ChipCmdBits */
494 StopReq = 0x80,
495 CmdReset = 0x10,
496 CmdRxEnb = 0x08,
497 CmdTxEnb = 0x04,
498 RxBufEmpty = 0x01,
499
500 /* TXPoll register p.5 */
501 HPQ = 0x80, /* Poll cmd on the high prio queue */
502 NPQ = 0x40, /* Poll cmd on the low prio queue */
503 FSWInt = 0x01, /* Forced software interrupt */
504
505 /* Cfg9346Bits */
506 Cfg9346_Lock = 0x00,
507 Cfg9346_Unlock = 0xc0,
508
509 /* rx_mode_bits */
510 AcceptErr = 0x20,
511 AcceptRunt = 0x10,
512 AcceptBroadcast = 0x08,
513 AcceptMulticast = 0x04,
514 AcceptMyPhys = 0x02,
515 AcceptAllPhys = 0x01,
516 #define RX_CONFIG_ACCEPT_MASK 0x3f
517
518 /* TxConfigBits */
519 TxInterFrameGapShift = 24,
520 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
521
522 /* Config1 register p.24 */
523 LEDS1 = (1 << 7),
524 LEDS0 = (1 << 6),
525 Speed_down = (1 << 4),
526 MEMMAP = (1 << 3),
527 IOMAP = (1 << 2),
528 VPD = (1 << 1),
529 PMEnable = (1 << 0), /* Power Management Enable */
530
531 /* Config2 register p. 25 */
532 ClkReqEn = (1 << 7), /* Clock Request Enable */
533 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
534 PCI_Clock_66MHz = 0x01,
535 PCI_Clock_33MHz = 0x00,
536
537 /* Config3 register p.25 */
538 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
539 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
540 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
541 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
542
543 /* Config4 register */
544 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
545
546 /* Config5 register p.27 */
547 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
548 MWF = (1 << 5), /* Accept Multicast wakeup frame */
549 UWF = (1 << 4), /* Accept Unicast wakeup frame */
550 Spi_en = (1 << 3),
551 LanWake = (1 << 1), /* LanWake enable/disable */
552 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
553 ASPM_en = (1 << 0), /* ASPM enable */
554
555 /* TBICSR p.28 */
556 TBIReset = 0x80000000,
557 TBILoopback = 0x40000000,
558 TBINwEnable = 0x20000000,
559 TBINwRestart = 0x10000000,
560 TBILinkOk = 0x02000000,
561 TBINwComplete = 0x01000000,
562
563 /* CPlusCmd p.31 */
564 EnableBist = (1 << 15), // 8168 8101
565 Mac_dbgo_oe = (1 << 14), // 8168 8101
566 Normal_mode = (1 << 13), // unused
567 Force_half_dup = (1 << 12), // 8168 8101
568 Force_rxflow_en = (1 << 11), // 8168 8101
569 Force_txflow_en = (1 << 10), // 8168 8101
570 Cxpl_dbg_sel = (1 << 9), // 8168 8101
571 ASF = (1 << 8), // 8168 8101
572 PktCntrDisable = (1 << 7), // 8168 8101
573 Mac_dbgo_sel = 0x001c, // 8168
574 RxVlan = (1 << 6),
575 RxChkSum = (1 << 5),
576 PCIDAC = (1 << 4),
577 PCIMulRW = (1 << 3),
578 INTT_0 = 0x0000, // 8168
579 INTT_1 = 0x0001, // 8168
580 INTT_2 = 0x0002, // 8168
581 INTT_3 = 0x0003, // 8168
582
583 /* rtl8169_PHYstatus */
584 TBI_Enable = 0x80,
585 TxFlowCtrl = 0x40,
586 RxFlowCtrl = 0x20,
587 _1000bpsF = 0x10,
588 _100bps = 0x08,
589 _10bps = 0x04,
590 LinkStatus = 0x02,
591 FullDup = 0x01,
592
593 /* _TBICSRBit */
594 TBILinkOK = 0x02000000,
595
596 /* DumpCounterCommand */
597 CounterDump = 0x8,
598 };
599
600 enum rtl_desc_bit {
601 /* First doubleword. */
602 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
603 RingEnd = (1 << 30), /* End of descriptor ring */
604 FirstFrag = (1 << 29), /* First segment of a packet */
605 LastFrag = (1 << 28), /* Final segment of a packet */
606 };
607
608 /* Generic case. */
609 enum rtl_tx_desc_bit {
610 /* First doubleword. */
611 TD_LSO = (1 << 27), /* Large Send Offload */
612 #define TD_MSS_MAX 0x07ffu /* MSS value */
613
614 /* Second doubleword. */
615 TxVlanTag = (1 << 17), /* Add VLAN tag */
616 };
617
618 /* 8169, 8168b and 810x except 8102e. */
619 enum rtl_tx_desc_bit_0 {
620 /* First doubleword. */
621 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
622 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
623 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
624 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
625 };
626
627 /* 8102e, 8168c and beyond. */
628 enum rtl_tx_desc_bit_1 {
629 /* Second doubleword. */
630 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
631 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
632 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
633 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
634 };
635
636 static const struct rtl_tx_desc_info {
637 struct {
638 u32 udp;
639 u32 tcp;
640 } checksum;
641 u16 mss_shift;
642 u16 opts_offset;
643 } tx_desc_info [] = {
644 [RTL_TD_0] = {
645 .checksum = {
646 .udp = TD0_IP_CS | TD0_UDP_CS,
647 .tcp = TD0_IP_CS | TD0_TCP_CS
648 },
649 .mss_shift = TD0_MSS_SHIFT,
650 .opts_offset = 0
651 },
652 [RTL_TD_1] = {
653 .checksum = {
654 .udp = TD1_IP_CS | TD1_UDP_CS,
655 .tcp = TD1_IP_CS | TD1_TCP_CS
656 },
657 .mss_shift = TD1_MSS_SHIFT,
658 .opts_offset = 1
659 }
660 };
661
662 enum rtl_rx_desc_bit {
663 /* Rx private */
664 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
665 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
666
667 #define RxProtoUDP (PID1)
668 #define RxProtoTCP (PID0)
669 #define RxProtoIP (PID1 | PID0)
670 #define RxProtoMask RxProtoIP
671
672 IPFail = (1 << 16), /* IP checksum failed */
673 UDPFail = (1 << 15), /* UDP/IP checksum failed */
674 TCPFail = (1 << 14), /* TCP/IP checksum failed */
675 RxVlanTag = (1 << 16), /* VLAN tag available */
676 };
677
678 #define RsvdMask 0x3fffc000
679
680 struct TxDesc {
681 __le32 opts1;
682 __le32 opts2;
683 __le64 addr;
684 };
685
686 struct RxDesc {
687 __le32 opts1;
688 __le32 opts2;
689 __le64 addr;
690 };
691
692 struct ring_info {
693 struct sk_buff *skb;
694 u32 len;
695 u8 __pad[sizeof(void *) - sizeof(u32)];
696 };
697
698 enum features {
699 RTL_FEATURE_WOL = (1 << 0),
700 RTL_FEATURE_MSI = (1 << 1),
701 RTL_FEATURE_GMII = (1 << 2),
702 };
703
704 struct rtl8169_counters {
705 __le64 tx_packets;
706 __le64 rx_packets;
707 __le64 tx_errors;
708 __le32 rx_errors;
709 __le16 rx_missed;
710 __le16 align_errors;
711 __le32 tx_one_collision;
712 __le32 tx_multi_collision;
713 __le64 rx_unicast;
714 __le64 rx_broadcast;
715 __le32 rx_multicast;
716 __le16 tx_aborted;
717 __le16 tx_underun;
718 };
719
720 enum rtl_flag {
721 RTL_FLAG_TASK_ENABLED,
722 RTL_FLAG_TASK_SLOW_PENDING,
723 RTL_FLAG_TASK_RESET_PENDING,
724 RTL_FLAG_TASK_PHY_PENDING,
725 RTL_FLAG_MAX
726 };
727
728 struct rtl8169_stats {
729 u64 packets;
730 u64 bytes;
731 struct u64_stats_sync syncp;
732 };
733
734 struct rtl8169_private {
735 void __iomem *mmio_addr; /* memory map physical address */
736 struct pci_dev *pci_dev;
737 struct net_device *dev;
738 struct napi_struct napi;
739 u32 msg_enable;
740 u16 txd_version;
741 u16 mac_version;
742 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
743 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
744 u32 dirty_tx;
745 struct rtl8169_stats rx_stats;
746 struct rtl8169_stats tx_stats;
747 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
748 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
749 dma_addr_t TxPhyAddr;
750 dma_addr_t RxPhyAddr;
751 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
752 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
753 struct timer_list timer;
754 u16 cp_cmd;
755
756 u16 event_slow;
757
758 struct mdio_ops {
759 void (*write)(struct rtl8169_private *, int, int);
760 int (*read)(struct rtl8169_private *, int);
761 } mdio_ops;
762
763 struct pll_power_ops {
764 void (*down)(struct rtl8169_private *);
765 void (*up)(struct rtl8169_private *);
766 } pll_power_ops;
767
768 struct jumbo_ops {
769 void (*enable)(struct rtl8169_private *);
770 void (*disable)(struct rtl8169_private *);
771 } jumbo_ops;
772
773 struct csi_ops {
774 void (*write)(struct rtl8169_private *, int, int);
775 u32 (*read)(struct rtl8169_private *, int);
776 } csi_ops;
777
778 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
779 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
780 void (*phy_reset_enable)(struct rtl8169_private *tp);
781 void (*hw_start)(struct net_device *);
782 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
783 unsigned int (*link_ok)(void __iomem *);
784 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
785
786 struct {
787 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
788 struct mutex mutex;
789 struct work_struct work;
790 } wk;
791
792 unsigned features;
793
794 struct mii_if_info mii;
795 struct rtl8169_counters counters;
796 u32 saved_wolopts;
797 u32 opts1_mask;
798
799 struct rtl_fw {
800 const struct firmware *fw;
801
802 #define RTL_VER_SIZE 32
803
804 char version[RTL_VER_SIZE];
805
806 struct rtl_fw_phy_action {
807 __le32 *code;
808 size_t size;
809 } phy_action;
810 } *rtl_fw;
811 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
812
813 u32 ocp_base;
814 };
815
816 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
817 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
818 module_param(use_dac, int, 0);
819 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
820 module_param_named(debug, debug.msg_enable, int, 0);
821 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
822 MODULE_LICENSE("GPL");
823 MODULE_VERSION(RTL8169_VERSION);
824 MODULE_FIRMWARE(FIRMWARE_8168D_1);
825 MODULE_FIRMWARE(FIRMWARE_8168D_2);
826 MODULE_FIRMWARE(FIRMWARE_8168E_1);
827 MODULE_FIRMWARE(FIRMWARE_8168E_2);
828 MODULE_FIRMWARE(FIRMWARE_8168E_3);
829 MODULE_FIRMWARE(FIRMWARE_8105E_1);
830 MODULE_FIRMWARE(FIRMWARE_8168F_1);
831 MODULE_FIRMWARE(FIRMWARE_8168F_2);
832 MODULE_FIRMWARE(FIRMWARE_8402_1);
833 MODULE_FIRMWARE(FIRMWARE_8411_1);
834 MODULE_FIRMWARE(FIRMWARE_8411_2);
835 MODULE_FIRMWARE(FIRMWARE_8106E_1);
836 MODULE_FIRMWARE(FIRMWARE_8106E_2);
837 MODULE_FIRMWARE(FIRMWARE_8168G_2);
838 MODULE_FIRMWARE(FIRMWARE_8168G_3);
839
840 static void rtl_lock_work(struct rtl8169_private *tp)
841 {
842 mutex_lock(&tp->wk.mutex);
843 }
844
845 static void rtl_unlock_work(struct rtl8169_private *tp)
846 {
847 mutex_unlock(&tp->wk.mutex);
848 }
849
850 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
851 {
852 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
853 PCI_EXP_DEVCTL_READRQ, force);
854 }
855
856 struct rtl_cond {
857 bool (*check)(struct rtl8169_private *);
858 const char *msg;
859 };
860
861 static void rtl_udelay(unsigned int d)
862 {
863 udelay(d);
864 }
865
866 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
867 void (*delay)(unsigned int), unsigned int d, int n,
868 bool high)
869 {
870 int i;
871
872 for (i = 0; i < n; i++) {
873 delay(d);
874 if (c->check(tp) == high)
875 return true;
876 }
877 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
878 c->msg, !high, n, d);
879 return false;
880 }
881
882 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
883 const struct rtl_cond *c,
884 unsigned int d, int n)
885 {
886 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
887 }
888
889 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
890 const struct rtl_cond *c,
891 unsigned int d, int n)
892 {
893 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
894 }
895
896 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
897 const struct rtl_cond *c,
898 unsigned int d, int n)
899 {
900 return rtl_loop_wait(tp, c, msleep, d, n, true);
901 }
902
903 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
904 const struct rtl_cond *c,
905 unsigned int d, int n)
906 {
907 return rtl_loop_wait(tp, c, msleep, d, n, false);
908 }
909
910 #define DECLARE_RTL_COND(name) \
911 static bool name ## _check(struct rtl8169_private *); \
912 \
913 static const struct rtl_cond name = { \
914 .check = name ## _check, \
915 .msg = #name \
916 }; \
917 \
918 static bool name ## _check(struct rtl8169_private *tp)
919
920 DECLARE_RTL_COND(rtl_ocpar_cond)
921 {
922 void __iomem *ioaddr = tp->mmio_addr;
923
924 return RTL_R32(OCPAR) & OCPAR_FLAG;
925 }
926
927 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
928 {
929 void __iomem *ioaddr = tp->mmio_addr;
930
931 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
932
933 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
934 RTL_R32(OCPDR) : ~0;
935 }
936
937 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
938 {
939 void __iomem *ioaddr = tp->mmio_addr;
940
941 RTL_W32(OCPDR, data);
942 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
943
944 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
945 }
946
947 DECLARE_RTL_COND(rtl_eriar_cond)
948 {
949 void __iomem *ioaddr = tp->mmio_addr;
950
951 return RTL_R32(ERIAR) & ERIAR_FLAG;
952 }
953
954 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
955 {
956 void __iomem *ioaddr = tp->mmio_addr;
957
958 RTL_W8(ERIDR, cmd);
959 RTL_W32(ERIAR, 0x800010e8);
960 msleep(2);
961
962 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
963 return;
964
965 ocp_write(tp, 0x1, 0x30, 0x00000001);
966 }
967
968 #define OOB_CMD_RESET 0x00
969 #define OOB_CMD_DRIVER_START 0x05
970 #define OOB_CMD_DRIVER_STOP 0x06
971
972 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
973 {
974 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
975 }
976
977 DECLARE_RTL_COND(rtl_ocp_read_cond)
978 {
979 u16 reg;
980
981 reg = rtl8168_get_ocp_reg(tp);
982
983 return ocp_read(tp, 0x0f, reg) & 0x00000800;
984 }
985
986 static void rtl8168_driver_start(struct rtl8169_private *tp)
987 {
988 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
989
990 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
991 }
992
993 static void rtl8168_driver_stop(struct rtl8169_private *tp)
994 {
995 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
996
997 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
998 }
999
1000 static int r8168dp_check_dash(struct rtl8169_private *tp)
1001 {
1002 u16 reg = rtl8168_get_ocp_reg(tp);
1003
1004 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1005 }
1006
1007 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1008 {
1009 if (reg & 0xffff0001) {
1010 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1011 return true;
1012 }
1013 return false;
1014 }
1015
1016 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1017 {
1018 void __iomem *ioaddr = tp->mmio_addr;
1019
1020 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1021 }
1022
1023 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1024 {
1025 void __iomem *ioaddr = tp->mmio_addr;
1026
1027 if (rtl_ocp_reg_failure(tp, reg))
1028 return;
1029
1030 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1031
1032 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1033 }
1034
1035 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1036 {
1037 void __iomem *ioaddr = tp->mmio_addr;
1038
1039 if (rtl_ocp_reg_failure(tp, reg))
1040 return 0;
1041
1042 RTL_W32(GPHY_OCP, reg << 15);
1043
1044 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1045 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1046 }
1047
1048 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1049 {
1050 void __iomem *ioaddr = tp->mmio_addr;
1051
1052 if (rtl_ocp_reg_failure(tp, reg))
1053 return;
1054
1055 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1056 }
1057
1058 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1059 {
1060 void __iomem *ioaddr = tp->mmio_addr;
1061
1062 if (rtl_ocp_reg_failure(tp, reg))
1063 return 0;
1064
1065 RTL_W32(OCPDR, reg << 15);
1066
1067 return RTL_R32(OCPDR);
1068 }
1069
1070 #define OCP_STD_PHY_BASE 0xa400
1071
1072 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1073 {
1074 if (reg == 0x1f) {
1075 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1076 return;
1077 }
1078
1079 if (tp->ocp_base != OCP_STD_PHY_BASE)
1080 reg -= 0x10;
1081
1082 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1083 }
1084
1085 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1086 {
1087 if (tp->ocp_base != OCP_STD_PHY_BASE)
1088 reg -= 0x10;
1089
1090 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1091 }
1092
1093 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1094 {
1095 if (reg == 0x1f) {
1096 tp->ocp_base = value << 4;
1097 return;
1098 }
1099
1100 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1101 }
1102
1103 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1104 {
1105 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1106 }
1107
1108 DECLARE_RTL_COND(rtl_phyar_cond)
1109 {
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(PHYAR) & 0x80000000;
1113 }
1114
1115 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1116 {
1117 void __iomem *ioaddr = tp->mmio_addr;
1118
1119 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1120
1121 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1122 /*
1123 * According to hardware specs a 20us delay is required after write
1124 * complete indication, but before sending next command.
1125 */
1126 udelay(20);
1127 }
1128
1129 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1130 {
1131 void __iomem *ioaddr = tp->mmio_addr;
1132 int value;
1133
1134 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1135
1136 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1137 RTL_R32(PHYAR) & 0xffff : ~0;
1138
1139 /*
1140 * According to hardware specs a 20us delay is required after read
1141 * complete indication, but before sending next command.
1142 */
1143 udelay(20);
1144
1145 return value;
1146 }
1147
1148 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1149 {
1150 void __iomem *ioaddr = tp->mmio_addr;
1151
1152 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1153 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1154 RTL_W32(EPHY_RXER_NUM, 0);
1155
1156 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1157 }
1158
1159 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1160 {
1161 r8168dp_1_mdio_access(tp, reg,
1162 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1163 }
1164
1165 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1166 {
1167 void __iomem *ioaddr = tp->mmio_addr;
1168
1169 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1170
1171 mdelay(1);
1172 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1173 RTL_W32(EPHY_RXER_NUM, 0);
1174
1175 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1176 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1177 }
1178
1179 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1180
1181 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1182 {
1183 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1184 }
1185
1186 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1187 {
1188 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1189 }
1190
1191 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1192 {
1193 void __iomem *ioaddr = tp->mmio_addr;
1194
1195 r8168dp_2_mdio_start(ioaddr);
1196
1197 r8169_mdio_write(tp, reg, value);
1198
1199 r8168dp_2_mdio_stop(ioaddr);
1200 }
1201
1202 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1203 {
1204 void __iomem *ioaddr = tp->mmio_addr;
1205 int value;
1206
1207 r8168dp_2_mdio_start(ioaddr);
1208
1209 value = r8169_mdio_read(tp, reg);
1210
1211 r8168dp_2_mdio_stop(ioaddr);
1212
1213 return value;
1214 }
1215
1216 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1217 {
1218 tp->mdio_ops.write(tp, location, val);
1219 }
1220
1221 static int rtl_readphy(struct rtl8169_private *tp, int location)
1222 {
1223 return tp->mdio_ops.read(tp, location);
1224 }
1225
1226 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1227 {
1228 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1229 }
1230
1231 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1232 {
1233 int val;
1234
1235 val = rtl_readphy(tp, reg_addr);
1236 rtl_writephy(tp, reg_addr, (val | p) & ~m);
1237 }
1238
1239 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1240 int val)
1241 {
1242 struct rtl8169_private *tp = netdev_priv(dev);
1243
1244 rtl_writephy(tp, location, val);
1245 }
1246
1247 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1248 {
1249 struct rtl8169_private *tp = netdev_priv(dev);
1250
1251 return rtl_readphy(tp, location);
1252 }
1253
1254 DECLARE_RTL_COND(rtl_ephyar_cond)
1255 {
1256 void __iomem *ioaddr = tp->mmio_addr;
1257
1258 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1259 }
1260
1261 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1262 {
1263 void __iomem *ioaddr = tp->mmio_addr;
1264
1265 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1266 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1267
1268 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1269
1270 udelay(10);
1271 }
1272
1273 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1274 {
1275 void __iomem *ioaddr = tp->mmio_addr;
1276
1277 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1278
1279 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1280 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1281 }
1282
1283 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1284 u32 val, int type)
1285 {
1286 void __iomem *ioaddr = tp->mmio_addr;
1287
1288 BUG_ON((addr & 3) || (mask == 0));
1289 RTL_W32(ERIDR, val);
1290 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1291
1292 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1293 }
1294
1295 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1296 {
1297 void __iomem *ioaddr = tp->mmio_addr;
1298
1299 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1300
1301 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1302 RTL_R32(ERIDR) : ~0;
1303 }
1304
1305 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1306 u32 m, int type)
1307 {
1308 u32 val;
1309
1310 val = rtl_eri_read(tp, addr, type);
1311 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1312 }
1313
1314 struct exgmac_reg {
1315 u16 addr;
1316 u16 mask;
1317 u32 val;
1318 };
1319
1320 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1321 const struct exgmac_reg *r, int len)
1322 {
1323 while (len-- > 0) {
1324 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1325 r++;
1326 }
1327 }
1328
1329 DECLARE_RTL_COND(rtl_efusear_cond)
1330 {
1331 void __iomem *ioaddr = tp->mmio_addr;
1332
1333 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1334 }
1335
1336 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1337 {
1338 void __iomem *ioaddr = tp->mmio_addr;
1339
1340 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1341
1342 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1343 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1344 }
1345
1346 static u16 rtl_get_events(struct rtl8169_private *tp)
1347 {
1348 void __iomem *ioaddr = tp->mmio_addr;
1349
1350 return RTL_R16(IntrStatus);
1351 }
1352
1353 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1354 {
1355 void __iomem *ioaddr = tp->mmio_addr;
1356
1357 RTL_W16(IntrStatus, bits);
1358 mmiowb();
1359 }
1360
1361 static void rtl_irq_disable(struct rtl8169_private *tp)
1362 {
1363 void __iomem *ioaddr = tp->mmio_addr;
1364
1365 RTL_W16(IntrMask, 0);
1366 mmiowb();
1367 }
1368
1369 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1370 {
1371 void __iomem *ioaddr = tp->mmio_addr;
1372
1373 RTL_W16(IntrMask, bits);
1374 }
1375
1376 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1377 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1378 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1379
1380 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1381 {
1382 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1383 }
1384
1385 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1386 {
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 rtl_irq_disable(tp);
1390 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1391 RTL_R8(ChipCmd);
1392 }
1393
1394 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1395 {
1396 void __iomem *ioaddr = tp->mmio_addr;
1397
1398 return RTL_R32(TBICSR) & TBIReset;
1399 }
1400
1401 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1402 {
1403 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1404 }
1405
1406 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1407 {
1408 return RTL_R32(TBICSR) & TBILinkOk;
1409 }
1410
1411 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1412 {
1413 return RTL_R8(PHYstatus) & LinkStatus;
1414 }
1415
1416 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1417 {
1418 void __iomem *ioaddr = tp->mmio_addr;
1419
1420 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1421 }
1422
1423 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1424 {
1425 unsigned int val;
1426
1427 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1428 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1429 }
1430
1431 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1432 {
1433 void __iomem *ioaddr = tp->mmio_addr;
1434 struct net_device *dev = tp->dev;
1435
1436 if (!netif_running(dev))
1437 return;
1438
1439 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1440 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1441 if (RTL_R8(PHYstatus) & _1000bpsF) {
1442 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443 ERIAR_EXGMAC);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445 ERIAR_EXGMAC);
1446 } else if (RTL_R8(PHYstatus) & _100bps) {
1447 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448 ERIAR_EXGMAC);
1449 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1450 ERIAR_EXGMAC);
1451 } else {
1452 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1453 ERIAR_EXGMAC);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1455 ERIAR_EXGMAC);
1456 }
1457 /* Reset packet filter */
1458 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1459 ERIAR_EXGMAC);
1460 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1461 ERIAR_EXGMAC);
1462 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1463 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1464 if (RTL_R8(PHYstatus) & _1000bpsF) {
1465 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1466 ERIAR_EXGMAC);
1467 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1468 ERIAR_EXGMAC);
1469 } else {
1470 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1471 ERIAR_EXGMAC);
1472 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1473 ERIAR_EXGMAC);
1474 }
1475 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1476 if (RTL_R8(PHYstatus) & _10bps) {
1477 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1478 ERIAR_EXGMAC);
1479 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1480 ERIAR_EXGMAC);
1481 } else {
1482 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1483 ERIAR_EXGMAC);
1484 }
1485 }
1486 }
1487
1488 static void __rtl8169_check_link_status(struct net_device *dev,
1489 struct rtl8169_private *tp,
1490 void __iomem *ioaddr, bool pm)
1491 {
1492 if (tp->link_ok(ioaddr)) {
1493 rtl_link_chg_patch(tp);
1494 /* This is to cancel a scheduled suspend if there's one. */
1495 if (pm)
1496 pm_request_resume(&tp->pci_dev->dev);
1497 netif_carrier_on(dev);
1498 if (net_ratelimit())
1499 netif_info(tp, ifup, dev, "link up\n");
1500 } else {
1501 netif_carrier_off(dev);
1502 netif_info(tp, ifdown, dev, "link down\n");
1503 if (pm)
1504 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1505 }
1506 }
1507
1508 static void rtl8169_check_link_status(struct net_device *dev,
1509 struct rtl8169_private *tp,
1510 void __iomem *ioaddr)
1511 {
1512 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1513 }
1514
1515 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1516
1517 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1518 {
1519 void __iomem *ioaddr = tp->mmio_addr;
1520 u8 options;
1521 u32 wolopts = 0;
1522
1523 options = RTL_R8(Config1);
1524 if (!(options & PMEnable))
1525 return 0;
1526
1527 options = RTL_R8(Config3);
1528 if (options & LinkUp)
1529 wolopts |= WAKE_PHY;
1530 if (options & MagicPacket)
1531 wolopts |= WAKE_MAGIC;
1532
1533 options = RTL_R8(Config5);
1534 if (options & UWF)
1535 wolopts |= WAKE_UCAST;
1536 if (options & BWF)
1537 wolopts |= WAKE_BCAST;
1538 if (options & MWF)
1539 wolopts |= WAKE_MCAST;
1540
1541 return wolopts;
1542 }
1543
1544 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1545 {
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547
1548 rtl_lock_work(tp);
1549
1550 wol->supported = WAKE_ANY;
1551 wol->wolopts = __rtl8169_get_wol(tp);
1552
1553 rtl_unlock_work(tp);
1554 }
1555
1556 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1557 {
1558 void __iomem *ioaddr = tp->mmio_addr;
1559 unsigned int i;
1560 static const struct {
1561 u32 opt;
1562 u16 reg;
1563 u8 mask;
1564 } cfg[] = {
1565 { WAKE_PHY, Config3, LinkUp },
1566 { WAKE_MAGIC, Config3, MagicPacket },
1567 { WAKE_UCAST, Config5, UWF },
1568 { WAKE_BCAST, Config5, BWF },
1569 { WAKE_MCAST, Config5, MWF },
1570 { WAKE_ANY, Config5, LanWake }
1571 };
1572 u8 options;
1573
1574 RTL_W8(Cfg9346, Cfg9346_Unlock);
1575
1576 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1577 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1578 if (wolopts & cfg[i].opt)
1579 options |= cfg[i].mask;
1580 RTL_W8(cfg[i].reg, options);
1581 }
1582
1583 switch (tp->mac_version) {
1584 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1585 options = RTL_R8(Config1) & ~PMEnable;
1586 if (wolopts)
1587 options |= PMEnable;
1588 RTL_W8(Config1, options);
1589 break;
1590 default:
1591 options = RTL_R8(Config2) & ~PME_SIGNAL;
1592 if (wolopts)
1593 options |= PME_SIGNAL;
1594 RTL_W8(Config2, options);
1595 break;
1596 }
1597
1598 RTL_W8(Cfg9346, Cfg9346_Lock);
1599 }
1600
1601 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1602 {
1603 struct rtl8169_private *tp = netdev_priv(dev);
1604
1605 rtl_lock_work(tp);
1606
1607 if (wol->wolopts)
1608 tp->features |= RTL_FEATURE_WOL;
1609 else
1610 tp->features &= ~RTL_FEATURE_WOL;
1611 __rtl8169_set_wol(tp, wol->wolopts);
1612
1613 rtl_unlock_work(tp);
1614
1615 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1616
1617 return 0;
1618 }
1619
1620 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1621 {
1622 return rtl_chip_infos[tp->mac_version].fw_name;
1623 }
1624
1625 static void rtl8169_get_drvinfo(struct net_device *dev,
1626 struct ethtool_drvinfo *info)
1627 {
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 struct rtl_fw *rtl_fw = tp->rtl_fw;
1630
1631 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1632 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1633 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1634 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1635 if (!IS_ERR_OR_NULL(rtl_fw))
1636 strlcpy(info->fw_version, rtl_fw->version,
1637 sizeof(info->fw_version));
1638 }
1639
1640 static int rtl8169_get_regs_len(struct net_device *dev)
1641 {
1642 return R8169_REGS_SIZE;
1643 }
1644
1645 static int rtl8169_set_speed_tbi(struct net_device *dev,
1646 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1647 {
1648 struct rtl8169_private *tp = netdev_priv(dev);
1649 void __iomem *ioaddr = tp->mmio_addr;
1650 int ret = 0;
1651 u32 reg;
1652
1653 reg = RTL_R32(TBICSR);
1654 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1655 (duplex == DUPLEX_FULL)) {
1656 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1657 } else if (autoneg == AUTONEG_ENABLE)
1658 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1659 else {
1660 netif_warn(tp, link, dev,
1661 "incorrect speed setting refused in TBI mode\n");
1662 ret = -EOPNOTSUPP;
1663 }
1664
1665 return ret;
1666 }
1667
1668 static int rtl8169_set_speed_xmii(struct net_device *dev,
1669 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1670 {
1671 struct rtl8169_private *tp = netdev_priv(dev);
1672 int giga_ctrl, bmcr;
1673 int rc = -EINVAL;
1674
1675 rtl_writephy(tp, 0x1f, 0x0000);
1676
1677 if (autoneg == AUTONEG_ENABLE) {
1678 int auto_nego;
1679
1680 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1681 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1682 ADVERTISE_100HALF | ADVERTISE_100FULL);
1683
1684 if (adv & ADVERTISED_10baseT_Half)
1685 auto_nego |= ADVERTISE_10HALF;
1686 if (adv & ADVERTISED_10baseT_Full)
1687 auto_nego |= ADVERTISE_10FULL;
1688 if (adv & ADVERTISED_100baseT_Half)
1689 auto_nego |= ADVERTISE_100HALF;
1690 if (adv & ADVERTISED_100baseT_Full)
1691 auto_nego |= ADVERTISE_100FULL;
1692
1693 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1694
1695 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1696 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1697
1698 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1699 if (tp->mii.supports_gmii) {
1700 if (adv & ADVERTISED_1000baseT_Half)
1701 giga_ctrl |= ADVERTISE_1000HALF;
1702 if (adv & ADVERTISED_1000baseT_Full)
1703 giga_ctrl |= ADVERTISE_1000FULL;
1704 } else if (adv & (ADVERTISED_1000baseT_Half |
1705 ADVERTISED_1000baseT_Full)) {
1706 netif_info(tp, link, dev,
1707 "PHY does not support 1000Mbps\n");
1708 goto out;
1709 }
1710
1711 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1712
1713 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1714 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1715 } else {
1716 giga_ctrl = 0;
1717
1718 if (speed == SPEED_10)
1719 bmcr = 0;
1720 else if (speed == SPEED_100)
1721 bmcr = BMCR_SPEED100;
1722 else
1723 goto out;
1724
1725 if (duplex == DUPLEX_FULL)
1726 bmcr |= BMCR_FULLDPLX;
1727 }
1728
1729 rtl_writephy(tp, MII_BMCR, bmcr);
1730
1731 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1732 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1733 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1734 rtl_writephy(tp, 0x17, 0x2138);
1735 rtl_writephy(tp, 0x0e, 0x0260);
1736 } else {
1737 rtl_writephy(tp, 0x17, 0x2108);
1738 rtl_writephy(tp, 0x0e, 0x0000);
1739 }
1740 }
1741
1742 rc = 0;
1743 out:
1744 return rc;
1745 }
1746
1747 static int rtl8169_set_speed(struct net_device *dev,
1748 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1749 {
1750 struct rtl8169_private *tp = netdev_priv(dev);
1751 int ret;
1752
1753 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1754 if (ret < 0)
1755 goto out;
1756
1757 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1758 (advertising & ADVERTISED_1000baseT_Full)) {
1759 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1760 }
1761 out:
1762 return ret;
1763 }
1764
1765 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1766 {
1767 struct rtl8169_private *tp = netdev_priv(dev);
1768 int ret;
1769
1770 del_timer_sync(&tp->timer);
1771
1772 rtl_lock_work(tp);
1773 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1774 cmd->duplex, cmd->advertising);
1775 rtl_unlock_work(tp);
1776
1777 return ret;
1778 }
1779
1780 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1781 netdev_features_t features)
1782 {
1783 struct rtl8169_private *tp = netdev_priv(dev);
1784
1785 if (dev->mtu > TD_MSS_MAX)
1786 features &= ~NETIF_F_ALL_TSO;
1787
1788 if (dev->mtu > JUMBO_1K &&
1789 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1790 features &= ~NETIF_F_IP_CSUM;
1791
1792 return features;
1793 }
1794
1795 static void __rtl8169_set_features(struct net_device *dev,
1796 netdev_features_t features)
1797 {
1798 struct rtl8169_private *tp = netdev_priv(dev);
1799 netdev_features_t changed = features ^ dev->features;
1800 void __iomem *ioaddr = tp->mmio_addr;
1801
1802 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1803 NETIF_F_HW_VLAN_CTAG_RX)))
1804 return;
1805
1806 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1807 if (features & NETIF_F_RXCSUM)
1808 tp->cp_cmd |= RxChkSum;
1809 else
1810 tp->cp_cmd &= ~RxChkSum;
1811
1812 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1813 tp->cp_cmd |= RxVlan;
1814 else
1815 tp->cp_cmd &= ~RxVlan;
1816
1817 RTL_W16(CPlusCmd, tp->cp_cmd);
1818 RTL_R16(CPlusCmd);
1819 }
1820 if (changed & NETIF_F_RXALL) {
1821 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1822 if (features & NETIF_F_RXALL)
1823 tmp |= (AcceptErr | AcceptRunt);
1824 RTL_W32(RxConfig, tmp);
1825 }
1826 }
1827
1828 static int rtl8169_set_features(struct net_device *dev,
1829 netdev_features_t features)
1830 {
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832
1833 rtl_lock_work(tp);
1834 __rtl8169_set_features(dev, features);
1835 rtl_unlock_work(tp);
1836
1837 return 0;
1838 }
1839
1840
1841 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1842 {
1843 return (vlan_tx_tag_present(skb)) ?
1844 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1845 }
1846
1847 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1848 {
1849 u32 opts2 = le32_to_cpu(desc->opts2);
1850
1851 if (opts2 & RxVlanTag)
1852 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1853 }
1854
1855 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1856 {
1857 struct rtl8169_private *tp = netdev_priv(dev);
1858 void __iomem *ioaddr = tp->mmio_addr;
1859 u32 status;
1860
1861 cmd->supported =
1862 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1863 cmd->port = PORT_FIBRE;
1864 cmd->transceiver = XCVR_INTERNAL;
1865
1866 status = RTL_R32(TBICSR);
1867 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1868 cmd->autoneg = !!(status & TBINwEnable);
1869
1870 ethtool_cmd_speed_set(cmd, SPEED_1000);
1871 cmd->duplex = DUPLEX_FULL; /* Always set */
1872
1873 return 0;
1874 }
1875
1876 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1877 {
1878 struct rtl8169_private *tp = netdev_priv(dev);
1879
1880 return mii_ethtool_gset(&tp->mii, cmd);
1881 }
1882
1883 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1884 {
1885 struct rtl8169_private *tp = netdev_priv(dev);
1886 int rc;
1887
1888 rtl_lock_work(tp);
1889 rc = tp->get_settings(dev, cmd);
1890 rtl_unlock_work(tp);
1891
1892 return rc;
1893 }
1894
1895 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1896 void *p)
1897 {
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899 u32 __iomem *data = tp->mmio_addr;
1900 u32 *dw = p;
1901 int i;
1902
1903 rtl_lock_work(tp);
1904 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1905 memcpy_fromio(dw++, data++, 4);
1906 rtl_unlock_work(tp);
1907 }
1908
1909 static u32 rtl8169_get_msglevel(struct net_device *dev)
1910 {
1911 struct rtl8169_private *tp = netdev_priv(dev);
1912
1913 return tp->msg_enable;
1914 }
1915
1916 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1917 {
1918 struct rtl8169_private *tp = netdev_priv(dev);
1919
1920 tp->msg_enable = value;
1921 }
1922
1923 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1924 "tx_packets",
1925 "rx_packets",
1926 "tx_errors",
1927 "rx_errors",
1928 "rx_missed",
1929 "align_errors",
1930 "tx_single_collisions",
1931 "tx_multi_collisions",
1932 "unicast",
1933 "broadcast",
1934 "multicast",
1935 "tx_aborted",
1936 "tx_underrun",
1937 };
1938
1939 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1940 {
1941 switch (sset) {
1942 case ETH_SS_STATS:
1943 return ARRAY_SIZE(rtl8169_gstrings);
1944 default:
1945 return -EOPNOTSUPP;
1946 }
1947 }
1948
1949 DECLARE_RTL_COND(rtl_counters_cond)
1950 {
1951 void __iomem *ioaddr = tp->mmio_addr;
1952
1953 return RTL_R32(CounterAddrLow) & CounterDump;
1954 }
1955
1956 static void rtl8169_update_counters(struct net_device *dev)
1957 {
1958 struct rtl8169_private *tp = netdev_priv(dev);
1959 void __iomem *ioaddr = tp->mmio_addr;
1960 struct device *d = &tp->pci_dev->dev;
1961 struct rtl8169_counters *counters;
1962 dma_addr_t paddr;
1963 u32 cmd;
1964
1965 /*
1966 * Some chips are unable to dump tally counters when the receiver
1967 * is disabled.
1968 */
1969 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1970 return;
1971
1972 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1973 if (!counters)
1974 return;
1975
1976 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1977 cmd = (u64)paddr & DMA_BIT_MASK(32);
1978 RTL_W32(CounterAddrLow, cmd);
1979 RTL_W32(CounterAddrLow, cmd | CounterDump);
1980
1981 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1982 memcpy(&tp->counters, counters, sizeof(*counters));
1983
1984 RTL_W32(CounterAddrLow, 0);
1985 RTL_W32(CounterAddrHigh, 0);
1986
1987 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1988 }
1989
1990 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1991 struct ethtool_stats *stats, u64 *data)
1992 {
1993 struct rtl8169_private *tp = netdev_priv(dev);
1994
1995 ASSERT_RTNL();
1996
1997 rtl8169_update_counters(dev);
1998
1999 data[0] = le64_to_cpu(tp->counters.tx_packets);
2000 data[1] = le64_to_cpu(tp->counters.rx_packets);
2001 data[2] = le64_to_cpu(tp->counters.tx_errors);
2002 data[3] = le32_to_cpu(tp->counters.rx_errors);
2003 data[4] = le16_to_cpu(tp->counters.rx_missed);
2004 data[5] = le16_to_cpu(tp->counters.align_errors);
2005 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2006 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2007 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2008 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2009 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2010 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2011 data[12] = le16_to_cpu(tp->counters.tx_underun);
2012 }
2013
2014 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2015 {
2016 switch(stringset) {
2017 case ETH_SS_STATS:
2018 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2019 break;
2020 }
2021 }
2022
2023 static const struct ethtool_ops rtl8169_ethtool_ops = {
2024 .get_drvinfo = rtl8169_get_drvinfo,
2025 .get_regs_len = rtl8169_get_regs_len,
2026 .get_link = ethtool_op_get_link,
2027 .get_settings = rtl8169_get_settings,
2028 .set_settings = rtl8169_set_settings,
2029 .get_msglevel = rtl8169_get_msglevel,
2030 .set_msglevel = rtl8169_set_msglevel,
2031 .get_regs = rtl8169_get_regs,
2032 .get_wol = rtl8169_get_wol,
2033 .set_wol = rtl8169_set_wol,
2034 .get_strings = rtl8169_get_strings,
2035 .get_sset_count = rtl8169_get_sset_count,
2036 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2037 .get_ts_info = ethtool_op_get_ts_info,
2038 };
2039
2040 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2041 struct net_device *dev, u8 default_version)
2042 {
2043 void __iomem *ioaddr = tp->mmio_addr;
2044 /*
2045 * The driver currently handles the 8168Bf and the 8168Be identically
2046 * but they can be identified more specifically through the test below
2047 * if needed:
2048 *
2049 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2050 *
2051 * Same thing for the 8101Eb and the 8101Ec:
2052 *
2053 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2054 */
2055 static const struct rtl_mac_info {
2056 u32 mask;
2057 u32 val;
2058 int mac_version;
2059 } mac_info[] = {
2060 /* 8168G family. */
2061 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2062 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2063 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2064 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2065
2066 /* 8168F family. */
2067 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2068 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2069 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2070
2071 /* 8168E family. */
2072 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2073 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2074 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2075 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2076
2077 /* 8168D family. */
2078 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2079 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2080 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2081
2082 /* 8168DP family. */
2083 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2084 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2085 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2086
2087 /* 8168C family. */
2088 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2089 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2090 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2091 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2092 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2093 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2094 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2095 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2096 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2097
2098 /* 8168B family. */
2099 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2100 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2101 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2102 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2103
2104 /* 8101 family. */
2105 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2106 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2107 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2108 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2109 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2110 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2111 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2112 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2113 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2115 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2116 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2117 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2118 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2119 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2120 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2121 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2122 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2123 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2124 /* FIXME: where did these entries come from ? -- FR */
2125 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2126 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2127
2128 /* 8110 family. */
2129 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2130 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2131 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2132 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2133 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2134 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2135
2136 /* Catch-all */
2137 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2138 };
2139 const struct rtl_mac_info *p = mac_info;
2140 u32 reg;
2141
2142 reg = RTL_R32(TxConfig);
2143 while ((reg & p->mask) != p->val)
2144 p++;
2145 tp->mac_version = p->mac_version;
2146
2147 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2148 netif_notice(tp, probe, dev,
2149 "unknown MAC, using family default\n");
2150 tp->mac_version = default_version;
2151 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2152 tp->mac_version = tp->mii.supports_gmii ?
2153 RTL_GIGA_MAC_VER_42 :
2154 RTL_GIGA_MAC_VER_43;
2155 }
2156 }
2157
2158 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2159 {
2160 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2161 }
2162
2163 struct phy_reg {
2164 u16 reg;
2165 u16 val;
2166 };
2167
2168 static void rtl_writephy_batch(struct rtl8169_private *tp,
2169 const struct phy_reg *regs, int len)
2170 {
2171 while (len-- > 0) {
2172 rtl_writephy(tp, regs->reg, regs->val);
2173 regs++;
2174 }
2175 }
2176
2177 #define PHY_READ 0x00000000
2178 #define PHY_DATA_OR 0x10000000
2179 #define PHY_DATA_AND 0x20000000
2180 #define PHY_BJMPN 0x30000000
2181 #define PHY_MDIO_CHG 0x40000000
2182 #define PHY_CLEAR_READCOUNT 0x70000000
2183 #define PHY_WRITE 0x80000000
2184 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2185 #define PHY_COMP_EQ_SKIPN 0xa0000000
2186 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2187 #define PHY_WRITE_PREVIOUS 0xc0000000
2188 #define PHY_SKIPN 0xd0000000
2189 #define PHY_DELAY_MS 0xe0000000
2190
2191 struct fw_info {
2192 u32 magic;
2193 char version[RTL_VER_SIZE];
2194 __le32 fw_start;
2195 __le32 fw_len;
2196 u8 chksum;
2197 } __packed;
2198
2199 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2200
2201 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2202 {
2203 const struct firmware *fw = rtl_fw->fw;
2204 struct fw_info *fw_info = (struct fw_info *)fw->data;
2205 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2206 char *version = rtl_fw->version;
2207 bool rc = false;
2208
2209 if (fw->size < FW_OPCODE_SIZE)
2210 goto out;
2211
2212 if (!fw_info->magic) {
2213 size_t i, size, start;
2214 u8 checksum = 0;
2215
2216 if (fw->size < sizeof(*fw_info))
2217 goto out;
2218
2219 for (i = 0; i < fw->size; i++)
2220 checksum += fw->data[i];
2221 if (checksum != 0)
2222 goto out;
2223
2224 start = le32_to_cpu(fw_info->fw_start);
2225 if (start > fw->size)
2226 goto out;
2227
2228 size = le32_to_cpu(fw_info->fw_len);
2229 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2230 goto out;
2231
2232 memcpy(version, fw_info->version, RTL_VER_SIZE);
2233
2234 pa->code = (__le32 *)(fw->data + start);
2235 pa->size = size;
2236 } else {
2237 if (fw->size % FW_OPCODE_SIZE)
2238 goto out;
2239
2240 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2241
2242 pa->code = (__le32 *)fw->data;
2243 pa->size = fw->size / FW_OPCODE_SIZE;
2244 }
2245 version[RTL_VER_SIZE - 1] = 0;
2246
2247 rc = true;
2248 out:
2249 return rc;
2250 }
2251
2252 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2253 struct rtl_fw_phy_action *pa)
2254 {
2255 bool rc = false;
2256 size_t index;
2257
2258 for (index = 0; index < pa->size; index++) {
2259 u32 action = le32_to_cpu(pa->code[index]);
2260 u32 regno = (action & 0x0fff0000) >> 16;
2261
2262 switch(action & 0xf0000000) {
2263 case PHY_READ:
2264 case PHY_DATA_OR:
2265 case PHY_DATA_AND:
2266 case PHY_MDIO_CHG:
2267 case PHY_CLEAR_READCOUNT:
2268 case PHY_WRITE:
2269 case PHY_WRITE_PREVIOUS:
2270 case PHY_DELAY_MS:
2271 break;
2272
2273 case PHY_BJMPN:
2274 if (regno > index) {
2275 netif_err(tp, ifup, tp->dev,
2276 "Out of range of firmware\n");
2277 goto out;
2278 }
2279 break;
2280 case PHY_READCOUNT_EQ_SKIP:
2281 if (index + 2 >= pa->size) {
2282 netif_err(tp, ifup, tp->dev,
2283 "Out of range of firmware\n");
2284 goto out;
2285 }
2286 break;
2287 case PHY_COMP_EQ_SKIPN:
2288 case PHY_COMP_NEQ_SKIPN:
2289 case PHY_SKIPN:
2290 if (index + 1 + regno >= pa->size) {
2291 netif_err(tp, ifup, tp->dev,
2292 "Out of range of firmware\n");
2293 goto out;
2294 }
2295 break;
2296
2297 default:
2298 netif_err(tp, ifup, tp->dev,
2299 "Invalid action 0x%08x\n", action);
2300 goto out;
2301 }
2302 }
2303 rc = true;
2304 out:
2305 return rc;
2306 }
2307
2308 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2309 {
2310 struct net_device *dev = tp->dev;
2311 int rc = -EINVAL;
2312
2313 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2314 netif_err(tp, ifup, dev, "invalid firwmare\n");
2315 goto out;
2316 }
2317
2318 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2319 rc = 0;
2320 out:
2321 return rc;
2322 }
2323
2324 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2325 {
2326 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2327 struct mdio_ops org, *ops = &tp->mdio_ops;
2328 u32 predata, count;
2329 size_t index;
2330
2331 predata = count = 0;
2332 org.write = ops->write;
2333 org.read = ops->read;
2334
2335 for (index = 0; index < pa->size; ) {
2336 u32 action = le32_to_cpu(pa->code[index]);
2337 u32 data = action & 0x0000ffff;
2338 u32 regno = (action & 0x0fff0000) >> 16;
2339
2340 if (!action)
2341 break;
2342
2343 switch(action & 0xf0000000) {
2344 case PHY_READ:
2345 predata = rtl_readphy(tp, regno);
2346 count++;
2347 index++;
2348 break;
2349 case PHY_DATA_OR:
2350 predata |= data;
2351 index++;
2352 break;
2353 case PHY_DATA_AND:
2354 predata &= data;
2355 index++;
2356 break;
2357 case PHY_BJMPN:
2358 index -= regno;
2359 break;
2360 case PHY_MDIO_CHG:
2361 if (data == 0) {
2362 ops->write = org.write;
2363 ops->read = org.read;
2364 } else if (data == 1) {
2365 ops->write = mac_mcu_write;
2366 ops->read = mac_mcu_read;
2367 }
2368
2369 index++;
2370 break;
2371 case PHY_CLEAR_READCOUNT:
2372 count = 0;
2373 index++;
2374 break;
2375 case PHY_WRITE:
2376 rtl_writephy(tp, regno, data);
2377 index++;
2378 break;
2379 case PHY_READCOUNT_EQ_SKIP:
2380 index += (count == data) ? 2 : 1;
2381 break;
2382 case PHY_COMP_EQ_SKIPN:
2383 if (predata == data)
2384 index += regno;
2385 index++;
2386 break;
2387 case PHY_COMP_NEQ_SKIPN:
2388 if (predata != data)
2389 index += regno;
2390 index++;
2391 break;
2392 case PHY_WRITE_PREVIOUS:
2393 rtl_writephy(tp, regno, predata);
2394 index++;
2395 break;
2396 case PHY_SKIPN:
2397 index += regno + 1;
2398 break;
2399 case PHY_DELAY_MS:
2400 mdelay(data);
2401 index++;
2402 break;
2403
2404 default:
2405 BUG();
2406 }
2407 }
2408
2409 ops->write = org.write;
2410 ops->read = org.read;
2411 }
2412
2413 static void rtl_release_firmware(struct rtl8169_private *tp)
2414 {
2415 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2416 release_firmware(tp->rtl_fw->fw);
2417 kfree(tp->rtl_fw);
2418 }
2419 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2420 }
2421
2422 static void rtl_apply_firmware(struct rtl8169_private *tp)
2423 {
2424 struct rtl_fw *rtl_fw = tp->rtl_fw;
2425
2426 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2427 if (!IS_ERR_OR_NULL(rtl_fw))
2428 rtl_phy_write_fw(tp, rtl_fw);
2429 }
2430
2431 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2432 {
2433 if (rtl_readphy(tp, reg) != val)
2434 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2435 else
2436 rtl_apply_firmware(tp);
2437 }
2438
2439 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2440 {
2441 static const struct phy_reg phy_reg_init[] = {
2442 { 0x1f, 0x0001 },
2443 { 0x06, 0x006e },
2444 { 0x08, 0x0708 },
2445 { 0x15, 0x4000 },
2446 { 0x18, 0x65c7 },
2447
2448 { 0x1f, 0x0001 },
2449 { 0x03, 0x00a1 },
2450 { 0x02, 0x0008 },
2451 { 0x01, 0x0120 },
2452 { 0x00, 0x1000 },
2453 { 0x04, 0x0800 },
2454 { 0x04, 0x0000 },
2455
2456 { 0x03, 0xff41 },
2457 { 0x02, 0xdf60 },
2458 { 0x01, 0x0140 },
2459 { 0x00, 0x0077 },
2460 { 0x04, 0x7800 },
2461 { 0x04, 0x7000 },
2462
2463 { 0x03, 0x802f },
2464 { 0x02, 0x4f02 },
2465 { 0x01, 0x0409 },
2466 { 0x00, 0xf0f9 },
2467 { 0x04, 0x9800 },
2468 { 0x04, 0x9000 },
2469
2470 { 0x03, 0xdf01 },
2471 { 0x02, 0xdf20 },
2472 { 0x01, 0xff95 },
2473 { 0x00, 0xba00 },
2474 { 0x04, 0xa800 },
2475 { 0x04, 0xa000 },
2476
2477 { 0x03, 0xff41 },
2478 { 0x02, 0xdf20 },
2479 { 0x01, 0x0140 },
2480 { 0x00, 0x00bb },
2481 { 0x04, 0xb800 },
2482 { 0x04, 0xb000 },
2483
2484 { 0x03, 0xdf41 },
2485 { 0x02, 0xdc60 },
2486 { 0x01, 0x6340 },
2487 { 0x00, 0x007d },
2488 { 0x04, 0xd800 },
2489 { 0x04, 0xd000 },
2490
2491 { 0x03, 0xdf01 },
2492 { 0x02, 0xdf20 },
2493 { 0x01, 0x100a },
2494 { 0x00, 0xa0ff },
2495 { 0x04, 0xf800 },
2496 { 0x04, 0xf000 },
2497
2498 { 0x1f, 0x0000 },
2499 { 0x0b, 0x0000 },
2500 { 0x00, 0x9200 }
2501 };
2502
2503 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504 }
2505
2506 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2507 {
2508 static const struct phy_reg phy_reg_init[] = {
2509 { 0x1f, 0x0002 },
2510 { 0x01, 0x90d0 },
2511 { 0x1f, 0x0000 }
2512 };
2513
2514 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2515 }
2516
2517 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2518 {
2519 struct pci_dev *pdev = tp->pci_dev;
2520
2521 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2522 (pdev->subsystem_device != 0xe000))
2523 return;
2524
2525 rtl_writephy(tp, 0x1f, 0x0001);
2526 rtl_writephy(tp, 0x10, 0xf01b);
2527 rtl_writephy(tp, 0x1f, 0x0000);
2528 }
2529
2530 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2531 {
2532 static const struct phy_reg phy_reg_init[] = {
2533 { 0x1f, 0x0001 },
2534 { 0x04, 0x0000 },
2535 { 0x03, 0x00a1 },
2536 { 0x02, 0x0008 },
2537 { 0x01, 0x0120 },
2538 { 0x00, 0x1000 },
2539 { 0x04, 0x0800 },
2540 { 0x04, 0x9000 },
2541 { 0x03, 0x802f },
2542 { 0x02, 0x4f02 },
2543 { 0x01, 0x0409 },
2544 { 0x00, 0xf099 },
2545 { 0x04, 0x9800 },
2546 { 0x04, 0xa000 },
2547 { 0x03, 0xdf01 },
2548 { 0x02, 0xdf20 },
2549 { 0x01, 0xff95 },
2550 { 0x00, 0xba00 },
2551 { 0x04, 0xa800 },
2552 { 0x04, 0xf000 },
2553 { 0x03, 0xdf01 },
2554 { 0x02, 0xdf20 },
2555 { 0x01, 0x101a },
2556 { 0x00, 0xa0ff },
2557 { 0x04, 0xf800 },
2558 { 0x04, 0x0000 },
2559 { 0x1f, 0x0000 },
2560
2561 { 0x1f, 0x0001 },
2562 { 0x10, 0xf41b },
2563 { 0x14, 0xfb54 },
2564 { 0x18, 0xf5c7 },
2565 { 0x1f, 0x0000 },
2566
2567 { 0x1f, 0x0001 },
2568 { 0x17, 0x0cc0 },
2569 { 0x1f, 0x0000 }
2570 };
2571
2572 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2573
2574 rtl8169scd_hw_phy_config_quirk(tp);
2575 }
2576
2577 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579 static const struct phy_reg phy_reg_init[] = {
2580 { 0x1f, 0x0001 },
2581 { 0x04, 0x0000 },
2582 { 0x03, 0x00a1 },
2583 { 0x02, 0x0008 },
2584 { 0x01, 0x0120 },
2585 { 0x00, 0x1000 },
2586 { 0x04, 0x0800 },
2587 { 0x04, 0x9000 },
2588 { 0x03, 0x802f },
2589 { 0x02, 0x4f02 },
2590 { 0x01, 0x0409 },
2591 { 0x00, 0xf099 },
2592 { 0x04, 0x9800 },
2593 { 0x04, 0xa000 },
2594 { 0x03, 0xdf01 },
2595 { 0x02, 0xdf20 },
2596 { 0x01, 0xff95 },
2597 { 0x00, 0xba00 },
2598 { 0x04, 0xa800 },
2599 { 0x04, 0xf000 },
2600 { 0x03, 0xdf01 },
2601 { 0x02, 0xdf20 },
2602 { 0x01, 0x101a },
2603 { 0x00, 0xa0ff },
2604 { 0x04, 0xf800 },
2605 { 0x04, 0x0000 },
2606 { 0x1f, 0x0000 },
2607
2608 { 0x1f, 0x0001 },
2609 { 0x0b, 0x8480 },
2610 { 0x1f, 0x0000 },
2611
2612 { 0x1f, 0x0001 },
2613 { 0x18, 0x67c7 },
2614 { 0x04, 0x2000 },
2615 { 0x03, 0x002f },
2616 { 0x02, 0x4360 },
2617 { 0x01, 0x0109 },
2618 { 0x00, 0x3022 },
2619 { 0x04, 0x2800 },
2620 { 0x1f, 0x0000 },
2621
2622 { 0x1f, 0x0001 },
2623 { 0x17, 0x0cc0 },
2624 { 0x1f, 0x0000 }
2625 };
2626
2627 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2628 }
2629
2630 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2631 {
2632 static const struct phy_reg phy_reg_init[] = {
2633 { 0x10, 0xf41b },
2634 { 0x1f, 0x0000 }
2635 };
2636
2637 rtl_writephy(tp, 0x1f, 0x0001);
2638 rtl_patchphy(tp, 0x16, 1 << 0);
2639
2640 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2641 }
2642
2643 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2644 {
2645 static const struct phy_reg phy_reg_init[] = {
2646 { 0x1f, 0x0001 },
2647 { 0x10, 0xf41b },
2648 { 0x1f, 0x0000 }
2649 };
2650
2651 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2652 }
2653
2654 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2655 {
2656 static const struct phy_reg phy_reg_init[] = {
2657 { 0x1f, 0x0000 },
2658 { 0x1d, 0x0f00 },
2659 { 0x1f, 0x0002 },
2660 { 0x0c, 0x1ec8 },
2661 { 0x1f, 0x0000 }
2662 };
2663
2664 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2665 }
2666
2667 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2668 {
2669 static const struct phy_reg phy_reg_init[] = {
2670 { 0x1f, 0x0001 },
2671 { 0x1d, 0x3d98 },
2672 { 0x1f, 0x0000 }
2673 };
2674
2675 rtl_writephy(tp, 0x1f, 0x0000);
2676 rtl_patchphy(tp, 0x14, 1 << 5);
2677 rtl_patchphy(tp, 0x0d, 1 << 5);
2678
2679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2680 }
2681
2682 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684 static const struct phy_reg phy_reg_init[] = {
2685 { 0x1f, 0x0001 },
2686 { 0x12, 0x2300 },
2687 { 0x1f, 0x0002 },
2688 { 0x00, 0x88d4 },
2689 { 0x01, 0x82b1 },
2690 { 0x03, 0x7002 },
2691 { 0x08, 0x9e30 },
2692 { 0x09, 0x01f0 },
2693 { 0x0a, 0x5500 },
2694 { 0x0c, 0x00c8 },
2695 { 0x1f, 0x0003 },
2696 { 0x12, 0xc096 },
2697 { 0x16, 0x000a },
2698 { 0x1f, 0x0000 },
2699 { 0x1f, 0x0000 },
2700 { 0x09, 0x2000 },
2701 { 0x09, 0x0000 }
2702 };
2703
2704 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2705
2706 rtl_patchphy(tp, 0x14, 1 << 5);
2707 rtl_patchphy(tp, 0x0d, 1 << 5);
2708 rtl_writephy(tp, 0x1f, 0x0000);
2709 }
2710
2711 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2712 {
2713 static const struct phy_reg phy_reg_init[] = {
2714 { 0x1f, 0x0001 },
2715 { 0x12, 0x2300 },
2716 { 0x03, 0x802f },
2717 { 0x02, 0x4f02 },
2718 { 0x01, 0x0409 },
2719 { 0x00, 0xf099 },
2720 { 0x04, 0x9800 },
2721 { 0x04, 0x9000 },
2722 { 0x1d, 0x3d98 },
2723 { 0x1f, 0x0002 },
2724 { 0x0c, 0x7eb8 },
2725 { 0x06, 0x0761 },
2726 { 0x1f, 0x0003 },
2727 { 0x16, 0x0f0a },
2728 { 0x1f, 0x0000 }
2729 };
2730
2731 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2732
2733 rtl_patchphy(tp, 0x16, 1 << 0);
2734 rtl_patchphy(tp, 0x14, 1 << 5);
2735 rtl_patchphy(tp, 0x0d, 1 << 5);
2736 rtl_writephy(tp, 0x1f, 0x0000);
2737 }
2738
2739 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2740 {
2741 static const struct phy_reg phy_reg_init[] = {
2742 { 0x1f, 0x0001 },
2743 { 0x12, 0x2300 },
2744 { 0x1d, 0x3d98 },
2745 { 0x1f, 0x0002 },
2746 { 0x0c, 0x7eb8 },
2747 { 0x06, 0x5461 },
2748 { 0x1f, 0x0003 },
2749 { 0x16, 0x0f0a },
2750 { 0x1f, 0x0000 }
2751 };
2752
2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755 rtl_patchphy(tp, 0x16, 1 << 0);
2756 rtl_patchphy(tp, 0x14, 1 << 5);
2757 rtl_patchphy(tp, 0x0d, 1 << 5);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2759 }
2760
2761 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2762 {
2763 rtl8168c_3_hw_phy_config(tp);
2764 }
2765
2766 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2767 {
2768 static const struct phy_reg phy_reg_init_0[] = {
2769 /* Channel Estimation */
2770 { 0x1f, 0x0001 },
2771 { 0x06, 0x4064 },
2772 { 0x07, 0x2863 },
2773 { 0x08, 0x059c },
2774 { 0x09, 0x26b4 },
2775 { 0x0a, 0x6a19 },
2776 { 0x0b, 0xdcc8 },
2777 { 0x10, 0xf06d },
2778 { 0x14, 0x7f68 },
2779 { 0x18, 0x7fd9 },
2780 { 0x1c, 0xf0ff },
2781 { 0x1d, 0x3d9c },
2782 { 0x1f, 0x0003 },
2783 { 0x12, 0xf49f },
2784 { 0x13, 0x070b },
2785 { 0x1a, 0x05ad },
2786 { 0x14, 0x94c0 },
2787
2788 /*
2789 * Tx Error Issue
2790 * Enhance line driver power
2791 */
2792 { 0x1f, 0x0002 },
2793 { 0x06, 0x5561 },
2794 { 0x1f, 0x0005 },
2795 { 0x05, 0x8332 },
2796 { 0x06, 0x5561 },
2797
2798 /*
2799 * Can not link to 1Gbps with bad cable
2800 * Decrease SNR threshold form 21.07dB to 19.04dB
2801 */
2802 { 0x1f, 0x0001 },
2803 { 0x17, 0x0cc0 },
2804
2805 { 0x1f, 0x0000 },
2806 { 0x0d, 0xf880 }
2807 };
2808
2809 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2810
2811 /*
2812 * Rx Error Issue
2813 * Fine Tune Switching regulator parameter
2814 */
2815 rtl_writephy(tp, 0x1f, 0x0002);
2816 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2817 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2818
2819 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2820 static const struct phy_reg phy_reg_init[] = {
2821 { 0x1f, 0x0002 },
2822 { 0x05, 0x669a },
2823 { 0x1f, 0x0005 },
2824 { 0x05, 0x8330 },
2825 { 0x06, 0x669a },
2826 { 0x1f, 0x0002 }
2827 };
2828 int val;
2829
2830 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2831
2832 val = rtl_readphy(tp, 0x0d);
2833
2834 if ((val & 0x00ff) != 0x006c) {
2835 static const u32 set[] = {
2836 0x0065, 0x0066, 0x0067, 0x0068,
2837 0x0069, 0x006a, 0x006b, 0x006c
2838 };
2839 int i;
2840
2841 rtl_writephy(tp, 0x1f, 0x0002);
2842
2843 val &= 0xff00;
2844 for (i = 0; i < ARRAY_SIZE(set); i++)
2845 rtl_writephy(tp, 0x0d, val | set[i]);
2846 }
2847 } else {
2848 static const struct phy_reg phy_reg_init[] = {
2849 { 0x1f, 0x0002 },
2850 { 0x05, 0x6662 },
2851 { 0x1f, 0x0005 },
2852 { 0x05, 0x8330 },
2853 { 0x06, 0x6662 }
2854 };
2855
2856 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857 }
2858
2859 /* RSET couple improve */
2860 rtl_writephy(tp, 0x1f, 0x0002);
2861 rtl_patchphy(tp, 0x0d, 0x0300);
2862 rtl_patchphy(tp, 0x0f, 0x0010);
2863
2864 /* Fine tune PLL performance */
2865 rtl_writephy(tp, 0x1f, 0x0002);
2866 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2867 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2868
2869 rtl_writephy(tp, 0x1f, 0x0005);
2870 rtl_writephy(tp, 0x05, 0x001b);
2871
2872 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2873
2874 rtl_writephy(tp, 0x1f, 0x0000);
2875 }
2876
2877 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879 static const struct phy_reg phy_reg_init_0[] = {
2880 /* Channel Estimation */
2881 { 0x1f, 0x0001 },
2882 { 0x06, 0x4064 },
2883 { 0x07, 0x2863 },
2884 { 0x08, 0x059c },
2885 { 0x09, 0x26b4 },
2886 { 0x0a, 0x6a19 },
2887 { 0x0b, 0xdcc8 },
2888 { 0x10, 0xf06d },
2889 { 0x14, 0x7f68 },
2890 { 0x18, 0x7fd9 },
2891 { 0x1c, 0xf0ff },
2892 { 0x1d, 0x3d9c },
2893 { 0x1f, 0x0003 },
2894 { 0x12, 0xf49f },
2895 { 0x13, 0x070b },
2896 { 0x1a, 0x05ad },
2897 { 0x14, 0x94c0 },
2898
2899 /*
2900 * Tx Error Issue
2901 * Enhance line driver power
2902 */
2903 { 0x1f, 0x0002 },
2904 { 0x06, 0x5561 },
2905 { 0x1f, 0x0005 },
2906 { 0x05, 0x8332 },
2907 { 0x06, 0x5561 },
2908
2909 /*
2910 * Can not link to 1Gbps with bad cable
2911 * Decrease SNR threshold form 21.07dB to 19.04dB
2912 */
2913 { 0x1f, 0x0001 },
2914 { 0x17, 0x0cc0 },
2915
2916 { 0x1f, 0x0000 },
2917 { 0x0d, 0xf880 }
2918 };
2919
2920 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2921
2922 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2923 static const struct phy_reg phy_reg_init[] = {
2924 { 0x1f, 0x0002 },
2925 { 0x05, 0x669a },
2926 { 0x1f, 0x0005 },
2927 { 0x05, 0x8330 },
2928 { 0x06, 0x669a },
2929
2930 { 0x1f, 0x0002 }
2931 };
2932 int val;
2933
2934 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2935
2936 val = rtl_readphy(tp, 0x0d);
2937 if ((val & 0x00ff) != 0x006c) {
2938 static const u32 set[] = {
2939 0x0065, 0x0066, 0x0067, 0x0068,
2940 0x0069, 0x006a, 0x006b, 0x006c
2941 };
2942 int i;
2943
2944 rtl_writephy(tp, 0x1f, 0x0002);
2945
2946 val &= 0xff00;
2947 for (i = 0; i < ARRAY_SIZE(set); i++)
2948 rtl_writephy(tp, 0x0d, val | set[i]);
2949 }
2950 } else {
2951 static const struct phy_reg phy_reg_init[] = {
2952 { 0x1f, 0x0002 },
2953 { 0x05, 0x2642 },
2954 { 0x1f, 0x0005 },
2955 { 0x05, 0x8330 },
2956 { 0x06, 0x2642 }
2957 };
2958
2959 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2960 }
2961
2962 /* Fine tune PLL performance */
2963 rtl_writephy(tp, 0x1f, 0x0002);
2964 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2965 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2966
2967 /* Switching regulator Slew rate */
2968 rtl_writephy(tp, 0x1f, 0x0002);
2969 rtl_patchphy(tp, 0x0f, 0x0017);
2970
2971 rtl_writephy(tp, 0x1f, 0x0005);
2972 rtl_writephy(tp, 0x05, 0x001b);
2973
2974 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2975
2976 rtl_writephy(tp, 0x1f, 0x0000);
2977 }
2978
2979 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2980 {
2981 static const struct phy_reg phy_reg_init[] = {
2982 { 0x1f, 0x0002 },
2983 { 0x10, 0x0008 },
2984 { 0x0d, 0x006c },
2985
2986 { 0x1f, 0x0000 },
2987 { 0x0d, 0xf880 },
2988
2989 { 0x1f, 0x0001 },
2990 { 0x17, 0x0cc0 },
2991
2992 { 0x1f, 0x0001 },
2993 { 0x0b, 0xa4d8 },
2994 { 0x09, 0x281c },
2995 { 0x07, 0x2883 },
2996 { 0x0a, 0x6b35 },
2997 { 0x1d, 0x3da4 },
2998 { 0x1c, 0xeffd },
2999 { 0x14, 0x7f52 },
3000 { 0x18, 0x7fc6 },
3001 { 0x08, 0x0601 },
3002 { 0x06, 0x4063 },
3003 { 0x10, 0xf074 },
3004 { 0x1f, 0x0003 },
3005 { 0x13, 0x0789 },
3006 { 0x12, 0xf4bd },
3007 { 0x1a, 0x04fd },
3008 { 0x14, 0x84b0 },
3009 { 0x1f, 0x0000 },
3010 { 0x00, 0x9200 },
3011
3012 { 0x1f, 0x0005 },
3013 { 0x01, 0x0340 },
3014 { 0x1f, 0x0001 },
3015 { 0x04, 0x4000 },
3016 { 0x03, 0x1d21 },
3017 { 0x02, 0x0c32 },
3018 { 0x01, 0x0200 },
3019 { 0x00, 0x5554 },
3020 { 0x04, 0x4800 },
3021 { 0x04, 0x4000 },
3022 { 0x04, 0xf000 },
3023 { 0x03, 0xdf01 },
3024 { 0x02, 0xdf20 },
3025 { 0x01, 0x101a },
3026 { 0x00, 0xa0ff },
3027 { 0x04, 0xf800 },
3028 { 0x04, 0xf000 },
3029 { 0x1f, 0x0000 },
3030
3031 { 0x1f, 0x0007 },
3032 { 0x1e, 0x0023 },
3033 { 0x16, 0x0000 },
3034 { 0x1f, 0x0000 }
3035 };
3036
3037 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3038 }
3039
3040 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3041 {
3042 static const struct phy_reg phy_reg_init[] = {
3043 { 0x1f, 0x0001 },
3044 { 0x17, 0x0cc0 },
3045
3046 { 0x1f, 0x0007 },
3047 { 0x1e, 0x002d },
3048 { 0x18, 0x0040 },
3049 { 0x1f, 0x0000 }
3050 };
3051
3052 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3053 rtl_patchphy(tp, 0x0d, 1 << 5);
3054 }
3055
3056 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3057 {
3058 static const struct phy_reg phy_reg_init[] = {
3059 /* Enable Delay cap */
3060 { 0x1f, 0x0005 },
3061 { 0x05, 0x8b80 },
3062 { 0x06, 0xc896 },
3063 { 0x1f, 0x0000 },
3064
3065 /* Channel estimation fine tune */
3066 { 0x1f, 0x0001 },
3067 { 0x0b, 0x6c20 },
3068 { 0x07, 0x2872 },
3069 { 0x1c, 0xefff },
3070 { 0x1f, 0x0003 },
3071 { 0x14, 0x6420 },
3072 { 0x1f, 0x0000 },
3073
3074 /* Update PFM & 10M TX idle timer */
3075 { 0x1f, 0x0007 },
3076 { 0x1e, 0x002f },
3077 { 0x15, 0x1919 },
3078 { 0x1f, 0x0000 },
3079
3080 { 0x1f, 0x0007 },
3081 { 0x1e, 0x00ac },
3082 { 0x18, 0x0006 },
3083 { 0x1f, 0x0000 }
3084 };
3085
3086 rtl_apply_firmware(tp);
3087
3088 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3089
3090 /* DCO enable for 10M IDLE Power */
3091 rtl_writephy(tp, 0x1f, 0x0007);
3092 rtl_writephy(tp, 0x1e, 0x0023);
3093 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3094 rtl_writephy(tp, 0x1f, 0x0000);
3095
3096 /* For impedance matching */
3097 rtl_writephy(tp, 0x1f, 0x0002);
3098 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100
3101 /* PHY auto speed down */
3102 rtl_writephy(tp, 0x1f, 0x0007);
3103 rtl_writephy(tp, 0x1e, 0x002d);
3104 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3107
3108 rtl_writephy(tp, 0x1f, 0x0005);
3109 rtl_writephy(tp, 0x05, 0x8b86);
3110 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3111 rtl_writephy(tp, 0x1f, 0x0000);
3112
3113 rtl_writephy(tp, 0x1f, 0x0005);
3114 rtl_writephy(tp, 0x05, 0x8b85);
3115 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3116 rtl_writephy(tp, 0x1f, 0x0007);
3117 rtl_writephy(tp, 0x1e, 0x0020);
3118 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3119 rtl_writephy(tp, 0x1f, 0x0006);
3120 rtl_writephy(tp, 0x00, 0x5a00);
3121 rtl_writephy(tp, 0x1f, 0x0000);
3122 rtl_writephy(tp, 0x0d, 0x0007);
3123 rtl_writephy(tp, 0x0e, 0x003c);
3124 rtl_writephy(tp, 0x0d, 0x4007);
3125 rtl_writephy(tp, 0x0e, 0x0000);
3126 rtl_writephy(tp, 0x0d, 0x0000);
3127 }
3128
3129 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3130 {
3131 const u16 w[] = {
3132 addr[0] | (addr[1] << 8),
3133 addr[2] | (addr[3] << 8),
3134 addr[4] | (addr[5] << 8)
3135 };
3136 const struct exgmac_reg e[] = {
3137 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3138 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3139 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3140 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3141 };
3142
3143 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3144 }
3145
3146 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3147 {
3148 static const struct phy_reg phy_reg_init[] = {
3149 /* Enable Delay cap */
3150 { 0x1f, 0x0004 },
3151 { 0x1f, 0x0007 },
3152 { 0x1e, 0x00ac },
3153 { 0x18, 0x0006 },
3154 { 0x1f, 0x0002 },
3155 { 0x1f, 0x0000 },
3156 { 0x1f, 0x0000 },
3157
3158 /* Channel estimation fine tune */
3159 { 0x1f, 0x0003 },
3160 { 0x09, 0xa20f },
3161 { 0x1f, 0x0000 },
3162 { 0x1f, 0x0000 },
3163
3164 /* Green Setting */
3165 { 0x1f, 0x0005 },
3166 { 0x05, 0x8b5b },
3167 { 0x06, 0x9222 },
3168 { 0x05, 0x8b6d },
3169 { 0x06, 0x8000 },
3170 { 0x05, 0x8b76 },
3171 { 0x06, 0x8000 },
3172 { 0x1f, 0x0000 }
3173 };
3174
3175 rtl_apply_firmware(tp);
3176
3177 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3178
3179 /* For 4-corner performance improve */
3180 rtl_writephy(tp, 0x1f, 0x0005);
3181 rtl_writephy(tp, 0x05, 0x8b80);
3182 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3183 rtl_writephy(tp, 0x1f, 0x0000);
3184
3185 /* PHY auto speed down */
3186 rtl_writephy(tp, 0x1f, 0x0004);
3187 rtl_writephy(tp, 0x1f, 0x0007);
3188 rtl_writephy(tp, 0x1e, 0x002d);
3189 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3190 rtl_writephy(tp, 0x1f, 0x0002);
3191 rtl_writephy(tp, 0x1f, 0x0000);
3192 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3193
3194 /* improve 10M EEE waveform */
3195 rtl_writephy(tp, 0x1f, 0x0005);
3196 rtl_writephy(tp, 0x05, 0x8b86);
3197 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3198 rtl_writephy(tp, 0x1f, 0x0000);
3199
3200 /* Improve 2-pair detection performance */
3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b85);
3203 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3204 rtl_writephy(tp, 0x1f, 0x0000);
3205
3206 /* EEE setting */
3207 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x8b85);
3210 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3211 rtl_writephy(tp, 0x1f, 0x0004);
3212 rtl_writephy(tp, 0x1f, 0x0007);
3213 rtl_writephy(tp, 0x1e, 0x0020);
3214 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3215 rtl_writephy(tp, 0x1f, 0x0002);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217 rtl_writephy(tp, 0x0d, 0x0007);
3218 rtl_writephy(tp, 0x0e, 0x003c);
3219 rtl_writephy(tp, 0x0d, 0x4007);
3220 rtl_writephy(tp, 0x0e, 0x0000);
3221 rtl_writephy(tp, 0x0d, 0x0000);
3222
3223 /* Green feature */
3224 rtl_writephy(tp, 0x1f, 0x0003);
3225 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3226 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3227 rtl_writephy(tp, 0x1f, 0x0000);
3228
3229 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3230 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3231 }
3232
3233 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3234 {
3235 /* For 4-corner performance improve */
3236 rtl_writephy(tp, 0x1f, 0x0005);
3237 rtl_writephy(tp, 0x05, 0x8b80);
3238 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3239 rtl_writephy(tp, 0x1f, 0x0000);
3240
3241 /* PHY auto speed down */
3242 rtl_writephy(tp, 0x1f, 0x0007);
3243 rtl_writephy(tp, 0x1e, 0x002d);
3244 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3245 rtl_writephy(tp, 0x1f, 0x0000);
3246 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3247
3248 /* Improve 10M EEE waveform */
3249 rtl_writephy(tp, 0x1f, 0x0005);
3250 rtl_writephy(tp, 0x05, 0x8b86);
3251 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0000);
3253 }
3254
3255 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3256 {
3257 static const struct phy_reg phy_reg_init[] = {
3258 /* Channel estimation fine tune */
3259 { 0x1f, 0x0003 },
3260 { 0x09, 0xa20f },
3261 { 0x1f, 0x0000 },
3262
3263 /* Modify green table for giga & fnet */
3264 { 0x1f, 0x0005 },
3265 { 0x05, 0x8b55 },
3266 { 0x06, 0x0000 },
3267 { 0x05, 0x8b5e },
3268 { 0x06, 0x0000 },
3269 { 0x05, 0x8b67 },
3270 { 0x06, 0x0000 },
3271 { 0x05, 0x8b70 },
3272 { 0x06, 0x0000 },
3273 { 0x1f, 0x0000 },
3274 { 0x1f, 0x0007 },
3275 { 0x1e, 0x0078 },
3276 { 0x17, 0x0000 },
3277 { 0x19, 0x00fb },
3278 { 0x1f, 0x0000 },
3279
3280 /* Modify green table for 10M */
3281 { 0x1f, 0x0005 },
3282 { 0x05, 0x8b79 },
3283 { 0x06, 0xaa00 },
3284 { 0x1f, 0x0000 },
3285
3286 /* Disable hiimpedance detection (RTCT) */
3287 { 0x1f, 0x0003 },
3288 { 0x01, 0x328a },
3289 { 0x1f, 0x0000 }
3290 };
3291
3292 rtl_apply_firmware(tp);
3293
3294 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3295
3296 rtl8168f_hw_phy_config(tp);
3297
3298 /* Improve 2-pair detection performance */
3299 rtl_writephy(tp, 0x1f, 0x0005);
3300 rtl_writephy(tp, 0x05, 0x8b85);
3301 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3302 rtl_writephy(tp, 0x1f, 0x0000);
3303 }
3304
3305 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3306 {
3307 rtl_apply_firmware(tp);
3308
3309 rtl8168f_hw_phy_config(tp);
3310 }
3311
3312 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3313 {
3314 static const struct phy_reg phy_reg_init[] = {
3315 /* Channel estimation fine tune */
3316 { 0x1f, 0x0003 },
3317 { 0x09, 0xa20f },
3318 { 0x1f, 0x0000 },
3319
3320 /* Modify green table for giga & fnet */
3321 { 0x1f, 0x0005 },
3322 { 0x05, 0x8b55 },
3323 { 0x06, 0x0000 },
3324 { 0x05, 0x8b5e },
3325 { 0x06, 0x0000 },
3326 { 0x05, 0x8b67 },
3327 { 0x06, 0x0000 },
3328 { 0x05, 0x8b70 },
3329 { 0x06, 0x0000 },
3330 { 0x1f, 0x0000 },
3331 { 0x1f, 0x0007 },
3332 { 0x1e, 0x0078 },
3333 { 0x17, 0x0000 },
3334 { 0x19, 0x00aa },
3335 { 0x1f, 0x0000 },
3336
3337 /* Modify green table for 10M */
3338 { 0x1f, 0x0005 },
3339 { 0x05, 0x8b79 },
3340 { 0x06, 0xaa00 },
3341 { 0x1f, 0x0000 },
3342
3343 /* Disable hiimpedance detection (RTCT) */
3344 { 0x1f, 0x0003 },
3345 { 0x01, 0x328a },
3346 { 0x1f, 0x0000 }
3347 };
3348
3349
3350 rtl_apply_firmware(tp);
3351
3352 rtl8168f_hw_phy_config(tp);
3353
3354 /* Improve 2-pair detection performance */
3355 rtl_writephy(tp, 0x1f, 0x0005);
3356 rtl_writephy(tp, 0x05, 0x8b85);
3357 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3358 rtl_writephy(tp, 0x1f, 0x0000);
3359
3360 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3361
3362 /* Modify green table for giga */
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b54);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366 rtl_writephy(tp, 0x05, 0x8b5d);
3367 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3368 rtl_writephy(tp, 0x05, 0x8a7c);
3369 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370 rtl_writephy(tp, 0x05, 0x8a7f);
3371 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3372 rtl_writephy(tp, 0x05, 0x8a82);
3373 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374 rtl_writephy(tp, 0x05, 0x8a85);
3375 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x05, 0x8a88);
3377 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3378 rtl_writephy(tp, 0x1f, 0x0000);
3379
3380 /* uc same-seed solution */
3381 rtl_writephy(tp, 0x1f, 0x0005);
3382 rtl_writephy(tp, 0x05, 0x8b85);
3383 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3384 rtl_writephy(tp, 0x1f, 0x0000);
3385
3386 /* eee setting */
3387 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b85);
3390 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3391 rtl_writephy(tp, 0x1f, 0x0004);
3392 rtl_writephy(tp, 0x1f, 0x0007);
3393 rtl_writephy(tp, 0x1e, 0x0020);
3394 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3395 rtl_writephy(tp, 0x1f, 0x0000);
3396 rtl_writephy(tp, 0x0d, 0x0007);
3397 rtl_writephy(tp, 0x0e, 0x003c);
3398 rtl_writephy(tp, 0x0d, 0x4007);
3399 rtl_writephy(tp, 0x0e, 0x0000);
3400 rtl_writephy(tp, 0x0d, 0x0000);
3401
3402 /* Green feature */
3403 rtl_writephy(tp, 0x1f, 0x0003);
3404 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3405 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3406 rtl_writephy(tp, 0x1f, 0x0000);
3407 }
3408
3409 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3410 {
3411 rtl_apply_firmware(tp);
3412
3413 rtl_writephy(tp, 0x1f, 0x0a46);
3414 if (rtl_readphy(tp, 0x10) & 0x0100) {
3415 rtl_writephy(tp, 0x1f, 0x0bcc);
3416 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3417 } else {
3418 rtl_writephy(tp, 0x1f, 0x0bcc);
3419 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3420 }
3421
3422 rtl_writephy(tp, 0x1f, 0x0a46);
3423 if (rtl_readphy(tp, 0x13) & 0x0100) {
3424 rtl_writephy(tp, 0x1f, 0x0c41);
3425 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3426 } else {
3427 rtl_writephy(tp, 0x1f, 0x0c41);
3428 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3429 }
3430
3431 /* Enable PHY auto speed down */
3432 rtl_writephy(tp, 0x1f, 0x0a44);
3433 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3434
3435 rtl_writephy(tp, 0x1f, 0x0bcc);
3436 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3437 rtl_writephy(tp, 0x1f, 0x0a44);
3438 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3439 rtl_writephy(tp, 0x1f, 0x0a43);
3440 rtl_writephy(tp, 0x13, 0x8084);
3441 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3442 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3443
3444 /* EEE auto-fallback function */
3445 rtl_writephy(tp, 0x1f, 0x0a4b);
3446 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3447
3448 /* Enable UC LPF tune function */
3449 rtl_writephy(tp, 0x1f, 0x0a43);
3450 rtl_writephy(tp, 0x13, 0x8012);
3451 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3452
3453 rtl_writephy(tp, 0x1f, 0x0c42);
3454 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3455
3456 /* Improve SWR Efficiency */
3457 rtl_writephy(tp, 0x1f, 0x0bcd);
3458 rtl_writephy(tp, 0x14, 0x5065);
3459 rtl_writephy(tp, 0x14, 0xd065);
3460 rtl_writephy(tp, 0x1f, 0x0bc8);
3461 rtl_writephy(tp, 0x11, 0x5655);
3462 rtl_writephy(tp, 0x1f, 0x0bcd);
3463 rtl_writephy(tp, 0x14, 0x1065);
3464 rtl_writephy(tp, 0x14, 0x9065);
3465 rtl_writephy(tp, 0x14, 0x1065);
3466
3467 /* Check ALDPS bit, disable it if enabled */
3468 rtl_writephy(tp, 0x1f, 0x0a43);
3469 if (rtl_readphy(tp, 0x10) & 0x0004)
3470 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3471
3472 rtl_writephy(tp, 0x1f, 0x0000);
3473 }
3474
3475 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3476 {
3477 rtl_apply_firmware(tp);
3478 }
3479
3480 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3481 {
3482 static const struct phy_reg phy_reg_init[] = {
3483 { 0x1f, 0x0003 },
3484 { 0x08, 0x441d },
3485 { 0x01, 0x9100 },
3486 { 0x1f, 0x0000 }
3487 };
3488
3489 rtl_writephy(tp, 0x1f, 0x0000);
3490 rtl_patchphy(tp, 0x11, 1 << 12);
3491 rtl_patchphy(tp, 0x19, 1 << 13);
3492 rtl_patchphy(tp, 0x10, 1 << 15);
3493
3494 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3495 }
3496
3497 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3498 {
3499 static const struct phy_reg phy_reg_init[] = {
3500 { 0x1f, 0x0005 },
3501 { 0x1a, 0x0000 },
3502 { 0x1f, 0x0000 },
3503
3504 { 0x1f, 0x0004 },
3505 { 0x1c, 0x0000 },
3506 { 0x1f, 0x0000 },
3507
3508 { 0x1f, 0x0001 },
3509 { 0x15, 0x7701 },
3510 { 0x1f, 0x0000 }
3511 };
3512
3513 /* Disable ALDPS before ram code */
3514 rtl_writephy(tp, 0x1f, 0x0000);
3515 rtl_writephy(tp, 0x18, 0x0310);
3516 msleep(100);
3517
3518 rtl_apply_firmware(tp);
3519
3520 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3521 }
3522
3523 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3524 {
3525 /* Disable ALDPS before setting firmware */
3526 rtl_writephy(tp, 0x1f, 0x0000);
3527 rtl_writephy(tp, 0x18, 0x0310);
3528 msleep(20);
3529
3530 rtl_apply_firmware(tp);
3531
3532 /* EEE setting */
3533 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3534 rtl_writephy(tp, 0x1f, 0x0004);
3535 rtl_writephy(tp, 0x10, 0x401f);
3536 rtl_writephy(tp, 0x19, 0x7030);
3537 rtl_writephy(tp, 0x1f, 0x0000);
3538 }
3539
3540 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3541 {
3542 static const struct phy_reg phy_reg_init[] = {
3543 { 0x1f, 0x0004 },
3544 { 0x10, 0xc07f },
3545 { 0x19, 0x7030 },
3546 { 0x1f, 0x0000 }
3547 };
3548
3549 /* Disable ALDPS before ram code */
3550 rtl_writephy(tp, 0x1f, 0x0000);
3551 rtl_writephy(tp, 0x18, 0x0310);
3552 msleep(100);
3553
3554 rtl_apply_firmware(tp);
3555
3556 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3558
3559 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3560 }
3561
3562 static void rtl_hw_phy_config(struct net_device *dev)
3563 {
3564 struct rtl8169_private *tp = netdev_priv(dev);
3565
3566 rtl8169_print_mac_version(tp);
3567
3568 switch (tp->mac_version) {
3569 case RTL_GIGA_MAC_VER_01:
3570 break;
3571 case RTL_GIGA_MAC_VER_02:
3572 case RTL_GIGA_MAC_VER_03:
3573 rtl8169s_hw_phy_config(tp);
3574 break;
3575 case RTL_GIGA_MAC_VER_04:
3576 rtl8169sb_hw_phy_config(tp);
3577 break;
3578 case RTL_GIGA_MAC_VER_05:
3579 rtl8169scd_hw_phy_config(tp);
3580 break;
3581 case RTL_GIGA_MAC_VER_06:
3582 rtl8169sce_hw_phy_config(tp);
3583 break;
3584 case RTL_GIGA_MAC_VER_07:
3585 case RTL_GIGA_MAC_VER_08:
3586 case RTL_GIGA_MAC_VER_09:
3587 rtl8102e_hw_phy_config(tp);
3588 break;
3589 case RTL_GIGA_MAC_VER_11:
3590 rtl8168bb_hw_phy_config(tp);
3591 break;
3592 case RTL_GIGA_MAC_VER_12:
3593 rtl8168bef_hw_phy_config(tp);
3594 break;
3595 case RTL_GIGA_MAC_VER_17:
3596 rtl8168bef_hw_phy_config(tp);
3597 break;
3598 case RTL_GIGA_MAC_VER_18:
3599 rtl8168cp_1_hw_phy_config(tp);
3600 break;
3601 case RTL_GIGA_MAC_VER_19:
3602 rtl8168c_1_hw_phy_config(tp);
3603 break;
3604 case RTL_GIGA_MAC_VER_20:
3605 rtl8168c_2_hw_phy_config(tp);
3606 break;
3607 case RTL_GIGA_MAC_VER_21:
3608 rtl8168c_3_hw_phy_config(tp);
3609 break;
3610 case RTL_GIGA_MAC_VER_22:
3611 rtl8168c_4_hw_phy_config(tp);
3612 break;
3613 case RTL_GIGA_MAC_VER_23:
3614 case RTL_GIGA_MAC_VER_24:
3615 rtl8168cp_2_hw_phy_config(tp);
3616 break;
3617 case RTL_GIGA_MAC_VER_25:
3618 rtl8168d_1_hw_phy_config(tp);
3619 break;
3620 case RTL_GIGA_MAC_VER_26:
3621 rtl8168d_2_hw_phy_config(tp);
3622 break;
3623 case RTL_GIGA_MAC_VER_27:
3624 rtl8168d_3_hw_phy_config(tp);
3625 break;
3626 case RTL_GIGA_MAC_VER_28:
3627 rtl8168d_4_hw_phy_config(tp);
3628 break;
3629 case RTL_GIGA_MAC_VER_29:
3630 case RTL_GIGA_MAC_VER_30:
3631 rtl8105e_hw_phy_config(tp);
3632 break;
3633 case RTL_GIGA_MAC_VER_31:
3634 /* None. */
3635 break;
3636 case RTL_GIGA_MAC_VER_32:
3637 case RTL_GIGA_MAC_VER_33:
3638 rtl8168e_1_hw_phy_config(tp);
3639 break;
3640 case RTL_GIGA_MAC_VER_34:
3641 rtl8168e_2_hw_phy_config(tp);
3642 break;
3643 case RTL_GIGA_MAC_VER_35:
3644 rtl8168f_1_hw_phy_config(tp);
3645 break;
3646 case RTL_GIGA_MAC_VER_36:
3647 rtl8168f_2_hw_phy_config(tp);
3648 break;
3649
3650 case RTL_GIGA_MAC_VER_37:
3651 rtl8402_hw_phy_config(tp);
3652 break;
3653
3654 case RTL_GIGA_MAC_VER_38:
3655 rtl8411_hw_phy_config(tp);
3656 break;
3657
3658 case RTL_GIGA_MAC_VER_39:
3659 rtl8106e_hw_phy_config(tp);
3660 break;
3661
3662 case RTL_GIGA_MAC_VER_40:
3663 rtl8168g_1_hw_phy_config(tp);
3664 break;
3665 case RTL_GIGA_MAC_VER_42:
3666 case RTL_GIGA_MAC_VER_43:
3667 case RTL_GIGA_MAC_VER_44:
3668 rtl8168g_2_hw_phy_config(tp);
3669 break;
3670
3671 case RTL_GIGA_MAC_VER_41:
3672 default:
3673 break;
3674 }
3675 }
3676
3677 static void rtl_phy_work(struct rtl8169_private *tp)
3678 {
3679 struct timer_list *timer = &tp->timer;
3680 void __iomem *ioaddr = tp->mmio_addr;
3681 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3682
3683 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3684
3685 if (tp->phy_reset_pending(tp)) {
3686 /*
3687 * A busy loop could burn quite a few cycles on nowadays CPU.
3688 * Let's delay the execution of the timer for a few ticks.
3689 */
3690 timeout = HZ/10;
3691 goto out_mod_timer;
3692 }
3693
3694 if (tp->link_ok(ioaddr))
3695 return;
3696
3697 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3698
3699 tp->phy_reset_enable(tp);
3700
3701 out_mod_timer:
3702 mod_timer(timer, jiffies + timeout);
3703 }
3704
3705 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3706 {
3707 if (!test_and_set_bit(flag, tp->wk.flags))
3708 schedule_work(&tp->wk.work);
3709 }
3710
3711 static void rtl8169_phy_timer(unsigned long __opaque)
3712 {
3713 struct net_device *dev = (struct net_device *)__opaque;
3714 struct rtl8169_private *tp = netdev_priv(dev);
3715
3716 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3717 }
3718
3719 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3720 void __iomem *ioaddr)
3721 {
3722 iounmap(ioaddr);
3723 pci_release_regions(pdev);
3724 pci_clear_mwi(pdev);
3725 pci_disable_device(pdev);
3726 free_netdev(dev);
3727 }
3728
3729 DECLARE_RTL_COND(rtl_phy_reset_cond)
3730 {
3731 return tp->phy_reset_pending(tp);
3732 }
3733
3734 static void rtl8169_phy_reset(struct net_device *dev,
3735 struct rtl8169_private *tp)
3736 {
3737 tp->phy_reset_enable(tp);
3738 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3739 }
3740
3741 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3742 {
3743 void __iomem *ioaddr = tp->mmio_addr;
3744
3745 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3746 (RTL_R8(PHYstatus) & TBI_Enable);
3747 }
3748
3749 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3750 {
3751 void __iomem *ioaddr = tp->mmio_addr;
3752
3753 rtl_hw_phy_config(dev);
3754
3755 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3756 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3757 RTL_W8(0x82, 0x01);
3758 }
3759
3760 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3761
3762 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3763 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3764
3765 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3766 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3767 RTL_W8(0x82, 0x01);
3768 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3769 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3770 }
3771
3772 rtl8169_phy_reset(dev, tp);
3773
3774 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3775 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3776 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3777 (tp->mii.supports_gmii ?
3778 ADVERTISED_1000baseT_Half |
3779 ADVERTISED_1000baseT_Full : 0));
3780
3781 if (rtl_tbi_enabled(tp))
3782 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3783 }
3784
3785 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3786 {
3787 void __iomem *ioaddr = tp->mmio_addr;
3788
3789 rtl_lock_work(tp);
3790
3791 RTL_W8(Cfg9346, Cfg9346_Unlock);
3792
3793 RTL_W32(MAC4, addr[4] | addr[5] << 8);
3794 RTL_R32(MAC4);
3795
3796 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3797 RTL_R32(MAC0);
3798
3799 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3800 rtl_rar_exgmac_set(tp, addr);
3801
3802 RTL_W8(Cfg9346, Cfg9346_Lock);
3803
3804 rtl_unlock_work(tp);
3805 }
3806
3807 static int rtl_set_mac_address(struct net_device *dev, void *p)
3808 {
3809 struct rtl8169_private *tp = netdev_priv(dev);
3810 struct sockaddr *addr = p;
3811
3812 if (!is_valid_ether_addr(addr->sa_data))
3813 return -EADDRNOTAVAIL;
3814
3815 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3816
3817 rtl_rar_set(tp, dev->dev_addr);
3818
3819 return 0;
3820 }
3821
3822 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3823 {
3824 struct rtl8169_private *tp = netdev_priv(dev);
3825 struct mii_ioctl_data *data = if_mii(ifr);
3826
3827 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3828 }
3829
3830 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3831 struct mii_ioctl_data *data, int cmd)
3832 {
3833 switch (cmd) {
3834 case SIOCGMIIPHY:
3835 data->phy_id = 32; /* Internal PHY */
3836 return 0;
3837
3838 case SIOCGMIIREG:
3839 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3840 return 0;
3841
3842 case SIOCSMIIREG:
3843 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3844 return 0;
3845 }
3846 return -EOPNOTSUPP;
3847 }
3848
3849 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3850 {
3851 return -EOPNOTSUPP;
3852 }
3853
3854 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3855 {
3856 if (tp->features & RTL_FEATURE_MSI) {
3857 pci_disable_msi(pdev);
3858 tp->features &= ~RTL_FEATURE_MSI;
3859 }
3860 }
3861
3862 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3863 {
3864 struct mdio_ops *ops = &tp->mdio_ops;
3865
3866 switch (tp->mac_version) {
3867 case RTL_GIGA_MAC_VER_27:
3868 ops->write = r8168dp_1_mdio_write;
3869 ops->read = r8168dp_1_mdio_read;
3870 break;
3871 case RTL_GIGA_MAC_VER_28:
3872 case RTL_GIGA_MAC_VER_31:
3873 ops->write = r8168dp_2_mdio_write;
3874 ops->read = r8168dp_2_mdio_read;
3875 break;
3876 case RTL_GIGA_MAC_VER_40:
3877 case RTL_GIGA_MAC_VER_41:
3878 case RTL_GIGA_MAC_VER_42:
3879 case RTL_GIGA_MAC_VER_43:
3880 case RTL_GIGA_MAC_VER_44:
3881 ops->write = r8168g_mdio_write;
3882 ops->read = r8168g_mdio_read;
3883 break;
3884 default:
3885 ops->write = r8169_mdio_write;
3886 ops->read = r8169_mdio_read;
3887 break;
3888 }
3889 }
3890
3891 static void rtl_speed_down(struct rtl8169_private *tp)
3892 {
3893 u32 adv;
3894 int lpa;
3895
3896 rtl_writephy(tp, 0x1f, 0x0000);
3897 lpa = rtl_readphy(tp, MII_LPA);
3898
3899 if (lpa & (LPA_10HALF | LPA_10FULL))
3900 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3901 else if (lpa & (LPA_100HALF | LPA_100FULL))
3902 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3903 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3904 else
3905 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3906 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3907 (tp->mii.supports_gmii ?
3908 ADVERTISED_1000baseT_Half |
3909 ADVERTISED_1000baseT_Full : 0);
3910
3911 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3912 adv);
3913 }
3914
3915 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3916 {
3917 void __iomem *ioaddr = tp->mmio_addr;
3918
3919 switch (tp->mac_version) {
3920 case RTL_GIGA_MAC_VER_25:
3921 case RTL_GIGA_MAC_VER_26:
3922 case RTL_GIGA_MAC_VER_29:
3923 case RTL_GIGA_MAC_VER_30:
3924 case RTL_GIGA_MAC_VER_32:
3925 case RTL_GIGA_MAC_VER_33:
3926 case RTL_GIGA_MAC_VER_34:
3927 case RTL_GIGA_MAC_VER_37:
3928 case RTL_GIGA_MAC_VER_38:
3929 case RTL_GIGA_MAC_VER_39:
3930 case RTL_GIGA_MAC_VER_40:
3931 case RTL_GIGA_MAC_VER_41:
3932 case RTL_GIGA_MAC_VER_42:
3933 case RTL_GIGA_MAC_VER_43:
3934 case RTL_GIGA_MAC_VER_44:
3935 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3936 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3937 break;
3938 default:
3939 break;
3940 }
3941 }
3942
3943 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3944 {
3945 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3946 return false;
3947
3948 rtl_speed_down(tp);
3949 rtl_wol_suspend_quirk(tp);
3950
3951 return true;
3952 }
3953
3954 static void r810x_phy_power_down(struct rtl8169_private *tp)
3955 {
3956 rtl_writephy(tp, 0x1f, 0x0000);
3957 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3958 }
3959
3960 static void r810x_phy_power_up(struct rtl8169_private *tp)
3961 {
3962 rtl_writephy(tp, 0x1f, 0x0000);
3963 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3964 }
3965
3966 static void r810x_pll_power_down(struct rtl8169_private *tp)
3967 {
3968 void __iomem *ioaddr = tp->mmio_addr;
3969
3970 if (rtl_wol_pll_power_down(tp))
3971 return;
3972
3973 r810x_phy_power_down(tp);
3974
3975 switch (tp->mac_version) {
3976 case RTL_GIGA_MAC_VER_07:
3977 case RTL_GIGA_MAC_VER_08:
3978 case RTL_GIGA_MAC_VER_09:
3979 case RTL_GIGA_MAC_VER_10:
3980 case RTL_GIGA_MAC_VER_13:
3981 case RTL_GIGA_MAC_VER_16:
3982 break;
3983 default:
3984 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3985 break;
3986 }
3987 }
3988
3989 static void r810x_pll_power_up(struct rtl8169_private *tp)
3990 {
3991 void __iomem *ioaddr = tp->mmio_addr;
3992
3993 r810x_phy_power_up(tp);
3994
3995 switch (tp->mac_version) {
3996 case RTL_GIGA_MAC_VER_07:
3997 case RTL_GIGA_MAC_VER_08:
3998 case RTL_GIGA_MAC_VER_09:
3999 case RTL_GIGA_MAC_VER_10:
4000 case RTL_GIGA_MAC_VER_13:
4001 case RTL_GIGA_MAC_VER_16:
4002 break;
4003 default:
4004 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4005 break;
4006 }
4007 }
4008
4009 static void r8168_phy_power_up(struct rtl8169_private *tp)
4010 {
4011 rtl_writephy(tp, 0x1f, 0x0000);
4012 switch (tp->mac_version) {
4013 case RTL_GIGA_MAC_VER_11:
4014 case RTL_GIGA_MAC_VER_12:
4015 case RTL_GIGA_MAC_VER_17:
4016 case RTL_GIGA_MAC_VER_18:
4017 case RTL_GIGA_MAC_VER_19:
4018 case RTL_GIGA_MAC_VER_20:
4019 case RTL_GIGA_MAC_VER_21:
4020 case RTL_GIGA_MAC_VER_22:
4021 case RTL_GIGA_MAC_VER_23:
4022 case RTL_GIGA_MAC_VER_24:
4023 case RTL_GIGA_MAC_VER_25:
4024 case RTL_GIGA_MAC_VER_26:
4025 case RTL_GIGA_MAC_VER_27:
4026 case RTL_GIGA_MAC_VER_28:
4027 case RTL_GIGA_MAC_VER_31:
4028 rtl_writephy(tp, 0x0e, 0x0000);
4029 break;
4030 default:
4031 break;
4032 }
4033 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4034 }
4035
4036 static void r8168_phy_power_down(struct rtl8169_private *tp)
4037 {
4038 rtl_writephy(tp, 0x1f, 0x0000);
4039 switch (tp->mac_version) {
4040 case RTL_GIGA_MAC_VER_32:
4041 case RTL_GIGA_MAC_VER_33:
4042 case RTL_GIGA_MAC_VER_40:
4043 case RTL_GIGA_MAC_VER_41:
4044 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4045 break;
4046
4047 case RTL_GIGA_MAC_VER_11:
4048 case RTL_GIGA_MAC_VER_12:
4049 case RTL_GIGA_MAC_VER_17:
4050 case RTL_GIGA_MAC_VER_18:
4051 case RTL_GIGA_MAC_VER_19:
4052 case RTL_GIGA_MAC_VER_20:
4053 case RTL_GIGA_MAC_VER_21:
4054 case RTL_GIGA_MAC_VER_22:
4055 case RTL_GIGA_MAC_VER_23:
4056 case RTL_GIGA_MAC_VER_24:
4057 case RTL_GIGA_MAC_VER_25:
4058 case RTL_GIGA_MAC_VER_26:
4059 case RTL_GIGA_MAC_VER_27:
4060 case RTL_GIGA_MAC_VER_28:
4061 case RTL_GIGA_MAC_VER_31:
4062 rtl_writephy(tp, 0x0e, 0x0200);
4063 default:
4064 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4065 break;
4066 }
4067 }
4068
4069 static void r8168_pll_power_down(struct rtl8169_private *tp)
4070 {
4071 void __iomem *ioaddr = tp->mmio_addr;
4072
4073 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4074 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4075 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4076 r8168dp_check_dash(tp)) {
4077 return;
4078 }
4079
4080 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4081 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4082 (RTL_R16(CPlusCmd) & ASF)) {
4083 return;
4084 }
4085
4086 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4087 tp->mac_version == RTL_GIGA_MAC_VER_33)
4088 rtl_ephy_write(tp, 0x19, 0xff64);
4089
4090 if (rtl_wol_pll_power_down(tp))
4091 return;
4092
4093 r8168_phy_power_down(tp);
4094
4095 switch (tp->mac_version) {
4096 case RTL_GIGA_MAC_VER_25:
4097 case RTL_GIGA_MAC_VER_26:
4098 case RTL_GIGA_MAC_VER_27:
4099 case RTL_GIGA_MAC_VER_28:
4100 case RTL_GIGA_MAC_VER_31:
4101 case RTL_GIGA_MAC_VER_32:
4102 case RTL_GIGA_MAC_VER_33:
4103 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4104 break;
4105 case RTL_GIGA_MAC_VER_40:
4106 case RTL_GIGA_MAC_VER_41:
4107 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4108 0xfc000000, ERIAR_EXGMAC);
4109 break;
4110 }
4111 }
4112
4113 static void r8168_pll_power_up(struct rtl8169_private *tp)
4114 {
4115 void __iomem *ioaddr = tp->mmio_addr;
4116
4117 switch (tp->mac_version) {
4118 case RTL_GIGA_MAC_VER_25:
4119 case RTL_GIGA_MAC_VER_26:
4120 case RTL_GIGA_MAC_VER_27:
4121 case RTL_GIGA_MAC_VER_28:
4122 case RTL_GIGA_MAC_VER_31:
4123 case RTL_GIGA_MAC_VER_32:
4124 case RTL_GIGA_MAC_VER_33:
4125 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4126 break;
4127 case RTL_GIGA_MAC_VER_40:
4128 case RTL_GIGA_MAC_VER_41:
4129 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4130 0x00000000, ERIAR_EXGMAC);
4131 break;
4132 }
4133
4134 r8168_phy_power_up(tp);
4135 }
4136
4137 static void rtl_generic_op(struct rtl8169_private *tp,
4138 void (*op)(struct rtl8169_private *))
4139 {
4140 if (op)
4141 op(tp);
4142 }
4143
4144 static void rtl_pll_power_down(struct rtl8169_private *tp)
4145 {
4146 rtl_generic_op(tp, tp->pll_power_ops.down);
4147 }
4148
4149 static void rtl_pll_power_up(struct rtl8169_private *tp)
4150 {
4151 rtl_generic_op(tp, tp->pll_power_ops.up);
4152 }
4153
4154 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4155 {
4156 struct pll_power_ops *ops = &tp->pll_power_ops;
4157
4158 switch (tp->mac_version) {
4159 case RTL_GIGA_MAC_VER_07:
4160 case RTL_GIGA_MAC_VER_08:
4161 case RTL_GIGA_MAC_VER_09:
4162 case RTL_GIGA_MAC_VER_10:
4163 case RTL_GIGA_MAC_VER_16:
4164 case RTL_GIGA_MAC_VER_29:
4165 case RTL_GIGA_MAC_VER_30:
4166 case RTL_GIGA_MAC_VER_37:
4167 case RTL_GIGA_MAC_VER_39:
4168 case RTL_GIGA_MAC_VER_43:
4169 ops->down = r810x_pll_power_down;
4170 ops->up = r810x_pll_power_up;
4171 break;
4172
4173 case RTL_GIGA_MAC_VER_11:
4174 case RTL_GIGA_MAC_VER_12:
4175 case RTL_GIGA_MAC_VER_17:
4176 case RTL_GIGA_MAC_VER_18:
4177 case RTL_GIGA_MAC_VER_19:
4178 case RTL_GIGA_MAC_VER_20:
4179 case RTL_GIGA_MAC_VER_21:
4180 case RTL_GIGA_MAC_VER_22:
4181 case RTL_GIGA_MAC_VER_23:
4182 case RTL_GIGA_MAC_VER_24:
4183 case RTL_GIGA_MAC_VER_25:
4184 case RTL_GIGA_MAC_VER_26:
4185 case RTL_GIGA_MAC_VER_27:
4186 case RTL_GIGA_MAC_VER_28:
4187 case RTL_GIGA_MAC_VER_31:
4188 case RTL_GIGA_MAC_VER_32:
4189 case RTL_GIGA_MAC_VER_33:
4190 case RTL_GIGA_MAC_VER_34:
4191 case RTL_GIGA_MAC_VER_35:
4192 case RTL_GIGA_MAC_VER_36:
4193 case RTL_GIGA_MAC_VER_38:
4194 case RTL_GIGA_MAC_VER_40:
4195 case RTL_GIGA_MAC_VER_41:
4196 case RTL_GIGA_MAC_VER_42:
4197 case RTL_GIGA_MAC_VER_44:
4198 ops->down = r8168_pll_power_down;
4199 ops->up = r8168_pll_power_up;
4200 break;
4201
4202 default:
4203 ops->down = NULL;
4204 ops->up = NULL;
4205 break;
4206 }
4207 }
4208
4209 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4210 {
4211 void __iomem *ioaddr = tp->mmio_addr;
4212
4213 switch (tp->mac_version) {
4214 case RTL_GIGA_MAC_VER_01:
4215 case RTL_GIGA_MAC_VER_02:
4216 case RTL_GIGA_MAC_VER_03:
4217 case RTL_GIGA_MAC_VER_04:
4218 case RTL_GIGA_MAC_VER_05:
4219 case RTL_GIGA_MAC_VER_06:
4220 case RTL_GIGA_MAC_VER_10:
4221 case RTL_GIGA_MAC_VER_11:
4222 case RTL_GIGA_MAC_VER_12:
4223 case RTL_GIGA_MAC_VER_13:
4224 case RTL_GIGA_MAC_VER_14:
4225 case RTL_GIGA_MAC_VER_15:
4226 case RTL_GIGA_MAC_VER_16:
4227 case RTL_GIGA_MAC_VER_17:
4228 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4229 break;
4230 case RTL_GIGA_MAC_VER_18:
4231 case RTL_GIGA_MAC_VER_19:
4232 case RTL_GIGA_MAC_VER_20:
4233 case RTL_GIGA_MAC_VER_21:
4234 case RTL_GIGA_MAC_VER_22:
4235 case RTL_GIGA_MAC_VER_23:
4236 case RTL_GIGA_MAC_VER_24:
4237 case RTL_GIGA_MAC_VER_34:
4238 case RTL_GIGA_MAC_VER_35:
4239 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4240 break;
4241 case RTL_GIGA_MAC_VER_40:
4242 case RTL_GIGA_MAC_VER_41:
4243 case RTL_GIGA_MAC_VER_42:
4244 case RTL_GIGA_MAC_VER_43:
4245 case RTL_GIGA_MAC_VER_44:
4246 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4247 break;
4248 default:
4249 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4250 break;
4251 }
4252 }
4253
4254 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4255 {
4256 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4257 }
4258
4259 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4260 {
4261 void __iomem *ioaddr = tp->mmio_addr;
4262
4263 RTL_W8(Cfg9346, Cfg9346_Unlock);
4264 rtl_generic_op(tp, tp->jumbo_ops.enable);
4265 RTL_W8(Cfg9346, Cfg9346_Lock);
4266 }
4267
4268 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4269 {
4270 void __iomem *ioaddr = tp->mmio_addr;
4271
4272 RTL_W8(Cfg9346, Cfg9346_Unlock);
4273 rtl_generic_op(tp, tp->jumbo_ops.disable);
4274 RTL_W8(Cfg9346, Cfg9346_Lock);
4275 }
4276
4277 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4278 {
4279 void __iomem *ioaddr = tp->mmio_addr;
4280
4281 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4282 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4283 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4284 }
4285
4286 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4287 {
4288 void __iomem *ioaddr = tp->mmio_addr;
4289
4290 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4291 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4292 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4293 }
4294
4295 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4296 {
4297 void __iomem *ioaddr = tp->mmio_addr;
4298
4299 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4300 }
4301
4302 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4303 {
4304 void __iomem *ioaddr = tp->mmio_addr;
4305
4306 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4307 }
4308
4309 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4310 {
4311 void __iomem *ioaddr = tp->mmio_addr;
4312
4313 RTL_W8(MaxTxPacketSize, 0x3f);
4314 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4315 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4316 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4317 }
4318
4319 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4320 {
4321 void __iomem *ioaddr = tp->mmio_addr;
4322
4323 RTL_W8(MaxTxPacketSize, 0x0c);
4324 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4325 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4326 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4327 }
4328
4329 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4330 {
4331 rtl_tx_performance_tweak(tp->pci_dev,
4332 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4333 }
4334
4335 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4336 {
4337 rtl_tx_performance_tweak(tp->pci_dev,
4338 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4339 }
4340
4341 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4342 {
4343 void __iomem *ioaddr = tp->mmio_addr;
4344
4345 r8168b_0_hw_jumbo_enable(tp);
4346
4347 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4348 }
4349
4350 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4351 {
4352 void __iomem *ioaddr = tp->mmio_addr;
4353
4354 r8168b_0_hw_jumbo_disable(tp);
4355
4356 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4357 }
4358
4359 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4360 {
4361 struct jumbo_ops *ops = &tp->jumbo_ops;
4362
4363 switch (tp->mac_version) {
4364 case RTL_GIGA_MAC_VER_11:
4365 ops->disable = r8168b_0_hw_jumbo_disable;
4366 ops->enable = r8168b_0_hw_jumbo_enable;
4367 break;
4368 case RTL_GIGA_MAC_VER_12:
4369 case RTL_GIGA_MAC_VER_17:
4370 ops->disable = r8168b_1_hw_jumbo_disable;
4371 ops->enable = r8168b_1_hw_jumbo_enable;
4372 break;
4373 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4374 case RTL_GIGA_MAC_VER_19:
4375 case RTL_GIGA_MAC_VER_20:
4376 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4377 case RTL_GIGA_MAC_VER_22:
4378 case RTL_GIGA_MAC_VER_23:
4379 case RTL_GIGA_MAC_VER_24:
4380 case RTL_GIGA_MAC_VER_25:
4381 case RTL_GIGA_MAC_VER_26:
4382 ops->disable = r8168c_hw_jumbo_disable;
4383 ops->enable = r8168c_hw_jumbo_enable;
4384 break;
4385 case RTL_GIGA_MAC_VER_27:
4386 case RTL_GIGA_MAC_VER_28:
4387 ops->disable = r8168dp_hw_jumbo_disable;
4388 ops->enable = r8168dp_hw_jumbo_enable;
4389 break;
4390 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4391 case RTL_GIGA_MAC_VER_32:
4392 case RTL_GIGA_MAC_VER_33:
4393 case RTL_GIGA_MAC_VER_34:
4394 ops->disable = r8168e_hw_jumbo_disable;
4395 ops->enable = r8168e_hw_jumbo_enable;
4396 break;
4397
4398 /*
4399 * No action needed for jumbo frames with 8169.
4400 * No jumbo for 810x at all.
4401 */
4402 case RTL_GIGA_MAC_VER_40:
4403 case RTL_GIGA_MAC_VER_41:
4404 case RTL_GIGA_MAC_VER_42:
4405 case RTL_GIGA_MAC_VER_43:
4406 case RTL_GIGA_MAC_VER_44:
4407 default:
4408 ops->disable = NULL;
4409 ops->enable = NULL;
4410 break;
4411 }
4412 }
4413
4414 DECLARE_RTL_COND(rtl_chipcmd_cond)
4415 {
4416 void __iomem *ioaddr = tp->mmio_addr;
4417
4418 return RTL_R8(ChipCmd) & CmdReset;
4419 }
4420
4421 static void rtl_hw_reset(struct rtl8169_private *tp)
4422 {
4423 void __iomem *ioaddr = tp->mmio_addr;
4424
4425 RTL_W8(ChipCmd, CmdReset);
4426
4427 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4428 }
4429
4430 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4431 {
4432 struct rtl_fw *rtl_fw;
4433 const char *name;
4434 int rc = -ENOMEM;
4435
4436 name = rtl_lookup_firmware_name(tp);
4437 if (!name)
4438 goto out_no_firmware;
4439
4440 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4441 if (!rtl_fw)
4442 goto err_warn;
4443
4444 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4445 if (rc < 0)
4446 goto err_free;
4447
4448 rc = rtl_check_firmware(tp, rtl_fw);
4449 if (rc < 0)
4450 goto err_release_firmware;
4451
4452 tp->rtl_fw = rtl_fw;
4453 out:
4454 return;
4455
4456 err_release_firmware:
4457 release_firmware(rtl_fw->fw);
4458 err_free:
4459 kfree(rtl_fw);
4460 err_warn:
4461 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4462 name, rc);
4463 out_no_firmware:
4464 tp->rtl_fw = NULL;
4465 goto out;
4466 }
4467
4468 static void rtl_request_firmware(struct rtl8169_private *tp)
4469 {
4470 if (IS_ERR(tp->rtl_fw))
4471 rtl_request_uncached_firmware(tp);
4472 }
4473
4474 static void rtl_rx_close(struct rtl8169_private *tp)
4475 {
4476 void __iomem *ioaddr = tp->mmio_addr;
4477
4478 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4479 }
4480
4481 DECLARE_RTL_COND(rtl_npq_cond)
4482 {
4483 void __iomem *ioaddr = tp->mmio_addr;
4484
4485 return RTL_R8(TxPoll) & NPQ;
4486 }
4487
4488 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4489 {
4490 void __iomem *ioaddr = tp->mmio_addr;
4491
4492 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4493 }
4494
4495 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4496 {
4497 void __iomem *ioaddr = tp->mmio_addr;
4498
4499 /* Disable interrupts */
4500 rtl8169_irq_mask_and_ack(tp);
4501
4502 rtl_rx_close(tp);
4503
4504 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4505 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4506 tp->mac_version == RTL_GIGA_MAC_VER_31) {
4507 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4508 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4509 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4510 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4511 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4512 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4513 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4514 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4515 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4516 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4517 tp->mac_version == RTL_GIGA_MAC_VER_38) {
4518 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4519 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4520 } else {
4521 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4522 udelay(100);
4523 }
4524
4525 rtl_hw_reset(tp);
4526 }
4527
4528 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4529 {
4530 void __iomem *ioaddr = tp->mmio_addr;
4531
4532 /* Set DMA burst size and Interframe Gap Time */
4533 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4534 (InterFrameGap << TxInterFrameGapShift));
4535 }
4536
4537 static void rtl_hw_start(struct net_device *dev)
4538 {
4539 struct rtl8169_private *tp = netdev_priv(dev);
4540
4541 tp->hw_start(dev);
4542
4543 rtl_irq_enable_all(tp);
4544 }
4545
4546 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4547 void __iomem *ioaddr)
4548 {
4549 /*
4550 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4551 * register to be written before TxDescAddrLow to work.
4552 * Switching from MMIO to I/O access fixes the issue as well.
4553 */
4554 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4555 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4556 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4557 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4558 }
4559
4560 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4561 {
4562 u16 cmd;
4563
4564 cmd = RTL_R16(CPlusCmd);
4565 RTL_W16(CPlusCmd, cmd);
4566 return cmd;
4567 }
4568
4569 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4570 {
4571 /* Low hurts. Let's disable the filtering. */
4572 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4573 }
4574
4575 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4576 {
4577 static const struct rtl_cfg2_info {
4578 u32 mac_version;
4579 u32 clk;
4580 u32 val;
4581 } cfg2_info [] = {
4582 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4583 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4584 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4585 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4586 };
4587 const struct rtl_cfg2_info *p = cfg2_info;
4588 unsigned int i;
4589 u32 clk;
4590
4591 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4592 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4593 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4594 RTL_W32(0x7c, p->val);
4595 break;
4596 }
4597 }
4598 }
4599
4600 static void rtl_set_rx_mode(struct net_device *dev)
4601 {
4602 struct rtl8169_private *tp = netdev_priv(dev);
4603 void __iomem *ioaddr = tp->mmio_addr;
4604 u32 mc_filter[2]; /* Multicast hash filter */
4605 int rx_mode;
4606 u32 tmp = 0;
4607
4608 if (dev->flags & IFF_PROMISC) {
4609 /* Unconditionally log net taps. */
4610 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4611 rx_mode =
4612 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4613 AcceptAllPhys;
4614 mc_filter[1] = mc_filter[0] = 0xffffffff;
4615 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4616 (dev->flags & IFF_ALLMULTI)) {
4617 /* Too many to filter perfectly -- accept all multicasts. */
4618 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4619 mc_filter[1] = mc_filter[0] = 0xffffffff;
4620 } else {
4621 struct netdev_hw_addr *ha;
4622
4623 rx_mode = AcceptBroadcast | AcceptMyPhys;
4624 mc_filter[1] = mc_filter[0] = 0;
4625 netdev_for_each_mc_addr(ha, dev) {
4626 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4627 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4628 rx_mode |= AcceptMulticast;
4629 }
4630 }
4631
4632 if (dev->features & NETIF_F_RXALL)
4633 rx_mode |= (AcceptErr | AcceptRunt);
4634
4635 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4636
4637 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4638 u32 data = mc_filter[0];
4639
4640 mc_filter[0] = swab32(mc_filter[1]);
4641 mc_filter[1] = swab32(data);
4642 }
4643
4644 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4645 mc_filter[1] = mc_filter[0] = 0xffffffff;
4646
4647 RTL_W32(MAR0 + 4, mc_filter[1]);
4648 RTL_W32(MAR0 + 0, mc_filter[0]);
4649
4650 RTL_W32(RxConfig, tmp);
4651 }
4652
4653 static void rtl_hw_start_8169(struct net_device *dev)
4654 {
4655 struct rtl8169_private *tp = netdev_priv(dev);
4656 void __iomem *ioaddr = tp->mmio_addr;
4657 struct pci_dev *pdev = tp->pci_dev;
4658
4659 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4660 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4661 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4662 }
4663
4664 RTL_W8(Cfg9346, Cfg9346_Unlock);
4665 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4666 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4667 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4668 tp->mac_version == RTL_GIGA_MAC_VER_04)
4669 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4670
4671 rtl_init_rxcfg(tp);
4672
4673 RTL_W8(EarlyTxThres, NoEarlyTx);
4674
4675 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4676
4677 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4678 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4679 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4680 tp->mac_version == RTL_GIGA_MAC_VER_04)
4681 rtl_set_rx_tx_config_registers(tp);
4682
4683 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4684
4685 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4686 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4687 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4688 "Bit-3 and bit-14 MUST be 1\n");
4689 tp->cp_cmd |= (1 << 14);
4690 }
4691
4692 RTL_W16(CPlusCmd, tp->cp_cmd);
4693
4694 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4695
4696 /*
4697 * Undocumented corner. Supposedly:
4698 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4699 */
4700 RTL_W16(IntrMitigate, 0x0000);
4701
4702 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4703
4704 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4705 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4706 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4707 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4708 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4709 rtl_set_rx_tx_config_registers(tp);
4710 }
4711
4712 RTL_W8(Cfg9346, Cfg9346_Lock);
4713
4714 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4715 RTL_R8(IntrMask);
4716
4717 RTL_W32(RxMissed, 0);
4718
4719 rtl_set_rx_mode(dev);
4720
4721 /* no early-rx interrupts */
4722 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4723 }
4724
4725 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4726 {
4727 if (tp->csi_ops.write)
4728 tp->csi_ops.write(tp, addr, value);
4729 }
4730
4731 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4732 {
4733 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4734 }
4735
4736 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4737 {
4738 u32 csi;
4739
4740 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4741 rtl_csi_write(tp, 0x070c, csi | bits);
4742 }
4743
4744 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4745 {
4746 rtl_csi_access_enable(tp, 0x17000000);
4747 }
4748
4749 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4750 {
4751 rtl_csi_access_enable(tp, 0x27000000);
4752 }
4753
4754 DECLARE_RTL_COND(rtl_csiar_cond)
4755 {
4756 void __iomem *ioaddr = tp->mmio_addr;
4757
4758 return RTL_R32(CSIAR) & CSIAR_FLAG;
4759 }
4760
4761 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4762 {
4763 void __iomem *ioaddr = tp->mmio_addr;
4764
4765 RTL_W32(CSIDR, value);
4766 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4767 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4768
4769 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4770 }
4771
4772 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4773 {
4774 void __iomem *ioaddr = tp->mmio_addr;
4775
4776 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4777 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4778
4779 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4780 RTL_R32(CSIDR) : ~0;
4781 }
4782
4783 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4784 {
4785 void __iomem *ioaddr = tp->mmio_addr;
4786
4787 RTL_W32(CSIDR, value);
4788 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4789 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4790 CSIAR_FUNC_NIC);
4791
4792 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4793 }
4794
4795 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4796 {
4797 void __iomem *ioaddr = tp->mmio_addr;
4798
4799 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4800 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4801
4802 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4803 RTL_R32(CSIDR) : ~0;
4804 }
4805
4806 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4807 {
4808 void __iomem *ioaddr = tp->mmio_addr;
4809
4810 RTL_W32(CSIDR, value);
4811 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4812 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4813 CSIAR_FUNC_NIC2);
4814
4815 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4816 }
4817
4818 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4819 {
4820 void __iomem *ioaddr = tp->mmio_addr;
4821
4822 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4823 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4824
4825 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4826 RTL_R32(CSIDR) : ~0;
4827 }
4828
4829 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4830 {
4831 struct csi_ops *ops = &tp->csi_ops;
4832
4833 switch (tp->mac_version) {
4834 case RTL_GIGA_MAC_VER_01:
4835 case RTL_GIGA_MAC_VER_02:
4836 case RTL_GIGA_MAC_VER_03:
4837 case RTL_GIGA_MAC_VER_04:
4838 case RTL_GIGA_MAC_VER_05:
4839 case RTL_GIGA_MAC_VER_06:
4840 case RTL_GIGA_MAC_VER_10:
4841 case RTL_GIGA_MAC_VER_11:
4842 case RTL_GIGA_MAC_VER_12:
4843 case RTL_GIGA_MAC_VER_13:
4844 case RTL_GIGA_MAC_VER_14:
4845 case RTL_GIGA_MAC_VER_15:
4846 case RTL_GIGA_MAC_VER_16:
4847 case RTL_GIGA_MAC_VER_17:
4848 ops->write = NULL;
4849 ops->read = NULL;
4850 break;
4851
4852 case RTL_GIGA_MAC_VER_37:
4853 case RTL_GIGA_MAC_VER_38:
4854 ops->write = r8402_csi_write;
4855 ops->read = r8402_csi_read;
4856 break;
4857
4858 case RTL_GIGA_MAC_VER_44:
4859 ops->write = r8411_csi_write;
4860 ops->read = r8411_csi_read;
4861 break;
4862
4863 default:
4864 ops->write = r8169_csi_write;
4865 ops->read = r8169_csi_read;
4866 break;
4867 }
4868 }
4869
4870 struct ephy_info {
4871 unsigned int offset;
4872 u16 mask;
4873 u16 bits;
4874 };
4875
4876 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4877 int len)
4878 {
4879 u16 w;
4880
4881 while (len-- > 0) {
4882 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4883 rtl_ephy_write(tp, e->offset, w);
4884 e++;
4885 }
4886 }
4887
4888 static void rtl_disable_clock_request(struct pci_dev *pdev)
4889 {
4890 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4891 PCI_EXP_LNKCTL_CLKREQ_EN);
4892 }
4893
4894 static void rtl_enable_clock_request(struct pci_dev *pdev)
4895 {
4896 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4897 PCI_EXP_LNKCTL_CLKREQ_EN);
4898 }
4899
4900 #define R8168_CPCMD_QUIRK_MASK (\
4901 EnableBist | \
4902 Mac_dbgo_oe | \
4903 Force_half_dup | \
4904 Force_rxflow_en | \
4905 Force_txflow_en | \
4906 Cxpl_dbg_sel | \
4907 ASF | \
4908 PktCntrDisable | \
4909 Mac_dbgo_sel)
4910
4911 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4912 {
4913 void __iomem *ioaddr = tp->mmio_addr;
4914 struct pci_dev *pdev = tp->pci_dev;
4915
4916 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4917
4918 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4919
4920 if (tp->dev->mtu <= ETH_DATA_LEN) {
4921 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4922 PCI_EXP_DEVCTL_NOSNOOP_EN);
4923 }
4924 }
4925
4926 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4927 {
4928 void __iomem *ioaddr = tp->mmio_addr;
4929
4930 rtl_hw_start_8168bb(tp);
4931
4932 RTL_W8(MaxTxPacketSize, TxPacketMax);
4933
4934 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4935 }
4936
4937 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4938 {
4939 void __iomem *ioaddr = tp->mmio_addr;
4940 struct pci_dev *pdev = tp->pci_dev;
4941
4942 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4943
4944 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4945
4946 if (tp->dev->mtu <= ETH_DATA_LEN)
4947 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4948
4949 rtl_disable_clock_request(pdev);
4950
4951 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4952 }
4953
4954 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4955 {
4956 static const struct ephy_info e_info_8168cp[] = {
4957 { 0x01, 0, 0x0001 },
4958 { 0x02, 0x0800, 0x1000 },
4959 { 0x03, 0, 0x0042 },
4960 { 0x06, 0x0080, 0x0000 },
4961 { 0x07, 0, 0x2000 }
4962 };
4963
4964 rtl_csi_access_enable_2(tp);
4965
4966 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4967
4968 __rtl_hw_start_8168cp(tp);
4969 }
4970
4971 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4972 {
4973 void __iomem *ioaddr = tp->mmio_addr;
4974 struct pci_dev *pdev = tp->pci_dev;
4975
4976 rtl_csi_access_enable_2(tp);
4977
4978 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4979
4980 if (tp->dev->mtu <= ETH_DATA_LEN)
4981 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4982
4983 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4984 }
4985
4986 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4987 {
4988 void __iomem *ioaddr = tp->mmio_addr;
4989 struct pci_dev *pdev = tp->pci_dev;
4990
4991 rtl_csi_access_enable_2(tp);
4992
4993 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4994
4995 /* Magic. */
4996 RTL_W8(DBG_REG, 0x20);
4997
4998 RTL_W8(MaxTxPacketSize, TxPacketMax);
4999
5000 if (tp->dev->mtu <= ETH_DATA_LEN)
5001 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5002
5003 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5004 }
5005
5006 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5007 {
5008 void __iomem *ioaddr = tp->mmio_addr;
5009 static const struct ephy_info e_info_8168c_1[] = {
5010 { 0x02, 0x0800, 0x1000 },
5011 { 0x03, 0, 0x0002 },
5012 { 0x06, 0x0080, 0x0000 }
5013 };
5014
5015 rtl_csi_access_enable_2(tp);
5016
5017 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5018
5019 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5020
5021 __rtl_hw_start_8168cp(tp);
5022 }
5023
5024 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5025 {
5026 static const struct ephy_info e_info_8168c_2[] = {
5027 { 0x01, 0, 0x0001 },
5028 { 0x03, 0x0400, 0x0220 }
5029 };
5030
5031 rtl_csi_access_enable_2(tp);
5032
5033 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5034
5035 __rtl_hw_start_8168cp(tp);
5036 }
5037
5038 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5039 {
5040 rtl_hw_start_8168c_2(tp);
5041 }
5042
5043 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5044 {
5045 rtl_csi_access_enable_2(tp);
5046
5047 __rtl_hw_start_8168cp(tp);
5048 }
5049
5050 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5051 {
5052 void __iomem *ioaddr = tp->mmio_addr;
5053 struct pci_dev *pdev = tp->pci_dev;
5054
5055 rtl_csi_access_enable_2(tp);
5056
5057 rtl_disable_clock_request(pdev);
5058
5059 RTL_W8(MaxTxPacketSize, TxPacketMax);
5060
5061 if (tp->dev->mtu <= ETH_DATA_LEN)
5062 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5063
5064 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5065 }
5066
5067 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5068 {
5069 void __iomem *ioaddr = tp->mmio_addr;
5070 struct pci_dev *pdev = tp->pci_dev;
5071
5072 rtl_csi_access_enable_1(tp);
5073
5074 if (tp->dev->mtu <= ETH_DATA_LEN)
5075 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5076
5077 RTL_W8(MaxTxPacketSize, TxPacketMax);
5078
5079 rtl_disable_clock_request(pdev);
5080 }
5081
5082 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5083 {
5084 void __iomem *ioaddr = tp->mmio_addr;
5085 struct pci_dev *pdev = tp->pci_dev;
5086 static const struct ephy_info e_info_8168d_4[] = {
5087 { 0x0b, ~0, 0x48 },
5088 { 0x19, 0x20, 0x50 },
5089 { 0x0c, ~0, 0x20 }
5090 };
5091 int i;
5092
5093 rtl_csi_access_enable_1(tp);
5094
5095 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5096
5097 RTL_W8(MaxTxPacketSize, TxPacketMax);
5098
5099 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5100 const struct ephy_info *e = e_info_8168d_4 + i;
5101 u16 w;
5102
5103 w = rtl_ephy_read(tp, e->offset);
5104 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5105 }
5106
5107 rtl_enable_clock_request(pdev);
5108 }
5109
5110 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5111 {
5112 void __iomem *ioaddr = tp->mmio_addr;
5113 struct pci_dev *pdev = tp->pci_dev;
5114 static const struct ephy_info e_info_8168e_1[] = {
5115 { 0x00, 0x0200, 0x0100 },
5116 { 0x00, 0x0000, 0x0004 },
5117 { 0x06, 0x0002, 0x0001 },
5118 { 0x06, 0x0000, 0x0030 },
5119 { 0x07, 0x0000, 0x2000 },
5120 { 0x00, 0x0000, 0x0020 },
5121 { 0x03, 0x5800, 0x2000 },
5122 { 0x03, 0x0000, 0x0001 },
5123 { 0x01, 0x0800, 0x1000 },
5124 { 0x07, 0x0000, 0x4000 },
5125 { 0x1e, 0x0000, 0x2000 },
5126 { 0x19, 0xffff, 0xfe6c },
5127 { 0x0a, 0x0000, 0x0040 }
5128 };
5129
5130 rtl_csi_access_enable_2(tp);
5131
5132 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5133
5134 if (tp->dev->mtu <= ETH_DATA_LEN)
5135 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5136
5137 RTL_W8(MaxTxPacketSize, TxPacketMax);
5138
5139 rtl_disable_clock_request(pdev);
5140
5141 /* Reset tx FIFO pointer */
5142 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5143 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5144
5145 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5146 }
5147
5148 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5149 {
5150 void __iomem *ioaddr = tp->mmio_addr;
5151 struct pci_dev *pdev = tp->pci_dev;
5152 static const struct ephy_info e_info_8168e_2[] = {
5153 { 0x09, 0x0000, 0x0080 },
5154 { 0x19, 0x0000, 0x0224 }
5155 };
5156
5157 rtl_csi_access_enable_1(tp);
5158
5159 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5160
5161 if (tp->dev->mtu <= ETH_DATA_LEN)
5162 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5163
5164 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5165 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5166 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5167 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5168 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5169 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5170 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5171 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5172
5173 RTL_W8(MaxTxPacketSize, EarlySize);
5174
5175 rtl_disable_clock_request(pdev);
5176
5177 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5178 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5179
5180 /* Adjust EEE LED frequency */
5181 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5182
5183 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5184 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5185 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5186 }
5187
5188 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5189 {
5190 void __iomem *ioaddr = tp->mmio_addr;
5191 struct pci_dev *pdev = tp->pci_dev;
5192
5193 rtl_csi_access_enable_2(tp);
5194
5195 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5196
5197 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5198 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5199 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5200 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5201 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5202 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5203 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5204 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5205 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5206 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5207
5208 RTL_W8(MaxTxPacketSize, EarlySize);
5209
5210 rtl_disable_clock_request(pdev);
5211
5212 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5213 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5214 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5215 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5216 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5217 }
5218
5219 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5220 {
5221 void __iomem *ioaddr = tp->mmio_addr;
5222 static const struct ephy_info e_info_8168f_1[] = {
5223 { 0x06, 0x00c0, 0x0020 },
5224 { 0x08, 0x0001, 0x0002 },
5225 { 0x09, 0x0000, 0x0080 },
5226 { 0x19, 0x0000, 0x0224 }
5227 };
5228
5229 rtl_hw_start_8168f(tp);
5230
5231 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5232
5233 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5234
5235 /* Adjust EEE LED frequency */
5236 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5237 }
5238
5239 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5240 {
5241 static const struct ephy_info e_info_8168f_1[] = {
5242 { 0x06, 0x00c0, 0x0020 },
5243 { 0x0f, 0xffff, 0x5200 },
5244 { 0x1e, 0x0000, 0x4000 },
5245 { 0x19, 0x0000, 0x0224 }
5246 };
5247
5248 rtl_hw_start_8168f(tp);
5249
5250 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5251
5252 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5253 }
5254
5255 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5256 {
5257 void __iomem *ioaddr = tp->mmio_addr;
5258 struct pci_dev *pdev = tp->pci_dev;
5259
5260 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5261
5262 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5263 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5264 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5265 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5266
5267 rtl_csi_access_enable_1(tp);
5268
5269 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5270
5271 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5272 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5273 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5274
5275 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5276 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5277 RTL_W8(MaxTxPacketSize, EarlySize);
5278
5279 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5280 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5281
5282 /* Adjust EEE LED frequency */
5283 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5284
5285 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5286 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5287 }
5288
5289 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5290 {
5291 void __iomem *ioaddr = tp->mmio_addr;
5292 static const struct ephy_info e_info_8168g_2[] = {
5293 { 0x00, 0x0000, 0x0008 },
5294 { 0x0c, 0x3df0, 0x0200 },
5295 { 0x19, 0xffff, 0xfc00 },
5296 { 0x1e, 0xffff, 0x20eb }
5297 };
5298
5299 rtl_hw_start_8168g_1(tp);
5300
5301 /* disable aspm and clock request before access ephy */
5302 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5303 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5304 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5305 }
5306
5307 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5308 {
5309 void __iomem *ioaddr = tp->mmio_addr;
5310 static const struct ephy_info e_info_8411_2[] = {
5311 { 0x00, 0x0000, 0x0008 },
5312 { 0x0c, 0x3df0, 0x0200 },
5313 { 0x0f, 0xffff, 0x5200 },
5314 { 0x19, 0x0020, 0x0000 },
5315 { 0x1e, 0x0000, 0x2000 }
5316 };
5317
5318 rtl_hw_start_8168g_1(tp);
5319
5320 /* disable aspm and clock request before access ephy */
5321 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5322 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5323 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5324 }
5325
5326 static void rtl_hw_start_8168(struct net_device *dev)
5327 {
5328 struct rtl8169_private *tp = netdev_priv(dev);
5329 void __iomem *ioaddr = tp->mmio_addr;
5330
5331 RTL_W8(Cfg9346, Cfg9346_Unlock);
5332
5333 RTL_W8(MaxTxPacketSize, TxPacketMax);
5334
5335 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5336
5337 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5338
5339 RTL_W16(CPlusCmd, tp->cp_cmd);
5340
5341 RTL_W16(IntrMitigate, 0x5151);
5342
5343 /* Work around for RxFIFO overflow. */
5344 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5345 tp->event_slow |= RxFIFOOver | PCSTimeout;
5346 tp->event_slow &= ~RxOverflow;
5347 }
5348
5349 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5350
5351 rtl_set_rx_tx_config_registers(tp);
5352
5353 RTL_R8(IntrMask);
5354
5355 switch (tp->mac_version) {
5356 case RTL_GIGA_MAC_VER_11:
5357 rtl_hw_start_8168bb(tp);
5358 break;
5359
5360 case RTL_GIGA_MAC_VER_12:
5361 case RTL_GIGA_MAC_VER_17:
5362 rtl_hw_start_8168bef(tp);
5363 break;
5364
5365 case RTL_GIGA_MAC_VER_18:
5366 rtl_hw_start_8168cp_1(tp);
5367 break;
5368
5369 case RTL_GIGA_MAC_VER_19:
5370 rtl_hw_start_8168c_1(tp);
5371 break;
5372
5373 case RTL_GIGA_MAC_VER_20:
5374 rtl_hw_start_8168c_2(tp);
5375 break;
5376
5377 case RTL_GIGA_MAC_VER_21:
5378 rtl_hw_start_8168c_3(tp);
5379 break;
5380
5381 case RTL_GIGA_MAC_VER_22:
5382 rtl_hw_start_8168c_4(tp);
5383 break;
5384
5385 case RTL_GIGA_MAC_VER_23:
5386 rtl_hw_start_8168cp_2(tp);
5387 break;
5388
5389 case RTL_GIGA_MAC_VER_24:
5390 rtl_hw_start_8168cp_3(tp);
5391 break;
5392
5393 case RTL_GIGA_MAC_VER_25:
5394 case RTL_GIGA_MAC_VER_26:
5395 case RTL_GIGA_MAC_VER_27:
5396 rtl_hw_start_8168d(tp);
5397 break;
5398
5399 case RTL_GIGA_MAC_VER_28:
5400 rtl_hw_start_8168d_4(tp);
5401 break;
5402
5403 case RTL_GIGA_MAC_VER_31:
5404 rtl_hw_start_8168dp(tp);
5405 break;
5406
5407 case RTL_GIGA_MAC_VER_32:
5408 case RTL_GIGA_MAC_VER_33:
5409 rtl_hw_start_8168e_1(tp);
5410 break;
5411 case RTL_GIGA_MAC_VER_34:
5412 rtl_hw_start_8168e_2(tp);
5413 break;
5414
5415 case RTL_GIGA_MAC_VER_35:
5416 case RTL_GIGA_MAC_VER_36:
5417 rtl_hw_start_8168f_1(tp);
5418 break;
5419
5420 case RTL_GIGA_MAC_VER_38:
5421 rtl_hw_start_8411(tp);
5422 break;
5423
5424 case RTL_GIGA_MAC_VER_40:
5425 case RTL_GIGA_MAC_VER_41:
5426 rtl_hw_start_8168g_1(tp);
5427 break;
5428 case RTL_GIGA_MAC_VER_42:
5429 rtl_hw_start_8168g_2(tp);
5430 break;
5431
5432 case RTL_GIGA_MAC_VER_44:
5433 rtl_hw_start_8411_2(tp);
5434 break;
5435
5436 default:
5437 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5438 dev->name, tp->mac_version);
5439 break;
5440 }
5441
5442 RTL_W8(Cfg9346, Cfg9346_Lock);
5443
5444 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5445
5446 rtl_set_rx_mode(dev);
5447
5448 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5449 }
5450
5451 #define R810X_CPCMD_QUIRK_MASK (\
5452 EnableBist | \
5453 Mac_dbgo_oe | \
5454 Force_half_dup | \
5455 Force_rxflow_en | \
5456 Force_txflow_en | \
5457 Cxpl_dbg_sel | \
5458 ASF | \
5459 PktCntrDisable | \
5460 Mac_dbgo_sel)
5461
5462 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5463 {
5464 void __iomem *ioaddr = tp->mmio_addr;
5465 struct pci_dev *pdev = tp->pci_dev;
5466 static const struct ephy_info e_info_8102e_1[] = {
5467 { 0x01, 0, 0x6e65 },
5468 { 0x02, 0, 0x091f },
5469 { 0x03, 0, 0xc2f9 },
5470 { 0x06, 0, 0xafb5 },
5471 { 0x07, 0, 0x0e00 },
5472 { 0x19, 0, 0xec80 },
5473 { 0x01, 0, 0x2e65 },
5474 { 0x01, 0, 0x6e65 }
5475 };
5476 u8 cfg1;
5477
5478 rtl_csi_access_enable_2(tp);
5479
5480 RTL_W8(DBG_REG, FIX_NAK_1);
5481
5482 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5483
5484 RTL_W8(Config1,
5485 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5486 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5487
5488 cfg1 = RTL_R8(Config1);
5489 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5490 RTL_W8(Config1, cfg1 & ~LEDS0);
5491
5492 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5493 }
5494
5495 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5496 {
5497 void __iomem *ioaddr = tp->mmio_addr;
5498 struct pci_dev *pdev = tp->pci_dev;
5499
5500 rtl_csi_access_enable_2(tp);
5501
5502 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5503
5504 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5505 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5506 }
5507
5508 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5509 {
5510 rtl_hw_start_8102e_2(tp);
5511
5512 rtl_ephy_write(tp, 0x03, 0xc2f9);
5513 }
5514
5515 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5516 {
5517 void __iomem *ioaddr = tp->mmio_addr;
5518 static const struct ephy_info e_info_8105e_1[] = {
5519 { 0x07, 0, 0x4000 },
5520 { 0x19, 0, 0x0200 },
5521 { 0x19, 0, 0x0020 },
5522 { 0x1e, 0, 0x2000 },
5523 { 0x03, 0, 0x0001 },
5524 { 0x19, 0, 0x0100 },
5525 { 0x19, 0, 0x0004 },
5526 { 0x0a, 0, 0x0020 }
5527 };
5528
5529 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5530 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5531
5532 /* Disable Early Tally Counter */
5533 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5534
5535 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5536 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5537
5538 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5539 }
5540
5541 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5542 {
5543 rtl_hw_start_8105e_1(tp);
5544 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5545 }
5546
5547 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5548 {
5549 void __iomem *ioaddr = tp->mmio_addr;
5550 static const struct ephy_info e_info_8402[] = {
5551 { 0x19, 0xffff, 0xff64 },
5552 { 0x1e, 0, 0x4000 }
5553 };
5554
5555 rtl_csi_access_enable_2(tp);
5556
5557 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5558 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5559
5560 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5561 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5562
5563 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5564
5565 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5566
5567 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5568 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5569 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5570 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5571 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5572 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5573 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5574 }
5575
5576 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5577 {
5578 void __iomem *ioaddr = tp->mmio_addr;
5579
5580 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5581 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5582
5583 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5584 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5585 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5586 }
5587
5588 static void rtl_hw_start_8101(struct net_device *dev)
5589 {
5590 struct rtl8169_private *tp = netdev_priv(dev);
5591 void __iomem *ioaddr = tp->mmio_addr;
5592 struct pci_dev *pdev = tp->pci_dev;
5593
5594 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5595 tp->event_slow &= ~RxFIFOOver;
5596
5597 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5598 tp->mac_version == RTL_GIGA_MAC_VER_16)
5599 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5600 PCI_EXP_DEVCTL_NOSNOOP_EN);
5601
5602 RTL_W8(Cfg9346, Cfg9346_Unlock);
5603
5604 RTL_W8(MaxTxPacketSize, TxPacketMax);
5605
5606 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5607
5608 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5609 RTL_W16(CPlusCmd, tp->cp_cmd);
5610
5611 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5612
5613 rtl_set_rx_tx_config_registers(tp);
5614
5615 switch (tp->mac_version) {
5616 case RTL_GIGA_MAC_VER_07:
5617 rtl_hw_start_8102e_1(tp);
5618 break;
5619
5620 case RTL_GIGA_MAC_VER_08:
5621 rtl_hw_start_8102e_3(tp);
5622 break;
5623
5624 case RTL_GIGA_MAC_VER_09:
5625 rtl_hw_start_8102e_2(tp);
5626 break;
5627
5628 case RTL_GIGA_MAC_VER_29:
5629 rtl_hw_start_8105e_1(tp);
5630 break;
5631 case RTL_GIGA_MAC_VER_30:
5632 rtl_hw_start_8105e_2(tp);
5633 break;
5634
5635 case RTL_GIGA_MAC_VER_37:
5636 rtl_hw_start_8402(tp);
5637 break;
5638
5639 case RTL_GIGA_MAC_VER_39:
5640 rtl_hw_start_8106(tp);
5641 break;
5642 case RTL_GIGA_MAC_VER_43:
5643 rtl_hw_start_8168g_2(tp);
5644 break;
5645 }
5646
5647 RTL_W8(Cfg9346, Cfg9346_Lock);
5648
5649 RTL_W16(IntrMitigate, 0x0000);
5650
5651 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5652
5653 rtl_set_rx_mode(dev);
5654
5655 RTL_R8(IntrMask);
5656
5657 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5658 }
5659
5660 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5661 {
5662 struct rtl8169_private *tp = netdev_priv(dev);
5663
5664 if (new_mtu < ETH_ZLEN ||
5665 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5666 return -EINVAL;
5667
5668 if (new_mtu > ETH_DATA_LEN)
5669 rtl_hw_jumbo_enable(tp);
5670 else
5671 rtl_hw_jumbo_disable(tp);
5672
5673 dev->mtu = new_mtu;
5674 netdev_update_features(dev);
5675
5676 return 0;
5677 }
5678
5679 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5680 {
5681 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5682 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5683 }
5684
5685 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5686 void **data_buff, struct RxDesc *desc)
5687 {
5688 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5689 DMA_FROM_DEVICE);
5690
5691 kfree(*data_buff);
5692 *data_buff = NULL;
5693 rtl8169_make_unusable_by_asic(desc);
5694 }
5695
5696 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5697 {
5698 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5699
5700 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5701 }
5702
5703 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5704 u32 rx_buf_sz)
5705 {
5706 desc->addr = cpu_to_le64(mapping);
5707 wmb();
5708 rtl8169_mark_to_asic(desc, rx_buf_sz);
5709 }
5710
5711 static inline void *rtl8169_align(void *data)
5712 {
5713 return (void *)ALIGN((long)data, 16);
5714 }
5715
5716 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5717 struct RxDesc *desc)
5718 {
5719 void *data;
5720 dma_addr_t mapping;
5721 struct device *d = &tp->pci_dev->dev;
5722 struct net_device *dev = tp->dev;
5723 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5724
5725 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5726 if (!data)
5727 return NULL;
5728
5729 if (rtl8169_align(data) != data) {
5730 kfree(data);
5731 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5732 if (!data)
5733 return NULL;
5734 }
5735
5736 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5737 DMA_FROM_DEVICE);
5738 if (unlikely(dma_mapping_error(d, mapping))) {
5739 if (net_ratelimit())
5740 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5741 goto err_out;
5742 }
5743
5744 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5745 return data;
5746
5747 err_out:
5748 kfree(data);
5749 return NULL;
5750 }
5751
5752 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5753 {
5754 unsigned int i;
5755
5756 for (i = 0; i < NUM_RX_DESC; i++) {
5757 if (tp->Rx_databuff[i]) {
5758 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5759 tp->RxDescArray + i);
5760 }
5761 }
5762 }
5763
5764 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5765 {
5766 desc->opts1 |= cpu_to_le32(RingEnd);
5767 }
5768
5769 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5770 {
5771 unsigned int i;
5772
5773 for (i = 0; i < NUM_RX_DESC; i++) {
5774 void *data;
5775
5776 if (tp->Rx_databuff[i])
5777 continue;
5778
5779 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5780 if (!data) {
5781 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5782 goto err_out;
5783 }
5784 tp->Rx_databuff[i] = data;
5785 }
5786
5787 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5788 return 0;
5789
5790 err_out:
5791 rtl8169_rx_clear(tp);
5792 return -ENOMEM;
5793 }
5794
5795 static int rtl8169_init_ring(struct net_device *dev)
5796 {
5797 struct rtl8169_private *tp = netdev_priv(dev);
5798
5799 rtl8169_init_ring_indexes(tp);
5800
5801 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5802 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5803
5804 return rtl8169_rx_fill(tp);
5805 }
5806
5807 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5808 struct TxDesc *desc)
5809 {
5810 unsigned int len = tx_skb->len;
5811
5812 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5813
5814 desc->opts1 = 0x00;
5815 desc->opts2 = 0x00;
5816 desc->addr = 0x00;
5817 tx_skb->len = 0;
5818 }
5819
5820 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5821 unsigned int n)
5822 {
5823 unsigned int i;
5824
5825 for (i = 0; i < n; i++) {
5826 unsigned int entry = (start + i) % NUM_TX_DESC;
5827 struct ring_info *tx_skb = tp->tx_skb + entry;
5828 unsigned int len = tx_skb->len;
5829
5830 if (len) {
5831 struct sk_buff *skb = tx_skb->skb;
5832
5833 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5834 tp->TxDescArray + entry);
5835 if (skb) {
5836 tp->dev->stats.tx_dropped++;
5837 dev_kfree_skb(skb);
5838 tx_skb->skb = NULL;
5839 }
5840 }
5841 }
5842 }
5843
5844 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5845 {
5846 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5847 tp->cur_tx = tp->dirty_tx = 0;
5848 }
5849
5850 static void rtl_reset_work(struct rtl8169_private *tp)
5851 {
5852 struct net_device *dev = tp->dev;
5853 int i;
5854
5855 napi_disable(&tp->napi);
5856 netif_stop_queue(dev);
5857 synchronize_sched();
5858
5859 rtl8169_hw_reset(tp);
5860
5861 for (i = 0; i < NUM_RX_DESC; i++)
5862 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5863
5864 rtl8169_tx_clear(tp);
5865 rtl8169_init_ring_indexes(tp);
5866
5867 napi_enable(&tp->napi);
5868 rtl_hw_start(dev);
5869 netif_wake_queue(dev);
5870 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5871 }
5872
5873 static void rtl8169_tx_timeout(struct net_device *dev)
5874 {
5875 struct rtl8169_private *tp = netdev_priv(dev);
5876
5877 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5878 }
5879
5880 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5881 u32 *opts)
5882 {
5883 struct skb_shared_info *info = skb_shinfo(skb);
5884 unsigned int cur_frag, entry;
5885 struct TxDesc * uninitialized_var(txd);
5886 struct device *d = &tp->pci_dev->dev;
5887
5888 entry = tp->cur_tx;
5889 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5890 const skb_frag_t *frag = info->frags + cur_frag;
5891 dma_addr_t mapping;
5892 u32 status, len;
5893 void *addr;
5894
5895 entry = (entry + 1) % NUM_TX_DESC;
5896
5897 txd = tp->TxDescArray + entry;
5898 len = skb_frag_size(frag);
5899 addr = skb_frag_address(frag);
5900 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5901 if (unlikely(dma_mapping_error(d, mapping))) {
5902 if (net_ratelimit())
5903 netif_err(tp, drv, tp->dev,
5904 "Failed to map TX fragments DMA!\n");
5905 goto err_out;
5906 }
5907
5908 /* Anti gcc 2.95.3 bugware (sic) */
5909 status = opts[0] | len |
5910 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5911
5912 txd->opts1 = cpu_to_le32(status);
5913 txd->opts2 = cpu_to_le32(opts[1]);
5914 txd->addr = cpu_to_le64(mapping);
5915
5916 tp->tx_skb[entry].len = len;
5917 }
5918
5919 if (cur_frag) {
5920 tp->tx_skb[entry].skb = skb;
5921 txd->opts1 |= cpu_to_le32(LastFrag);
5922 }
5923
5924 return cur_frag;
5925
5926 err_out:
5927 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5928 return -EIO;
5929 }
5930
5931 static bool rtl_skb_pad(struct sk_buff *skb)
5932 {
5933 if (skb_padto(skb, ETH_ZLEN))
5934 return false;
5935 skb_put(skb, ETH_ZLEN - skb->len);
5936 return true;
5937 }
5938
5939 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5940 {
5941 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5942 }
5943
5944 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5945 struct sk_buff *skb, u32 *opts)
5946 {
5947 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5948 u32 mss = skb_shinfo(skb)->gso_size;
5949 int offset = info->opts_offset;
5950
5951 if (mss) {
5952 opts[0] |= TD_LSO;
5953 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5954 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5955 const struct iphdr *ip = ip_hdr(skb);
5956
5957 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5958 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5959
5960 if (ip->protocol == IPPROTO_TCP)
5961 opts[offset] |= info->checksum.tcp;
5962 else if (ip->protocol == IPPROTO_UDP)
5963 opts[offset] |= info->checksum.udp;
5964 else
5965 WARN_ON_ONCE(1);
5966 } else {
5967 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5968 return rtl_skb_pad(skb);
5969 }
5970 return true;
5971 }
5972
5973 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5974 struct net_device *dev)
5975 {
5976 struct rtl8169_private *tp = netdev_priv(dev);
5977 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5978 struct TxDesc *txd = tp->TxDescArray + entry;
5979 void __iomem *ioaddr = tp->mmio_addr;
5980 struct device *d = &tp->pci_dev->dev;
5981 dma_addr_t mapping;
5982 u32 status, len;
5983 u32 opts[2];
5984 int frags;
5985
5986 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5987 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5988 goto err_stop_0;
5989 }
5990
5991 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5992 goto err_stop_0;
5993
5994 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5995 opts[0] = DescOwn;
5996
5997 if (!rtl8169_tso_csum(tp, skb, opts))
5998 goto err_update_stats;
5999
6000 len = skb_headlen(skb);
6001 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6002 if (unlikely(dma_mapping_error(d, mapping))) {
6003 if (net_ratelimit())
6004 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6005 goto err_dma_0;
6006 }
6007
6008 tp->tx_skb[entry].len = len;
6009 txd->addr = cpu_to_le64(mapping);
6010
6011 frags = rtl8169_xmit_frags(tp, skb, opts);
6012 if (frags < 0)
6013 goto err_dma_1;
6014 else if (frags)
6015 opts[0] |= FirstFrag;
6016 else {
6017 opts[0] |= FirstFrag | LastFrag;
6018 tp->tx_skb[entry].skb = skb;
6019 }
6020
6021 txd->opts2 = cpu_to_le32(opts[1]);
6022
6023 skb_tx_timestamp(skb);
6024
6025 wmb();
6026
6027 /* Anti gcc 2.95.3 bugware (sic) */
6028 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6029 txd->opts1 = cpu_to_le32(status);
6030
6031 tp->cur_tx += frags + 1;
6032
6033 wmb();
6034
6035 RTL_W8(TxPoll, NPQ);
6036
6037 mmiowb();
6038
6039 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6040 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6041 * not miss a ring update when it notices a stopped queue.
6042 */
6043 smp_wmb();
6044 netif_stop_queue(dev);
6045 /* Sync with rtl_tx:
6046 * - publish queue status and cur_tx ring index (write barrier)
6047 * - refresh dirty_tx ring index (read barrier).
6048 * May the current thread have a pessimistic view of the ring
6049 * status and forget to wake up queue, a racing rtl_tx thread
6050 * can't.
6051 */
6052 smp_mb();
6053 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6054 netif_wake_queue(dev);
6055 }
6056
6057 return NETDEV_TX_OK;
6058
6059 err_dma_1:
6060 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6061 err_dma_0:
6062 dev_kfree_skb(skb);
6063 err_update_stats:
6064 dev->stats.tx_dropped++;
6065 return NETDEV_TX_OK;
6066
6067 err_stop_0:
6068 netif_stop_queue(dev);
6069 dev->stats.tx_dropped++;
6070 return NETDEV_TX_BUSY;
6071 }
6072
6073 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6074 {
6075 struct rtl8169_private *tp = netdev_priv(dev);
6076 struct pci_dev *pdev = tp->pci_dev;
6077 u16 pci_status, pci_cmd;
6078
6079 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6080 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6081
6082 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6083 pci_cmd, pci_status);
6084
6085 /*
6086 * The recovery sequence below admits a very elaborated explanation:
6087 * - it seems to work;
6088 * - I did not see what else could be done;
6089 * - it makes iop3xx happy.
6090 *
6091 * Feel free to adjust to your needs.
6092 */
6093 if (pdev->broken_parity_status)
6094 pci_cmd &= ~PCI_COMMAND_PARITY;
6095 else
6096 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6097
6098 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6099
6100 pci_write_config_word(pdev, PCI_STATUS,
6101 pci_status & (PCI_STATUS_DETECTED_PARITY |
6102 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6103 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6104
6105 /* The infamous DAC f*ckup only happens at boot time */
6106 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6107 void __iomem *ioaddr = tp->mmio_addr;
6108
6109 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6110 tp->cp_cmd &= ~PCIDAC;
6111 RTL_W16(CPlusCmd, tp->cp_cmd);
6112 dev->features &= ~NETIF_F_HIGHDMA;
6113 }
6114
6115 rtl8169_hw_reset(tp);
6116
6117 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6118 }
6119
6120 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6121 {
6122 unsigned int dirty_tx, tx_left;
6123
6124 dirty_tx = tp->dirty_tx;
6125 smp_rmb();
6126 tx_left = tp->cur_tx - dirty_tx;
6127
6128 while (tx_left > 0) {
6129 unsigned int entry = dirty_tx % NUM_TX_DESC;
6130 struct ring_info *tx_skb = tp->tx_skb + entry;
6131 u32 status;
6132
6133 rmb();
6134 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6135 if (status & DescOwn)
6136 break;
6137
6138 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6139 tp->TxDescArray + entry);
6140 if (status & LastFrag) {
6141 u64_stats_update_begin(&tp->tx_stats.syncp);
6142 tp->tx_stats.packets++;
6143 tp->tx_stats.bytes += tx_skb->skb->len;
6144 u64_stats_update_end(&tp->tx_stats.syncp);
6145 dev_kfree_skb(tx_skb->skb);
6146 tx_skb->skb = NULL;
6147 }
6148 dirty_tx++;
6149 tx_left--;
6150 }
6151
6152 if (tp->dirty_tx != dirty_tx) {
6153 tp->dirty_tx = dirty_tx;
6154 /* Sync with rtl8169_start_xmit:
6155 * - publish dirty_tx ring index (write barrier)
6156 * - refresh cur_tx ring index and queue status (read barrier)
6157 * May the current thread miss the stopped queue condition,
6158 * a racing xmit thread can only have a right view of the
6159 * ring status.
6160 */
6161 smp_mb();
6162 if (netif_queue_stopped(dev) &&
6163 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6164 netif_wake_queue(dev);
6165 }
6166 /*
6167 * 8168 hack: TxPoll requests are lost when the Tx packets are
6168 * too close. Let's kick an extra TxPoll request when a burst
6169 * of start_xmit activity is detected (if it is not detected,
6170 * it is slow enough). -- FR
6171 */
6172 if (tp->cur_tx != dirty_tx) {
6173 void __iomem *ioaddr = tp->mmio_addr;
6174
6175 RTL_W8(TxPoll, NPQ);
6176 }
6177 }
6178 }
6179
6180 static inline int rtl8169_fragmented_frame(u32 status)
6181 {
6182 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6183 }
6184
6185 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6186 {
6187 u32 status = opts1 & RxProtoMask;
6188
6189 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6190 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6191 skb->ip_summed = CHECKSUM_UNNECESSARY;
6192 else
6193 skb_checksum_none_assert(skb);
6194 }
6195
6196 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6197 struct rtl8169_private *tp,
6198 int pkt_size,
6199 dma_addr_t addr)
6200 {
6201 struct sk_buff *skb;
6202 struct device *d = &tp->pci_dev->dev;
6203
6204 data = rtl8169_align(data);
6205 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6206 prefetch(data);
6207 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6208 if (skb)
6209 memcpy(skb->data, data, pkt_size);
6210 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6211
6212 return skb;
6213 }
6214
6215 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6216 {
6217 unsigned int cur_rx, rx_left;
6218 unsigned int count;
6219
6220 cur_rx = tp->cur_rx;
6221
6222 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6223 unsigned int entry = cur_rx % NUM_RX_DESC;
6224 struct RxDesc *desc = tp->RxDescArray + entry;
6225 u32 status;
6226
6227 rmb();
6228 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6229
6230 if (status & DescOwn)
6231 break;
6232 if (unlikely(status & RxRES)) {
6233 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6234 status);
6235 dev->stats.rx_errors++;
6236 if (status & (RxRWT | RxRUNT))
6237 dev->stats.rx_length_errors++;
6238 if (status & RxCRC)
6239 dev->stats.rx_crc_errors++;
6240 if (status & RxFOVF) {
6241 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6242 dev->stats.rx_fifo_errors++;
6243 }
6244 if ((status & (RxRUNT | RxCRC)) &&
6245 !(status & (RxRWT | RxFOVF)) &&
6246 (dev->features & NETIF_F_RXALL))
6247 goto process_pkt;
6248 } else {
6249 struct sk_buff *skb;
6250 dma_addr_t addr;
6251 int pkt_size;
6252
6253 process_pkt:
6254 addr = le64_to_cpu(desc->addr);
6255 if (likely(!(dev->features & NETIF_F_RXFCS)))
6256 pkt_size = (status & 0x00003fff) - 4;
6257 else
6258 pkt_size = status & 0x00003fff;
6259
6260 /*
6261 * The driver does not support incoming fragmented
6262 * frames. They are seen as a symptom of over-mtu
6263 * sized frames.
6264 */
6265 if (unlikely(rtl8169_fragmented_frame(status))) {
6266 dev->stats.rx_dropped++;
6267 dev->stats.rx_length_errors++;
6268 goto release_descriptor;
6269 }
6270
6271 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6272 tp, pkt_size, addr);
6273 if (!skb) {
6274 dev->stats.rx_dropped++;
6275 goto release_descriptor;
6276 }
6277
6278 rtl8169_rx_csum(skb, status);
6279 skb_put(skb, pkt_size);
6280 skb->protocol = eth_type_trans(skb, dev);
6281
6282 rtl8169_rx_vlan_tag(desc, skb);
6283
6284 napi_gro_receive(&tp->napi, skb);
6285
6286 u64_stats_update_begin(&tp->rx_stats.syncp);
6287 tp->rx_stats.packets++;
6288 tp->rx_stats.bytes += pkt_size;
6289 u64_stats_update_end(&tp->rx_stats.syncp);
6290 }
6291 release_descriptor:
6292 desc->opts2 = 0;
6293 wmb();
6294 rtl8169_mark_to_asic(desc, rx_buf_sz);
6295 }
6296
6297 count = cur_rx - tp->cur_rx;
6298 tp->cur_rx = cur_rx;
6299
6300 return count;
6301 }
6302
6303 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6304 {
6305 struct net_device *dev = dev_instance;
6306 struct rtl8169_private *tp = netdev_priv(dev);
6307 int handled = 0;
6308 u16 status;
6309
6310 status = rtl_get_events(tp);
6311 if (status && status != 0xffff) {
6312 status &= RTL_EVENT_NAPI | tp->event_slow;
6313 if (status) {
6314 handled = 1;
6315
6316 rtl_irq_disable(tp);
6317 napi_schedule(&tp->napi);
6318 }
6319 }
6320 return IRQ_RETVAL(handled);
6321 }
6322
6323 /*
6324 * Workqueue context.
6325 */
6326 static void rtl_slow_event_work(struct rtl8169_private *tp)
6327 {
6328 struct net_device *dev = tp->dev;
6329 u16 status;
6330
6331 status = rtl_get_events(tp) & tp->event_slow;
6332 rtl_ack_events(tp, status);
6333
6334 if (unlikely(status & RxFIFOOver)) {
6335 switch (tp->mac_version) {
6336 /* Work around for rx fifo overflow */
6337 case RTL_GIGA_MAC_VER_11:
6338 netif_stop_queue(dev);
6339 /* XXX - Hack alert. See rtl_task(). */
6340 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6341 default:
6342 break;
6343 }
6344 }
6345
6346 if (unlikely(status & SYSErr))
6347 rtl8169_pcierr_interrupt(dev);
6348
6349 if (status & LinkChg)
6350 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6351
6352 rtl_irq_enable_all(tp);
6353 }
6354
6355 static void rtl_task(struct work_struct *work)
6356 {
6357 static const struct {
6358 int bitnr;
6359 void (*action)(struct rtl8169_private *);
6360 } rtl_work[] = {
6361 /* XXX - keep rtl_slow_event_work() as first element. */
6362 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6363 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6364 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6365 };
6366 struct rtl8169_private *tp =
6367 container_of(work, struct rtl8169_private, wk.work);
6368 struct net_device *dev = tp->dev;
6369 int i;
6370
6371 rtl_lock_work(tp);
6372
6373 if (!netif_running(dev) ||
6374 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6375 goto out_unlock;
6376
6377 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6378 bool pending;
6379
6380 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6381 if (pending)
6382 rtl_work[i].action(tp);
6383 }
6384
6385 out_unlock:
6386 rtl_unlock_work(tp);
6387 }
6388
6389 static int rtl8169_poll(struct napi_struct *napi, int budget)
6390 {
6391 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6392 struct net_device *dev = tp->dev;
6393 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6394 int work_done= 0;
6395 u16 status;
6396
6397 status = rtl_get_events(tp);
6398 rtl_ack_events(tp, status & ~tp->event_slow);
6399
6400 if (status & RTL_EVENT_NAPI_RX)
6401 work_done = rtl_rx(dev, tp, (u32) budget);
6402
6403 if (status & RTL_EVENT_NAPI_TX)
6404 rtl_tx(dev, tp);
6405
6406 if (status & tp->event_slow) {
6407 enable_mask &= ~tp->event_slow;
6408
6409 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6410 }
6411
6412 if (work_done < budget) {
6413 napi_complete(napi);
6414
6415 rtl_irq_enable(tp, enable_mask);
6416 mmiowb();
6417 }
6418
6419 return work_done;
6420 }
6421
6422 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6423 {
6424 struct rtl8169_private *tp = netdev_priv(dev);
6425
6426 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6427 return;
6428
6429 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6430 RTL_W32(RxMissed, 0);
6431 }
6432
6433 static void rtl8169_down(struct net_device *dev)
6434 {
6435 struct rtl8169_private *tp = netdev_priv(dev);
6436 void __iomem *ioaddr = tp->mmio_addr;
6437
6438 del_timer_sync(&tp->timer);
6439
6440 napi_disable(&tp->napi);
6441 netif_stop_queue(dev);
6442
6443 rtl8169_hw_reset(tp);
6444 /*
6445 * At this point device interrupts can not be enabled in any function,
6446 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6447 * and napi is disabled (rtl8169_poll).
6448 */
6449 rtl8169_rx_missed(dev, ioaddr);
6450
6451 /* Give a racing hard_start_xmit a few cycles to complete. */
6452 synchronize_sched();
6453
6454 rtl8169_tx_clear(tp);
6455
6456 rtl8169_rx_clear(tp);
6457
6458 rtl_pll_power_down(tp);
6459 }
6460
6461 static int rtl8169_close(struct net_device *dev)
6462 {
6463 struct rtl8169_private *tp = netdev_priv(dev);
6464 struct pci_dev *pdev = tp->pci_dev;
6465
6466 pm_runtime_get_sync(&pdev->dev);
6467
6468 /* Update counters before going down */
6469 rtl8169_update_counters(dev);
6470
6471 rtl_lock_work(tp);
6472 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6473
6474 rtl8169_down(dev);
6475 rtl_unlock_work(tp);
6476
6477 cancel_work_sync(&tp->wk.work);
6478
6479 free_irq(pdev->irq, dev);
6480
6481 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6482 tp->RxPhyAddr);
6483 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6484 tp->TxPhyAddr);
6485 tp->TxDescArray = NULL;
6486 tp->RxDescArray = NULL;
6487
6488 pm_runtime_put_sync(&pdev->dev);
6489
6490 return 0;
6491 }
6492
6493 #ifdef CONFIG_NET_POLL_CONTROLLER
6494 static void rtl8169_netpoll(struct net_device *dev)
6495 {
6496 struct rtl8169_private *tp = netdev_priv(dev);
6497
6498 rtl8169_interrupt(tp->pci_dev->irq, dev);
6499 }
6500 #endif
6501
6502 static int rtl_open(struct net_device *dev)
6503 {
6504 struct rtl8169_private *tp = netdev_priv(dev);
6505 void __iomem *ioaddr = tp->mmio_addr;
6506 struct pci_dev *pdev = tp->pci_dev;
6507 int retval = -ENOMEM;
6508
6509 pm_runtime_get_sync(&pdev->dev);
6510
6511 /*
6512 * Rx and Tx descriptors needs 256 bytes alignment.
6513 * dma_alloc_coherent provides more.
6514 */
6515 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6516 &tp->TxPhyAddr, GFP_KERNEL);
6517 if (!tp->TxDescArray)
6518 goto err_pm_runtime_put;
6519
6520 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6521 &tp->RxPhyAddr, GFP_KERNEL);
6522 if (!tp->RxDescArray)
6523 goto err_free_tx_0;
6524
6525 retval = rtl8169_init_ring(dev);
6526 if (retval < 0)
6527 goto err_free_rx_1;
6528
6529 INIT_WORK(&tp->wk.work, rtl_task);
6530
6531 smp_mb();
6532
6533 rtl_request_firmware(tp);
6534
6535 retval = request_irq(pdev->irq, rtl8169_interrupt,
6536 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6537 dev->name, dev);
6538 if (retval < 0)
6539 goto err_release_fw_2;
6540
6541 rtl_lock_work(tp);
6542
6543 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6544
6545 napi_enable(&tp->napi);
6546
6547 rtl8169_init_phy(dev, tp);
6548
6549 __rtl8169_set_features(dev, dev->features);
6550
6551 rtl_pll_power_up(tp);
6552
6553 rtl_hw_start(dev);
6554
6555 netif_start_queue(dev);
6556
6557 rtl_unlock_work(tp);
6558
6559 tp->saved_wolopts = 0;
6560 pm_runtime_put_noidle(&pdev->dev);
6561
6562 rtl8169_check_link_status(dev, tp, ioaddr);
6563 out:
6564 return retval;
6565
6566 err_release_fw_2:
6567 rtl_release_firmware(tp);
6568 rtl8169_rx_clear(tp);
6569 err_free_rx_1:
6570 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6571 tp->RxPhyAddr);
6572 tp->RxDescArray = NULL;
6573 err_free_tx_0:
6574 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6575 tp->TxPhyAddr);
6576 tp->TxDescArray = NULL;
6577 err_pm_runtime_put:
6578 pm_runtime_put_noidle(&pdev->dev);
6579 goto out;
6580 }
6581
6582 static struct rtnl_link_stats64 *
6583 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6584 {
6585 struct rtl8169_private *tp = netdev_priv(dev);
6586 void __iomem *ioaddr = tp->mmio_addr;
6587 unsigned int start;
6588
6589 if (netif_running(dev))
6590 rtl8169_rx_missed(dev, ioaddr);
6591
6592 do {
6593 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6594 stats->rx_packets = tp->rx_stats.packets;
6595 stats->rx_bytes = tp->rx_stats.bytes;
6596 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6597
6598
6599 do {
6600 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6601 stats->tx_packets = tp->tx_stats.packets;
6602 stats->tx_bytes = tp->tx_stats.bytes;
6603 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6604
6605 stats->rx_dropped = dev->stats.rx_dropped;
6606 stats->tx_dropped = dev->stats.tx_dropped;
6607 stats->rx_length_errors = dev->stats.rx_length_errors;
6608 stats->rx_errors = dev->stats.rx_errors;
6609 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6610 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6611 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6612
6613 return stats;
6614 }
6615
6616 static void rtl8169_net_suspend(struct net_device *dev)
6617 {
6618 struct rtl8169_private *tp = netdev_priv(dev);
6619
6620 if (!netif_running(dev))
6621 return;
6622
6623 netif_device_detach(dev);
6624 netif_stop_queue(dev);
6625
6626 rtl_lock_work(tp);
6627 napi_disable(&tp->napi);
6628 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6629 rtl_unlock_work(tp);
6630
6631 rtl_pll_power_down(tp);
6632 }
6633
6634 #ifdef CONFIG_PM
6635
6636 static int rtl8169_suspend(struct device *device)
6637 {
6638 struct pci_dev *pdev = to_pci_dev(device);
6639 struct net_device *dev = pci_get_drvdata(pdev);
6640
6641 rtl8169_net_suspend(dev);
6642
6643 return 0;
6644 }
6645
6646 static void __rtl8169_resume(struct net_device *dev)
6647 {
6648 struct rtl8169_private *tp = netdev_priv(dev);
6649
6650 netif_device_attach(dev);
6651
6652 rtl_pll_power_up(tp);
6653
6654 rtl_lock_work(tp);
6655 napi_enable(&tp->napi);
6656 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6657 rtl_unlock_work(tp);
6658
6659 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6660 }
6661
6662 static int rtl8169_resume(struct device *device)
6663 {
6664 struct pci_dev *pdev = to_pci_dev(device);
6665 struct net_device *dev = pci_get_drvdata(pdev);
6666 struct rtl8169_private *tp = netdev_priv(dev);
6667
6668 rtl8169_init_phy(dev, tp);
6669
6670 if (netif_running(dev))
6671 __rtl8169_resume(dev);
6672
6673 return 0;
6674 }
6675
6676 static int rtl8169_runtime_suspend(struct device *device)
6677 {
6678 struct pci_dev *pdev = to_pci_dev(device);
6679 struct net_device *dev = pci_get_drvdata(pdev);
6680 struct rtl8169_private *tp = netdev_priv(dev);
6681
6682 if (!tp->TxDescArray)
6683 return 0;
6684
6685 rtl_lock_work(tp);
6686 tp->saved_wolopts = __rtl8169_get_wol(tp);
6687 __rtl8169_set_wol(tp, WAKE_ANY);
6688 rtl_unlock_work(tp);
6689
6690 rtl8169_net_suspend(dev);
6691
6692 return 0;
6693 }
6694
6695 static int rtl8169_runtime_resume(struct device *device)
6696 {
6697 struct pci_dev *pdev = to_pci_dev(device);
6698 struct net_device *dev = pci_get_drvdata(pdev);
6699 struct rtl8169_private *tp = netdev_priv(dev);
6700
6701 if (!tp->TxDescArray)
6702 return 0;
6703
6704 rtl_lock_work(tp);
6705 __rtl8169_set_wol(tp, tp->saved_wolopts);
6706 tp->saved_wolopts = 0;
6707 rtl_unlock_work(tp);
6708
6709 rtl8169_init_phy(dev, tp);
6710
6711 __rtl8169_resume(dev);
6712
6713 return 0;
6714 }
6715
6716 static int rtl8169_runtime_idle(struct device *device)
6717 {
6718 struct pci_dev *pdev = to_pci_dev(device);
6719 struct net_device *dev = pci_get_drvdata(pdev);
6720 struct rtl8169_private *tp = netdev_priv(dev);
6721
6722 return tp->TxDescArray ? -EBUSY : 0;
6723 }
6724
6725 static const struct dev_pm_ops rtl8169_pm_ops = {
6726 .suspend = rtl8169_suspend,
6727 .resume = rtl8169_resume,
6728 .freeze = rtl8169_suspend,
6729 .thaw = rtl8169_resume,
6730 .poweroff = rtl8169_suspend,
6731 .restore = rtl8169_resume,
6732 .runtime_suspend = rtl8169_runtime_suspend,
6733 .runtime_resume = rtl8169_runtime_resume,
6734 .runtime_idle = rtl8169_runtime_idle,
6735 };
6736
6737 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6738
6739 #else /* !CONFIG_PM */
6740
6741 #define RTL8169_PM_OPS NULL
6742
6743 #endif /* !CONFIG_PM */
6744
6745 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6746 {
6747 void __iomem *ioaddr = tp->mmio_addr;
6748
6749 /* WoL fails with 8168b when the receiver is disabled. */
6750 switch (tp->mac_version) {
6751 case RTL_GIGA_MAC_VER_11:
6752 case RTL_GIGA_MAC_VER_12:
6753 case RTL_GIGA_MAC_VER_17:
6754 pci_clear_master(tp->pci_dev);
6755
6756 RTL_W8(ChipCmd, CmdRxEnb);
6757 /* PCI commit */
6758 RTL_R8(ChipCmd);
6759 break;
6760 default:
6761 break;
6762 }
6763 }
6764
6765 static void rtl_shutdown(struct pci_dev *pdev)
6766 {
6767 struct net_device *dev = pci_get_drvdata(pdev);
6768 struct rtl8169_private *tp = netdev_priv(dev);
6769 struct device *d = &pdev->dev;
6770
6771 pm_runtime_get_sync(d);
6772
6773 rtl8169_net_suspend(dev);
6774
6775 /* Restore original MAC address */
6776 rtl_rar_set(tp, dev->perm_addr);
6777
6778 rtl8169_hw_reset(tp);
6779
6780 if (system_state == SYSTEM_POWER_OFF) {
6781 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6782 rtl_wol_suspend_quirk(tp);
6783 rtl_wol_shutdown_quirk(tp);
6784 }
6785
6786 pci_wake_from_d3(pdev, true);
6787 pci_set_power_state(pdev, PCI_D3hot);
6788 }
6789
6790 pm_runtime_put_noidle(d);
6791 }
6792
6793 static void rtl_remove_one(struct pci_dev *pdev)
6794 {
6795 struct net_device *dev = pci_get_drvdata(pdev);
6796 struct rtl8169_private *tp = netdev_priv(dev);
6797
6798 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6799 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6800 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6801 rtl8168_driver_stop(tp);
6802 }
6803
6804 netif_napi_del(&tp->napi);
6805
6806 unregister_netdev(dev);
6807
6808 rtl_release_firmware(tp);
6809
6810 if (pci_dev_run_wake(pdev))
6811 pm_runtime_get_noresume(&pdev->dev);
6812
6813 /* restore original MAC address */
6814 rtl_rar_set(tp, dev->perm_addr);
6815
6816 rtl_disable_msi(pdev, tp);
6817 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6818 }
6819
6820 static const struct net_device_ops rtl_netdev_ops = {
6821 .ndo_open = rtl_open,
6822 .ndo_stop = rtl8169_close,
6823 .ndo_get_stats64 = rtl8169_get_stats64,
6824 .ndo_start_xmit = rtl8169_start_xmit,
6825 .ndo_tx_timeout = rtl8169_tx_timeout,
6826 .ndo_validate_addr = eth_validate_addr,
6827 .ndo_change_mtu = rtl8169_change_mtu,
6828 .ndo_fix_features = rtl8169_fix_features,
6829 .ndo_set_features = rtl8169_set_features,
6830 .ndo_set_mac_address = rtl_set_mac_address,
6831 .ndo_do_ioctl = rtl8169_ioctl,
6832 .ndo_set_rx_mode = rtl_set_rx_mode,
6833 #ifdef CONFIG_NET_POLL_CONTROLLER
6834 .ndo_poll_controller = rtl8169_netpoll,
6835 #endif
6836
6837 };
6838
6839 static const struct rtl_cfg_info {
6840 void (*hw_start)(struct net_device *);
6841 unsigned int region;
6842 unsigned int align;
6843 u16 event_slow;
6844 unsigned features;
6845 u8 default_ver;
6846 } rtl_cfg_infos [] = {
6847 [RTL_CFG_0] = {
6848 .hw_start = rtl_hw_start_8169,
6849 .region = 1,
6850 .align = 0,
6851 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6852 .features = RTL_FEATURE_GMII,
6853 .default_ver = RTL_GIGA_MAC_VER_01,
6854 },
6855 [RTL_CFG_1] = {
6856 .hw_start = rtl_hw_start_8168,
6857 .region = 2,
6858 .align = 8,
6859 .event_slow = SYSErr | LinkChg | RxOverflow,
6860 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6861 .default_ver = RTL_GIGA_MAC_VER_11,
6862 },
6863 [RTL_CFG_2] = {
6864 .hw_start = rtl_hw_start_8101,
6865 .region = 2,
6866 .align = 8,
6867 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6868 PCSTimeout,
6869 .features = RTL_FEATURE_MSI,
6870 .default_ver = RTL_GIGA_MAC_VER_13,
6871 }
6872 };
6873
6874 /* Cfg9346_Unlock assumed. */
6875 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6876 const struct rtl_cfg_info *cfg)
6877 {
6878 void __iomem *ioaddr = tp->mmio_addr;
6879 unsigned msi = 0;
6880 u8 cfg2;
6881
6882 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6883 if (cfg->features & RTL_FEATURE_MSI) {
6884 if (pci_enable_msi(tp->pci_dev)) {
6885 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6886 } else {
6887 cfg2 |= MSIEnable;
6888 msi = RTL_FEATURE_MSI;
6889 }
6890 }
6891 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6892 RTL_W8(Config2, cfg2);
6893 return msi;
6894 }
6895
6896 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6897 {
6898 void __iomem *ioaddr = tp->mmio_addr;
6899
6900 return RTL_R8(MCU) & LINK_LIST_RDY;
6901 }
6902
6903 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6904 {
6905 void __iomem *ioaddr = tp->mmio_addr;
6906
6907 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6908 }
6909
6910 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6911 {
6912 void __iomem *ioaddr = tp->mmio_addr;
6913 u32 data;
6914
6915 tp->ocp_base = OCP_STD_PHY_BASE;
6916
6917 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6918
6919 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6920 return;
6921
6922 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6923 return;
6924
6925 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6926 msleep(1);
6927 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6928
6929 data = r8168_mac_ocp_read(tp, 0xe8de);
6930 data &= ~(1 << 14);
6931 r8168_mac_ocp_write(tp, 0xe8de, data);
6932
6933 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6934 return;
6935
6936 data = r8168_mac_ocp_read(tp, 0xe8de);
6937 data |= (1 << 15);
6938 r8168_mac_ocp_write(tp, 0xe8de, data);
6939
6940 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6941 return;
6942 }
6943
6944 static void rtl_hw_initialize(struct rtl8169_private *tp)
6945 {
6946 switch (tp->mac_version) {
6947 case RTL_GIGA_MAC_VER_40:
6948 case RTL_GIGA_MAC_VER_41:
6949 case RTL_GIGA_MAC_VER_42:
6950 case RTL_GIGA_MAC_VER_43:
6951 case RTL_GIGA_MAC_VER_44:
6952 rtl_hw_init_8168g(tp);
6953 break;
6954
6955 default:
6956 break;
6957 }
6958 }
6959
6960 static int
6961 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6962 {
6963 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6964 const unsigned int region = cfg->region;
6965 struct rtl8169_private *tp;
6966 struct mii_if_info *mii;
6967 struct net_device *dev;
6968 void __iomem *ioaddr;
6969 int chipset, i;
6970 int rc;
6971
6972 if (netif_msg_drv(&debug)) {
6973 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6974 MODULENAME, RTL8169_VERSION);
6975 }
6976
6977 dev = alloc_etherdev(sizeof (*tp));
6978 if (!dev) {
6979 rc = -ENOMEM;
6980 goto out;
6981 }
6982
6983 SET_NETDEV_DEV(dev, &pdev->dev);
6984 dev->netdev_ops = &rtl_netdev_ops;
6985 tp = netdev_priv(dev);
6986 tp->dev = dev;
6987 tp->pci_dev = pdev;
6988 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6989
6990 mii = &tp->mii;
6991 mii->dev = dev;
6992 mii->mdio_read = rtl_mdio_read;
6993 mii->mdio_write = rtl_mdio_write;
6994 mii->phy_id_mask = 0x1f;
6995 mii->reg_num_mask = 0x1f;
6996 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6997
6998 /* disable ASPM completely as that cause random device stop working
6999 * problems as well as full system hangs for some PCIe devices users */
7000 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7001 PCIE_LINK_STATE_CLKPM);
7002
7003 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7004 rc = pci_enable_device(pdev);
7005 if (rc < 0) {
7006 netif_err(tp, probe, dev, "enable failure\n");
7007 goto err_out_free_dev_1;
7008 }
7009
7010 if (pci_set_mwi(pdev) < 0)
7011 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7012
7013 /* make sure PCI base addr 1 is MMIO */
7014 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7015 netif_err(tp, probe, dev,
7016 "region #%d not an MMIO resource, aborting\n",
7017 region);
7018 rc = -ENODEV;
7019 goto err_out_mwi_2;
7020 }
7021
7022 /* check for weird/broken PCI region reporting */
7023 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7024 netif_err(tp, probe, dev,
7025 "Invalid PCI region size(s), aborting\n");
7026 rc = -ENODEV;
7027 goto err_out_mwi_2;
7028 }
7029
7030 rc = pci_request_regions(pdev, MODULENAME);
7031 if (rc < 0) {
7032 netif_err(tp, probe, dev, "could not request regions\n");
7033 goto err_out_mwi_2;
7034 }
7035
7036 tp->cp_cmd = RxChkSum;
7037
7038 if ((sizeof(dma_addr_t) > 4) &&
7039 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7040 tp->cp_cmd |= PCIDAC;
7041 dev->features |= NETIF_F_HIGHDMA;
7042 } else {
7043 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7044 if (rc < 0) {
7045 netif_err(tp, probe, dev, "DMA configuration failed\n");
7046 goto err_out_free_res_3;
7047 }
7048 }
7049
7050 /* ioremap MMIO region */
7051 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7052 if (!ioaddr) {
7053 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7054 rc = -EIO;
7055 goto err_out_free_res_3;
7056 }
7057 tp->mmio_addr = ioaddr;
7058
7059 if (!pci_is_pcie(pdev))
7060 netif_info(tp, probe, dev, "not PCI Express\n");
7061
7062 /* Identify chip attached to board */
7063 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7064
7065 rtl_init_rxcfg(tp);
7066
7067 rtl_irq_disable(tp);
7068
7069 rtl_hw_initialize(tp);
7070
7071 rtl_hw_reset(tp);
7072
7073 rtl_ack_events(tp, 0xffff);
7074
7075 pci_set_master(pdev);
7076
7077 /*
7078 * Pretend we are using VLANs; This bypasses a nasty bug where
7079 * Interrupts stop flowing on high load on 8110SCd controllers.
7080 */
7081 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7082 tp->cp_cmd |= RxVlan;
7083
7084 rtl_init_mdio_ops(tp);
7085 rtl_init_pll_power_ops(tp);
7086 rtl_init_jumbo_ops(tp);
7087 rtl_init_csi_ops(tp);
7088
7089 rtl8169_print_mac_version(tp);
7090
7091 chipset = tp->mac_version;
7092 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7093
7094 RTL_W8(Cfg9346, Cfg9346_Unlock);
7095 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7096 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7097 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7098 tp->features |= RTL_FEATURE_WOL;
7099 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7100 tp->features |= RTL_FEATURE_WOL;
7101 tp->features |= rtl_try_msi(tp, cfg);
7102 RTL_W8(Cfg9346, Cfg9346_Lock);
7103
7104 if (rtl_tbi_enabled(tp)) {
7105 tp->set_speed = rtl8169_set_speed_tbi;
7106 tp->get_settings = rtl8169_gset_tbi;
7107 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7108 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7109 tp->link_ok = rtl8169_tbi_link_ok;
7110 tp->do_ioctl = rtl_tbi_ioctl;
7111 } else {
7112 tp->set_speed = rtl8169_set_speed_xmii;
7113 tp->get_settings = rtl8169_gset_xmii;
7114 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7115 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7116 tp->link_ok = rtl8169_xmii_link_ok;
7117 tp->do_ioctl = rtl_xmii_ioctl;
7118 }
7119
7120 mutex_init(&tp->wk.mutex);
7121 u64_stats_init(&tp->rx_stats.syncp);
7122 u64_stats_init(&tp->tx_stats.syncp);
7123
7124 /* Get MAC address */
7125 for (i = 0; i < ETH_ALEN; i++)
7126 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7127
7128 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7129 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7130
7131 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7132
7133 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7134 * properly for all devices */
7135 dev->features |= NETIF_F_RXCSUM |
7136 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7137
7138 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7139 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7140 NETIF_F_HW_VLAN_CTAG_RX;
7141 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7142 NETIF_F_HIGHDMA;
7143
7144 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7145 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7146 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7147
7148 dev->hw_features |= NETIF_F_RXALL;
7149 dev->hw_features |= NETIF_F_RXFCS;
7150
7151 tp->hw_start = cfg->hw_start;
7152 tp->event_slow = cfg->event_slow;
7153
7154 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7155 ~(RxBOVF | RxFOVF) : ~0;
7156
7157 init_timer(&tp->timer);
7158 tp->timer.data = (unsigned long) dev;
7159 tp->timer.function = rtl8169_phy_timer;
7160
7161 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7162
7163 rc = register_netdev(dev);
7164 if (rc < 0)
7165 goto err_out_msi_4;
7166
7167 pci_set_drvdata(pdev, dev);
7168
7169 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7170 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7171 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7172 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7173 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7174 "tx checksumming: %s]\n",
7175 rtl_chip_infos[chipset].jumbo_max,
7176 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7177 }
7178
7179 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7180 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7181 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7182 rtl8168_driver_start(tp);
7183 }
7184
7185 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7186
7187 if (pci_dev_run_wake(pdev))
7188 pm_runtime_put_noidle(&pdev->dev);
7189
7190 netif_carrier_off(dev);
7191
7192 out:
7193 return rc;
7194
7195 err_out_msi_4:
7196 netif_napi_del(&tp->napi);
7197 rtl_disable_msi(pdev, tp);
7198 iounmap(ioaddr);
7199 err_out_free_res_3:
7200 pci_release_regions(pdev);
7201 err_out_mwi_2:
7202 pci_clear_mwi(pdev);
7203 pci_disable_device(pdev);
7204 err_out_free_dev_1:
7205 free_netdev(dev);
7206 goto out;
7207 }
7208
7209 static struct pci_driver rtl8169_pci_driver = {
7210 .name = MODULENAME,
7211 .id_table = rtl8169_pci_tbl,
7212 .probe = rtl_init_one,
7213 .remove = rtl_remove_one,
7214 .shutdown = rtl_shutdown,
7215 .driver.pm = RTL8169_PM_OPS,
7216 };
7217
7218 module_pci_driver(rtl8169_pci_driver);
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