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ath5k: PHY code cleanup
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath5k / rfbuffer.h
blob526cf6cb845f651f075cb1656ec091d2148252f2
1 /*
2 * RF Buffer handling functions
3 *
4 * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 /*
21 * Struct to hold default mode specific RF
22 * register values (RF Banks)
23 */
24 struct ath5k_ini_rfbuffer {
25 u8 rfb_bank; /* RF Bank number */
26 u16 rfb_ctrl_register; /* RF Buffer control register */
27 u32 rfb_mode_data[5]; /* RF Buffer data for each mode */
28 };
29
30 /*
31 * Struct to hold RF Buffer field
32 * infos used to access certain RF
33 * analog registers
34 */
35 struct ath5k_rfb_field {
36 u8 len; /* Field length */
37 u16 pos; /* Offset on the raw packet */
38 u8 col; /* Column -used for shifting */
39 };
40
41 /*
42 * RF analog register definition
43 */
44 struct ath5k_rf_reg {
45 u8 bank; /* RF Buffer Bank number */
46 u8 index; /* Register's index on rf_regs_idx */
47 struct ath5k_rfb_field field; /* RF Buffer field for this register */
48 };
49
50 /* Map RF registers to indexes
51 * We do this to handle common bits and make our
52 * life easier by using an index for each register
53 * instead of a full rfb_field */
54 enum ath5k_rf_regs_idx {
55 /* BANK 6 */
56 AR5K_RF_OB_2GHZ = 0,
57 AR5K_RF_OB_5GHZ,
58 AR5K_RF_DB_2GHZ,
59 AR5K_RF_DB_5GHZ,
60 AR5K_RF_FIXED_BIAS_A,
61 AR5K_RF_FIXED_BIAS_B,
62 AR5K_RF_PWD_XPD,
63 AR5K_RF_XPD_SEL,
64 AR5K_RF_XPD_GAIN,
65 AR5K_RF_PD_GAIN_LO,
66 AR5K_RF_PD_GAIN_HI,
67 AR5K_RF_HIGH_VC_CP,
68 AR5K_RF_MID_VC_CP,
69 AR5K_RF_LOW_VC_CP,
70 AR5K_RF_PUSH_UP,
71 AR5K_RF_PAD2GND,
72 AR5K_RF_XB2_LVL,
73 AR5K_RF_XB5_LVL,
74 AR5K_RF_PWD_ICLOBUF_2G,
75 AR5K_RF_DERBY_CHAN_SEL_MODE,
76 /* BANK 7 */
77 AR5K_RF_GAIN_I,
78 AR5K_RF_PLO_SEL,
79 AR5K_RF_RFGAIN_SEL,
80 AR5K_RF_WAIT_S,
81 AR5K_RF_WAIT_I,
82 AR5K_RF_MAX_TIME,
83 AR5K_RF_MIXGAIN_OVR,
84 AR5K_RF_PD_DELAY_A,
85 AR5K_RF_PD_DELAY_B,
86 AR5K_RF_PD_DELAY_XR,
87 AR5K_RF_PD_PERIOD_A,
88 AR5K_RF_PD_PERIOD_B,
89 AR5K_RF_PD_PERIOD_XR,
90 };
91
92
93 /*******************\
94 * RF5111 (Sombrero) *
95 \*******************/
96
97 /* BANK 6 len pos col */
98 #define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
99 #define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
100
101 #define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
102 #define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
103
104 #define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
105 #define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
106
107 /* Access to PWD registers */
108 #define AR5K_RF5111_PWD(_n) { 1, (135 - _n), 3 }
109
110 /* BANK 7 len pos col */
111 #define AR5K_RF5111_GAIN_I { 6, 29, 0 }
112 #define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
113 #define AR5K_RF5111_RFGAIN_SEL { 1, 36, 0 }
114 /* Only on AR5212 BaseBand and up */
115 #define AR5K_RF5111_WAIT_S { 5, 19, 0 }
116 #define AR5K_RF5111_WAIT_I { 5, 24, 0 }
117 #define AR5K_RF5111_MAX_TIME { 2, 49, 0 }
118
119 static const struct ath5k_rf_reg rf_regs_5111[] = {
120 {6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
121 {6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
122 {6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
123 {6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
124 {6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
125 {6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
126 {7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
127 {7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
128 {7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
129 {7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
130 {7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
131 {7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
132
133 };
134
135 /* Default mode specific settings */
136 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
137 { 0, 0x989c,
138 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
139 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
140 { 0, 0x989c,
141 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
142 { 0, 0x989c,
143 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
144 { 0, 0x989c,
145 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
146 { 0, 0x989c,
147 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
148 { 0, 0x989c,
149 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
150 { 0, 0x989c,
151 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
152 { 0, 0x989c,
153 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
154 { 0, 0x989c,
155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
156 { 0, 0x989c,
157 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
158 { 0, 0x989c,
159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
160 { 0, 0x989c,
161 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
162 { 0, 0x989c,
163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
164 { 0, 0x989c,
165 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
166 { 0, 0x989c,
167 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
168 { 0, 0x989c,
169 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
170 { 0, 0x98d4,
171 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
172 { 1, 0x98d4,
173 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
174 { 2, 0x98d4,
175 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
176 { 3, 0x98d8,
177 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
178 { 6, 0x989c,
179 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
180 { 6, 0x989c,
181 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
182 { 6, 0x989c,
183 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
184 { 6, 0x989c,
185 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
186 { 6, 0x989c,
187 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
188 { 6, 0x989c,
189 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
190 { 6, 0x989c,
191 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
192 { 6, 0x989c,
193 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
194 { 6, 0x989c,
195 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
196 { 6, 0x989c,
197 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
198 { 6, 0x989c,
199 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
200 { 6, 0x989c,
201 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
202 { 6, 0x989c,
203 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
204 { 6, 0x989c,
205 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
206 { 6, 0x989c,
207 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
208 { 6, 0x989c,
209 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
210 { 6, 0x98d4,
211 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
212 { 7, 0x989c,
213 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
214 { 7, 0x989c,
215 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
216 { 7, 0x989c,
217 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
218 { 7, 0x989c,
219 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
220 { 7, 0x989c,
221 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
222 { 7, 0x989c,
223 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
224 { 7, 0x989c,
225 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
226 { 7, 0x98cc,
227 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
228 };
229
230
231
232 /***********************\
233 * RF5112/RF2112 (Derby) *
234 \***********************/
235
236 /* BANK 7 (Common) len pos col */
237 #define AR5K_RF5112X_GAIN_I { 6, 14, 0 }
238 #define AR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 }
239 #define AR5K_RF5112X_PD_DELAY_A { 4, 58, 0 }
240 #define AR5K_RF5112X_PD_DELAY_B { 4, 62, 0 }
241 #define AR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 }
242 #define AR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 }
243 #define AR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 }
244 #define AR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 }
245
246 /* RFX112 (Derby 1) */
247
248 /* BANK 6 len pos col */
249 #define AR5K_RF5112_OB_2GHZ { 3, 269, 0 }
250 #define AR5K_RF5112_DB_2GHZ { 3, 272, 0 }
251
252 #define AR5K_RF5112_OB_5GHZ { 3, 261, 0 }
253 #define AR5K_RF5112_DB_5GHZ { 3, 264, 0 }
254
255 #define AR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 }
256 #define AR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 }
257
258 #define AR5K_RF5112_XPD_SEL { 1, 284, 0 }
259 #define AR5K_RF5112_XPD_GAIN { 2, 252, 0 }
260
261 /* Access to PWD registers */
262 #define AR5K_RF5112_PWD(_n) { 1, (302 - _n), 3 }
263
264 static const struct ath5k_rf_reg rf_regs_5112[] = {
265 {6, AR5K_RF_OB_2GHZ, AR5K_RF5112_OB_2GHZ},
266 {6, AR5K_RF_DB_2GHZ, AR5K_RF5112_DB_2GHZ},
267 {6, AR5K_RF_OB_5GHZ, AR5K_RF5112_OB_5GHZ},
268 {6, AR5K_RF_DB_5GHZ, AR5K_RF5112_DB_5GHZ},
269 {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112_FIXED_BIAS_A},
270 {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B},
271 {6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL},
272 {6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN},
273 {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
274 {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
275 {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
276 {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
277 {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
278 {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
279 {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
280 {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
281 };
282
283 /* Default mode specific settings */
284 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
285 { 1, 0x98d4,
286 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
287 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
288 { 2, 0x98d0,
289 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
290 { 3, 0x98dc,
291 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
292 { 6, 0x989c,
293 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
294 { 6, 0x989c,
295 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
296 { 6, 0x989c,
297 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
298 { 6, 0x989c,
299 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
300 { 6, 0x989c,
301 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
302 { 6, 0x989c,
303 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
304 { 6, 0x989c,
305 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
306 { 6, 0x989c,
307 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
308 { 6, 0x989c,
309 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
310 { 6, 0x989c,
311 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
312 { 6, 0x989c,
313 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
314 { 6, 0x989c,
315 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
316 { 6, 0x989c,
317 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
318 { 6, 0x989c,
319 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
320 { 6, 0x989c,
321 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
322 { 6, 0x989c,
323 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
324 { 6, 0x989c,
325 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
326 { 6, 0x989c,
327 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
328 { 6, 0x989c,
329 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
330 { 6, 0x989c,
331 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
332 { 6, 0x989c,
333 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
334 { 6, 0x989c,
335 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
336 { 6, 0x989c,
337 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
338 { 6, 0x989c,
339 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
340 { 6, 0x989c,
341 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
342 { 6, 0x989c,
343 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
344 { 6, 0x989c,
345 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
346 { 6, 0x989c,
347 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
348 { 6, 0x989c,
349 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
350 { 6, 0x989c,
351 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
352 { 6, 0x989c,
353 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
354 { 6, 0x989c,
355 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
356 { 6, 0x989c,
357 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
358 { 6, 0x989c,
359 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
360 { 6, 0x989c,
361 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
362 { 6, 0x989c,
363 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
364 { 6, 0x989c,
365 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
366 { 6, 0x98d0,
367 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
368 { 7, 0x989c,
369 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
370 { 7, 0x989c,
371 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
372 { 7, 0x989c,
373 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
374 { 7, 0x989c,
375 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
376 { 7, 0x989c,
377 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
378 { 7, 0x989c,
379 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
380 { 7, 0x989c,
381 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
382 { 7, 0x989c,
383 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
384 { 7, 0x989c,
385 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
386 { 7, 0x989c,
387 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
388 { 7, 0x989c,
389 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
390 { 7, 0x989c,
391 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
392 { 7, 0x98c4,
393 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
394 };
395
396 /* RFX112A (Derby 2) */
397
398 /* BANK 6 len pos col */
399 #define AR5K_RF5112A_OB_2GHZ { 3, 287, 0 }
400 #define AR5K_RF5112A_DB_2GHZ { 3, 290, 0 }
401
402 #define AR5K_RF5112A_OB_5GHZ { 3, 279, 0 }
403 #define AR5K_RF5112A_DB_5GHZ { 3, 282, 0 }
404
405 #define AR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 }
406 #define AR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 }
407
408 #define AR5K_RF5112A_XPD_SEL { 1, 302, 0 }
409 #define AR5K_RF5112A_PDGAINLO { 2, 270, 0 }
410 #define AR5K_RF5112A_PDGAINHI { 2, 257, 0 }
411
412 /* Access to PWD registers */
413 #define AR5K_RF5112A_PWD(_n) { 1, (306 - _n), 3 }
414
415 /* Voltage regulators */
416 #define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 }
417 #define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 }
418 #define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 }
419 #define AR5K_RF5112A_PUSH_UP { 2, 94, 2 }
420
421 /* Power consumption */
422 #define AR5K_RF5112A_PAD2GND { 1, 281, 1 }
423 #define AR5K_RF5112A_XB2_LVL { 2, 1, 3 }
424 #define AR5K_RF5112A_XB5_LVL { 2, 3, 3 }
425
426 static const struct ath5k_rf_reg rf_regs_5112a[] = {
427 {6, AR5K_RF_OB_2GHZ, AR5K_RF5112A_OB_2GHZ},
428 {6, AR5K_RF_DB_2GHZ, AR5K_RF5112A_DB_2GHZ},
429 {6, AR5K_RF_OB_5GHZ, AR5K_RF5112A_OB_5GHZ},
430 {6, AR5K_RF_DB_5GHZ, AR5K_RF5112A_DB_5GHZ},
431 {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112A_FIXED_BIAS_A},
432 {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112A_FIXED_BIAS_B},
433 {6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL},
434 {6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO},
435 {6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI},
436 {6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP},
437 {6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP},
438 {6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP},
439 {6, AR5K_RF_PUSH_UP, AR5K_RF5112A_PUSH_UP},
440 {6, AR5K_RF_PAD2GND, AR5K_RF5112A_PAD2GND},
441 {6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL},
442 {6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL},
443 {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
444 {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
445 {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
446 {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
447 {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
448 {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
449 {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
450 {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
451 };
452
453 /* Default mode specific settings */
454 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
455 { 1, 0x98d4,
456 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
457 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
458 { 2, 0x98d0,
459 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
460 { 3, 0x98dc,
461 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
462 { 6, 0x989c,
463 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
464 { 6, 0x989c,
465 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
466 { 6, 0x989c,
467 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
468 { 6, 0x989c,
469 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
470 { 6, 0x989c,
471 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
472 { 6, 0x989c,
473 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
474 { 6, 0x989c,
475 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
476 { 6, 0x989c,
477 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
478 { 6, 0x989c,
479 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
480 { 6, 0x989c,
481 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
482 { 6, 0x989c,
483 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
484 { 6, 0x989c,
485 { 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 } },
486 { 6, 0x989c,
487 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
488 { 6, 0x989c,
489 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
490 { 6, 0x989c,
491 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
492 { 6, 0x989c,
493 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
494 { 6, 0x989c,
495 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
496 { 6, 0x989c,
497 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
498 { 6, 0x989c,
499 { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } },
500 { 6, 0x989c,
501 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
502 { 6, 0x989c,
503 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
504 { 6, 0x989c,
505 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
506 { 6, 0x989c,
507 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
508 { 6, 0x989c,
509 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
510 { 6, 0x989c,
511 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
512 { 6, 0x989c,
513 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
514 { 6, 0x989c,
515 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
516 { 6, 0x989c,
517 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
518 { 6, 0x989c,
519 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
520 { 6, 0x989c,
521 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
522 { 6, 0x989c,
523 { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } },
524 { 6, 0x989c,
525 { 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 } },
526 { 6, 0x989c,
527 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
528 { 6, 0x989c,
529 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
530 { 6, 0x989c,
531 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
532 { 6, 0x989c,
533 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
534 { 6, 0x989c,
535 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
536 { 6, 0x989c,
537 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
538 { 6, 0x989c,
539 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
540 { 6, 0x98d8,
541 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
542 { 7, 0x989c,
543 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
544 { 7, 0x989c,
545 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
546 { 7, 0x989c,
547 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
548 { 7, 0x989c,
549 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
550 { 7, 0x989c,
551 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
552 { 7, 0x989c,
553 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
554 { 7, 0x989c,
555 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
556 { 7, 0x989c,
557 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
558 { 7, 0x989c,
559 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
560 { 7, 0x989c,
561 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
562 { 7, 0x989c,
563 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
564 { 7, 0x989c,
565 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
566 { 7, 0x98c4,
567 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
568 };
569
570
571
572 /******************\
573 * RF2413 (Griffin) *
574 \******************/
575
576 /* BANK 6 len pos col */
577 #define AR5K_RF2413_OB_2GHZ { 3, 168, 0 }
578 #define AR5K_RF2413_DB_2GHZ { 3, 165, 0 }
579
580 static const struct ath5k_rf_reg rf_regs_2413[] = {
581 {6, AR5K_RF_OB_2GHZ, AR5K_RF2413_OB_2GHZ},
582 {6, AR5K_RF_DB_2GHZ, AR5K_RF2413_DB_2GHZ},
583 };
584
585 /* Default mode specific settings
586 * XXX: a/aTurbo ???
587 */
588 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
589 { 1, 0x98d4,
590 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
591 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
592 { 2, 0x98d0,
593 { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
594 { 3, 0x98dc,
595 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
596 { 6, 0x989c,
597 { 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 } },
598 { 6, 0x989c,
599 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
600 { 6, 0x989c,
601 { 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 } },
602 { 6, 0x989c,
603 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
604 { 6, 0x989c,
605 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
606 { 6, 0x989c,
607 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
608 { 6, 0x989c,
609 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
610 { 6, 0x989c,
611 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
612 { 6, 0x989c,
613 { 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 } },
614 { 6, 0x989c,
615 { 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 } },
616 { 6, 0x989c,
617 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
618 { 6, 0x989c,
619 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
620 { 6, 0x989c,
621 { 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 } },
622 { 6, 0x989c,
623 { 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 } },
624 { 6, 0x989c,
625 { 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 } },
626 { 6, 0x989c,
627 { 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 } },
628 { 6, 0x989c,
629 { 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 } },
630 { 6, 0x989c,
631 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
632 { 6, 0x989c,
633 { 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 } },
634 { 6, 0x989c,
635 { 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 } },
636 { 6, 0x989c,
637 { 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 } },
638 { 6, 0x989c,
639 { 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 } },
640 { 6, 0x989c,
641 { 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f } },
642 { 6, 0x989c,
643 { 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 } },
644 { 6, 0x989c,
645 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
646 { 6, 0x989c,
647 { 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 } },
648 { 6, 0x98d8,
649 { 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 } },
650 { 7, 0x989c,
651 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
652 { 7, 0x989c,
653 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
654 { 7, 0x98cc,
655 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
656 };
657
658
659
660 /***************************\
661 * RF2315/RF2316 (Cobra SoC) *
662 \***************************/
663
664 /* BANK 6 len pos col */
665 #define AR5K_RF2316_OB_2GHZ { 3, 178, 0 }
666 #define AR5K_RF2316_DB_2GHZ { 3, 175, 0 }
667
668 static const struct ath5k_rf_reg rf_regs_2316[] = {
669 {6, AR5K_RF_OB_2GHZ, AR5K_RF2316_OB_2GHZ},
670 {6, AR5K_RF_DB_2GHZ, AR5K_RF2316_DB_2GHZ},
671 };
672
673 /* Default mode specific settings */
674 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
675 { 1, 0x98d4,
676 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
677 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
678 { 2, 0x98d0,
679 { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
680 { 3, 0x98dc,
681 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
682 { 6, 0x989c,
683 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
684 { 6, 0x989c,
685 { 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 } },
686 { 6, 0x989c,
687 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
688 { 6, 0x989c,
689 { 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 } },
690 { 6, 0x989c,
691 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
692 { 6, 0x989c,
693 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
694 { 6, 0x989c,
695 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
696 { 6, 0x989c,
697 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
698 { 6, 0x989c,
699 { 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 } },
700 { 6, 0x989c,
701 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
702 { 6, 0x989c,
703 { 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 } },
704 { 6, 0x989c,
705 { 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 } },
706 { 6, 0x989c,
707 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
708 { 6, 0x989c,
709 { 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 } },
710 { 6, 0x989c,
711 { 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 } },
712 { 6, 0x989c,
713 { 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 } },
714 { 6, 0x989c,
715 { 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
716 { 6, 0x989c,
717 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
718 { 6, 0x989c,
719 { 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 } },
720 { 6, 0x989c,
721 { 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 } },
722 { 6, 0x989c,
723 { 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 } },
724 { 6, 0x989c,
725 { 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 } },
726 { 6, 0x989c,
727 { 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d } },
728 { 6, 0x989c,
729 { 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 } },
730 { 6, 0x989c,
731 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
732 { 6, 0x989c,
733 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
734 { 6, 0x989c,
735 { 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 } },
736 { 6, 0x989c,
737 { 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 } },
738 { 6, 0x98c0,
739 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
740 { 7, 0x989c,
741 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
742 { 7, 0x989c,
743 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
744 { 7, 0x98cc,
745 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
746 };
747
748
749
750 /******************************\
751 * RF5413/RF5424 (Eagle/Condor) *
752 \******************************/
753
754 /* BANK 6 len pos col */
755 #define AR5K_RF5413_OB_2GHZ { 3, 241, 0 }
756 #define AR5K_RF5413_DB_2GHZ { 3, 238, 0 }
757
758 #define AR5K_RF5413_OB_5GHZ { 3, 247, 0 }
759 #define AR5K_RF5413_DB_5GHZ { 3, 244, 0 }
760
761 #define AR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 }
762 #define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 }
763
764 static const struct ath5k_rf_reg rf_regs_5413[] = {
765 {6, AR5K_RF_OB_2GHZ, AR5K_RF5413_OB_2GHZ},
766 {6, AR5K_RF_DB_2GHZ, AR5K_RF5413_DB_2GHZ},
767 {6, AR5K_RF_OB_5GHZ, AR5K_RF5413_OB_5GHZ},
768 {6, AR5K_RF_DB_5GHZ, AR5K_RF5413_DB_5GHZ},
769 {6, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF5413_PWD_ICLOBUF2G},
770 {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE},
771 };
772
773 /* Default mode specific settings */
774 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
775 { 1, 0x98d4,
776 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
777 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
778 { 2, 0x98d0,
779 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
780 { 3, 0x98dc,
781 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
782 { 6, 0x989c,
783 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
784 { 6, 0x989c,
785 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
786 { 6, 0x989c,
787 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
788 { 6, 0x989c,
789 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
790 { 6, 0x989c,
791 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
792 { 6, 0x989c,
793 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
794 { 6, 0x989c,
795 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
796 { 6, 0x989c,
797 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
798 { 6, 0x989c,
799 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
800 { 6, 0x989c,
801 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
802 { 6, 0x989c,
803 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
804 { 6, 0x989c,
805 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
806 { 6, 0x989c,
807 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
808 { 6, 0x989c,
809 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
810 { 6, 0x989c,
811 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
812 { 6, 0x989c,
813 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
814 { 6, 0x989c,
815 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
816 { 6, 0x989c,
817 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
818 { 6, 0x989c,
819 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
820 { 6, 0x989c,
821 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
822 { 6, 0x989c,
823 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
824 { 6, 0x989c,
825 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
826 { 6, 0x989c,
827 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
828 { 6, 0x989c,
829 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
830 { 6, 0x989c,
831 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
832 { 6, 0x989c,
833 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
834 { 6, 0x989c,
835 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
836 { 6, 0x989c,
837 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
838 { 6, 0x989c,
839 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
840 { 6, 0x989c,
841 { 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 } },
842 { 6, 0x989c,
843 { 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da } },
844 { 6, 0x989c,
845 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
846 { 6, 0x989c,
847 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
848 { 6, 0x989c,
849 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
850 { 6, 0x989c,
851 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
852 { 6, 0x989c,
853 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 } },
854 { 6, 0x98c8,
855 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
856 { 7, 0x989c,
857 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
858 { 7, 0x989c,
859 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
860 { 7, 0x98cc,
861 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
862 };
863
864
865
866 /***************************\
867 * RF2425/RF2417 (Swan/Nala) *
868 * AR2317 (Spider SoC) *
869 \***************************/
870
871 /* BANK 6 len pos col */
872 #define AR5K_RF2425_OB_2GHZ { 3, 193, 0 }
873 #define AR5K_RF2425_DB_2GHZ { 3, 190, 0 }
874
875 static const struct ath5k_rf_reg rf_regs_2425[] = {
876 {6, AR5K_RF_OB_2GHZ, AR5K_RF2425_OB_2GHZ},
877 {6, AR5K_RF_DB_2GHZ, AR5K_RF2425_DB_2GHZ},
878 };
879
880 /* Default mode specific settings
881 * XXX: a/aTurbo ?
882 */
883 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
884 { 1, 0x98d4,
885 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
886 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
887 { 2, 0x98d0,
888 { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
889 { 3, 0x98dc,
890 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
891 { 6, 0x989c,
892 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
893 { 6, 0x989c,
894 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
895 { 6, 0x989c,
896 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
897 { 6, 0x989c,
898 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
899 { 6, 0x989c,
900 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
901 { 6, 0x989c,
902 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
903 { 6, 0x989c,
904 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
905 { 6, 0x989c,
906 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
907 { 6, 0x989c,
908 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
909 { 6, 0x989c,
910 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
911 { 6, 0x989c,
912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
913 { 6, 0x989c,
914 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
915 { 6, 0x989c,
916 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
917 { 6, 0x989c,
918 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
919 { 6, 0x989c,
920 { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
921 { 6, 0x989c,
922 { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
923 { 6, 0x989c,
924 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
925 { 6, 0x989c,
926 { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
927 { 6, 0x989c,
928 { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
929 { 6, 0x989c,
930 { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
931 { 6, 0x989c,
932 { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
933 { 6, 0x989c,
934 { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
935 { 6, 0x989c,
936 { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
937 { 6, 0x989c,
938 { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
939 { 6, 0x989c,
940 { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
941 { 6, 0x989c,
942 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
943 { 6, 0x989c,
944 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
945 { 6, 0x989c,
946 { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
947 { 6, 0x989c,
948 { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
949 { 6, 0x98c4,
950 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
951 { 7, 0x989c,
952 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
953 { 7, 0x989c,
954 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
955 { 7, 0x98cc,
956 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
957 };
958
959 /*
960 * TODO: Handle the few differences with swan during
961 * bank modification and get rid of this
962 */
963 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
964 { 1, 0x98d4,
965 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
966 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
967 { 2, 0x98d0,
968 { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
969 { 3, 0x98dc,
970 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
971 { 6, 0x989c,
972 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
973 { 6, 0x989c,
974 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
975 { 6, 0x989c,
976 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
977 { 6, 0x989c,
978 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
979 { 6, 0x989c,
980 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
981 { 6, 0x989c,
982 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
983 { 6, 0x989c,
984 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
985 { 6, 0x989c,
986 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
987 { 6, 0x989c,
988 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
989 { 6, 0x989c,
990 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
991 { 6, 0x989c,
992 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
993 { 6, 0x989c,
994 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
995 { 6, 0x989c,
996 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
997 { 6, 0x989c,
998 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
999 { 6, 0x989c,
1000 { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
1001 { 6, 0x989c,
1002 { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
1003 { 6, 0x989c,
1004 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
1005 { 6, 0x989c,
1006 { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
1007 { 6, 0x989c,
1008 { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
1009 { 6, 0x989c,
1010 { 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 } },
1011 { 6, 0x989c,
1012 { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
1013 { 6, 0x989c,
1014 { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
1015 { 6, 0x989c,
1016 { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
1017 { 6, 0x989c,
1018 { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
1019 { 6, 0x989c,
1020 { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
1021 { 6, 0x989c,
1022 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1023 { 6, 0x989c,
1024 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1025 { 6, 0x989c,
1026 { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
1027 { 6, 0x989c,
1028 { 0x00009688, 0x00009688, 0x00009688, 0x00009688, 0x00009688 } },
1029 { 6, 0x98c4,
1030 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1031 { 7, 0x989c,
1032 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
1033 { 7, 0x989c,
1034 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
1035 { 7, 0x98cc,
1036 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
1037 };
1038
1039 /*
1040 * TODO: Handle the few differences with swan during
1041 * bank modification and get rid of this
1042 * XXX: a/aTurbo ?
1043 */
1044 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
1045 { 1, 0x98d4,
1046 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
1047 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
1048 { 2, 0x98d0,
1049 { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
1050 { 3, 0x98dc,
1051 { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
1052 { 6, 0x989c,
1053 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
1054 { 6, 0x989c,
1055 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1056 { 6, 0x989c,
1057 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1058 { 6, 0x989c,
1059 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1060 { 6, 0x989c,
1061 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1062 { 6, 0x989c,
1063 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1064 { 6, 0x989c,
1065 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1066 { 6, 0x989c,
1067 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1068 { 6, 0x989c,
1069 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1070 { 6, 0x989c,
1071 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1072 { 6, 0x989c,
1073 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1074 { 6, 0x989c,
1075 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
1076 { 6, 0x989c,
1077 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1078 { 6, 0x989c,
1079 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1080 { 6, 0x989c,
1081 { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
1082 { 6, 0x989c,
1083 { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
1084 { 6, 0x989c,
1085 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
1086 { 6, 0x989c,
1087 { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
1088 { 6, 0x989c,
1089 { 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 } },
1090 { 6, 0x989c,
1091 { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
1092 { 6, 0x989c,
1093 { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
1094 { 6, 0x989c,
1095 { 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a } },
1096 { 6, 0x989c,
1097 { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
1098 { 6, 0x989c,
1099 { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
1100 { 6, 0x989c,
1101 { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
1102 { 6, 0x989c,
1103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1104 { 6, 0x989c,
1105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1106 { 6, 0x989c,
1107 { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
1108 { 6, 0x989c,
1109 { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
1110 { 6, 0x98c4,
1111 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1112 { 7, 0x989c,
1113 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
1114 { 7, 0x989c,
1115 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
1116 { 7, 0x98cc,
1117 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
1118 };
(deprecated) Btrfs devel tree