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bnx2x: fix MF for 4-port devices
[linux-2.6/btrfs-unstable.git] / drivers / net / bnx2x / bnx2x_main.c
blob9633e9b6853ce25f79ce1e6b2cf62c8c0f345fd5
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
41 #include <net/ip.h>
42 #include <net/ipv6.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
51 #include <linux/io.h>
52 #include <linux/stringify.h>
53 #include <linux/vmalloc.h>
54
55 #include "bnx2x.h"
56 #include "bnx2x_init.h"
57 #include "bnx2x_init_ops.h"
58 #include "bnx2x_cmn.h"
59 #include "bnx2x_dcb.h"
60 #include "bnx2x_sp.h"
61
62 #include <linux/firmware.h>
63 #include "bnx2x_fw_file_hdr.h"
64 /* FW files */
65 #define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
70 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
72 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
73
74 /* Time in jiffies before concluding the transmitter is hung */
75 #define TX_TIMEOUT (5*HZ)
76
77 static char version[] __devinitdata =
78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
81 MODULE_AUTHOR("Eliezer Tamir");
82 MODULE_DESCRIPTION("Broadcom NetXtreme II "
83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
86 MODULE_LICENSE("GPL");
87 MODULE_VERSION(DRV_MODULE_VERSION);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1);
89 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
90 MODULE_FIRMWARE(FW_FILE_NAME_E2);
91
92 static int multi_mode = 1;
93 module_param(multi_mode, int, 0);
94 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
96
97 int num_queues;
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
101
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
108 static int int_mode;
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
111 "(1 INT#x; 2 MSI)");
112
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
117 static int poll;
118 module_param(poll, int, 0);
119 MODULE_PARM_DESC(poll, " Use polling (for debug)");
120
121 static int mrrs = -1;
122 module_param(mrrs, int, 0);
123 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
124
125 static int debug;
126 module_param(debug, int, 0);
127 MODULE_PARM_DESC(debug, " Default debug msglevel");
128
129
130
131 struct workqueue_struct *bnx2x_wq;
132
133 enum bnx2x_board_type {
134 BCM57710 = 0,
135 BCM57711,
136 BCM57711E,
137 BCM57712,
138 BCM57712_MF,
139 BCM57800,
140 BCM57800_MF,
141 BCM57810,
142 BCM57810_MF,
143 BCM57840,
144 BCM57840_MF
145 };
146
147 /* indexed by board_type, above */
148 static struct {
149 char *name;
150 } board_info[] __devinitdata = {
151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
163 };
164
165 #ifndef PCI_DEVICE_ID_NX2_57710
166 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167 #endif
168 #ifndef PCI_DEVICE_ID_NX2_57711
169 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170 #endif
171 #ifndef PCI_DEVICE_ID_NX2_57711E
172 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57712
175 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57712_MF
178 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57800
181 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57800_MF
184 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57810
187 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57810_MF
190 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57840
193 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57840_MF
196 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197 #endif
198 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
210 { 0 }
211 };
212
213 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
214
215 /****************************************************************************
216 * General service functions
217 ****************************************************************************/
218
219 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
221 {
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
224 }
225
226 static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
228 {
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
231
232 __storm_memset_dma_mapping(bp, addr, mapping);
233 }
234
235 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
236 u16 pf_id)
237 {
238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
239 pf_id);
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
241 pf_id);
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
243 pf_id);
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
245 pf_id);
246 }
247
248 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
249 u8 enable)
250 {
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
252 enable);
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
254 enable);
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
256 enable);
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
258 enable);
259 }
260
261 static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
263 u16 pfid)
264 {
265 size_t size = sizeof(struct event_ring_data);
266
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
268
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
270 }
271
272 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
273 u16 pfid)
274 {
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
277 }
278
279 /* used only at init
280 * locking is done by mcp
281 */
282 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
283 {
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
288 }
289
290 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
291 {
292 u32 val;
293
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
298
299 return val;
300 }
301
302 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306 #define DMAE_DP_DST_NONE "dst_addr [none]"
307
308 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
309 int msglvl)
310 {
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
312
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
322 dmae->comp_val);
323 else
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
330 dmae->comp_val);
331 break;
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
340 dmae->comp_val);
341 else
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
348 dmae->comp_val);
349 break;
350 default:
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
354 "dst_addr [none]\n"
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
358 dmae->comp_val);
359 else
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
362 "dst_addr [none]\n"
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
366 dmae->comp_val);
367 break;
368 }
369
370 }
371
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
374 {
375 u32 cmd_offset;
376 int i;
377
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
381
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
384 }
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
386 }
387
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
389 {
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
391 DMAE_CMD_C_ENABLE);
392 }
393
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
395 {
396 return opcode & ~DMAE_CMD_SRC_RESET;
397 }
398
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
401 {
402 u32 opcode = 0;
403
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
406
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
413
414 #ifdef __BIG_ENDIAN
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
416 #else
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
418 #endif
419 if (with_comp)
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
421 return opcode;
422 }
423
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
427 {
428 memset(dmae, 0, sizeof(struct dmae_command));
429
430 /* set the opcode */
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
433
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
438 }
439
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
443 {
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
446 int rc = 0;
447
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
451
452 /*
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
456 */
457 spin_lock_bh(&bp->dmae_lock);
458
459 /* reset completion */
460 *wb_comp = 0;
461
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
464
465 /* wait for completion */
466 udelay(5);
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
469
470 if (!cnt) {
471 BNX2X_ERR("DMAE timeout!\n");
472 rc = DMAE_TIMEOUT;
473 goto unlock;
474 }
475 cnt--;
476 udelay(50);
477 }
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
480 rc = DMAE_PCI_ERROR;
481 }
482
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
486
487 unlock:
488 spin_unlock_bh(&bp->dmae_lock);
489 return rc;
490 }
491
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
493 u32 len32)
494 {
495 struct dmae_command dmae;
496
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
499
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
503 return;
504 }
505
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
508
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
514 dmae.len = len32;
515
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
517
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
520 }
521
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
523 {
524 struct dmae_command dmae;
525
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
528 int i;
529
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
534 return;
535 }
536
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
539
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
545 dmae.len = len32;
546
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
548
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
551 }
552
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
554 u32 addr, u32 len)
555 {
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
557 int offset = 0;
558
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
563 len -= dmae_wr_max;
564 }
565
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
567 }
568
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
571 {
572 u32 wb_write[2];
573
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
577 }
578
579 #ifdef USE_WB_RD
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
581 {
582 u32 wb_data[2];
583
584 REG_RD_DMAE(bp, reg, wb_data, 2);
585
586 return HILO_U64(wb_data[0], wb_data[1]);
587 }
588 #endif
589
590 static int bnx2x_mc_assert(struct bnx2x *bp)
591 {
592 char last_idx;
593 int i, rc = 0;
594 u32 row0, row1, row2, row3;
595
596 /* XSTORM */
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
599 if (last_idx)
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
601
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
604
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
613
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
618 rc++;
619 } else {
620 break;
621 }
622 }
623
624 /* TSTORM */
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
627 if (last_idx)
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
629
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
632
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
641
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
646 rc++;
647 } else {
648 break;
649 }
650 }
651
652 /* CSTORM */
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
655 if (last_idx)
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
657
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
660
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
669
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
674 rc++;
675 } else {
676 break;
677 }
678 }
679
680 /* USTORM */
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
683 if (last_idx)
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
685
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
688
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
697
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
702 rc++;
703 } else {
704 break;
705 }
706 }
707
708 return rc;
709 }
710
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
712 {
713 u32 addr, val;
714 u32 mark, offset;
715 __be32 data[9];
716 int word;
717 u32 trace_shmem_base;
718 if (BP_NOMCP(bp)) {
719 BNX2X_ERR("NO MCP - can not dump\n");
720 return;
721 }
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
726
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
730
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
733 else
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
740
741 printk("%s", lvl);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
745 data[8] = 0x0;
746 pr_cont("%s", (char *)data);
747 }
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
751 data[8] = 0x0;
752 pr_cont("%s", (char *)data);
753 }
754 printk("%s" "end of fw dump\n", lvl);
755 }
756
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
758 {
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
760 }
761
762 void bnx2x_panic_dump(struct bnx2x *bp)
763 {
764 int i;
765 u16 j;
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
770 u8 cos;
771 #endif
772
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
775
776 BNX2X_ERR("begin crash dump -----------------\n");
777
778 /* Indices */
779 /* Common */
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
789 BNX2X_ERR(" def (");
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
791 pr_cont("0x%x%s",
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
794
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
798 i*sizeof(u32));
799
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
801 "pf_id(0x%x) vnic_id(0x%x) "
802 "vf_id(0x%x) vf_valid (0x%x) "
803 "state(0x%x)\n",
804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
809 sp_sb_data.p_func.vf_valid,
810 sp_sb_data.state);
811
812
813 for_each_eth_queue(bp, i) {
814 struct bnx2x_fastpath *fp = &bp->fp[i];
815 int loop;
816 struct hc_status_block_data_e2 sb_data_e2;
817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
819 CHIP_IS_E1x(bp) ?
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
822 struct hc_index_data *hc_index_p =
823 CHIP_IS_E1x(bp) ?
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
826 u8 data_size, cos;
827 u32 *sb_data_p;
828 struct bnx2x_fp_txdata txdata;
829
830 /* Rx */
831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
832 " rx_comp_prod(0x%x)"
833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
834 i, fp->rx_bd_prod, fp->rx_bd_cons,
835 fp->rx_comp_prod,
836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
838 " fp_hc_idx(0x%x)\n",
839 fp->rx_sge_prod, fp->last_max_sge,
840 le16_to_cpu(fp->fp_hc_idx));
841
842 /* Tx */
843 for_each_cos_in_tx_queue(fp, cos)
844 {
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
851 txdata.tx_bd_cons,
852 le16_to_cpu(*txdata.tx_cons_sb));
853 }
854
855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
857
858 /* host sb data */
859
860 #ifdef BCM_CNIC
861 if (IS_FCOE_FP(fp))
862 continue;
863 #endif
864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
866 pr_cont("0x%x%s",
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
869
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
872 pr_cont("0x%x%s",
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
875 /* fw sb data */
876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
879 data_size /= sizeof(u32);
880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
882 (u32 *)&sb_data_e2;
883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
887 j * sizeof(u32));
888
889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
892 "state(0x%x)\n",
893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
899 } else {
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
902 "state(0x%x)\n",
903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
909 }
910
911 /* SB_SMs data */
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
917 hc_sm_p[j].__flags,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
922 }
923
924 /* Indecies data */
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
928 hc_index_p[j].flags,
929 hc_index_p[j].timeout);
930 }
931 }
932
933 #ifdef BNX2X_STOP_ON_ERROR
934 /* Rings */
935 /* Rx */
936 for_each_rx_queue(bp, i) {
937 struct bnx2x_fastpath *fp = &bp->fp[i];
938
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
941 for (j = start; j != end; j = RX_BD(j + 1)) {
942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
944
945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
947 }
948
949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
951 for (j = start; j != end; j = RX_SGE(j + 1)) {
952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
954
955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
957 }
958
959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
963
964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
966 }
967 }
968
969 /* Tx */
970 for_each_tx_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
974
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
980
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
984 sw_bd->first_bd);
985 }
986
987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
991
992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
993 "[%x:%x:%x:%x]\n",
994 i, cos, j, tx_bd[0], tx_bd[1],
995 tx_bd[2], tx_bd[3]);
996 }
997 }
998 }
999 #endif
1000 bnx2x_fw_dump(bp);
1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
1003 }
1004
1005 /*
1006 * FLR Support for E2
1007 *
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 * initialization.
1010 */
1011 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012 #define FLR_WAIT_INTERAVAL 50 /* usec */
1013 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1014
1015 struct pbf_pN_buf_regs {
1016 int pN;
1017 u32 init_crd;
1018 u32 crd;
1019 u32 crd_freed;
1020 };
1021
1022 struct pbf_pN_cmd_regs {
1023 int pN;
1024 u32 lines_occup;
1025 u32 lines_freed;
1026 };
1027
1028 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1030 u32 poll_count)
1031 {
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1034
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1038
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1042
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1045 if (cur_cnt--) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1049 } else {
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1051 regs->pN);
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1053 regs->pN, crd);
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1056 break;
1057 }
1058 }
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1061 }
1062
1063 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1065 u32 poll_count)
1066 {
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1069
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1072
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1075
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1077 if (cur_cnt--) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1081 } else {
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1083 regs->pN);
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1085 regs->pN, occup);
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1087 regs->pN, freed);
1088 break;
1089 }
1090 }
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1093 }
1094
1095 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1097 {
1098 u32 cur_cnt = poll_count;
1099 u32 val;
1100
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1103
1104 return val;
1105 }
1106
1107 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1109 {
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1111 if (val != 0) {
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1113 return 1;
1114 }
1115 return 0;
1116 }
1117
1118 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1119 {
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1123
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1126
1127 return FLR_POLL_CNT;
1128 }
1129
1130 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1131 {
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1151 };
1152
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1158 PBF_REG_CREDIT_Q0 :
1159 PBF_REG_P0_CREDIT,
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1167 PBF_REG_CREDIT_Q1 :
1168 PBF_REG_P1_CREDIT,
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1177 PBF_REG_P4_CREDIT,
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1181 };
1182
1183 int i;
1184
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1188
1189
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1193 }
1194
1195 #define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1197
1198 #define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1200
1201 #define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203
1204
1205 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1206 u32 poll_cnt)
1207 {
1208 struct sdm_op_gen op_gen = {0};
1209
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1212 int ret = 0;
1213
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1216 return 1;
1217 }
1218
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1223
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1226
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 ret = 1;
1230 }
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1233
1234 return ret;
1235 }
1236
1237 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1238 {
1239 int pos;
1240 u16 status;
1241
1242 pos = pci_pcie_cap(dev);
1243 if (!pos)
1244 return false;
1245
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1248 }
1249
1250 /* PF FLR specific routines
1251 */
1252 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1253 {
1254
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1259 poll_cnt))
1260 return 1;
1261
1262
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1267 poll_cnt))
1268 return 1;
1269
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1274 poll_cnt))
1275 return 1;
1276
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1281 poll_cnt))
1282 return 1;
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1286 poll_cnt))
1287 return 1;
1288
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1293 poll_cnt))
1294 return 1;
1295
1296 return 0;
1297 }
1298
1299 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1300 {
1301 u32 val;
1302
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1305
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1308
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1311
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1314
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1317
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1320
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1323
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1326 val);
1327 }
1328
1329 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1330 {
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1332
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1334
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1337
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1340 return -EBUSY;
1341
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1343
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1346 return -EBUSY;
1347
1348 /* ATC cleanup */
1349
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1352
1353 /* Wait 100ms (not adjusted according to platform) */
1354 msleep(100);
1355
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1359
1360 /* Debug */
1361 bnx2x_hw_enable_status(bp);
1362
1363 /*
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1366 */
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1368
1369 return 0;
1370 }
1371
1372 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1373 {
1374 int port = BP_PORT(bp);
1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1379
1380 if (msix) {
1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1385 } else if (msi) {
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1390 } else {
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1395
1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1398 val, port, addr);
1399
1400 REG_WR(bp, addr, val);
1401
1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1403 }
1404 }
1405
1406 if (CHIP_IS_E1(bp))
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1408
1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1411
1412 REG_WR(bp, addr, val);
1413 /*
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1415 */
1416 mmiowb();
1417 barrier();
1418
1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */
1421 if (IS_MF(bp)) {
1422 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1423 if (bp->port.pmf)
1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100;
1426 } else
1427 val = 0xffff;
1428
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1431 }
1432
1433 /* Make sure that interrupts are indeed enabled from here on */
1434 mmiowb();
1435 }
1436
1437 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1438 {
1439 u32 val;
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1442
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1444
1445 if (msix) {
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1451 } else if (msi) {
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1457 } else {
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1463 }
1464
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1467
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1469
1470 barrier();
1471
1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100;
1478 } else
1479 val = 0xffff;
1480
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1483
1484 /* Make sure that interrupts are indeed enabled from here on */
1485 mmiowb();
1486 }
1487
1488 void bnx2x_int_enable(struct bnx2x *bp)
1489 {
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1492 else
1493 bnx2x_igu_int_enable(bp);
1494 }
1495
1496 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1497 {
1498 int port = BP_PORT(bp);
1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1501
1502 /*
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1506 */
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1511 */
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1513
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517 } else
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1522
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1524 val, port, addr);
1525
1526 /* flush all outstanding writes */
1527 mmiowb();
1528
1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532 }
1533
1534 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1535 {
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1537
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1541
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1543
1544 /* flush all outstanding writes */
1545 mmiowb();
1546
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550 }
1551
1552 void bnx2x_int_disable(struct bnx2x *bp)
1553 {
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1556 else
1557 bnx2x_igu_int_disable(bp);
1558 }
1559
1560 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1561 {
1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1563 int i, offset;
1564
1565 if (disable_hw)
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
1568
1569 /* make sure all ISRs are done */
1570 if (msix) {
1571 synchronize_irq(bp->msix_table[0].vector);
1572 offset = 1;
1573 #ifdef BCM_CNIC
1574 offset++;
1575 #endif
1576 for_each_eth_queue(bp, i)
1577 synchronize_irq(bp->msix_table[offset++].vector);
1578 } else
1579 synchronize_irq(bp->pdev->irq);
1580
1581 /* make sure sp_task is not running */
1582 cancel_delayed_work(&bp->sp_task);
1583 cancel_delayed_work(&bp->period_task);
1584 flush_workqueue(bnx2x_wq);
1585 }
1586
1587 /* fast path */
1588
1589 /*
1590 * General service functions
1591 */
1592
1593 /* Return true if succeeded to acquire the lock */
1594 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1595 {
1596 u32 lock_status;
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1600
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1602
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1605 DP(NETIF_MSG_HW,
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1608 return false;
1609 }
1610
1611 if (func <= 5)
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1613 else
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1616
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1621 return true;
1622
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1624 return false;
1625 }
1626
1627 /**
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1629 *
1630 * @bp: driver handle
1631 *
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1634 */
1635 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1636 {
1637 if (BP_PATH(bp))
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1639 else
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1641 }
1642
1643 /**
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1645 *
1646 * @bp: driver handle
1647 *
1648 * Tries to aquire a leader lock for cuurent engine.
1649 */
1650 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1651 {
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1653 }
1654
1655 #ifdef BCM_CNIC
1656 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1657 #endif
1658
1659 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1660 {
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1666
1667 DP(BNX2X_MSG_SP,
1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1669 fp->index, cid, command, bp->state,
1670 rr_cqe->ramrod_cqe.ramrod_type);
1671
1672 switch (command) {
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1676 break;
1677
1678 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1679 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1680 drv_cmd = BNX2X_Q_CMD_SETUP;
1681 break;
1682
1683 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1684 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1685 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1686 break;
1687
1688 case (RAMROD_CMD_ID_ETH_HALT):
1689 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1690 drv_cmd = BNX2X_Q_CMD_HALT;
1691 break;
1692
1693 case (RAMROD_CMD_ID_ETH_TERMINATE):
1694 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1695 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1696 break;
1697
1698 case (RAMROD_CMD_ID_ETH_EMPTY):
1699 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1700 drv_cmd = BNX2X_Q_CMD_EMPTY;
1701 break;
1702
1703 default:
1704 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1705 command, fp->index);
1706 return;
1707 }
1708
1709 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1710 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1711 /* q_obj->complete_cmd() failure means that this was
1712 * an unexpected completion.
1713 *
1714 * In this case we don't want to increase the bp->spq_left
1715 * because apparently we haven't sent this command the first
1716 * place.
1717 */
1718 #ifdef BNX2X_STOP_ON_ERROR
1719 bnx2x_panic();
1720 #else
1721 return;
1722 #endif
1723
1724 smp_mb__before_atomic_inc();
1725 atomic_inc(&bp->cq_spq_left);
1726 /* push the change in bp->spq_left and towards the memory */
1727 smp_mb__after_atomic_inc();
1728
1729 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1730
1731 return;
1732 }
1733
1734 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1735 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1736 {
1737 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1738
1739 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1740 start);
1741 }
1742
1743 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1744 {
1745 struct bnx2x *bp = netdev_priv(dev_instance);
1746 u16 status = bnx2x_ack_int(bp);
1747 u16 mask;
1748 int i;
1749 u8 cos;
1750
1751 /* Return here if interrupt is shared and it's not for us */
1752 if (unlikely(status == 0)) {
1753 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1754 return IRQ_NONE;
1755 }
1756 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1757
1758 #ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic))
1760 return IRQ_HANDLED;
1761 #endif
1762
1763 for_each_eth_queue(bp, i) {
1764 struct bnx2x_fastpath *fp = &bp->fp[i];
1765
1766 mask = 0x2 << (fp->index + CNIC_PRESENT);
1767 if (status & mask) {
1768 /* Handle Rx or Tx according to SB id */
1769 prefetch(fp->rx_cons_sb);
1770 for_each_cos_in_tx_queue(fp, cos)
1771 prefetch(fp->txdata[cos].tx_cons_sb);
1772 prefetch(&fp->sb_running_index[SM_RX_ID]);
1773 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1774 status &= ~mask;
1775 }
1776 }
1777
1778 #ifdef BCM_CNIC
1779 mask = 0x2;
1780 if (status & (mask | 0x1)) {
1781 struct cnic_ops *c_ops = NULL;
1782
1783 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1784 rcu_read_lock();
1785 c_ops = rcu_dereference(bp->cnic_ops);
1786 if (c_ops)
1787 c_ops->cnic_handler(bp->cnic_data, NULL);
1788 rcu_read_unlock();
1789 }
1790
1791 status &= ~mask;
1792 }
1793 #endif
1794
1795 if (unlikely(status & 0x1)) {
1796 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1797
1798 status &= ~0x1;
1799 if (!status)
1800 return IRQ_HANDLED;
1801 }
1802
1803 if (unlikely(status))
1804 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1805 status);
1806
1807 return IRQ_HANDLED;
1808 }
1809
1810 /* Link */
1811
1812 /*
1813 * General service functions
1814 */
1815
1816 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1817 {
1818 u32 lock_status;
1819 u32 resource_bit = (1 << resource);
1820 int func = BP_FUNC(bp);
1821 u32 hw_lock_control_reg;
1822 int cnt;
1823
1824 /* Validating that the resource is within range */
1825 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1826 DP(NETIF_MSG_HW,
1827 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1828 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1829 return -EINVAL;
1830 }
1831
1832 if (func <= 5) {
1833 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1834 } else {
1835 hw_lock_control_reg =
1836 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1837 }
1838
1839 /* Validating that the resource is not already taken */
1840 lock_status = REG_RD(bp, hw_lock_control_reg);
1841 if (lock_status & resource_bit) {
1842 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1843 lock_status, resource_bit);
1844 return -EEXIST;
1845 }
1846
1847 /* Try for 5 second every 5ms */
1848 for (cnt = 0; cnt < 1000; cnt++) {
1849 /* Try to acquire the lock */
1850 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1851 lock_status = REG_RD(bp, hw_lock_control_reg);
1852 if (lock_status & resource_bit)
1853 return 0;
1854
1855 msleep(5);
1856 }
1857 DP(NETIF_MSG_HW, "Timeout\n");
1858 return -EAGAIN;
1859 }
1860
1861 int bnx2x_release_leader_lock(struct bnx2x *bp)
1862 {
1863 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1864 }
1865
1866 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1867 {
1868 u32 lock_status;
1869 u32 resource_bit = (1 << resource);
1870 int func = BP_FUNC(bp);
1871 u32 hw_lock_control_reg;
1872
1873 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1874
1875 /* Validating that the resource is within range */
1876 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1877 DP(NETIF_MSG_HW,
1878 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1879 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1880 return -EINVAL;
1881 }
1882
1883 if (func <= 5) {
1884 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1885 } else {
1886 hw_lock_control_reg =
1887 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1888 }
1889
1890 /* Validating that the resource is currently taken */
1891 lock_status = REG_RD(bp, hw_lock_control_reg);
1892 if (!(lock_status & resource_bit)) {
1893 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1894 lock_status, resource_bit);
1895 return -EFAULT;
1896 }
1897
1898 REG_WR(bp, hw_lock_control_reg, resource_bit);
1899 return 0;
1900 }
1901
1902
1903 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1904 {
1905 /* The GPIO should be swapped if swap register is set and active */
1906 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1907 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1908 int gpio_shift = gpio_num +
1909 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1910 u32 gpio_mask = (1 << gpio_shift);
1911 u32 gpio_reg;
1912 int value;
1913
1914 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1915 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1916 return -EINVAL;
1917 }
1918
1919 /* read GPIO value */
1920 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1921
1922 /* get the requested pin value */
1923 if ((gpio_reg & gpio_mask) == gpio_mask)
1924 value = 1;
1925 else
1926 value = 0;
1927
1928 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1929
1930 return value;
1931 }
1932
1933 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1934 {
1935 /* The GPIO should be swapped if swap register is set and active */
1936 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1937 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1938 int gpio_shift = gpio_num +
1939 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1940 u32 gpio_mask = (1 << gpio_shift);
1941 u32 gpio_reg;
1942
1943 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1944 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1945 return -EINVAL;
1946 }
1947
1948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1949 /* read GPIO and mask except the float bits */
1950 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1951
1952 switch (mode) {
1953 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1954 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1955 gpio_num, gpio_shift);
1956 /* clear FLOAT and set CLR */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1959 break;
1960
1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set SET */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1967 break;
1968
1969 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1971 gpio_num, gpio_shift);
1972 /* set FLOAT */
1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1974 break;
1975
1976 default:
1977 break;
1978 }
1979
1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1981 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1982
1983 return 0;
1984 }
1985
1986 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1987 {
1988 u32 gpio_reg = 0;
1989 int rc = 0;
1990
1991 /* Any port swapping should be handled by caller. */
1992
1993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 /* read GPIO and mask except the float bits */
1995 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1997 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1998 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1999
2000 switch (mode) {
2001 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2003 /* set CLR */
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2005 break;
2006
2007 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2009 /* set SET */
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2011 break;
2012
2013 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2015 /* set FLOAT */
2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2017 break;
2018
2019 default:
2020 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2021 rc = -EINVAL;
2022 break;
2023 }
2024
2025 if (rc == 0)
2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2027
2028 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2029
2030 return rc;
2031 }
2032
2033 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2034 {
2035 /* The GPIO should be swapped if swap register is set and active */
2036 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2037 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2038 int gpio_shift = gpio_num +
2039 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2040 u32 gpio_mask = (1 << gpio_shift);
2041 u32 gpio_reg;
2042
2043 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2044 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2045 return -EINVAL;
2046 }
2047
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2049 /* read GPIO int */
2050 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2051
2052 switch (mode) {
2053 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2054 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2055 "output low\n", gpio_num, gpio_shift);
2056 /* clear SET and set CLR */
2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2059 break;
2060
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2062 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2063 "output high\n", gpio_num, gpio_shift);
2064 /* clear CLR and set SET */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2067 break;
2068
2069 default:
2070 break;
2071 }
2072
2073 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2075
2076 return 0;
2077 }
2078
2079 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2080 {
2081 u32 spio_mask = (1 << spio_num);
2082 u32 spio_reg;
2083
2084 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2085 (spio_num > MISC_REGISTERS_SPIO_7)) {
2086 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2087 return -EINVAL;
2088 }
2089
2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2091 /* read SPIO and mask except the float bits */
2092 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2093
2094 switch (mode) {
2095 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2096 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2097 /* clear FLOAT and set CLR */
2098 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2100 break;
2101
2102 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2103 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2104 /* clear FLOAT and set SET */
2105 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2107 break;
2108
2109 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2110 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2111 /* set FLOAT */
2112 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2113 break;
2114
2115 default:
2116 break;
2117 }
2118
2119 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2121
2122 return 0;
2123 }
2124
2125 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2126 {
2127 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2128 switch (bp->link_vars.ieee_fc &
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2130 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2131 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2132 ADVERTISED_Pause);
2133 break;
2134
2135 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2136 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2137 ADVERTISED_Pause);
2138 break;
2139
2140 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2141 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2142 break;
2143
2144 default:
2145 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2146 ADVERTISED_Pause);
2147 break;
2148 }
2149 }
2150
2151 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2152 {
2153 if (!BP_NOMCP(bp)) {
2154 u8 rc;
2155 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2156 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2157 /*
2158 * Initialize link parameters structure variables
2159 * It is recommended to turn off RX FC for jumbo frames
2160 * for better performance
2161 */
2162 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2164 else
2165 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2166
2167 bnx2x_acquire_phy_lock(bp);
2168
2169 if (load_mode == LOAD_DIAG) {
2170 struct link_params *lp = &bp->link_params;
2171 lp->loopback_mode = LOOPBACK_XGXS;
2172 /* do PHY loopback at 10G speed, if possible */
2173 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2174 if (lp->speed_cap_mask[cfx_idx] &
2175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2176 lp->req_line_speed[cfx_idx] =
2177 SPEED_10000;
2178 else
2179 lp->req_line_speed[cfx_idx] =
2180 SPEED_1000;
2181 }
2182 }
2183
2184 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2185
2186 bnx2x_release_phy_lock(bp);
2187
2188 bnx2x_calc_fc_adv(bp);
2189
2190 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2191 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2192 bnx2x_link_report(bp);
2193 } else
2194 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2195 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2196 return rc;
2197 }
2198 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2199 return -EINVAL;
2200 }
2201
2202 void bnx2x_link_set(struct bnx2x *bp)
2203 {
2204 if (!BP_NOMCP(bp)) {
2205 bnx2x_acquire_phy_lock(bp);
2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2207 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2208 bnx2x_release_phy_lock(bp);
2209
2210 bnx2x_calc_fc_adv(bp);
2211 } else
2212 BNX2X_ERR("Bootcode is missing - can not set link\n");
2213 }
2214
2215 static void bnx2x__link_reset(struct bnx2x *bp)
2216 {
2217 if (!BP_NOMCP(bp)) {
2218 bnx2x_acquire_phy_lock(bp);
2219 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2220 bnx2x_release_phy_lock(bp);
2221 } else
2222 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2223 }
2224
2225 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2226 {
2227 u8 rc = 0;
2228
2229 if (!BP_NOMCP(bp)) {
2230 bnx2x_acquire_phy_lock(bp);
2231 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2232 is_serdes);
2233 bnx2x_release_phy_lock(bp);
2234 } else
2235 BNX2X_ERR("Bootcode is missing - can not test link\n");
2236
2237 return rc;
2238 }
2239
2240 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2241 {
2242 u32 r_param = bp->link_vars.line_speed / 8;
2243 u32 fair_periodic_timeout_usec;
2244 u32 t_fair;
2245
2246 memset(&(bp->cmng.rs_vars), 0,
2247 sizeof(struct rate_shaping_vars_per_port));
2248 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2249
2250 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2251 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2252
2253 /* this is the threshold below which no timer arming will occur
2254 1.25 coefficient is for the threshold to be a little bigger
2255 than the real time, to compensate for timer in-accuracy */
2256 bp->cmng.rs_vars.rs_threshold =
2257 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2258
2259 /* resolution of fairness timer */
2260 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2261 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2262 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2263
2264 /* this is the threshold below which we won't arm the timer anymore */
2265 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2266
2267 /* we multiply by 1e3/8 to get bytes/msec.
2268 We don't want the credits to pass a credit
2269 of the t_fair*FAIR_MEM (algorithm resolution) */
2270 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2271 /* since each tick is 4 usec */
2272 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2273 }
2274
2275 /* Calculates the sum of vn_min_rates.
2276 It's needed for further normalizing of the min_rates.
2277 Returns:
2278 sum of vn_min_rates.
2279 or
2280 0 - if all the min_rates are 0.
2281 In the later case fainess algorithm should be deactivated.
2282 If not all min_rates are zero then those that are zeroes will be set to 1.
2283 */
2284 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2285 {
2286 int all_zero = 1;
2287 int vn;
2288
2289 bp->vn_weight_sum = 0;
2290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2291 u32 vn_cfg = bp->mf_config[vn];
2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2294
2295 /* Skip hidden vns */
2296 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2297 continue;
2298
2299 /* If min rate is zero - set it to 1 */
2300 if (!vn_min_rate)
2301 vn_min_rate = DEF_MIN_RATE;
2302 else
2303 all_zero = 0;
2304
2305 bp->vn_weight_sum += vn_min_rate;
2306 }
2307
2308 /* if ETS or all min rates are zeros - disable fairness */
2309 if (BNX2X_IS_ETS_ENABLED(bp)) {
2310 bp->cmng.flags.cmng_enables &=
2311 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2312 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2313 } else if (all_zero) {
2314 bp->cmng.flags.cmng_enables &=
2315 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2316 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2317 " fairness will be disabled\n");
2318 } else
2319 bp->cmng.flags.cmng_enables |=
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2321 }
2322
2323 /* returns func by VN for current port */
2324 static inline int func_by_vn(struct bnx2x *bp, int vn)
2325 {
2326 return 2 * vn + BP_PORT(bp);
2327 }
2328
2329 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2330 {
2331 struct rate_shaping_vars_per_vn m_rs_vn;
2332 struct fairness_vars_per_vn m_fair_vn;
2333 u32 vn_cfg = bp->mf_config[vn];
2334 int func = func_by_vn(bp, vn);
2335 u16 vn_min_rate, vn_max_rate;
2336 int i;
2337
2338 /* If function is hidden - set min and max to zeroes */
2339 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2340 vn_min_rate = 0;
2341 vn_max_rate = 0;
2342
2343 } else {
2344 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2345
2346 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2347 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2348 /* If fairness is enabled (not all min rates are zeroes) and
2349 if current min rate is zero - set it to 1.
2350 This is a requirement of the algorithm. */
2351 if (bp->vn_weight_sum && (vn_min_rate == 0))
2352 vn_min_rate = DEF_MIN_RATE;
2353
2354 if (IS_MF_SI(bp))
2355 /* maxCfg in percents of linkspeed */
2356 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2357 else
2358 /* maxCfg is absolute in 100Mb units */
2359 vn_max_rate = maxCfg * 100;
2360 }
2361
2362 DP(NETIF_MSG_IFUP,
2363 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2364 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2365
2366 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2367 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2368
2369 /* global vn counter - maximal Mbps for this vn */
2370 m_rs_vn.vn_counter.rate = vn_max_rate;
2371
2372 /* quota - number of bytes transmitted in this period */
2373 m_rs_vn.vn_counter.quota =
2374 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2375
2376 if (bp->vn_weight_sum) {
2377 /* credit for each period of the fairness algorithm:
2378 number of bytes in T_FAIR (the vn share the port rate).
2379 vn_weight_sum should not be larger than 10000, thus
2380 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2381 than zero */
2382 m_fair_vn.vn_credit_delta =
2383 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2384 (8 * bp->vn_weight_sum))),
2385 (bp->cmng.fair_vars.fair_threshold +
2386 MIN_ABOVE_THRESH));
2387 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2388 m_fair_vn.vn_credit_delta);
2389 }
2390
2391 /* Store it to internal memory */
2392 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2393 REG_WR(bp, BAR_XSTRORM_INTMEM +
2394 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2395 ((u32 *)(&m_rs_vn))[i]);
2396
2397 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2398 REG_WR(bp, BAR_XSTRORM_INTMEM +
2399 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2400 ((u32 *)(&m_fair_vn))[i]);
2401 }
2402
2403 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2404 {
2405 if (CHIP_REV_IS_SLOW(bp))
2406 return CMNG_FNS_NONE;
2407 if (IS_MF(bp))
2408 return CMNG_FNS_MINMAX;
2409
2410 return CMNG_FNS_NONE;
2411 }
2412
2413 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2414 {
2415 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2416
2417 if (BP_NOMCP(bp))
2418 return; /* what should be the default bvalue in this case */
2419
2420 /* For 2 port configuration the absolute function number formula
2421 * is:
2422 * abs_func = 2 * vn + BP_PORT + BP_PATH
2423 *
2424 * and there are 4 functions per port
2425 *
2426 * For 4 port configuration it is
2427 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2428 *
2429 * and there are 2 functions per port
2430 */
2431 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2432 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2433
2434 if (func >= E1H_FUNC_MAX)
2435 break;
2436
2437 bp->mf_config[vn] =
2438 MF_CFG_RD(bp, func_mf_config[func].config);
2439 }
2440 }
2441
2442 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2443 {
2444
2445 if (cmng_type == CMNG_FNS_MINMAX) {
2446 int vn;
2447
2448 /* clear cmng_enables */
2449 bp->cmng.flags.cmng_enables = 0;
2450
2451 /* read mf conf from shmem */
2452 if (read_cfg)
2453 bnx2x_read_mf_cfg(bp);
2454
2455 /* Init rate shaping and fairness contexts */
2456 bnx2x_init_port_minmax(bp);
2457
2458 /* vn_weight_sum and enable fairness if not 0 */
2459 bnx2x_calc_vn_weight_sum(bp);
2460
2461 /* calculate and set min-max rate for each vn */
2462 if (bp->port.pmf)
2463 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2464 bnx2x_init_vn_minmax(bp, vn);
2465
2466 /* always enable rate shaping and fairness */
2467 bp->cmng.flags.cmng_enables |=
2468 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2469 if (!bp->vn_weight_sum)
2470 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2471 " fairness will be disabled\n");
2472 return;
2473 }
2474
2475 /* rate shaping and fairness are disabled */
2476 DP(NETIF_MSG_IFUP,
2477 "rate shaping and fairness are disabled\n");
2478 }
2479
2480 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2481 {
2482 int func;
2483 int vn;
2484
2485 /* Set the attention towards other drivers on the same port */
2486 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2487 if (vn == BP_VN(bp))
2488 continue;
2489
2490 func = func_by_vn(bp, vn);
2491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2492 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2493 }
2494 }
2495
2496 /* This function is called upon link interrupt */
2497 static void bnx2x_link_attn(struct bnx2x *bp)
2498 {
2499 /* Make sure that we are synced with the current statistics */
2500 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2501
2502 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2503
2504 if (bp->link_vars.link_up) {
2505
2506 /* dropless flow control */
2507 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2508 int port = BP_PORT(bp);
2509 u32 pause_enabled = 0;
2510
2511 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2512 pause_enabled = 1;
2513
2514 REG_WR(bp, BAR_USTRORM_INTMEM +
2515 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2516 pause_enabled);
2517 }
2518
2519 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2520 struct host_port_stats *pstats;
2521
2522 pstats = bnx2x_sp(bp, port_stats);
2523 /* reset old mac stats */
2524 memset(&(pstats->mac_stx[0]), 0,
2525 sizeof(struct mac_stx));
2526 }
2527 if (bp->state == BNX2X_STATE_OPEN)
2528 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2529 }
2530
2531 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2532 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2533
2534 if (cmng_fns != CMNG_FNS_NONE) {
2535 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2536 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2537 } else
2538 /* rate shaping and fairness are disabled */
2539 DP(NETIF_MSG_IFUP,
2540 "single function mode without fairness\n");
2541 }
2542
2543 __bnx2x_link_report(bp);
2544
2545 if (IS_MF(bp))
2546 bnx2x_link_sync_notify(bp);
2547 }
2548
2549 void bnx2x__link_status_update(struct bnx2x *bp)
2550 {
2551 if (bp->state != BNX2X_STATE_OPEN)
2552 return;
2553
2554 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2555
2556 if (bp->link_vars.link_up)
2557 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2558 else
2559 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2560
2561 /* indicate link status */
2562 bnx2x_link_report(bp);
2563 }
2564
2565 static void bnx2x_pmf_update(struct bnx2x *bp)
2566 {
2567 int port = BP_PORT(bp);
2568 u32 val;
2569
2570 bp->port.pmf = 1;
2571 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2572
2573 /*
2574 * We need the mb() to ensure the ordering between the writing to
2575 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2576 */
2577 smp_mb();
2578
2579 /* queue a periodic task */
2580 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2581
2582 bnx2x_dcbx_pmf_update(bp);
2583
2584 /* enable nig attention */
2585 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2586 if (bp->common.int_block == INT_BLOCK_HC) {
2587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2589 } else if (!CHIP_IS_E1x(bp)) {
2590 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2591 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2592 }
2593
2594 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2595 }
2596
2597 /* end of Link */
2598
2599 /* slow path */
2600
2601 /*
2602 * General service functions
2603 */
2604
2605 /* send the MCP a request, block until there is a reply */
2606 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2607 {
2608 int mb_idx = BP_FW_MB_IDX(bp);
2609 u32 seq;
2610 u32 rc = 0;
2611 u32 cnt = 1;
2612 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2613
2614 mutex_lock(&bp->fw_mb_mutex);
2615 seq = ++bp->fw_seq;
2616 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2617 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2618
2619 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2620 (command | seq), param);
2621
2622 do {
2623 /* let the FW do it's magic ... */
2624 msleep(delay);
2625
2626 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2627
2628 /* Give the FW up to 5 second (500*10ms) */
2629 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2630
2631 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2632 cnt*delay, rc, seq);
2633
2634 /* is this a reply to our command? */
2635 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2636 rc &= FW_MSG_CODE_MASK;
2637 else {
2638 /* FW BUG! */
2639 BNX2X_ERR("FW failed to respond!\n");
2640 bnx2x_fw_dump(bp);
2641 rc = 0;
2642 }
2643 mutex_unlock(&bp->fw_mb_mutex);
2644
2645 return rc;
2646 }
2647
2648 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2649 {
2650 #ifdef BCM_CNIC
2651 /* Statistics are not supported for CNIC Clients at the moment */
2652 if (IS_FCOE_FP(fp))
2653 return false;
2654 #endif
2655 return true;
2656 }
2657
2658 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2659 {
2660 if (CHIP_IS_E1x(bp)) {
2661 struct tstorm_eth_function_common_config tcfg = {0};
2662
2663 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2664 }
2665
2666 /* Enable the function in the FW */
2667 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2668 storm_memset_func_en(bp, p->func_id, 1);
2669
2670 /* spq */
2671 if (p->func_flgs & FUNC_FLG_SPQ) {
2672 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2673 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2674 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2675 }
2676 }
2677
2678 /**
2679 * bnx2x_get_tx_only_flags - Return common flags
2680 *
2681 * @bp device handle
2682 * @fp queue handle
2683 * @zero_stats TRUE if statistics zeroing is needed
2684 *
2685 * Return the flags that are common for the Tx-only and not normal connections.
2686 */
2687 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2688 struct bnx2x_fastpath *fp,
2689 bool zero_stats)
2690 {
2691 unsigned long flags = 0;
2692
2693 /* PF driver will always initialize the Queue to an ACTIVE state */
2694 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2695
2696 /* tx only connections collect statistics (on the same index as the
2697 * parent connection). The statistics are zeroed when the parent
2698 * connection is initialized.
2699 */
2700 if (stat_counter_valid(bp, fp)) {
2701 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2702 if (zero_stats)
2703 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2704 }
2705
2706 return flags;
2707 }
2708
2709 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2710 struct bnx2x_fastpath *fp,
2711 bool leading)
2712 {
2713 unsigned long flags = 0;
2714
2715 /* calculate other queue flags */
2716 if (IS_MF_SD(bp))
2717 __set_bit(BNX2X_Q_FLG_OV, &flags);
2718
2719 if (IS_FCOE_FP(fp))
2720 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2721
2722 if (!fp->disable_tpa) {
2723 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2724 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2725 }
2726
2727 if (leading) {
2728 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2729 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2730 }
2731
2732 /* Always set HW VLAN stripping */
2733 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2734
2735
2736 return flags | bnx2x_get_common_flags(bp, fp, true);
2737 }
2738
2739 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2740 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2741 u8 cos)
2742 {
2743 gen_init->stat_id = bnx2x_stats_id(fp);
2744 gen_init->spcl_id = fp->cl_id;
2745
2746 /* Always use mini-jumbo MTU for FCoE L2 ring */
2747 if (IS_FCOE_FP(fp))
2748 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2749 else
2750 gen_init->mtu = bp->dev->mtu;
2751
2752 gen_init->cos = cos;
2753 }
2754
2755 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2756 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2757 struct bnx2x_rxq_setup_params *rxq_init)
2758 {
2759 u8 max_sge = 0;
2760 u16 sge_sz = 0;
2761 u16 tpa_agg_size = 0;
2762
2763 if (!fp->disable_tpa) {
2764 pause->sge_th_lo = SGE_TH_LO(bp);
2765 pause->sge_th_hi = SGE_TH_HI(bp);
2766
2767 /* validate SGE ring has enough to cross high threshold */
2768 WARN_ON(bp->dropless_fc &&
2769 pause->sge_th_hi + FW_PREFETCH_CNT >
2770 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2771
2772 tpa_agg_size = min_t(u32,
2773 (min_t(u32, 8, MAX_SKB_FRAGS) *
2774 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2775 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2776 SGE_PAGE_SHIFT;
2777 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2778 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2779 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2780 0xffff);
2781 }
2782
2783 /* pause - not for e1 */
2784 if (!CHIP_IS_E1(bp)) {
2785 pause->bd_th_lo = BD_TH_LO(bp);
2786 pause->bd_th_hi = BD_TH_HI(bp);
2787
2788 pause->rcq_th_lo = RCQ_TH_LO(bp);
2789 pause->rcq_th_hi = RCQ_TH_HI(bp);
2790 /*
2791 * validate that rings have enough entries to cross
2792 * high thresholds
2793 */
2794 WARN_ON(bp->dropless_fc &&
2795 pause->bd_th_hi + FW_PREFETCH_CNT >
2796 bp->rx_ring_size);
2797 WARN_ON(bp->dropless_fc &&
2798 pause->rcq_th_hi + FW_PREFETCH_CNT >
2799 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2800
2801 pause->pri_map = 1;
2802 }
2803
2804 /* rxq setup */
2805 rxq_init->dscr_map = fp->rx_desc_mapping;
2806 rxq_init->sge_map = fp->rx_sge_mapping;
2807 rxq_init->rcq_map = fp->rx_comp_mapping;
2808 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2809
2810 /* This should be a maximum number of data bytes that may be
2811 * placed on the BD (not including paddings).
2812 */
2813 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2814 IP_HEADER_ALIGNMENT_PADDING;
2815
2816 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2817 rxq_init->tpa_agg_sz = tpa_agg_size;
2818 rxq_init->sge_buf_sz = sge_sz;
2819 rxq_init->max_sges_pkt = max_sge;
2820 rxq_init->rss_engine_id = BP_FUNC(bp);
2821
2822 /* Maximum number or simultaneous TPA aggregation for this Queue.
2823 *
2824 * For PF Clients it should be the maximum avaliable number.
2825 * VF driver(s) may want to define it to a smaller value.
2826 */
2827 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2828
2829 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2830 rxq_init->fw_sb_id = fp->fw_sb_id;
2831
2832 if (IS_FCOE_FP(fp))
2833 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2834 else
2835 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2836 }
2837
2838 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2839 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2840 u8 cos)
2841 {
2842 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2843 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2844 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2845 txq_init->fw_sb_id = fp->fw_sb_id;
2846
2847 /*
2848 * set the tss leading client id for TX classfication ==
2849 * leading RSS client id
2850 */
2851 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2852
2853 if (IS_FCOE_FP(fp)) {
2854 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2855 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2856 }
2857 }
2858
2859 static void bnx2x_pf_init(struct bnx2x *bp)
2860 {
2861 struct bnx2x_func_init_params func_init = {0};
2862 struct event_ring_data eq_data = { {0} };
2863 u16 flags;
2864
2865 if (!CHIP_IS_E1x(bp)) {
2866 /* reset IGU PF statistics: MSIX + ATTN */
2867 /* PF */
2868 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2869 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2870 (CHIP_MODE_IS_4_PORT(bp) ?
2871 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2872 /* ATTN */
2873 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2874 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2875 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2876 (CHIP_MODE_IS_4_PORT(bp) ?
2877 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2878 }
2879
2880 /* function setup flags */
2881 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2882
2883 /* This flag is relevant for E1x only.
2884 * E2 doesn't have a TPA configuration in a function level.
2885 */
2886 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2887
2888 func_init.func_flgs = flags;
2889 func_init.pf_id = BP_FUNC(bp);
2890 func_init.func_id = BP_FUNC(bp);
2891 func_init.spq_map = bp->spq_mapping;
2892 func_init.spq_prod = bp->spq_prod_idx;
2893
2894 bnx2x_func_init(bp, &func_init);
2895
2896 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2897
2898 /*
2899 * Congestion management values depend on the link rate
2900 * There is no active link so initial link rate is set to 10 Gbps.
2901 * When the link comes up The congestion management values are
2902 * re-calculated according to the actual link rate.
2903 */
2904 bp->link_vars.line_speed = SPEED_10000;
2905 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2906
2907 /* Only the PMF sets the HW */
2908 if (bp->port.pmf)
2909 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2910
2911 /* init Event Queue */
2912 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2913 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2914 eq_data.producer = bp->eq_prod;
2915 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2916 eq_data.sb_id = DEF_SB_ID;
2917 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2918 }
2919
2920
2921 static void bnx2x_e1h_disable(struct bnx2x *bp)
2922 {
2923 int port = BP_PORT(bp);
2924
2925 bnx2x_tx_disable(bp);
2926
2927 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2928 }
2929
2930 static void bnx2x_e1h_enable(struct bnx2x *bp)
2931 {
2932 int port = BP_PORT(bp);
2933
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2935
2936 /* Tx queue should be only reenabled */
2937 netif_tx_wake_all_queues(bp->dev);
2938
2939 /*
2940 * Should not call netif_carrier_on since it will be called if the link
2941 * is up when checking for link state
2942 */
2943 }
2944
2945 /* called due to MCP event (on pmf):
2946 * reread new bandwidth configuration
2947 * configure FW
2948 * notify others function about the change
2949 */
2950 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2951 {
2952 if (bp->link_vars.link_up) {
2953 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2954 bnx2x_link_sync_notify(bp);
2955 }
2956 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2957 }
2958
2959 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2960 {
2961 bnx2x_config_mf_bw(bp);
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2963 }
2964
2965 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2966 {
2967 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2968
2969 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2970
2971 /*
2972 * This is the only place besides the function initialization
2973 * where the bp->flags can change so it is done without any
2974 * locks
2975 */
2976 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2977 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2978 bp->flags |= MF_FUNC_DIS;
2979
2980 bnx2x_e1h_disable(bp);
2981 } else {
2982 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2983 bp->flags &= ~MF_FUNC_DIS;
2984
2985 bnx2x_e1h_enable(bp);
2986 }
2987 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2988 }
2989 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2990 bnx2x_config_mf_bw(bp);
2991 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2992 }
2993
2994 /* Report results to MCP */
2995 if (dcc_event)
2996 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2997 else
2998 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2999 }
3000
3001 /* must be called under the spq lock */
3002 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3003 {
3004 struct eth_spe *next_spe = bp->spq_prod_bd;
3005
3006 if (bp->spq_prod_bd == bp->spq_last_bd) {
3007 bp->spq_prod_bd = bp->spq;
3008 bp->spq_prod_idx = 0;
3009 DP(NETIF_MSG_TIMER, "end of spq\n");
3010 } else {
3011 bp->spq_prod_bd++;
3012 bp->spq_prod_idx++;
3013 }
3014 return next_spe;
3015 }
3016
3017 /* must be called under the spq lock */
3018 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3019 {
3020 int func = BP_FUNC(bp);
3021
3022 /*
3023 * Make sure that BD data is updated before writing the producer:
3024 * BD data is written to the memory, the producer is read from the
3025 * memory, thus we need a full memory barrier to ensure the ordering.
3026 */
3027 mb();
3028
3029 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3030 bp->spq_prod_idx);
3031 mmiowb();
3032 }
3033
3034 /**
3035 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3036 *
3037 * @cmd: command to check
3038 * @cmd_type: command type
3039 */
3040 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3041 {
3042 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3043 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3044 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3045 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3046 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3047 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3048 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3049 return true;
3050 else
3051 return false;
3052
3053 }
3054
3055
3056 /**
3057 * bnx2x_sp_post - place a single command on an SP ring
3058 *
3059 * @bp: driver handle
3060 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3061 * @cid: SW CID the command is related to
3062 * @data_hi: command private data address (high 32 bits)
3063 * @data_lo: command private data address (low 32 bits)
3064 * @cmd_type: command type (e.g. NONE, ETH)
3065 *
3066 * SP data is handled as if it's always an address pair, thus data fields are
3067 * not swapped to little endian in upper functions. Instead this function swaps
3068 * data as if it's two u32 fields.
3069 */
3070 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3071 u32 data_hi, u32 data_lo, int cmd_type)
3072 {
3073 struct eth_spe *spe;
3074 u16 type;
3075 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3076
3077 #ifdef BNX2X_STOP_ON_ERROR
3078 if (unlikely(bp->panic))
3079 return -EIO;
3080 #endif
3081
3082 spin_lock_bh(&bp->spq_lock);
3083
3084 if (common) {
3085 if (!atomic_read(&bp->eq_spq_left)) {
3086 BNX2X_ERR("BUG! EQ ring full!\n");
3087 spin_unlock_bh(&bp->spq_lock);
3088 bnx2x_panic();
3089 return -EBUSY;
3090 }
3091 } else if (!atomic_read(&bp->cq_spq_left)) {
3092 BNX2X_ERR("BUG! SPQ ring full!\n");
3093 spin_unlock_bh(&bp->spq_lock);
3094 bnx2x_panic();
3095 return -EBUSY;
3096 }
3097
3098 spe = bnx2x_sp_get_next(bp);
3099
3100 /* CID needs port number to be encoded int it */
3101 spe->hdr.conn_and_cmd_data =
3102 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3103 HW_CID(bp, cid));
3104
3105 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3106
3107 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3108 SPE_HDR_FUNCTION_ID);
3109
3110 spe->hdr.type = cpu_to_le16(type);
3111
3112 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3113 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3114
3115 /*
3116 * It's ok if the actual decrement is issued towards the memory
3117 * somewhere between the spin_lock and spin_unlock. Thus no
3118 * more explict memory barrier is needed.
3119 */
3120 if (common)
3121 atomic_dec(&bp->eq_spq_left);
3122 else
3123 atomic_dec(&bp->cq_spq_left);
3124
3125
3126 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3127 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3128 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3129 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3130 (u32)(U64_LO(bp->spq_mapping) +
3131 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3132 HW_CID(bp, cid), data_hi, data_lo, type,
3133 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3134
3135 bnx2x_sp_prod_update(bp);
3136 spin_unlock_bh(&bp->spq_lock);
3137 return 0;
3138 }
3139
3140 /* acquire split MCP access lock register */
3141 static int bnx2x_acquire_alr(struct bnx2x *bp)
3142 {
3143 u32 j, val;
3144 int rc = 0;
3145
3146 might_sleep();
3147 for (j = 0; j < 1000; j++) {
3148 val = (1UL << 31);
3149 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3150 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3151 if (val & (1L << 31))
3152 break;
3153
3154 msleep(5);
3155 }
3156 if (!(val & (1L << 31))) {
3157 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3158 rc = -EBUSY;
3159 }
3160
3161 return rc;
3162 }
3163
3164 /* release split MCP access lock register */
3165 static void bnx2x_release_alr(struct bnx2x *bp)
3166 {
3167 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3168 }
3169
3170 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3171 #define BNX2X_DEF_SB_IDX 0x0002
3172
3173 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3174 {
3175 struct host_sp_status_block *def_sb = bp->def_status_blk;
3176 u16 rc = 0;
3177
3178 barrier(); /* status block is written to by the chip */
3179 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3180 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3181 rc |= BNX2X_DEF_SB_ATT_IDX;
3182 }
3183
3184 if (bp->def_idx != def_sb->sp_sb.running_index) {
3185 bp->def_idx = def_sb->sp_sb.running_index;
3186 rc |= BNX2X_DEF_SB_IDX;
3187 }
3188
3189 /* Do not reorder: indecies reading should complete before handling */
3190 barrier();
3191 return rc;
3192 }
3193
3194 /*
3195 * slow path service functions
3196 */
3197
3198 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3199 {
3200 int port = BP_PORT(bp);
3201 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3202 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3203 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3204 NIG_REG_MASK_INTERRUPT_PORT0;
3205 u32 aeu_mask;
3206 u32 nig_mask = 0;
3207 u32 reg_addr;
3208
3209 if (bp->attn_state & asserted)
3210 BNX2X_ERR("IGU ERROR\n");
3211
3212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3213 aeu_mask = REG_RD(bp, aeu_addr);
3214
3215 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3216 aeu_mask, asserted);
3217 aeu_mask &= ~(asserted & 0x3ff);
3218 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3219
3220 REG_WR(bp, aeu_addr, aeu_mask);
3221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3222
3223 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3224 bp->attn_state |= asserted;
3225 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3226
3227 if (asserted & ATTN_HARD_WIRED_MASK) {
3228 if (asserted & ATTN_NIG_FOR_FUNC) {
3229
3230 bnx2x_acquire_phy_lock(bp);
3231
3232 /* save nig interrupt mask */
3233 nig_mask = REG_RD(bp, nig_int_mask_addr);
3234
3235 /* If nig_mask is not set, no need to call the update
3236 * function.
3237 */
3238 if (nig_mask) {
3239 REG_WR(bp, nig_int_mask_addr, 0);
3240
3241 bnx2x_link_attn(bp);
3242 }
3243
3244 /* handle unicore attn? */
3245 }
3246 if (asserted & ATTN_SW_TIMER_4_FUNC)
3247 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3248
3249 if (asserted & GPIO_2_FUNC)
3250 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3251
3252 if (asserted & GPIO_3_FUNC)
3253 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3254
3255 if (asserted & GPIO_4_FUNC)
3256 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3257
3258 if (port == 0) {
3259 if (asserted & ATTN_GENERAL_ATTN_1) {
3260 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3262 }
3263 if (asserted & ATTN_GENERAL_ATTN_2) {
3264 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3266 }
3267 if (asserted & ATTN_GENERAL_ATTN_3) {
3268 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3269 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3270 }
3271 } else {
3272 if (asserted & ATTN_GENERAL_ATTN_4) {
3273 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3274 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3275 }
3276 if (asserted & ATTN_GENERAL_ATTN_5) {
3277 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3278 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3279 }
3280 if (asserted & ATTN_GENERAL_ATTN_6) {
3281 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3282 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3283 }
3284 }
3285
3286 } /* if hardwired */
3287
3288 if (bp->common.int_block == INT_BLOCK_HC)
3289 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3290 COMMAND_REG_ATTN_BITS_SET);
3291 else
3292 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3293
3294 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3295 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3296 REG_WR(bp, reg_addr, asserted);
3297
3298 /* now set back the mask */
3299 if (asserted & ATTN_NIG_FOR_FUNC) {
3300 REG_WR(bp, nig_int_mask_addr, nig_mask);
3301 bnx2x_release_phy_lock(bp);
3302 }
3303 }
3304
3305 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3306 {
3307 int port = BP_PORT(bp);
3308 u32 ext_phy_config;
3309 /* mark the failure */
3310 ext_phy_config =
3311 SHMEM_RD(bp,
3312 dev_info.port_hw_config[port].external_phy_config);
3313
3314 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3315 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3316 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3317 ext_phy_config);
3318
3319 /* log the failure */
3320 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3321 " the driver to shutdown the card to prevent permanent"
3322 " damage. Please contact OEM Support for assistance\n");
3323 }
3324
3325 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3326 {
3327 int port = BP_PORT(bp);
3328 int reg_offset;
3329 u32 val;
3330
3331 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3332 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3333
3334 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3335
3336 val = REG_RD(bp, reg_offset);
3337 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3338 REG_WR(bp, reg_offset, val);
3339
3340 BNX2X_ERR("SPIO5 hw attention\n");
3341
3342 /* Fan failure attention */
3343 bnx2x_hw_reset_phy(&bp->link_params);
3344 bnx2x_fan_failure(bp);
3345 }
3346
3347 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3348 bnx2x_acquire_phy_lock(bp);
3349 bnx2x_handle_module_detect_int(&bp->link_params);
3350 bnx2x_release_phy_lock(bp);
3351 }
3352
3353 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3354
3355 val = REG_RD(bp, reg_offset);
3356 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3357 REG_WR(bp, reg_offset, val);
3358
3359 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3360 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3361 bnx2x_panic();
3362 }
3363 }
3364
3365 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3366 {
3367 u32 val;
3368
3369 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3370
3371 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3372 BNX2X_ERR("DB hw attention 0x%x\n", val);
3373 /* DORQ discard attention */
3374 if (val & 0x2)
3375 BNX2X_ERR("FATAL error from DORQ\n");
3376 }
3377
3378 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3379
3380 int port = BP_PORT(bp);
3381 int reg_offset;
3382
3383 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3384 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3385
3386 val = REG_RD(bp, reg_offset);
3387 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3388 REG_WR(bp, reg_offset, val);
3389
3390 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3391 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3392 bnx2x_panic();
3393 }
3394 }
3395
3396 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3397 {
3398 u32 val;
3399
3400 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3401
3402 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3403 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3404 /* CFC error attention */
3405 if (val & 0x2)
3406 BNX2X_ERR("FATAL error from CFC\n");
3407 }
3408
3409 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3410 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3411 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3412 /* RQ_USDMDP_FIFO_OVERFLOW */
3413 if (val & 0x18000)
3414 BNX2X_ERR("FATAL error from PXP\n");
3415
3416 if (!CHIP_IS_E1x(bp)) {
3417 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3418 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3419 }
3420 }
3421
3422 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3423
3424 int port = BP_PORT(bp);
3425 int reg_offset;
3426
3427 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3428 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3429
3430 val = REG_RD(bp, reg_offset);
3431 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3432 REG_WR(bp, reg_offset, val);
3433
3434 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3435 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3436 bnx2x_panic();
3437 }
3438 }
3439
3440 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3441 {
3442 u32 val;
3443
3444 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3445
3446 if (attn & BNX2X_PMF_LINK_ASSERT) {
3447 int func = BP_FUNC(bp);
3448
3449 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3450 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3451 func_mf_config[BP_ABS_FUNC(bp)].config);
3452 val = SHMEM_RD(bp,
3453 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3454 if (val & DRV_STATUS_DCC_EVENT_MASK)
3455 bnx2x_dcc_event(bp,
3456 (val & DRV_STATUS_DCC_EVENT_MASK));
3457
3458 if (val & DRV_STATUS_SET_MF_BW)
3459 bnx2x_set_mf_bw(bp);
3460
3461 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3462 bnx2x_pmf_update(bp);
3463
3464 if (bp->port.pmf &&
3465 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3466 bp->dcbx_enabled > 0)
3467 /* start dcbx state machine */
3468 bnx2x_dcbx_set_params(bp,
3469 BNX2X_DCBX_STATE_NEG_RECEIVED);
3470 if (bp->link_vars.periodic_flags &
3471 PERIODIC_FLAGS_LINK_EVENT) {
3472 /* sync with link */
3473 bnx2x_acquire_phy_lock(bp);
3474 bp->link_vars.periodic_flags &=
3475 ~PERIODIC_FLAGS_LINK_EVENT;
3476 bnx2x_release_phy_lock(bp);
3477 if (IS_MF(bp))
3478 bnx2x_link_sync_notify(bp);
3479 bnx2x_link_report(bp);
3480 }
3481 /* Always call it here: bnx2x_link_report() will
3482 * prevent the link indication duplication.
3483 */
3484 bnx2x__link_status_update(bp);
3485 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3486
3487 BNX2X_ERR("MC assert!\n");
3488 bnx2x_mc_assert(bp);
3489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3492 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3493 bnx2x_panic();
3494
3495 } else if (attn & BNX2X_MCP_ASSERT) {
3496
3497 BNX2X_ERR("MCP assert!\n");
3498 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3499 bnx2x_fw_dump(bp);
3500
3501 } else
3502 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3503 }
3504
3505 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3506 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3507 if (attn & BNX2X_GRC_TIMEOUT) {
3508 val = CHIP_IS_E1(bp) ? 0 :
3509 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3510 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3511 }
3512 if (attn & BNX2X_GRC_RSV) {
3513 val = CHIP_IS_E1(bp) ? 0 :
3514 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3515 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3516 }
3517 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3518 }
3519 }
3520
3521 /*
3522 * Bits map:
3523 * 0-7 - Engine0 load counter.
3524 * 8-15 - Engine1 load counter.
3525 * 16 - Engine0 RESET_IN_PROGRESS bit.
3526 * 17 - Engine1 RESET_IN_PROGRESS bit.
3527 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3528 * on the engine
3529 * 19 - Engine1 ONE_IS_LOADED.
3530 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3531 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3532 * just the one belonging to its engine).
3533 *
3534 */
3535 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3536
3537 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3538 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3539 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3540 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3541 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3542 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3543 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3544
3545 /*
3546 * Set the GLOBAL_RESET bit.
3547 *
3548 * Should be run under rtnl lock
3549 */
3550 void bnx2x_set_reset_global(struct bnx2x *bp)
3551 {
3552 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3553
3554 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3555 barrier();
3556 mmiowb();
3557 }
3558
3559 /*
3560 * Clear the GLOBAL_RESET bit.
3561 *
3562 * Should be run under rtnl lock
3563 */
3564 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3565 {
3566 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3567
3568 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3569 barrier();
3570 mmiowb();
3571 }
3572
3573 /*
3574 * Checks the GLOBAL_RESET bit.
3575 *
3576 * should be run under rtnl lock
3577 */
3578 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3579 {
3580 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3581
3582 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3583 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3584 }
3585
3586 /*
3587 * Clear RESET_IN_PROGRESS bit for the current engine.
3588 *
3589 * Should be run under rtnl lock
3590 */
3591 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3592 {
3593 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3594 u32 bit = BP_PATH(bp) ?
3595 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3596
3597 /* Clear the bit */
3598 val &= ~bit;
3599 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3600 barrier();
3601 mmiowb();
3602 }
3603
3604 /*
3605 * Set RESET_IN_PROGRESS for the current engine.
3606 *
3607 * should be run under rtnl lock
3608 */
3609 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3610 {
3611 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3612 u32 bit = BP_PATH(bp) ?
3613 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3614
3615 /* Set the bit */
3616 val |= bit;
3617 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3618 barrier();
3619 mmiowb();
3620 }
3621
3622 /*
3623 * Checks the RESET_IN_PROGRESS bit for the given engine.
3624 * should be run under rtnl lock
3625 */
3626 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3627 {
3628 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3629 u32 bit = engine ?
3630 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3631
3632 /* return false if bit is set */
3633 return (val & bit) ? false : true;
3634 }
3635
3636 /*
3637 * Increment the load counter for the current engine.
3638 *
3639 * should be run under rtnl lock
3640 */
3641 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3642 {
3643 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3644 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3645 BNX2X_PATH0_LOAD_CNT_MASK;
3646 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3647 BNX2X_PATH0_LOAD_CNT_SHIFT;
3648
3649 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3650
3651 /* get the current counter value */
3652 val1 = (val & mask) >> shift;
3653
3654 /* increment... */
3655 val1++;
3656
3657 /* clear the old value */
3658 val &= ~mask;
3659
3660 /* set the new one */
3661 val |= ((val1 << shift) & mask);
3662
3663 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3664 barrier();
3665 mmiowb();
3666 }
3667
3668 /**
3669 * bnx2x_dec_load_cnt - decrement the load counter
3670 *
3671 * @bp: driver handle
3672 *
3673 * Should be run under rtnl lock.
3674 * Decrements the load counter for the current engine. Returns
3675 * the new counter value.
3676 */
3677 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3678 {
3679 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3680 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3681 BNX2X_PATH0_LOAD_CNT_MASK;
3682 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3683 BNX2X_PATH0_LOAD_CNT_SHIFT;
3684
3685 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3686
3687 /* get the current counter value */
3688 val1 = (val & mask) >> shift;
3689
3690 /* decrement... */
3691 val1--;
3692
3693 /* clear the old value */
3694 val &= ~mask;
3695
3696 /* set the new one */
3697 val |= ((val1 << shift) & mask);
3698
3699 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3700 barrier();
3701 mmiowb();
3702
3703 return val1;
3704 }
3705
3706 /*
3707 * Read the load counter for the current engine.
3708 *
3709 * should be run under rtnl lock
3710 */
3711 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3712 {
3713 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3714 BNX2X_PATH0_LOAD_CNT_MASK);
3715 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3716 BNX2X_PATH0_LOAD_CNT_SHIFT);
3717 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3718
3719 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3720
3721 val = (val & mask) >> shift;
3722
3723 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3724
3725 return val;
3726 }
3727
3728 /*
3729 * Reset the load counter for the current engine.
3730 *
3731 * should be run under rtnl lock
3732 */
3733 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3734 {
3735 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3736 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3737 BNX2X_PATH0_LOAD_CNT_MASK);
3738
3739 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3740 }
3741
3742 static inline void _print_next_block(int idx, const char *blk)
3743 {
3744 if (idx)
3745 pr_cont(", ");
3746 pr_cont("%s", blk);
3747 }
3748
3749 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3750 bool print)
3751 {
3752 int i = 0;
3753 u32 cur_bit = 0;
3754 for (i = 0; sig; i++) {
3755 cur_bit = ((u32)0x1 << i);
3756 if (sig & cur_bit) {
3757 switch (cur_bit) {
3758 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3759 if (print)
3760 _print_next_block(par_num++, "BRB");
3761 break;
3762 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3763 if (print)
3764 _print_next_block(par_num++, "PARSER");
3765 break;
3766 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3767 if (print)
3768 _print_next_block(par_num++, "TSDM");
3769 break;
3770 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3771 if (print)
3772 _print_next_block(par_num++,
3773 "SEARCHER");
3774 break;
3775 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3776 if (print)
3777 _print_next_block(par_num++, "TCM");
3778 break;
3779 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3780 if (print)
3781 _print_next_block(par_num++, "TSEMI");
3782 break;
3783 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3784 if (print)
3785 _print_next_block(par_num++, "XPB");
3786 break;
3787 }
3788
3789 /* Clear the bit */
3790 sig &= ~cur_bit;
3791 }
3792 }
3793
3794 return par_num;
3795 }
3796
3797 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3798 bool *global, bool print)
3799 {
3800 int i = 0;
3801 u32 cur_bit = 0;
3802 for (i = 0; sig; i++) {
3803 cur_bit = ((u32)0x1 << i);
3804 if (sig & cur_bit) {
3805 switch (cur_bit) {
3806 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3807 if (print)
3808 _print_next_block(par_num++, "PBF");
3809 break;
3810 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3811 if (print)
3812 _print_next_block(par_num++, "QM");
3813 break;
3814 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3815 if (print)
3816 _print_next_block(par_num++, "TM");
3817 break;
3818 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3819 if (print)
3820 _print_next_block(par_num++, "XSDM");
3821 break;
3822 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3823 if (print)
3824 _print_next_block(par_num++, "XCM");
3825 break;
3826 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3827 if (print)
3828 _print_next_block(par_num++, "XSEMI");
3829 break;
3830 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3831 if (print)
3832 _print_next_block(par_num++,
3833 "DOORBELLQ");
3834 break;
3835 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3836 if (print)
3837 _print_next_block(par_num++, "NIG");
3838 break;
3839 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3840 if (print)
3841 _print_next_block(par_num++,
3842 "VAUX PCI CORE");
3843 *global = true;
3844 break;
3845 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3846 if (print)
3847 _print_next_block(par_num++, "DEBUG");
3848 break;
3849 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3850 if (print)
3851 _print_next_block(par_num++, "USDM");
3852 break;
3853 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3854 if (print)
3855 _print_next_block(par_num++, "UCM");
3856 break;
3857 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3858 if (print)
3859 _print_next_block(par_num++, "USEMI");
3860 break;
3861 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3862 if (print)
3863 _print_next_block(par_num++, "UPB");
3864 break;
3865 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3866 if (print)
3867 _print_next_block(par_num++, "CSDM");
3868 break;
3869 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3870 if (print)
3871 _print_next_block(par_num++, "CCM");
3872 break;
3873 }
3874
3875 /* Clear the bit */
3876 sig &= ~cur_bit;
3877 }
3878 }
3879
3880 return par_num;
3881 }
3882
3883 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3884 bool print)
3885 {
3886 int i = 0;
3887 u32 cur_bit = 0;
3888 for (i = 0; sig; i++) {
3889 cur_bit = ((u32)0x1 << i);
3890 if (sig & cur_bit) {
3891 switch (cur_bit) {
3892 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3893 if (print)
3894 _print_next_block(par_num++, "CSEMI");
3895 break;
3896 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3897 if (print)
3898 _print_next_block(par_num++, "PXP");
3899 break;
3900 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3901 if (print)
3902 _print_next_block(par_num++,
3903 "PXPPCICLOCKCLIENT");
3904 break;
3905 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3906 if (print)
3907 _print_next_block(par_num++, "CFC");
3908 break;
3909 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3910 if (print)
3911 _print_next_block(par_num++, "CDU");
3912 break;
3913 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3914 if (print)
3915 _print_next_block(par_num++, "DMAE");
3916 break;
3917 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3918 if (print)
3919 _print_next_block(par_num++, "IGU");
3920 break;
3921 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3922 if (print)
3923 _print_next_block(par_num++, "MISC");
3924 break;
3925 }
3926
3927 /* Clear the bit */
3928 sig &= ~cur_bit;
3929 }
3930 }
3931
3932 return par_num;
3933 }
3934
3935 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3936 bool *global, bool print)
3937 {
3938 int i = 0;
3939 u32 cur_bit = 0;
3940 for (i = 0; sig; i++) {
3941 cur_bit = ((u32)0x1 << i);
3942 if (sig & cur_bit) {
3943 switch (cur_bit) {
3944 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3945 if (print)
3946 _print_next_block(par_num++, "MCP ROM");
3947 *global = true;
3948 break;
3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3950 if (print)
3951 _print_next_block(par_num++,
3952 "MCP UMP RX");
3953 *global = true;
3954 break;
3955 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3956 if (print)
3957 _print_next_block(par_num++,
3958 "MCP UMP TX");
3959 *global = true;
3960 break;
3961 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3962 if (print)
3963 _print_next_block(par_num++,
3964 "MCP SCPAD");
3965 *global = true;
3966 break;
3967 }
3968
3969 /* Clear the bit */
3970 sig &= ~cur_bit;
3971 }
3972 }
3973
3974 return par_num;
3975 }
3976
3977 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3978 bool print)
3979 {
3980 int i = 0;
3981 u32 cur_bit = 0;
3982 for (i = 0; sig; i++) {
3983 cur_bit = ((u32)0x1 << i);
3984 if (sig & cur_bit) {
3985 switch (cur_bit) {
3986 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3987 if (print)
3988 _print_next_block(par_num++, "PGLUE_B");
3989 break;
3990 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3991 if (print)
3992 _print_next_block(par_num++, "ATC");
3993 break;
3994 }
3995
3996 /* Clear the bit */
3997 sig &= ~cur_bit;
3998 }
3999 }
4000
4001 return par_num;
4002 }
4003
4004 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4005 u32 *sig)
4006 {
4007 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4008 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4009 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4010 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4011 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4012 int par_num = 0;
4013 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4014 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4015 "[4]:0x%08x\n",
4016 sig[0] & HW_PRTY_ASSERT_SET_0,
4017 sig[1] & HW_PRTY_ASSERT_SET_1,
4018 sig[2] & HW_PRTY_ASSERT_SET_2,
4019 sig[3] & HW_PRTY_ASSERT_SET_3,
4020 sig[4] & HW_PRTY_ASSERT_SET_4);
4021 if (print)
4022 netdev_err(bp->dev,
4023 "Parity errors detected in blocks: ");
4024 par_num = bnx2x_check_blocks_with_parity0(
4025 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4026 par_num = bnx2x_check_blocks_with_parity1(
4027 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4028 par_num = bnx2x_check_blocks_with_parity2(
4029 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4030 par_num = bnx2x_check_blocks_with_parity3(
4031 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4032 par_num = bnx2x_check_blocks_with_parity4(
4033 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4034
4035 if (print)
4036 pr_cont("\n");
4037
4038 return true;
4039 } else
4040 return false;
4041 }
4042
4043 /**
4044 * bnx2x_chk_parity_attn - checks for parity attentions.
4045 *
4046 * @bp: driver handle
4047 * @global: true if there was a global attention
4048 * @print: show parity attention in syslog
4049 */
4050 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4051 {
4052 struct attn_route attn = { {0} };
4053 int port = BP_PORT(bp);
4054
4055 attn.sig[0] = REG_RD(bp,
4056 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4057 port*4);
4058 attn.sig[1] = REG_RD(bp,
4059 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4060 port*4);
4061 attn.sig[2] = REG_RD(bp,
4062 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4063 port*4);
4064 attn.sig[3] = REG_RD(bp,
4065 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4066 port*4);
4067
4068 if (!CHIP_IS_E1x(bp))
4069 attn.sig[4] = REG_RD(bp,
4070 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4071 port*4);
4072
4073 return bnx2x_parity_attn(bp, global, print, attn.sig);
4074 }
4075
4076
4077 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4078 {
4079 u32 val;
4080 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4081
4082 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4083 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4086 "ADDRESS_ERROR\n");
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "INCORRECT_RCV_BEHAVIOR\n");
4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4092 "WAS_ERROR_ATTN\n");
4093 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4094 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4095 "VF_LENGTH_VIOLATION_ATTN\n");
4096 if (val &
4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4099 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4100 if (val &
4101 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4102 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4103 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4104 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4105 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4106 "TCPL_ERROR_ATTN\n");
4107 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4108 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4109 "TCPL_IN_TWO_RCBS_ATTN\n");
4110 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4111 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4112 "CSSNOOP_FIFO_OVERFLOW\n");
4113 }
4114 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4115 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4116 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4117 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4118 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4119 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4120 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4121 "_ATC_TCPL_TO_NOT_PEND\n");
4122 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4123 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4124 "ATC_GPA_MULTIPLE_HITS\n");
4125 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4126 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4127 "ATC_RCPL_TO_EMPTY_CNT\n");
4128 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4129 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4130 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4131 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4132 "ATC_IREQ_LESS_THAN_STU\n");
4133 }
4134
4135 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4136 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4137 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4138 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4139 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4140 }
4141
4142 }
4143
4144 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4145 {
4146 struct attn_route attn, *group_mask;
4147 int port = BP_PORT(bp);
4148 int index;
4149 u32 reg_addr;
4150 u32 val;
4151 u32 aeu_mask;
4152 bool global = false;
4153
4154 /* need to take HW lock because MCP or other port might also
4155 try to handle this event */
4156 bnx2x_acquire_alr(bp);
4157
4158 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4159 #ifndef BNX2X_STOP_ON_ERROR
4160 bp->recovery_state = BNX2X_RECOVERY_INIT;
4161 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4162 /* Disable HW interrupts */
4163 bnx2x_int_disable(bp);
4164 /* In case of parity errors don't handle attentions so that
4165 * other function would "see" parity errors.
4166 */
4167 #else
4168 bnx2x_panic();
4169 #endif
4170 bnx2x_release_alr(bp);
4171 return;
4172 }
4173
4174 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4175 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4176 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4177 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4178 if (!CHIP_IS_E1x(bp))
4179 attn.sig[4] =
4180 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4181 else
4182 attn.sig[4] = 0;
4183
4184 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4185 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4186
4187 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4188 if (deasserted & (1 << index)) {
4189 group_mask = &bp->attn_group[index];
4190
4191 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4192 "%08x %08x %08x\n",
4193 index,
4194 group_mask->sig[0], group_mask->sig[1],
4195 group_mask->sig[2], group_mask->sig[3],
4196 group_mask->sig[4]);
4197
4198 bnx2x_attn_int_deasserted4(bp,
4199 attn.sig[4] & group_mask->sig[4]);
4200 bnx2x_attn_int_deasserted3(bp,
4201 attn.sig[3] & group_mask->sig[3]);
4202 bnx2x_attn_int_deasserted1(bp,
4203 attn.sig[1] & group_mask->sig[1]);
4204 bnx2x_attn_int_deasserted2(bp,
4205 attn.sig[2] & group_mask->sig[2]);
4206 bnx2x_attn_int_deasserted0(bp,
4207 attn.sig[0] & group_mask->sig[0]);
4208 }
4209 }
4210
4211 bnx2x_release_alr(bp);
4212
4213 if (bp->common.int_block == INT_BLOCK_HC)
4214 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4215 COMMAND_REG_ATTN_BITS_CLR);
4216 else
4217 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4218
4219 val = ~deasserted;
4220 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4221 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4222 REG_WR(bp, reg_addr, val);
4223
4224 if (~bp->attn_state & deasserted)
4225 BNX2X_ERR("IGU ERROR\n");
4226
4227 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4228 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4229
4230 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4231 aeu_mask = REG_RD(bp, reg_addr);
4232
4233 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4234 aeu_mask, deasserted);
4235 aeu_mask |= (deasserted & 0x3ff);
4236 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4237
4238 REG_WR(bp, reg_addr, aeu_mask);
4239 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4240
4241 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4242 bp->attn_state &= ~deasserted;
4243 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4244 }
4245
4246 static void bnx2x_attn_int(struct bnx2x *bp)
4247 {
4248 /* read local copy of bits */
4249 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4250 attn_bits);
4251 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4252 attn_bits_ack);
4253 u32 attn_state = bp->attn_state;
4254
4255 /* look for changed bits */
4256 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4257 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4258
4259 DP(NETIF_MSG_HW,
4260 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4261 attn_bits, attn_ack, asserted, deasserted);
4262
4263 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4264 BNX2X_ERR("BAD attention state\n");
4265
4266 /* handle bits that were raised */
4267 if (asserted)
4268 bnx2x_attn_int_asserted(bp, asserted);
4269
4270 if (deasserted)
4271 bnx2x_attn_int_deasserted(bp, deasserted);
4272 }
4273
4274 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4275 u16 index, u8 op, u8 update)
4276 {
4277 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4278
4279 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4280 igu_addr);
4281 }
4282
4283 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4284 {
4285 /* No memory barriers */
4286 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4287 mmiowb(); /* keep prod updates ordered */
4288 }
4289
4290 #ifdef BCM_CNIC
4291 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4292 union event_ring_elem *elem)
4293 {
4294 u8 err = elem->message.error;
4295
4296 if (!bp->cnic_eth_dev.starting_cid ||
4297 (cid < bp->cnic_eth_dev.starting_cid &&
4298 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4299 return 1;
4300
4301 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4302
4303 if (unlikely(err)) {
4304
4305 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4306 cid);
4307 bnx2x_panic_dump(bp);
4308 }
4309 bnx2x_cnic_cfc_comp(bp, cid, err);
4310 return 0;
4311 }
4312 #endif
4313
4314 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4315 {
4316 struct bnx2x_mcast_ramrod_params rparam;
4317 int rc;
4318
4319 memset(&rparam, 0, sizeof(rparam));
4320
4321 rparam.mcast_obj = &bp->mcast_obj;
4322
4323 netif_addr_lock_bh(bp->dev);
4324
4325 /* Clear pending state for the last command */
4326 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4327
4328 /* If there are pending mcast commands - send them */
4329 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4330 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4331 if (rc < 0)
4332 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4333 rc);
4334 }
4335
4336 netif_addr_unlock_bh(bp->dev);
4337 }
4338
4339 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4340 union event_ring_elem *elem)
4341 {
4342 unsigned long ramrod_flags = 0;
4343 int rc = 0;
4344 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4345 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4346
4347 /* Always push next commands out, don't wait here */
4348 __set_bit(RAMROD_CONT, &ramrod_flags);
4349
4350 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4351 case BNX2X_FILTER_MAC_PENDING:
4352 #ifdef BCM_CNIC
4353 if (cid == BNX2X_ISCSI_ETH_CID)
4354 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4355 else
4356 #endif
4357 vlan_mac_obj = &bp->fp[cid].mac_obj;
4358
4359 break;
4360 vlan_mac_obj = &bp->fp[cid].mac_obj;
4361
4362 case BNX2X_FILTER_MCAST_PENDING:
4363 /* This is only relevant for 57710 where multicast MACs are
4364 * configured as unicast MACs using the same ramrod.
4365 */
4366 bnx2x_handle_mcast_eqe(bp);
4367 return;
4368 default:
4369 BNX2X_ERR("Unsupported classification command: %d\n",
4370 elem->message.data.eth_event.echo);
4371 return;
4372 }
4373
4374 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4375
4376 if (rc < 0)
4377 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4378 else if (rc > 0)
4379 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4380
4381 }
4382
4383 #ifdef BCM_CNIC
4384 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4385 #endif
4386
4387 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4388 {
4389 netif_addr_lock_bh(bp->dev);
4390
4391 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4392
4393 /* Send rx_mode command again if was requested */
4394 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4395 bnx2x_set_storm_rx_mode(bp);
4396 #ifdef BCM_CNIC
4397 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4398 &bp->sp_state))
4399 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4400 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4401 &bp->sp_state))
4402 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4403 #endif
4404
4405 netif_addr_unlock_bh(bp->dev);
4406 }
4407
4408 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4409 struct bnx2x *bp, u32 cid)
4410 {
4411 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
4412 #ifdef BCM_CNIC
4413 if (cid == BNX2X_FCOE_ETH_CID)
4414 return &bnx2x_fcoe(bp, q_obj);
4415 else
4416 #endif
4417 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4418 }
4419
4420 static void bnx2x_eq_int(struct bnx2x *bp)
4421 {
4422 u16 hw_cons, sw_cons, sw_prod;
4423 union event_ring_elem *elem;
4424 u32 cid;
4425 u8 opcode;
4426 int spqe_cnt = 0;
4427 struct bnx2x_queue_sp_obj *q_obj;
4428 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4429 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4430
4431 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4432
4433 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4434 * when we get the the next-page we nned to adjust so the loop
4435 * condition below will be met. The next element is the size of a
4436 * regular element and hence incrementing by 1
4437 */
4438 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4439 hw_cons++;
4440
4441 /* This function may never run in parallel with itself for a
4442 * specific bp, thus there is no need in "paired" read memory
4443 * barrier here.
4444 */
4445 sw_cons = bp->eq_cons;
4446 sw_prod = bp->eq_prod;
4447
4448 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4449 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4450
4451 for (; sw_cons != hw_cons;
4452 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4453
4454
4455 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4456
4457 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4458 opcode = elem->message.opcode;
4459
4460
4461 /* handle eq element */
4462 switch (opcode) {
4463 case EVENT_RING_OPCODE_STAT_QUERY:
4464 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4465 bp->stats_comp++);
4466 /* nothing to do with stats comp */
4467 goto next_spqe;
4468
4469 case EVENT_RING_OPCODE_CFC_DEL:
4470 /* handle according to cid range */
4471 /*
4472 * we may want to verify here that the bp state is
4473 * HALTING
4474 */
4475 DP(BNX2X_MSG_SP,
4476 "got delete ramrod for MULTI[%d]\n", cid);
4477 #ifdef BCM_CNIC
4478 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4479 goto next_spqe;
4480 #endif
4481 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4482
4483 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4484 break;
4485
4486
4487
4488 goto next_spqe;
4489
4490 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4491 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4492 if (f_obj->complete_cmd(bp, f_obj,
4493 BNX2X_F_CMD_TX_STOP))
4494 break;
4495 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4496 goto next_spqe;
4497
4498 case EVENT_RING_OPCODE_START_TRAFFIC:
4499 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4500 if (f_obj->complete_cmd(bp, f_obj,
4501 BNX2X_F_CMD_TX_START))
4502 break;
4503 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4504 goto next_spqe;
4505 case EVENT_RING_OPCODE_FUNCTION_START:
4506 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4507 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4508 break;
4509
4510 goto next_spqe;
4511
4512 case EVENT_RING_OPCODE_FUNCTION_STOP:
4513 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4514 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4515 break;
4516
4517 goto next_spqe;
4518 }
4519
4520 switch (opcode | bp->state) {
4521 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4522 BNX2X_STATE_OPEN):
4523 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4524 BNX2X_STATE_OPENING_WAIT4_PORT):
4525 cid = elem->message.data.eth_event.echo &
4526 BNX2X_SWCID_MASK;
4527 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4528 cid);
4529 rss_raw->clear_pending(rss_raw);
4530 break;
4531
4532 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4533 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4534 case (EVENT_RING_OPCODE_SET_MAC |
4535 BNX2X_STATE_CLOSING_WAIT4_HALT):
4536 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4537 BNX2X_STATE_OPEN):
4538 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4539 BNX2X_STATE_DIAG):
4540 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4541 BNX2X_STATE_CLOSING_WAIT4_HALT):
4542 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4543 bnx2x_handle_classification_eqe(bp, elem);
4544 break;
4545
4546 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4547 BNX2X_STATE_OPEN):
4548 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4549 BNX2X_STATE_DIAG):
4550 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4551 BNX2X_STATE_CLOSING_WAIT4_HALT):
4552 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4553 bnx2x_handle_mcast_eqe(bp);
4554 break;
4555
4556 case (EVENT_RING_OPCODE_FILTERS_RULES |
4557 BNX2X_STATE_OPEN):
4558 case (EVENT_RING_OPCODE_FILTERS_RULES |
4559 BNX2X_STATE_DIAG):
4560 case (EVENT_RING_OPCODE_FILTERS_RULES |
4561 BNX2X_STATE_CLOSING_WAIT4_HALT):
4562 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4563 bnx2x_handle_rx_mode_eqe(bp);
4564 break;
4565 default:
4566 /* unknown event log error and continue */
4567 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4568 elem->message.opcode, bp->state);
4569 }
4570 next_spqe:
4571 spqe_cnt++;
4572 } /* for */
4573
4574 smp_mb__before_atomic_inc();
4575 atomic_add(spqe_cnt, &bp->eq_spq_left);
4576
4577 bp->eq_cons = sw_cons;
4578 bp->eq_prod = sw_prod;
4579 /* Make sure that above mem writes were issued towards the memory */
4580 smp_wmb();
4581
4582 /* update producer */
4583 bnx2x_update_eq_prod(bp, bp->eq_prod);
4584 }
4585
4586 static void bnx2x_sp_task(struct work_struct *work)
4587 {
4588 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4589 u16 status;
4590
4591 status = bnx2x_update_dsb_idx(bp);
4592 /* if (status == 0) */
4593 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4594
4595 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4596
4597 /* HW attentions */
4598 if (status & BNX2X_DEF_SB_ATT_IDX) {
4599 bnx2x_attn_int(bp);
4600 status &= ~BNX2X_DEF_SB_ATT_IDX;
4601 }
4602
4603 /* SP events: STAT_QUERY and others */
4604 if (status & BNX2X_DEF_SB_IDX) {
4605 #ifdef BCM_CNIC
4606 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4607
4608 if ((!NO_FCOE(bp)) &&
4609 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4610 /*
4611 * Prevent local bottom-halves from running as
4612 * we are going to change the local NAPI list.
4613 */
4614 local_bh_disable();
4615 napi_schedule(&bnx2x_fcoe(bp, napi));
4616 local_bh_enable();
4617 }
4618 #endif
4619 /* Handle EQ completions */
4620 bnx2x_eq_int(bp);
4621
4622 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4623 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4624
4625 status &= ~BNX2X_DEF_SB_IDX;
4626 }
4627
4628 if (unlikely(status))
4629 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4630 status);
4631
4632 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4633 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4634 }
4635
4636 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4637 {
4638 struct net_device *dev = dev_instance;
4639 struct bnx2x *bp = netdev_priv(dev);
4640
4641 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4642 IGU_INT_DISABLE, 0);
4643
4644 #ifdef BNX2X_STOP_ON_ERROR
4645 if (unlikely(bp->panic))
4646 return IRQ_HANDLED;
4647 #endif
4648
4649 #ifdef BCM_CNIC
4650 {
4651 struct cnic_ops *c_ops;
4652
4653 rcu_read_lock();
4654 c_ops = rcu_dereference(bp->cnic_ops);
4655 if (c_ops)
4656 c_ops->cnic_handler(bp->cnic_data, NULL);
4657 rcu_read_unlock();
4658 }
4659 #endif
4660 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4661
4662 return IRQ_HANDLED;
4663 }
4664
4665 /* end of slow path */
4666
4667
4668 void bnx2x_drv_pulse(struct bnx2x *bp)
4669 {
4670 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4671 bp->fw_drv_pulse_wr_seq);
4672 }
4673
4674
4675 static void bnx2x_timer(unsigned long data)
4676 {
4677 u8 cos;
4678 struct bnx2x *bp = (struct bnx2x *) data;
4679
4680 if (!netif_running(bp->dev))
4681 return;
4682
4683 if (poll) {
4684 struct bnx2x_fastpath *fp = &bp->fp[0];
4685
4686 for_each_cos_in_tx_queue(fp, cos)
4687 bnx2x_tx_int(bp, &fp->txdata[cos]);
4688 bnx2x_rx_int(fp, 1000);
4689 }
4690
4691 if (!BP_NOMCP(bp)) {
4692 int mb_idx = BP_FW_MB_IDX(bp);
4693 u32 drv_pulse;
4694 u32 mcp_pulse;
4695
4696 ++bp->fw_drv_pulse_wr_seq;
4697 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4698 /* TBD - add SYSTEM_TIME */
4699 drv_pulse = bp->fw_drv_pulse_wr_seq;
4700 bnx2x_drv_pulse(bp);
4701
4702 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4703 MCP_PULSE_SEQ_MASK);
4704 /* The delta between driver pulse and mcp response
4705 * should be 1 (before mcp response) or 0 (after mcp response)
4706 */
4707 if ((drv_pulse != mcp_pulse) &&
4708 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4709 /* someone lost a heartbeat... */
4710 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4711 drv_pulse, mcp_pulse);
4712 }
4713 }
4714
4715 if (bp->state == BNX2X_STATE_OPEN)
4716 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4717
4718 mod_timer(&bp->timer, jiffies + bp->current_interval);
4719 }
4720
4721 /* end of Statistics */
4722
4723 /* nic init */
4724
4725 /*
4726 * nic init service functions
4727 */
4728
4729 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4730 {
4731 u32 i;
4732 if (!(len%4) && !(addr%4))
4733 for (i = 0; i < len; i += 4)
4734 REG_WR(bp, addr + i, fill);
4735 else
4736 for (i = 0; i < len; i++)
4737 REG_WR8(bp, addr + i, fill);
4738
4739 }
4740
4741 /* helper: writes FP SP data to FW - data_size in dwords */
4742 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4743 int fw_sb_id,
4744 u32 *sb_data_p,
4745 u32 data_size)
4746 {
4747 int index;
4748 for (index = 0; index < data_size; index++)
4749 REG_WR(bp, BAR_CSTRORM_INTMEM +
4750 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4751 sizeof(u32)*index,
4752 *(sb_data_p + index));
4753 }
4754
4755 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4756 {
4757 u32 *sb_data_p;
4758 u32 data_size = 0;
4759 struct hc_status_block_data_e2 sb_data_e2;
4760 struct hc_status_block_data_e1x sb_data_e1x;
4761
4762 /* disable the function first */
4763 if (!CHIP_IS_E1x(bp)) {
4764 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4765 sb_data_e2.common.state = SB_DISABLED;
4766 sb_data_e2.common.p_func.vf_valid = false;
4767 sb_data_p = (u32 *)&sb_data_e2;
4768 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4769 } else {
4770 memset(&sb_data_e1x, 0,
4771 sizeof(struct hc_status_block_data_e1x));
4772 sb_data_e1x.common.state = SB_DISABLED;
4773 sb_data_e1x.common.p_func.vf_valid = false;
4774 sb_data_p = (u32 *)&sb_data_e1x;
4775 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4776 }
4777 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4778
4779 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4780 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4781 CSTORM_STATUS_BLOCK_SIZE);
4782 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4783 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4784 CSTORM_SYNC_BLOCK_SIZE);
4785 }
4786
4787 /* helper: writes SP SB data to FW */
4788 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4789 struct hc_sp_status_block_data *sp_sb_data)
4790 {
4791 int func = BP_FUNC(bp);
4792 int i;
4793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4794 REG_WR(bp, BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4796 i*sizeof(u32),
4797 *((u32 *)sp_sb_data + i));
4798 }
4799
4800 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4801 {
4802 int func = BP_FUNC(bp);
4803 struct hc_sp_status_block_data sp_sb_data;
4804 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4805
4806 sp_sb_data.state = SB_DISABLED;
4807 sp_sb_data.p_func.vf_valid = false;
4808
4809 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4810
4811 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4812 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4813 CSTORM_SP_STATUS_BLOCK_SIZE);
4814 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4815 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4816 CSTORM_SP_SYNC_BLOCK_SIZE);
4817
4818 }
4819
4820
4821 static inline
4822 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4823 int igu_sb_id, int igu_seg_id)
4824 {
4825 hc_sm->igu_sb_id = igu_sb_id;
4826 hc_sm->igu_seg_id = igu_seg_id;
4827 hc_sm->timer_value = 0xFF;
4828 hc_sm->time_to_expire = 0xFFFFFFFF;
4829 }
4830
4831 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4832 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4833 {
4834 int igu_seg_id;
4835
4836 struct hc_status_block_data_e2 sb_data_e2;
4837 struct hc_status_block_data_e1x sb_data_e1x;
4838 struct hc_status_block_sm *hc_sm_p;
4839 int data_size;
4840 u32 *sb_data_p;
4841
4842 if (CHIP_INT_MODE_IS_BC(bp))
4843 igu_seg_id = HC_SEG_ACCESS_NORM;
4844 else
4845 igu_seg_id = IGU_SEG_ACCESS_NORM;
4846
4847 bnx2x_zero_fp_sb(bp, fw_sb_id);
4848
4849 if (!CHIP_IS_E1x(bp)) {
4850 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4851 sb_data_e2.common.state = SB_ENABLED;
4852 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4853 sb_data_e2.common.p_func.vf_id = vfid;
4854 sb_data_e2.common.p_func.vf_valid = vf_valid;
4855 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4856 sb_data_e2.common.same_igu_sb_1b = true;
4857 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4858 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4859 hc_sm_p = sb_data_e2.common.state_machine;
4860 sb_data_p = (u32 *)&sb_data_e2;
4861 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4862 } else {
4863 memset(&sb_data_e1x, 0,
4864 sizeof(struct hc_status_block_data_e1x));
4865 sb_data_e1x.common.state = SB_ENABLED;
4866 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4867 sb_data_e1x.common.p_func.vf_id = 0xff;
4868 sb_data_e1x.common.p_func.vf_valid = false;
4869 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4870 sb_data_e1x.common.same_igu_sb_1b = true;
4871 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4872 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4873 hc_sm_p = sb_data_e1x.common.state_machine;
4874 sb_data_p = (u32 *)&sb_data_e1x;
4875 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4876 }
4877
4878 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4879 igu_sb_id, igu_seg_id);
4880 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4881 igu_sb_id, igu_seg_id);
4882
4883 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4884
4885 /* write indecies to HW */
4886 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4887 }
4888
4889 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4890 u16 tx_usec, u16 rx_usec)
4891 {
4892 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4893 false, rx_usec);
4894 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4895 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4896 tx_usec);
4897 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4898 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4899 tx_usec);
4900 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4901 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4902 tx_usec);
4903 }
4904
4905 static void bnx2x_init_def_sb(struct bnx2x *bp)
4906 {
4907 struct host_sp_status_block *def_sb = bp->def_status_blk;
4908 dma_addr_t mapping = bp->def_status_blk_mapping;
4909 int igu_sp_sb_index;
4910 int igu_seg_id;
4911 int port = BP_PORT(bp);
4912 int func = BP_FUNC(bp);
4913 int reg_offset;
4914 u64 section;
4915 int index;
4916 struct hc_sp_status_block_data sp_sb_data;
4917 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4918
4919 if (CHIP_INT_MODE_IS_BC(bp)) {
4920 igu_sp_sb_index = DEF_SB_IGU_ID;
4921 igu_seg_id = HC_SEG_ACCESS_DEF;
4922 } else {
4923 igu_sp_sb_index = bp->igu_dsb_id;
4924 igu_seg_id = IGU_SEG_ACCESS_DEF;
4925 }
4926
4927 /* ATTN */
4928 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4929 atten_status_block);
4930 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4931
4932 bp->attn_state = 0;
4933
4934 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4935 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4936 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4937 int sindex;
4938 /* take care of sig[0]..sig[4] */
4939 for (sindex = 0; sindex < 4; sindex++)
4940 bp->attn_group[index].sig[sindex] =
4941 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4942
4943 if (!CHIP_IS_E1x(bp))
4944 /*
4945 * enable5 is separate from the rest of the registers,
4946 * and therefore the address skip is 4
4947 * and not 16 between the different groups
4948 */
4949 bp->attn_group[index].sig[4] = REG_RD(bp,
4950 reg_offset + 0x10 + 0x4*index);
4951 else
4952 bp->attn_group[index].sig[4] = 0;
4953 }
4954
4955 if (bp->common.int_block == INT_BLOCK_HC) {
4956 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4957 HC_REG_ATTN_MSG0_ADDR_L);
4958
4959 REG_WR(bp, reg_offset, U64_LO(section));
4960 REG_WR(bp, reg_offset + 4, U64_HI(section));
4961 } else if (!CHIP_IS_E1x(bp)) {
4962 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4963 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4964 }
4965
4966 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4967 sp_sb);
4968
4969 bnx2x_zero_sp_sb(bp);
4970
4971 sp_sb_data.state = SB_ENABLED;
4972 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4973 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4974 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4975 sp_sb_data.igu_seg_id = igu_seg_id;
4976 sp_sb_data.p_func.pf_id = func;
4977 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4978 sp_sb_data.p_func.vf_id = 0xff;
4979
4980 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4981
4982 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4983 }
4984
4985 void bnx2x_update_coalesce(struct bnx2x *bp)
4986 {
4987 int i;
4988
4989 for_each_eth_queue(bp, i)
4990 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4991 bp->tx_ticks, bp->rx_ticks);
4992 }
4993
4994 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4995 {
4996 spin_lock_init(&bp->spq_lock);
4997 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4998
4999 bp->spq_prod_idx = 0;
5000 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5001 bp->spq_prod_bd = bp->spq;
5002 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5003 }
5004
5005 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5006 {
5007 int i;
5008 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5009 union event_ring_elem *elem =
5010 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5011
5012 elem->next_page.addr.hi =
5013 cpu_to_le32(U64_HI(bp->eq_mapping +
5014 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5015 elem->next_page.addr.lo =
5016 cpu_to_le32(U64_LO(bp->eq_mapping +
5017 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5018 }
5019 bp->eq_cons = 0;
5020 bp->eq_prod = NUM_EQ_DESC;
5021 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5022 /* we want a warning message before it gets rought... */
5023 atomic_set(&bp->eq_spq_left,
5024 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5025 }
5026
5027
5028 /* called with netif_addr_lock_bh() */
5029 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5030 unsigned long rx_mode_flags,
5031 unsigned long rx_accept_flags,
5032 unsigned long tx_accept_flags,
5033 unsigned long ramrod_flags)
5034 {
5035 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5036 int rc;
5037
5038 memset(&ramrod_param, 0, sizeof(ramrod_param));
5039
5040 /* Prepare ramrod parameters */
5041 ramrod_param.cid = 0;
5042 ramrod_param.cl_id = cl_id;
5043 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5044 ramrod_param.func_id = BP_FUNC(bp);
5045
5046 ramrod_param.pstate = &bp->sp_state;
5047 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5048
5049 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5050 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5051
5052 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5053
5054 ramrod_param.ramrod_flags = ramrod_flags;
5055 ramrod_param.rx_mode_flags = rx_mode_flags;
5056
5057 ramrod_param.rx_accept_flags = rx_accept_flags;
5058 ramrod_param.tx_accept_flags = tx_accept_flags;
5059
5060 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5061 if (rc < 0) {
5062 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5063 return;
5064 }
5065 }
5066
5067 /* called with netif_addr_lock_bh() */
5068 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5069 {
5070 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5071 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5072
5073 #ifdef BCM_CNIC
5074 if (!NO_FCOE(bp))
5075
5076 /* Configure rx_mode of FCoE Queue */
5077 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5078 #endif
5079
5080 switch (bp->rx_mode) {
5081 case BNX2X_RX_MODE_NONE:
5082 /*
5083 * 'drop all' supersedes any accept flags that may have been
5084 * passed to the function.
5085 */
5086 break;
5087 case BNX2X_RX_MODE_NORMAL:
5088 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5089 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5090 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5091
5092 /* internal switching mode */
5093 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5094 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5095 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5096
5097 break;
5098 case BNX2X_RX_MODE_ALLMULTI:
5099 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5100 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5101 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5102
5103 /* internal switching mode */
5104 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5105 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5106 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5107
5108 break;
5109 case BNX2X_RX_MODE_PROMISC:
5110 /* According to deffinition of SI mode, iface in promisc mode
5111 * should receive matched and unmatched (in resolution of port)
5112 * unicast packets.
5113 */
5114 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5115 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5116 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5117 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5118
5119 /* internal switching mode */
5120 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5121 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5122
5123 if (IS_MF_SI(bp))
5124 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5125 else
5126 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5127
5128 break;
5129 default:
5130 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5131 return;
5132 }
5133
5134 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5135 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5136 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5137 }
5138
5139 __set_bit(RAMROD_RX, &ramrod_flags);
5140 __set_bit(RAMROD_TX, &ramrod_flags);
5141
5142 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5143 tx_accept_flags, ramrod_flags);
5144 }
5145
5146 static void bnx2x_init_internal_common(struct bnx2x *bp)
5147 {
5148 int i;
5149
5150 if (IS_MF_SI(bp))
5151 /*
5152 * In switch independent mode, the TSTORM needs to accept
5153 * packets that failed classification, since approximate match
5154 * mac addresses aren't written to NIG LLH
5155 */
5156 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5157 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5158 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5159 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5160 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5161
5162 /* Zero this manually as its initialization is
5163 currently missing in the initTool */
5164 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5165 REG_WR(bp, BAR_USTRORM_INTMEM +
5166 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5167 if (!CHIP_IS_E1x(bp)) {
5168 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5169 CHIP_INT_MODE_IS_BC(bp) ?
5170 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5171 }
5172 }
5173
5174 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5175 {
5176 switch (load_code) {
5177 case FW_MSG_CODE_DRV_LOAD_COMMON:
5178 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5179 bnx2x_init_internal_common(bp);
5180 /* no break */
5181
5182 case FW_MSG_CODE_DRV_LOAD_PORT:
5183 /* nothing to do */
5184 /* no break */
5185
5186 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5187 /* internal memory per function is
5188 initialized inside bnx2x_pf_init */
5189 break;
5190
5191 default:
5192 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5193 break;
5194 }
5195 }
5196
5197 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5198 {
5199 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5200 }
5201
5202 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5203 {
5204 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5205 }
5206
5207 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5208 {
5209 if (CHIP_IS_E1x(fp->bp))
5210 return BP_L_ID(fp->bp) + fp->index;
5211 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5212 return bnx2x_fp_igu_sb_id(fp);
5213 }
5214
5215 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5216 {
5217 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5218 u8 cos;
5219 unsigned long q_type = 0;
5220 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5221
5222 fp->cid = fp_idx;
5223 fp->cl_id = bnx2x_fp_cl_id(fp);
5224 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5225 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5226 /* qZone id equals to FW (per path) client id */
5227 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5228
5229 /* init shortcut */
5230 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5231 /* Setup SB indicies */
5232 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5233
5234 /* Configure Queue State object */
5235 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5236 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5237
5238 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5239
5240 /* init tx data */
5241 for_each_cos_in_tx_queue(fp, cos) {
5242 bnx2x_init_txdata(bp, &fp->txdata[cos],
5243 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5244 FP_COS_TO_TXQ(fp, cos),
5245 BNX2X_TX_SB_INDEX_BASE + cos);
5246 cids[cos] = fp->txdata[cos].cid;
5247 }
5248
5249 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5250 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5251 bnx2x_sp_mapping(bp, q_rdata), q_type);
5252
5253 /**
5254 * Configure classification DBs: Always enable Tx switching
5255 */
5256 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5257
5258 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5259 "cl_id %d fw_sb %d igu_sb %d\n",
5260 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5261 fp->igu_sb_id);
5262 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5263 fp->fw_sb_id, fp->igu_sb_id);
5264
5265 bnx2x_update_fpsb_idx(fp);
5266 }
5267
5268 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5269 {
5270 int i;
5271
5272 for_each_eth_queue(bp, i)
5273 bnx2x_init_eth_fp(bp, i);
5274 #ifdef BCM_CNIC
5275 if (!NO_FCOE(bp))
5276 bnx2x_init_fcoe_fp(bp);
5277
5278 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5279 BNX2X_VF_ID_INVALID, false,
5280 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5281
5282 #endif
5283
5284 /* Initialize MOD_ABS interrupts */
5285 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5286 bp->common.shmem_base, bp->common.shmem2_base,
5287 BP_PORT(bp));
5288 /* ensure status block indices were read */
5289 rmb();
5290
5291 bnx2x_init_def_sb(bp);
5292 bnx2x_update_dsb_idx(bp);
5293 bnx2x_init_rx_rings(bp);
5294 bnx2x_init_tx_rings(bp);
5295 bnx2x_init_sp_ring(bp);
5296 bnx2x_init_eq_ring(bp);
5297 bnx2x_init_internal(bp, load_code);
5298 bnx2x_pf_init(bp);
5299 bnx2x_stats_init(bp);
5300
5301 /* flush all before enabling interrupts */
5302 mb();
5303 mmiowb();
5304
5305 bnx2x_int_enable(bp);
5306
5307 /* Check for SPIO5 */
5308 bnx2x_attn_int_deasserted0(bp,
5309 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5310 AEU_INPUTS_ATTN_BITS_SPIO5);
5311 }
5312
5313 /* end of nic init */
5314
5315 /*
5316 * gzip service functions
5317 */
5318
5319 static int bnx2x_gunzip_init(struct bnx2x *bp)
5320 {
5321 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5322 &bp->gunzip_mapping, GFP_KERNEL);
5323 if (bp->gunzip_buf == NULL)
5324 goto gunzip_nomem1;
5325
5326 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5327 if (bp->strm == NULL)
5328 goto gunzip_nomem2;
5329
5330 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5331 if (bp->strm->workspace == NULL)
5332 goto gunzip_nomem3;
5333
5334 return 0;
5335
5336 gunzip_nomem3:
5337 kfree(bp->strm);
5338 bp->strm = NULL;
5339
5340 gunzip_nomem2:
5341 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5342 bp->gunzip_mapping);
5343 bp->gunzip_buf = NULL;
5344
5345 gunzip_nomem1:
5346 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5347 " un-compression\n");
5348 return -ENOMEM;
5349 }
5350
5351 static void bnx2x_gunzip_end(struct bnx2x *bp)
5352 {
5353 if (bp->strm) {
5354 vfree(bp->strm->workspace);
5355 kfree(bp->strm);
5356 bp->strm = NULL;
5357 }
5358
5359 if (bp->gunzip_buf) {
5360 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5361 bp->gunzip_mapping);
5362 bp->gunzip_buf = NULL;
5363 }
5364 }
5365
5366 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5367 {
5368 int n, rc;
5369
5370 /* check gzip header */
5371 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5372 BNX2X_ERR("Bad gzip header\n");
5373 return -EINVAL;
5374 }
5375
5376 n = 10;
5377
5378 #define FNAME 0x8
5379
5380 if (zbuf[3] & FNAME)
5381 while ((zbuf[n++] != 0) && (n < len));
5382
5383 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5384 bp->strm->avail_in = len - n;
5385 bp->strm->next_out = bp->gunzip_buf;
5386 bp->strm->avail_out = FW_BUF_SIZE;
5387
5388 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5389 if (rc != Z_OK)
5390 return rc;
5391
5392 rc = zlib_inflate(bp->strm, Z_FINISH);
5393 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5394 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5395 bp->strm->msg);
5396
5397 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5398 if (bp->gunzip_outlen & 0x3)
5399 netdev_err(bp->dev, "Firmware decompression error:"
5400 " gunzip_outlen (%d) not aligned\n",
5401 bp->gunzip_outlen);
5402 bp->gunzip_outlen >>= 2;
5403
5404 zlib_inflateEnd(bp->strm);
5405
5406 if (rc == Z_STREAM_END)
5407 return 0;
5408
5409 return rc;
5410 }
5411
5412 /* nic load/unload */
5413
5414 /*
5415 * General service functions
5416 */
5417
5418 /* send a NIG loopback debug packet */
5419 static void bnx2x_lb_pckt(struct bnx2x *bp)
5420 {
5421 u32 wb_write[3];
5422
5423 /* Ethernet source and destination addresses */
5424 wb_write[0] = 0x55555555;
5425 wb_write[1] = 0x55555555;
5426 wb_write[2] = 0x20; /* SOP */
5427 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5428
5429 /* NON-IP protocol */
5430 wb_write[0] = 0x09000000;
5431 wb_write[1] = 0x55555555;
5432 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5433 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5434 }
5435
5436 /* some of the internal memories
5437 * are not directly readable from the driver
5438 * to test them we send debug packets
5439 */
5440 static int bnx2x_int_mem_test(struct bnx2x *bp)
5441 {
5442 int factor;
5443 int count, i;
5444 u32 val = 0;
5445
5446 if (CHIP_REV_IS_FPGA(bp))
5447 factor = 120;
5448 else if (CHIP_REV_IS_EMUL(bp))
5449 factor = 200;
5450 else
5451 factor = 1;
5452
5453 /* Disable inputs of parser neighbor blocks */
5454 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5455 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5456 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5457 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5458
5459 /* Write 0 to parser credits for CFC search request */
5460 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5461
5462 /* send Ethernet packet */
5463 bnx2x_lb_pckt(bp);
5464
5465 /* TODO do i reset NIG statistic? */
5466 /* Wait until NIG register shows 1 packet of size 0x10 */
5467 count = 1000 * factor;
5468 while (count) {
5469
5470 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5471 val = *bnx2x_sp(bp, wb_data[0]);
5472 if (val == 0x10)
5473 break;
5474
5475 msleep(10);
5476 count--;
5477 }
5478 if (val != 0x10) {
5479 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5480 return -1;
5481 }
5482
5483 /* Wait until PRS register shows 1 packet */
5484 count = 1000 * factor;
5485 while (count) {
5486 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5487 if (val == 1)
5488 break;
5489
5490 msleep(10);
5491 count--;
5492 }
5493 if (val != 0x1) {
5494 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5495 return -2;
5496 }
5497
5498 /* Reset and init BRB, PRS */
5499 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5500 msleep(50);
5501 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5502 msleep(50);
5503 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5504 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5505
5506 DP(NETIF_MSG_HW, "part2\n");
5507
5508 /* Disable inputs of parser neighbor blocks */
5509 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5510 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5511 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5512 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5513
5514 /* Write 0 to parser credits for CFC search request */
5515 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5516
5517 /* send 10 Ethernet packets */
5518 for (i = 0; i < 10; i++)
5519 bnx2x_lb_pckt(bp);
5520
5521 /* Wait until NIG register shows 10 + 1
5522 packets of size 11*0x10 = 0xb0 */
5523 count = 1000 * factor;
5524 while (count) {
5525
5526 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5527 val = *bnx2x_sp(bp, wb_data[0]);
5528 if (val == 0xb0)
5529 break;
5530
5531 msleep(10);
5532 count--;
5533 }
5534 if (val != 0xb0) {
5535 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5536 return -3;
5537 }
5538
5539 /* Wait until PRS register shows 2 packets */
5540 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5541 if (val != 2)
5542 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5543
5544 /* Write 1 to parser credits for CFC search request */
5545 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5546
5547 /* Wait until PRS register shows 3 packets */
5548 msleep(10 * factor);
5549 /* Wait until NIG register shows 1 packet of size 0x10 */
5550 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5551 if (val != 3)
5552 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5553
5554 /* clear NIG EOP FIFO */
5555 for (i = 0; i < 11; i++)
5556 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5557 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5558 if (val != 1) {
5559 BNX2X_ERR("clear of NIG failed\n");
5560 return -4;
5561 }
5562
5563 /* Reset and init BRB, PRS, NIG */
5564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5565 msleep(50);
5566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5567 msleep(50);
5568 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5569 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5570 #ifndef BCM_CNIC
5571 /* set NIC mode */
5572 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5573 #endif
5574
5575 /* Enable inputs of parser neighbor blocks */
5576 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5577 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5578 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5579 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5580
5581 DP(NETIF_MSG_HW, "done\n");
5582
5583 return 0; /* OK */
5584 }
5585
5586 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5587 {
5588 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5589 if (!CHIP_IS_E1x(bp))
5590 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5591 else
5592 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5593 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5594 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5595 /*
5596 * mask read length error interrupts in brb for parser
5597 * (parsing unit and 'checksum and crc' unit)
5598 * these errors are legal (PU reads fixed length and CAC can cause
5599 * read length error on truncated packets)
5600 */
5601 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5602 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5603 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5604 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5605 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5606 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5607 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5608 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5609 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5610 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5611 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5612 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5613 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5614 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5615 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5616 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5617 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5618 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5619 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5620
5621 if (CHIP_REV_IS_FPGA(bp))
5622 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5623 else if (!CHIP_IS_E1x(bp))
5624 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5625 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5626 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5627 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5628 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5629 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5630 else
5631 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5632 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5633 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5634 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5635 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5636
5637 if (!CHIP_IS_E1x(bp))
5638 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5639 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5640
5641 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5642 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5643 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5644 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5645 }
5646
5647 static void bnx2x_reset_common(struct bnx2x *bp)
5648 {
5649 u32 val = 0x1400;
5650
5651 /* reset_common */
5652 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5653 0xd3ffff7f);
5654
5655 if (CHIP_IS_E3(bp)) {
5656 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5657 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5658 }
5659
5660 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5661 }
5662
5663 static void bnx2x_setup_dmae(struct bnx2x *bp)
5664 {
5665 bp->dmae_ready = 0;
5666 spin_lock_init(&bp->dmae_lock);
5667 }
5668
5669 static void bnx2x_init_pxp(struct bnx2x *bp)
5670 {
5671 u16 devctl;
5672 int r_order, w_order;
5673
5674 pci_read_config_word(bp->pdev,
5675 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5676 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5677 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5678 if (bp->mrrs == -1)
5679 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5680 else {
5681 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5682 r_order = bp->mrrs;
5683 }
5684
5685 bnx2x_init_pxp_arb(bp, r_order, w_order);
5686 }
5687
5688 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5689 {
5690 int is_required;
5691 u32 val;
5692 int port;
5693
5694 if (BP_NOMCP(bp))
5695 return;
5696
5697 is_required = 0;
5698 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5699 SHARED_HW_CFG_FAN_FAILURE_MASK;
5700
5701 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5702 is_required = 1;
5703
5704 /*
5705 * The fan failure mechanism is usually related to the PHY type since
5706 * the power consumption of the board is affected by the PHY. Currently,
5707 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5708 */
5709 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5710 for (port = PORT_0; port < PORT_MAX; port++) {
5711 is_required |=
5712 bnx2x_fan_failure_det_req(
5713 bp,
5714 bp->common.shmem_base,
5715 bp->common.shmem2_base,
5716 port);
5717 }
5718
5719 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5720
5721 if (is_required == 0)
5722 return;
5723
5724 /* Fan failure is indicated by SPIO 5 */
5725 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5726 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5727
5728 /* set to active low mode */
5729 val = REG_RD(bp, MISC_REG_SPIO_INT);
5730 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5731 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5732 REG_WR(bp, MISC_REG_SPIO_INT, val);
5733
5734 /* enable interrupt to signal the IGU */
5735 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5736 val |= (1 << MISC_REGISTERS_SPIO_5);
5737 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5738 }
5739
5740 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5741 {
5742 u32 offset = 0;
5743
5744 if (CHIP_IS_E1(bp))
5745 return;
5746 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5747 return;
5748
5749 switch (BP_ABS_FUNC(bp)) {
5750 case 0:
5751 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5752 break;
5753 case 1:
5754 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5755 break;
5756 case 2:
5757 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5758 break;
5759 case 3:
5760 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5761 break;
5762 case 4:
5763 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5764 break;
5765 case 5:
5766 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5767 break;
5768 case 6:
5769 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5770 break;
5771 case 7:
5772 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5773 break;
5774 default:
5775 return;
5776 }
5777
5778 REG_WR(bp, offset, pretend_func_num);
5779 REG_RD(bp, offset);
5780 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5781 }
5782
5783 void bnx2x_pf_disable(struct bnx2x *bp)
5784 {
5785 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5786 val &= ~IGU_PF_CONF_FUNC_EN;
5787
5788 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5789 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5790 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5791 }
5792
5793 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5794 {
5795 u32 shmem_base[2], shmem2_base[2];
5796 shmem_base[0] = bp->common.shmem_base;
5797 shmem2_base[0] = bp->common.shmem2_base;
5798 if (!CHIP_IS_E1x(bp)) {
5799 shmem_base[1] =
5800 SHMEM2_RD(bp, other_shmem_base_addr);
5801 shmem2_base[1] =
5802 SHMEM2_RD(bp, other_shmem2_base_addr);
5803 }
5804 bnx2x_acquire_phy_lock(bp);
5805 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5806 bp->common.chip_id);
5807 bnx2x_release_phy_lock(bp);
5808 }
5809
5810 /**
5811 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5812 *
5813 * @bp: driver handle
5814 */
5815 static int bnx2x_init_hw_common(struct bnx2x *bp)
5816 {
5817 u32 val;
5818
5819 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5820
5821 /*
5822 * take the UNDI lock to protect undi_unload flow from accessing
5823 * registers while we're resetting the chip
5824 */
5825 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5826
5827 bnx2x_reset_common(bp);
5828 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5829
5830 val = 0xfffc;
5831 if (CHIP_IS_E3(bp)) {
5832 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5833 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5834 }
5835 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5836
5837 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
5838
5839 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5840
5841 if (!CHIP_IS_E1x(bp)) {
5842 u8 abs_func_id;
5843
5844 /**
5845 * 4-port mode or 2-port mode we need to turn of master-enable
5846 * for everyone, after that, turn it back on for self.
5847 * so, we disregard multi-function or not, and always disable
5848 * for all functions on the given path, this means 0,2,4,6 for
5849 * path 0 and 1,3,5,7 for path 1
5850 */
5851 for (abs_func_id = BP_PATH(bp);
5852 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5853 if (abs_func_id == BP_ABS_FUNC(bp)) {
5854 REG_WR(bp,
5855 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5856 1);
5857 continue;
5858 }
5859
5860 bnx2x_pretend_func(bp, abs_func_id);
5861 /* clear pf enable */
5862 bnx2x_pf_disable(bp);
5863 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5864 }
5865 }
5866
5867 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5868 if (CHIP_IS_E1(bp)) {
5869 /* enable HW interrupt from PXP on USDM overflow
5870 bit 16 on INT_MASK_0 */
5871 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5872 }
5873
5874 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5875 bnx2x_init_pxp(bp);
5876
5877 #ifdef __BIG_ENDIAN
5878 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5879 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5880 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5881 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5882 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5883 /* make sure this value is 0 */
5884 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5885
5886 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5887 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5888 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5889 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5890 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5891 #endif
5892
5893 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5894
5895 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5896 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5897
5898 /* let the HW do it's magic ... */
5899 msleep(100);
5900 /* finish PXP init */
5901 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5902 if (val != 1) {
5903 BNX2X_ERR("PXP2 CFG failed\n");
5904 return -EBUSY;
5905 }
5906 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5907 if (val != 1) {
5908 BNX2X_ERR("PXP2 RD_INIT failed\n");
5909 return -EBUSY;
5910 }
5911
5912 /* Timers bug workaround E2 only. We need to set the entire ILT to
5913 * have entries with value "0" and valid bit on.
5914 * This needs to be done by the first PF that is loaded in a path
5915 * (i.e. common phase)
5916 */
5917 if (!CHIP_IS_E1x(bp)) {
5918 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5919 * (i.e. vnic3) to start even if it is marked as "scan-off".
5920 * This occurs when a different function (func2,3) is being marked
5921 * as "scan-off". Real-life scenario for example: if a driver is being
5922 * load-unloaded while func6,7 are down. This will cause the timer to access
5923 * the ilt, translate to a logical address and send a request to read/write.
5924 * Since the ilt for the function that is down is not valid, this will cause
5925 * a translation error which is unrecoverable.
5926 * The Workaround is intended to make sure that when this happens nothing fatal
5927 * will occur. The workaround:
5928 * 1. First PF driver which loads on a path will:
5929 * a. After taking the chip out of reset, by using pretend,
5930 * it will write "0" to the following registers of
5931 * the other vnics.
5932 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5933 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5934 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5935 * And for itself it will write '1' to
5936 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5937 * dmae-operations (writing to pram for example.)
5938 * note: can be done for only function 6,7 but cleaner this
5939 * way.
5940 * b. Write zero+valid to the entire ILT.
5941 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5942 * VNIC3 (of that port). The range allocated will be the
5943 * entire ILT. This is needed to prevent ILT range error.
5944 * 2. Any PF driver load flow:
5945 * a. ILT update with the physical addresses of the allocated
5946 * logical pages.
5947 * b. Wait 20msec. - note that this timeout is needed to make
5948 * sure there are no requests in one of the PXP internal
5949 * queues with "old" ILT addresses.
5950 * c. PF enable in the PGLC.
5951 * d. Clear the was_error of the PF in the PGLC. (could have
5952 * occured while driver was down)
5953 * e. PF enable in the CFC (WEAK + STRONG)
5954 * f. Timers scan enable
5955 * 3. PF driver unload flow:
5956 * a. Clear the Timers scan_en.
5957 * b. Polling for scan_on=0 for that PF.
5958 * c. Clear the PF enable bit in the PXP.
5959 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5960 * e. Write zero+valid to all ILT entries (The valid bit must
5961 * stay set)
5962 * f. If this is VNIC 3 of a port then also init
5963 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5964 * to the last enrty in the ILT.
5965 *
5966 * Notes:
5967 * Currently the PF error in the PGLC is non recoverable.
5968 * In the future the there will be a recovery routine for this error.
5969 * Currently attention is masked.
5970 * Having an MCP lock on the load/unload process does not guarantee that
5971 * there is no Timer disable during Func6/7 enable. This is because the
5972 * Timers scan is currently being cleared by the MCP on FLR.
5973 * Step 2.d can be done only for PF6/7 and the driver can also check if
5974 * there is error before clearing it. But the flow above is simpler and
5975 * more general.
5976 * All ILT entries are written by zero+valid and not just PF6/7
5977 * ILT entries since in the future the ILT entries allocation for
5978 * PF-s might be dynamic.
5979 */
5980 struct ilt_client_info ilt_cli;
5981 struct bnx2x_ilt ilt;
5982 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5983 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5984
5985 /* initialize dummy TM client */
5986 ilt_cli.start = 0;
5987 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5988 ilt_cli.client_num = ILT_CLIENT_TM;
5989
5990 /* Step 1: set zeroes to all ilt page entries with valid bit on
5991 * Step 2: set the timers first/last ilt entry to point
5992 * to the entire range to prevent ILT range error for 3rd/4th
5993 * vnic (this code assumes existance of the vnic)
5994 *
5995 * both steps performed by call to bnx2x_ilt_client_init_op()
5996 * with dummy TM client
5997 *
5998 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5999 * and his brother are split registers
6000 */
6001 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6002 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6003 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6004
6005 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6006 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6007 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6008 }
6009
6010
6011 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6012 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6013
6014 if (!CHIP_IS_E1x(bp)) {
6015 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6016 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6017 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6018
6019 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6020
6021 /* let the HW do it's magic ... */
6022 do {
6023 msleep(200);
6024 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6025 } while (factor-- && (val != 1));
6026
6027 if (val != 1) {
6028 BNX2X_ERR("ATC_INIT failed\n");
6029 return -EBUSY;
6030 }
6031 }
6032
6033 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6034
6035 /* clean the DMAE memory */
6036 bp->dmae_ready = 1;
6037 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6038
6039 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6040
6041 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6042
6043 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6044
6045 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6046
6047 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6048 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6049 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6050 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6051
6052 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6053
6054
6055 /* QM queues pointers table */
6056 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6057
6058 /* soft reset pulse */
6059 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6060 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6061
6062 #ifdef BCM_CNIC
6063 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6064 #endif
6065
6066 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6067 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6068 if (!CHIP_REV_IS_SLOW(bp))
6069 /* enable hw interrupt from doorbell Q */
6070 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6071
6072 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6073
6074 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6075 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6076
6077 if (!CHIP_IS_E1(bp))
6078 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6079
6080 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6081 /* Bit-map indicating which L2 hdrs may appear
6082 * after the basic Ethernet header
6083 */
6084 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6085 bp->path_has_ovlan ? 7 : 6);
6086
6087 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6088 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6089 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6090 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6091
6092 if (!CHIP_IS_E1x(bp)) {
6093 /* reset VFC memories */
6094 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6095 VFC_MEMORIES_RST_REG_CAM_RST |
6096 VFC_MEMORIES_RST_REG_RAM_RST);
6097 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6098 VFC_MEMORIES_RST_REG_CAM_RST |
6099 VFC_MEMORIES_RST_REG_RAM_RST);
6100
6101 msleep(20);
6102 }
6103
6104 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6105 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6106 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6107 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6108
6109 /* sync semi rtc */
6110 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6111 0x80000000);
6112 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6113 0x80000000);
6114
6115 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6116 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6117 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6118
6119 if (!CHIP_IS_E1x(bp))
6120 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6121 bp->path_has_ovlan ? 7 : 6);
6122
6123 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6124
6125 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6126
6127 #ifdef BCM_CNIC
6128 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6129 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6130 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6131 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6132 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6133 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6134 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6135 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6136 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6137 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6138 #endif
6139 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6140
6141 if (sizeof(union cdu_context) != 1024)
6142 /* we currently assume that a context is 1024 bytes */
6143 dev_alert(&bp->pdev->dev, "please adjust the size "
6144 "of cdu_context(%ld)\n",
6145 (long)sizeof(union cdu_context));
6146
6147 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6148 val = (4 << 24) + (0 << 12) + 1024;
6149 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6150
6151 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6152 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6153 /* enable context validation interrupt from CFC */
6154 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6155
6156 /* set the thresholds to prevent CFC/CDU race */
6157 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6158
6159 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6160
6161 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6162 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6163
6164 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6165 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6166
6167 /* Reset PCIE errors for debug */
6168 REG_WR(bp, 0x2814, 0xffffffff);
6169 REG_WR(bp, 0x3820, 0xffffffff);
6170
6171 if (!CHIP_IS_E1x(bp)) {
6172 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6173 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6174 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6175 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6176 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6177 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6178 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6179 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6180 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6181 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6182 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6183 }
6184
6185 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6186 if (!CHIP_IS_E1(bp)) {
6187 /* in E3 this done in per-port section */
6188 if (!CHIP_IS_E3(bp))
6189 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6190 }
6191 if (CHIP_IS_E1H(bp))
6192 /* not applicable for E2 (and above ...) */
6193 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6194
6195 if (CHIP_REV_IS_SLOW(bp))
6196 msleep(200);
6197
6198 /* finish CFC init */
6199 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6200 if (val != 1) {
6201 BNX2X_ERR("CFC LL_INIT failed\n");
6202 return -EBUSY;
6203 }
6204 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6205 if (val != 1) {
6206 BNX2X_ERR("CFC AC_INIT failed\n");
6207 return -EBUSY;
6208 }
6209 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6210 if (val != 1) {
6211 BNX2X_ERR("CFC CAM_INIT failed\n");
6212 return -EBUSY;
6213 }
6214 REG_WR(bp, CFC_REG_DEBUG0, 0);
6215
6216 if (CHIP_IS_E1(bp)) {
6217 /* read NIG statistic
6218 to see if this is our first up since powerup */
6219 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6220 val = *bnx2x_sp(bp, wb_data[0]);
6221
6222 /* do internal memory self test */
6223 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6224 BNX2X_ERR("internal mem self test failed\n");
6225 return -EBUSY;
6226 }
6227 }
6228
6229 bnx2x_setup_fan_failure_detection(bp);
6230
6231 /* clear PXP2 attentions */
6232 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6233
6234 bnx2x_enable_blocks_attention(bp);
6235 bnx2x_enable_blocks_parity(bp);
6236
6237 if (!BP_NOMCP(bp)) {
6238 if (CHIP_IS_E1x(bp))
6239 bnx2x__common_init_phy(bp);
6240 } else
6241 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6242
6243 return 0;
6244 }
6245
6246 /**
6247 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6248 *
6249 * @bp: driver handle
6250 */
6251 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6252 {
6253 int rc = bnx2x_init_hw_common(bp);
6254
6255 if (rc)
6256 return rc;
6257
6258 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6259 if (!BP_NOMCP(bp))
6260 bnx2x__common_init_phy(bp);
6261
6262 return 0;
6263 }
6264
6265 static int bnx2x_init_hw_port(struct bnx2x *bp)
6266 {
6267 int port = BP_PORT(bp);
6268 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6269 u32 low, high;
6270 u32 val;
6271
6272 bnx2x__link_reset(bp);
6273
6274 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6275
6276 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6277
6278 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6279 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6280 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6281
6282 /* Timers bug workaround: disables the pf_master bit in pglue at
6283 * common phase, we need to enable it here before any dmae access are
6284 * attempted. Therefore we manually added the enable-master to the
6285 * port phase (it also happens in the function phase)
6286 */
6287 if (!CHIP_IS_E1x(bp))
6288 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6289
6290 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6291 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6292 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6293 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6294
6295 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6296 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6297 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6298 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6299
6300 /* QM cid (connection) count */
6301 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6302
6303 #ifdef BCM_CNIC
6304 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6305 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6306 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6307 #endif
6308
6309 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6310
6311 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6312 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6313
6314 if (IS_MF(bp))
6315 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6316 else if (bp->dev->mtu > 4096) {
6317 if (bp->flags & ONE_PORT_FLAG)
6318 low = 160;
6319 else {
6320 val = bp->dev->mtu;
6321 /* (24*1024 + val*4)/256 */
6322 low = 96 + (val/64) +
6323 ((val % 64) ? 1 : 0);
6324 }
6325 } else
6326 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6327 high = low + 56; /* 14*1024/256 */
6328 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6329 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6330 }
6331
6332 if (CHIP_MODE_IS_4_PORT(bp))
6333 REG_WR(bp, (BP_PORT(bp) ?
6334 BRB1_REG_MAC_GUARANTIED_1 :
6335 BRB1_REG_MAC_GUARANTIED_0), 40);
6336
6337
6338 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6339 if (CHIP_IS_E3B0(bp))
6340 /* Ovlan exists only if we are in multi-function +
6341 * switch-dependent mode, in switch-independent there
6342 * is no ovlan headers
6343 */
6344 REG_WR(bp, BP_PORT(bp) ?
6345 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6346 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6347 (bp->path_has_ovlan ? 7 : 6));
6348
6349 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6350 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6351 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6352 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6353
6354 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6355 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6356 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6357 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6358
6359 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6360 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6361
6362 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6363
6364 if (CHIP_IS_E1x(bp)) {
6365 /* configure PBF to work without PAUSE mtu 9000 */
6366 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6367
6368 /* update threshold */
6369 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6370 /* update init credit */
6371 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6372
6373 /* probe changes */
6374 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6375 udelay(50);
6376 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6377 }
6378
6379 #ifdef BCM_CNIC
6380 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6381 #endif
6382 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6383 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6384
6385 if (CHIP_IS_E1(bp)) {
6386 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6387 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6388 }
6389 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6390
6391 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6392
6393 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6394 /* init aeu_mask_attn_func_0/1:
6395 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6396 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6397 * bits 4-7 are used for "per vn group attention" */
6398 val = IS_MF(bp) ? 0xF7 : 0x7;
6399 /* Enable DCBX attention for all but E1 */
6400 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6401 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6402
6403 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6404
6405 if (!CHIP_IS_E1x(bp)) {
6406 /* Bit-map indicating which L2 hdrs may appear after the
6407 * basic Ethernet header
6408 */
6409 REG_WR(bp, BP_PORT(bp) ?
6410 NIG_REG_P1_HDRS_AFTER_BASIC :
6411 NIG_REG_P0_HDRS_AFTER_BASIC,
6412 IS_MF_SD(bp) ? 7 : 6);
6413
6414 if (CHIP_IS_E3(bp))
6415 REG_WR(bp, BP_PORT(bp) ?
6416 NIG_REG_LLH1_MF_MODE :
6417 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6418 }
6419 if (!CHIP_IS_E3(bp))
6420 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6421
6422 if (!CHIP_IS_E1(bp)) {
6423 /* 0x2 disable mf_ov, 0x1 enable */
6424 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6425 (IS_MF_SD(bp) ? 0x1 : 0x2));
6426
6427 if (!CHIP_IS_E1x(bp)) {
6428 val = 0;
6429 switch (bp->mf_mode) {
6430 case MULTI_FUNCTION_SD:
6431 val = 1;
6432 break;
6433 case MULTI_FUNCTION_SI:
6434 val = 2;
6435 break;
6436 }
6437
6438 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6439 NIG_REG_LLH0_CLS_TYPE), val);
6440 }
6441 {
6442 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6443 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6444 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6445 }
6446 }
6447
6448
6449 /* If SPIO5 is set to generate interrupts, enable it for this port */
6450 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6451 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6452 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6453 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6454 val = REG_RD(bp, reg_addr);
6455 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6456 REG_WR(bp, reg_addr, val);
6457 }
6458
6459 return 0;
6460 }
6461
6462 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6463 {
6464 int reg;
6465
6466 if (CHIP_IS_E1(bp))
6467 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6468 else
6469 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6470
6471 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6472 }
6473
6474 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6475 {
6476 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6477 }
6478
6479 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6480 {
6481 u32 i, base = FUNC_ILT_BASE(func);
6482 for (i = base; i < base + ILT_PER_FUNC; i++)
6483 bnx2x_ilt_wr(bp, i, 0);
6484 }
6485
6486 static int bnx2x_init_hw_func(struct bnx2x *bp)
6487 {
6488 int port = BP_PORT(bp);
6489 int func = BP_FUNC(bp);
6490 int init_phase = PHASE_PF0 + func;
6491 struct bnx2x_ilt *ilt = BP_ILT(bp);
6492 u16 cdu_ilt_start;
6493 u32 addr, val;
6494 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6495 int i, main_mem_width;
6496
6497 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6498
6499 /* FLR cleanup - hmmm */
6500 if (!CHIP_IS_E1x(bp))
6501 bnx2x_pf_flr_clnup(bp);
6502
6503 /* set MSI reconfigure capability */
6504 if (bp->common.int_block == INT_BLOCK_HC) {
6505 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6506 val = REG_RD(bp, addr);
6507 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6508 REG_WR(bp, addr, val);
6509 }
6510
6511 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6512 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6513
6514 ilt = BP_ILT(bp);
6515 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6516
6517 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6518 ilt->lines[cdu_ilt_start + i].page =
6519 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6520 ilt->lines[cdu_ilt_start + i].page_mapping =
6521 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6522 /* cdu ilt pages are allocated manually so there's no need to
6523 set the size */
6524 }
6525 bnx2x_ilt_init_op(bp, INITOP_SET);
6526
6527 #ifdef BCM_CNIC
6528 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6529
6530 /* T1 hash bits value determines the T1 number of entries */
6531 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6532 #endif
6533
6534 #ifndef BCM_CNIC
6535 /* set NIC mode */
6536 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6537 #endif /* BCM_CNIC */
6538
6539 if (!CHIP_IS_E1x(bp)) {
6540 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6541
6542 /* Turn on a single ISR mode in IGU if driver is going to use
6543 * INT#x or MSI
6544 */
6545 if (!(bp->flags & USING_MSIX_FLAG))
6546 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6547 /*
6548 * Timers workaround bug: function init part.
6549 * Need to wait 20msec after initializing ILT,
6550 * needed to make sure there are no requests in
6551 * one of the PXP internal queues with "old" ILT addresses
6552 */
6553 msleep(20);
6554 /*
6555 * Master enable - Due to WB DMAE writes performed before this
6556 * register is re-initialized as part of the regular function
6557 * init
6558 */
6559 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6560 /* Enable the function in IGU */
6561 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6562 }
6563
6564 bp->dmae_ready = 1;
6565
6566 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6567
6568 if (!CHIP_IS_E1x(bp))
6569 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6570
6571 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6572 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6573 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6574 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6575 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6576 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6577 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6578 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6579 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6580 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6581 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6582 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6583 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6584
6585 if (!CHIP_IS_E1x(bp))
6586 REG_WR(bp, QM_REG_PF_EN, 1);
6587
6588 if (!CHIP_IS_E1x(bp)) {
6589 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6590 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6591 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6592 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6593 }
6594 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6595
6596 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6597 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6598 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6599 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6600 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6601 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6602 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6603 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6604 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6605 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6606 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6607 if (!CHIP_IS_E1x(bp))
6608 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6609
6610 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6611
6612 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6613
6614 if (!CHIP_IS_E1x(bp))
6615 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6616
6617 if (IS_MF(bp)) {
6618 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6619 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6620 }
6621
6622 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6623
6624 /* HC init per function */
6625 if (bp->common.int_block == INT_BLOCK_HC) {
6626 if (CHIP_IS_E1H(bp)) {
6627 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6628
6629 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6630 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6631 }
6632 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6633
6634 } else {
6635 int num_segs, sb_idx, prod_offset;
6636
6637 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6638
6639 if (!CHIP_IS_E1x(bp)) {
6640 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6641 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6642 }
6643
6644 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6645
6646 if (!CHIP_IS_E1x(bp)) {
6647 int dsb_idx = 0;
6648 /**
6649 * Producer memory:
6650 * E2 mode: address 0-135 match to the mapping memory;
6651 * 136 - PF0 default prod; 137 - PF1 default prod;
6652 * 138 - PF2 default prod; 139 - PF3 default prod;
6653 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6654 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6655 * 144-147 reserved.
6656 *
6657 * E1.5 mode - In backward compatible mode;
6658 * for non default SB; each even line in the memory
6659 * holds the U producer and each odd line hold
6660 * the C producer. The first 128 producers are for
6661 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6662 * producers are for the DSB for each PF.
6663 * Each PF has five segments: (the order inside each
6664 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6665 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6666 * 144-147 attn prods;
6667 */
6668 /* non-default-status-blocks */
6669 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6670 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6671 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6672 prod_offset = (bp->igu_base_sb + sb_idx) *
6673 num_segs;
6674
6675 for (i = 0; i < num_segs; i++) {
6676 addr = IGU_REG_PROD_CONS_MEMORY +
6677 (prod_offset + i) * 4;
6678 REG_WR(bp, addr, 0);
6679 }
6680 /* send consumer update with value 0 */
6681 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6682 USTORM_ID, 0, IGU_INT_NOP, 1);
6683 bnx2x_igu_clear_sb(bp,
6684 bp->igu_base_sb + sb_idx);
6685 }
6686
6687 /* default-status-blocks */
6688 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6689 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6690
6691 if (CHIP_MODE_IS_4_PORT(bp))
6692 dsb_idx = BP_FUNC(bp);
6693 else
6694 dsb_idx = BP_VN(bp);
6695
6696 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6697 IGU_BC_BASE_DSB_PROD + dsb_idx :
6698 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6699
6700 /*
6701 * igu prods come in chunks of E1HVN_MAX (4) -
6702 * does not matters what is the current chip mode
6703 */
6704 for (i = 0; i < (num_segs * E1HVN_MAX);
6705 i += E1HVN_MAX) {
6706 addr = IGU_REG_PROD_CONS_MEMORY +
6707 (prod_offset + i)*4;
6708 REG_WR(bp, addr, 0);
6709 }
6710 /* send consumer update with 0 */
6711 if (CHIP_INT_MODE_IS_BC(bp)) {
6712 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6713 USTORM_ID, 0, IGU_INT_NOP, 1);
6714 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6715 CSTORM_ID, 0, IGU_INT_NOP, 1);
6716 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6717 XSTORM_ID, 0, IGU_INT_NOP, 1);
6718 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6719 TSTORM_ID, 0, IGU_INT_NOP, 1);
6720 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6721 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6722 } else {
6723 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6724 USTORM_ID, 0, IGU_INT_NOP, 1);
6725 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6726 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6727 }
6728 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6729
6730 /* !!! these should become driver const once
6731 rf-tool supports split-68 const */
6732 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6733 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6734 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6735 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6736 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6737 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6738 }
6739 }
6740
6741 /* Reset PCIE errors for debug */
6742 REG_WR(bp, 0x2114, 0xffffffff);
6743 REG_WR(bp, 0x2120, 0xffffffff);
6744
6745 if (CHIP_IS_E1x(bp)) {
6746 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6747 main_mem_base = HC_REG_MAIN_MEMORY +
6748 BP_PORT(bp) * (main_mem_size * 4);
6749 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6750 main_mem_width = 8;
6751
6752 val = REG_RD(bp, main_mem_prty_clr);
6753 if (val)
6754 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6755 "block during "
6756 "function init (0x%x)!\n", val);
6757
6758 /* Clear "false" parity errors in MSI-X table */
6759 for (i = main_mem_base;
6760 i < main_mem_base + main_mem_size * 4;
6761 i += main_mem_width) {
6762 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6763 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6764 i, main_mem_width / 4);
6765 }
6766 /* Clear HC parity attention */
6767 REG_RD(bp, main_mem_prty_clr);
6768 }
6769
6770 #ifdef BNX2X_STOP_ON_ERROR
6771 /* Enable STORMs SP logging */
6772 REG_WR8(bp, BAR_USTRORM_INTMEM +
6773 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6774 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6775 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6776 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6777 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6778 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6779 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6780 #endif
6781
6782 bnx2x_phy_probe(&bp->link_params);
6783
6784 return 0;
6785 }
6786
6787
6788 void bnx2x_free_mem(struct bnx2x *bp)
6789 {
6790 /* fastpath */
6791 bnx2x_free_fp_mem(bp);
6792 /* end of fastpath */
6793
6794 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6795 sizeof(struct host_sp_status_block));
6796
6797 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6798 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6799
6800 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6801 sizeof(struct bnx2x_slowpath));
6802
6803 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6804 bp->context.size);
6805
6806 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6807
6808 BNX2X_FREE(bp->ilt->lines);
6809
6810 #ifdef BCM_CNIC
6811 if (!CHIP_IS_E1x(bp))
6812 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6813 sizeof(struct host_hc_status_block_e2));
6814 else
6815 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6816 sizeof(struct host_hc_status_block_e1x));
6817
6818 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6819 #endif
6820
6821 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6822
6823 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6824 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6825 }
6826
6827 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6828 {
6829 int num_groups;
6830
6831 /* number of eth_queues */
6832 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6833
6834 /* Total number of FW statistics requests =
6835 * 1 for port stats + 1 for PF stats + num_eth_queues */
6836 bp->fw_stats_num = 2 + num_queue_stats;
6837
6838
6839 /* Request is built from stats_query_header and an array of
6840 * stats_query_cmd_group each of which contains
6841 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6842 * configured in the stats_query_header.
6843 */
6844 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6845 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6846
6847 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6848 num_groups * sizeof(struct stats_query_cmd_group);
6849
6850 /* Data for statistics requests + stats_conter
6851 *
6852 * stats_counter holds per-STORM counters that are incremented
6853 * when STORM has finished with the current request.
6854 */
6855 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6856 sizeof(struct per_pf_stats) +
6857 sizeof(struct per_queue_stats) * num_queue_stats +
6858 sizeof(struct stats_counter);
6859
6860 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6861 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6862
6863 /* Set shortcuts */
6864 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6865 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6866
6867 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6868 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6869
6870 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6871 bp->fw_stats_req_sz;
6872 return 0;
6873
6874 alloc_mem_err:
6875 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6876 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6877 return -ENOMEM;
6878 }
6879
6880
6881 int bnx2x_alloc_mem(struct bnx2x *bp)
6882 {
6883 #ifdef BCM_CNIC
6884 if (!CHIP_IS_E1x(bp))
6885 /* size = the status block + ramrod buffers */
6886 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6887 sizeof(struct host_hc_status_block_e2));
6888 else
6889 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6890 sizeof(struct host_hc_status_block_e1x));
6891
6892 /* allocate searcher T2 table */
6893 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6894 #endif
6895
6896
6897 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6898 sizeof(struct host_sp_status_block));
6899
6900 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6901 sizeof(struct bnx2x_slowpath));
6902
6903 /* Allocated memory for FW statistics */
6904 if (bnx2x_alloc_fw_stats_mem(bp))
6905 goto alloc_mem_err;
6906
6907 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6908
6909 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6910 bp->context.size);
6911
6912 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6913
6914 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6915 goto alloc_mem_err;
6916
6917 /* Slow path ring */
6918 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6919
6920 /* EQ */
6921 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6922 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6923
6924
6925 /* fastpath */
6926 /* need to be done at the end, since it's self adjusting to amount
6927 * of memory available for RSS queues
6928 */
6929 if (bnx2x_alloc_fp_mem(bp))
6930 goto alloc_mem_err;
6931 return 0;
6932
6933 alloc_mem_err:
6934 bnx2x_free_mem(bp);
6935 return -ENOMEM;
6936 }
6937
6938 /*
6939 * Init service functions
6940 */
6941
6942 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6943 struct bnx2x_vlan_mac_obj *obj, bool set,
6944 int mac_type, unsigned long *ramrod_flags)
6945 {
6946 int rc;
6947 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6948
6949 memset(&ramrod_param, 0, sizeof(ramrod_param));
6950
6951 /* Fill general parameters */
6952 ramrod_param.vlan_mac_obj = obj;
6953 ramrod_param.ramrod_flags = *ramrod_flags;
6954
6955 /* Fill a user request section if needed */
6956 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6957 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6958
6959 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6960
6961 /* Set the command: ADD or DEL */
6962 if (set)
6963 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6964 else
6965 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
6966 }
6967
6968 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
6969 if (rc < 0)
6970 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
6971 return rc;
6972 }
6973
6974 int bnx2x_del_all_macs(struct bnx2x *bp,
6975 struct bnx2x_vlan_mac_obj *mac_obj,
6976 int mac_type, bool wait_for_comp)
6977 {
6978 int rc;
6979 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
6980
6981 /* Wait for completion of requested */
6982 if (wait_for_comp)
6983 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6984
6985 /* Set the mac type of addresses we want to clear */
6986 __set_bit(mac_type, &vlan_mac_flags);
6987
6988 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
6989 if (rc < 0)
6990 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
6991
6992 return rc;
6993 }
6994
6995 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
6996 {
6997 unsigned long ramrod_flags = 0;
6998
6999 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7000
7001 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7002 /* Eth MAC is set on RSS leading client (fp[0]) */
7003 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7004 BNX2X_ETH_MAC, &ramrod_flags);
7005 }
7006
7007 int bnx2x_setup_leading(struct bnx2x *bp)
7008 {
7009 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7010 }
7011
7012 /**
7013 * bnx2x_set_int_mode - configure interrupt mode
7014 *
7015 * @bp: driver handle
7016 *
7017 * In case of MSI-X it will also try to enable MSI-X.
7018 */
7019 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7020 {
7021 switch (int_mode) {
7022 case INT_MODE_MSI:
7023 bnx2x_enable_msi(bp);
7024 /* falling through... */
7025 case INT_MODE_INTx:
7026 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7027 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7028 break;
7029 default:
7030 /* Set number of queues according to bp->multi_mode value */
7031 bnx2x_set_num_queues(bp);
7032
7033 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7034 bp->num_queues);
7035
7036 /* if we can't use MSI-X we only need one fp,
7037 * so try to enable MSI-X with the requested number of fp's
7038 * and fallback to MSI or legacy INTx with one fp
7039 */
7040 if (bnx2x_enable_msix(bp)) {
7041 /* failed to enable MSI-X */
7042 if (bp->multi_mode)
7043 DP(NETIF_MSG_IFUP,
7044 "Multi requested but failed to "
7045 "enable MSI-X (%d), "
7046 "set number of queues to %d\n",
7047 bp->num_queues,
7048 1 + NON_ETH_CONTEXT_USE);
7049 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7050
7051 /* Try to enable MSI */
7052 if (!(bp->flags & DISABLE_MSI_FLAG))
7053 bnx2x_enable_msi(bp);
7054 }
7055 break;
7056 }
7057 }
7058
7059 /* must be called prioir to any HW initializations */
7060 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7061 {
7062 return L2_ILT_LINES(bp);
7063 }
7064
7065 void bnx2x_ilt_set_info(struct bnx2x *bp)
7066 {
7067 struct ilt_client_info *ilt_client;
7068 struct bnx2x_ilt *ilt = BP_ILT(bp);
7069 u16 line = 0;
7070
7071 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7072 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7073
7074 /* CDU */
7075 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7076 ilt_client->client_num = ILT_CLIENT_CDU;
7077 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7078 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7079 ilt_client->start = line;
7080 line += bnx2x_cid_ilt_lines(bp);
7081 #ifdef BCM_CNIC
7082 line += CNIC_ILT_LINES;
7083 #endif
7084 ilt_client->end = line - 1;
7085
7086 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7087 "flags 0x%x, hw psz %d\n",
7088 ilt_client->start,
7089 ilt_client->end,
7090 ilt_client->page_size,
7091 ilt_client->flags,
7092 ilog2(ilt_client->page_size >> 12));
7093
7094 /* QM */
7095 if (QM_INIT(bp->qm_cid_count)) {
7096 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7097 ilt_client->client_num = ILT_CLIENT_QM;
7098 ilt_client->page_size = QM_ILT_PAGE_SZ;
7099 ilt_client->flags = 0;
7100 ilt_client->start = line;
7101
7102 /* 4 bytes for each cid */
7103 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7104 QM_ILT_PAGE_SZ);
7105
7106 ilt_client->end = line - 1;
7107
7108 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7109 "flags 0x%x, hw psz %d\n",
7110 ilt_client->start,
7111 ilt_client->end,
7112 ilt_client->page_size,
7113 ilt_client->flags,
7114 ilog2(ilt_client->page_size >> 12));
7115
7116 }
7117 /* SRC */
7118 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7119 #ifdef BCM_CNIC
7120 ilt_client->client_num = ILT_CLIENT_SRC;
7121 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7122 ilt_client->flags = 0;
7123 ilt_client->start = line;
7124 line += SRC_ILT_LINES;
7125 ilt_client->end = line - 1;
7126
7127 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7128 "flags 0x%x, hw psz %d\n",
7129 ilt_client->start,
7130 ilt_client->end,
7131 ilt_client->page_size,
7132 ilt_client->flags,
7133 ilog2(ilt_client->page_size >> 12));
7134
7135 #else
7136 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7137 #endif
7138
7139 /* TM */
7140 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7141 #ifdef BCM_CNIC
7142 ilt_client->client_num = ILT_CLIENT_TM;
7143 ilt_client->page_size = TM_ILT_PAGE_SZ;
7144 ilt_client->flags = 0;
7145 ilt_client->start = line;
7146 line += TM_ILT_LINES;
7147 ilt_client->end = line - 1;
7148
7149 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7150 "flags 0x%x, hw psz %d\n",
7151 ilt_client->start,
7152 ilt_client->end,
7153 ilt_client->page_size,
7154 ilt_client->flags,
7155 ilog2(ilt_client->page_size >> 12));
7156
7157 #else
7158 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7159 #endif
7160 BUG_ON(line > ILT_MAX_LINES);
7161 }
7162
7163 /**
7164 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7165 *
7166 * @bp: driver handle
7167 * @fp: pointer to fastpath
7168 * @init_params: pointer to parameters structure
7169 *
7170 * parameters configured:
7171 * - HC configuration
7172 * - Queue's CDU context
7173 */
7174 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7175 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7176 {
7177
7178 u8 cos;
7179 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7180 if (!IS_FCOE_FP(fp)) {
7181 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7182 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7183
7184 /* If HC is supporterd, enable host coalescing in the transition
7185 * to INIT state.
7186 */
7187 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7188 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7189
7190 /* HC rate */
7191 init_params->rx.hc_rate = bp->rx_ticks ?
7192 (1000000 / bp->rx_ticks) : 0;
7193 init_params->tx.hc_rate = bp->tx_ticks ?
7194 (1000000 / bp->tx_ticks) : 0;
7195
7196 /* FW SB ID */
7197 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7198 fp->fw_sb_id;
7199
7200 /*
7201 * CQ index among the SB indices: FCoE clients uses the default
7202 * SB, therefore it's different.
7203 */
7204 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7205 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7206 }
7207
7208 /* set maximum number of COSs supported by this queue */
7209 init_params->max_cos = fp->max_cos;
7210
7211 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7212 fp->index, init_params->max_cos);
7213
7214 /* set the context pointers queue object */
7215 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7216 init_params->cxts[cos] =
7217 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7218 }
7219
7220 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7221 struct bnx2x_queue_state_params *q_params,
7222 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7223 int tx_index, bool leading)
7224 {
7225 memset(tx_only_params, 0, sizeof(*tx_only_params));
7226
7227 /* Set the command */
7228 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7229
7230 /* Set tx-only QUEUE flags: don't zero statistics */
7231 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7232
7233 /* choose the index of the cid to send the slow path on */
7234 tx_only_params->cid_index = tx_index;
7235
7236 /* Set general TX_ONLY_SETUP parameters */
7237 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7238
7239 /* Set Tx TX_ONLY_SETUP parameters */
7240 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7241
7242 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7243 "cos %d, primary cid %d, cid %d, "
7244 "client id %d, sp-client id %d, flags %lx",
7245 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7246 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7247 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7248
7249 /* send the ramrod */
7250 return bnx2x_queue_state_change(bp, q_params);
7251 }
7252
7253
7254 /**
7255 * bnx2x_setup_queue - setup queue
7256 *
7257 * @bp: driver handle
7258 * @fp: pointer to fastpath
7259 * @leading: is leading
7260 *
7261 * This function performs 2 steps in a Queue state machine
7262 * actually: 1) RESET->INIT 2) INIT->SETUP
7263 */
7264
7265 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7266 bool leading)
7267 {
7268 struct bnx2x_queue_state_params q_params = {0};
7269 struct bnx2x_queue_setup_params *setup_params =
7270 &q_params.params.setup;
7271 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7272 &q_params.params.tx_only;
7273 int rc;
7274 u8 tx_index;
7275
7276 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
7277
7278 /* reset IGU state skip FCoE L2 queue */
7279 if (!IS_FCOE_FP(fp))
7280 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7281 IGU_INT_ENABLE, 0);
7282
7283 q_params.q_obj = &fp->q_obj;
7284 /* We want to wait for completion in this context */
7285 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7286
7287 /* Prepare the INIT parameters */
7288 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7289
7290 /* Set the command */
7291 q_params.cmd = BNX2X_Q_CMD_INIT;
7292
7293 /* Change the state to INIT */
7294 rc = bnx2x_queue_state_change(bp, &q_params);
7295 if (rc) {
7296 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7297 return rc;
7298 }
7299
7300 DP(BNX2X_MSG_SP, "init complete");
7301
7302
7303 /* Now move the Queue to the SETUP state... */
7304 memset(setup_params, 0, sizeof(*setup_params));
7305
7306 /* Set QUEUE flags */
7307 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7308
7309 /* Set general SETUP parameters */
7310 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7311 FIRST_TX_COS_INDEX);
7312
7313 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7314 &setup_params->rxq_params);
7315
7316 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7317 FIRST_TX_COS_INDEX);
7318
7319 /* Set the command */
7320 q_params.cmd = BNX2X_Q_CMD_SETUP;
7321
7322 /* Change the state to SETUP */
7323 rc = bnx2x_queue_state_change(bp, &q_params);
7324 if (rc) {
7325 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7326 return rc;
7327 }
7328
7329 /* loop through the relevant tx-only indices */
7330 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7331 tx_index < fp->max_cos;
7332 tx_index++) {
7333
7334 /* prepare and send tx-only ramrod*/
7335 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7336 tx_only_params, tx_index, leading);
7337 if (rc) {
7338 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7339 fp->index, tx_index);
7340 return rc;
7341 }
7342 }
7343
7344 return rc;
7345 }
7346
7347 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7348 {
7349 struct bnx2x_fastpath *fp = &bp->fp[index];
7350 struct bnx2x_fp_txdata *txdata;
7351 struct bnx2x_queue_state_params q_params = {0};
7352 int rc, tx_index;
7353
7354 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
7355
7356 q_params.q_obj = &fp->q_obj;
7357 /* We want to wait for completion in this context */
7358 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7359
7360
7361 /* close tx-only connections */
7362 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7363 tx_index < fp->max_cos;
7364 tx_index++){
7365
7366 /* ascertain this is a normal queue*/
7367 txdata = &fp->txdata[tx_index];
7368
7369 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7370 txdata->txq_index);
7371
7372 /* send halt terminate on tx-only connection */
7373 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7374 memset(&q_params.params.terminate, 0,
7375 sizeof(q_params.params.terminate));
7376 q_params.params.terminate.cid_index = tx_index;
7377
7378 rc = bnx2x_queue_state_change(bp, &q_params);
7379 if (rc)
7380 return rc;
7381
7382 /* send halt terminate on tx-only connection */
7383 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7384 memset(&q_params.params.cfc_del, 0,
7385 sizeof(q_params.params.cfc_del));
7386 q_params.params.cfc_del.cid_index = tx_index;
7387 rc = bnx2x_queue_state_change(bp, &q_params);
7388 if (rc)
7389 return rc;
7390 }
7391 /* Stop the primary connection: */
7392 /* ...halt the connection */
7393 q_params.cmd = BNX2X_Q_CMD_HALT;
7394 rc = bnx2x_queue_state_change(bp, &q_params);
7395 if (rc)
7396 return rc;
7397
7398 /* ...terminate the connection */
7399 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7400 memset(&q_params.params.terminate, 0,
7401 sizeof(q_params.params.terminate));
7402 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7403 rc = bnx2x_queue_state_change(bp, &q_params);
7404 if (rc)
7405 return rc;
7406 /* ...delete cfc entry */
7407 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7408 memset(&q_params.params.cfc_del, 0,
7409 sizeof(q_params.params.cfc_del));
7410 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7411 return bnx2x_queue_state_change(bp, &q_params);
7412 }
7413
7414
7415 static void bnx2x_reset_func(struct bnx2x *bp)
7416 {
7417 int port = BP_PORT(bp);
7418 int func = BP_FUNC(bp);
7419 int i;
7420
7421 /* Disable the function in the FW */
7422 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7423 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7424 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7425 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7426
7427 /* FP SBs */
7428 for_each_eth_queue(bp, i) {
7429 struct bnx2x_fastpath *fp = &bp->fp[i];
7430 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7431 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7432 SB_DISABLED);
7433 }
7434
7435 #ifdef BCM_CNIC
7436 /* CNIC SB */
7437 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7438 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7439 SB_DISABLED);
7440 #endif
7441 /* SP SB */
7442 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7443 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7444 SB_DISABLED);
7445
7446 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7447 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7448 0);
7449
7450 /* Configure IGU */
7451 if (bp->common.int_block == INT_BLOCK_HC) {
7452 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7453 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7454 } else {
7455 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7456 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7457 }
7458
7459 #ifdef BCM_CNIC
7460 /* Disable Timer scan */
7461 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7462 /*
7463 * Wait for at least 10ms and up to 2 second for the timers scan to
7464 * complete
7465 */
7466 for (i = 0; i < 200; i++) {
7467 msleep(10);
7468 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7469 break;
7470 }
7471 #endif
7472 /* Clear ILT */
7473 bnx2x_clear_func_ilt(bp, func);
7474
7475 /* Timers workaround bug for E2: if this is vnic-3,
7476 * we need to set the entire ilt range for this timers.
7477 */
7478 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7479 struct ilt_client_info ilt_cli;
7480 /* use dummy TM client */
7481 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7482 ilt_cli.start = 0;
7483 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7484 ilt_cli.client_num = ILT_CLIENT_TM;
7485
7486 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7487 }
7488
7489 /* this assumes that reset_port() called before reset_func()*/
7490 if (!CHIP_IS_E1x(bp))
7491 bnx2x_pf_disable(bp);
7492
7493 bp->dmae_ready = 0;
7494 }
7495
7496 static void bnx2x_reset_port(struct bnx2x *bp)
7497 {
7498 int port = BP_PORT(bp);
7499 u32 val;
7500
7501 /* Reset physical Link */
7502 bnx2x__link_reset(bp);
7503
7504 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7505
7506 /* Do not rcv packets to BRB */
7507 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7508 /* Do not direct rcv packets that are not for MCP to the BRB */
7509 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7510 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7511
7512 /* Configure AEU */
7513 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7514
7515 msleep(100);
7516 /* Check for BRB port occupancy */
7517 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7518 if (val)
7519 DP(NETIF_MSG_IFDOWN,
7520 "BRB1 is not empty %d blocks are occupied\n", val);
7521
7522 /* TODO: Close Doorbell port? */
7523 }
7524
7525 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7526 {
7527 struct bnx2x_func_state_params func_params = {0};
7528
7529 /* Prepare parameters for function state transitions */
7530 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7531
7532 func_params.f_obj = &bp->func_obj;
7533 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7534
7535 func_params.params.hw_init.load_phase = load_code;
7536
7537 return bnx2x_func_state_change(bp, &func_params);
7538 }
7539
7540 static inline int bnx2x_func_stop(struct bnx2x *bp)
7541 {
7542 struct bnx2x_func_state_params func_params = {0};
7543 int rc;
7544
7545 /* Prepare parameters for function state transitions */
7546 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7547 func_params.f_obj = &bp->func_obj;
7548 func_params.cmd = BNX2X_F_CMD_STOP;
7549
7550 /*
7551 * Try to stop the function the 'good way'. If fails (in case
7552 * of a parity error during bnx2x_chip_cleanup()) and we are
7553 * not in a debug mode, perform a state transaction in order to
7554 * enable further HW_RESET transaction.
7555 */
7556 rc = bnx2x_func_state_change(bp, &func_params);
7557 if (rc) {
7558 #ifdef BNX2X_STOP_ON_ERROR
7559 return rc;
7560 #else
7561 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7562 "transaction\n");
7563 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7564 return bnx2x_func_state_change(bp, &func_params);
7565 #endif
7566 }
7567
7568 return 0;
7569 }
7570
7571 /**
7572 * bnx2x_send_unload_req - request unload mode from the MCP.
7573 *
7574 * @bp: driver handle
7575 * @unload_mode: requested function's unload mode
7576 *
7577 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7578 */
7579 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7580 {
7581 u32 reset_code = 0;
7582 int port = BP_PORT(bp);
7583
7584 /* Select the UNLOAD request mode */
7585 if (unload_mode == UNLOAD_NORMAL)
7586 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7587
7588 else if (bp->flags & NO_WOL_FLAG)
7589 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7590
7591 else if (bp->wol) {
7592 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7593 u8 *mac_addr = bp->dev->dev_addr;
7594 u32 val;
7595 /* The mac address is written to entries 1-4 to
7596 preserve entry 0 which is used by the PMF */
7597 u8 entry = (BP_VN(bp) + 1)*8;
7598
7599 val = (mac_addr[0] << 8) | mac_addr[1];
7600 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7601
7602 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7603 (mac_addr[4] << 8) | mac_addr[5];
7604 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7605
7606 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7607
7608 } else
7609 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7610
7611 /* Send the request to the MCP */
7612 if (!BP_NOMCP(bp))
7613 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7614 else {
7615 int path = BP_PATH(bp);
7616
7617 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7618 "%d, %d, %d\n",
7619 path, load_count[path][0], load_count[path][1],
7620 load_count[path][2]);
7621 load_count[path][0]--;
7622 load_count[path][1 + port]--;
7623 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7624 "%d, %d, %d\n",
7625 path, load_count[path][0], load_count[path][1],
7626 load_count[path][2]);
7627 if (load_count[path][0] == 0)
7628 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7629 else if (load_count[path][1 + port] == 0)
7630 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7631 else
7632 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7633 }
7634
7635 return reset_code;
7636 }
7637
7638 /**
7639 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7640 *
7641 * @bp: driver handle
7642 */
7643 void bnx2x_send_unload_done(struct bnx2x *bp)
7644 {
7645 /* Report UNLOAD_DONE to MCP */
7646 if (!BP_NOMCP(bp))
7647 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7648 }
7649
7650 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7651 {
7652 int tout = 50;
7653 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7654
7655 if (!bp->port.pmf)
7656 return 0;
7657
7658 /*
7659 * (assumption: No Attention from MCP at this stage)
7660 * PMF probably in the middle of TXdisable/enable transaction
7661 * 1. Sync IRS for default SB
7662 * 2. Sync SP queue - this guarantes us that attention handling started
7663 * 3. Wait, that TXdisable/enable transaction completes
7664 *
7665 * 1+2 guranty that if DCBx attention was scheduled it already changed
7666 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7667 * received complettion for the transaction the state is TX_STOPPED.
7668 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7669 * transaction.
7670 */
7671
7672 /* make sure default SB ISR is done */
7673 if (msix)
7674 synchronize_irq(bp->msix_table[0].vector);
7675 else
7676 synchronize_irq(bp->pdev->irq);
7677
7678 flush_workqueue(bnx2x_wq);
7679
7680 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7681 BNX2X_F_STATE_STARTED && tout--)
7682 msleep(20);
7683
7684 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7685 BNX2X_F_STATE_STARTED) {
7686 #ifdef BNX2X_STOP_ON_ERROR
7687 return -EBUSY;
7688 #else
7689 /*
7690 * Failed to complete the transaction in a "good way"
7691 * Force both transactions with CLR bit
7692 */
7693 struct bnx2x_func_state_params func_params = {0};
7694
7695 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7696 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7697
7698 func_params.f_obj = &bp->func_obj;
7699 __set_bit(RAMROD_DRV_CLR_ONLY,
7700 &func_params.ramrod_flags);
7701
7702 /* STARTED-->TX_ST0PPED */
7703 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7704 bnx2x_func_state_change(bp, &func_params);
7705
7706 /* TX_ST0PPED-->STARTED */
7707 func_params.cmd = BNX2X_F_CMD_TX_START;
7708 return bnx2x_func_state_change(bp, &func_params);
7709 #endif
7710 }
7711
7712 return 0;
7713 }
7714
7715 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7716 {
7717 int port = BP_PORT(bp);
7718 int i, rc = 0;
7719 u8 cos;
7720 struct bnx2x_mcast_ramrod_params rparam = {0};
7721 u32 reset_code;
7722
7723 /* Wait until tx fastpath tasks complete */
7724 for_each_tx_queue(bp, i) {
7725 struct bnx2x_fastpath *fp = &bp->fp[i];
7726
7727 for_each_cos_in_tx_queue(fp, cos)
7728 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7729 #ifdef BNX2X_STOP_ON_ERROR
7730 if (rc)
7731 return;
7732 #endif
7733 }
7734
7735 /* Give HW time to discard old tx messages */
7736 usleep_range(1000, 1000);
7737
7738 /* Clean all ETH MACs */
7739 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7740 if (rc < 0)
7741 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7742
7743 /* Clean up UC list */
7744 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7745 true);
7746 if (rc < 0)
7747 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7748 "%d\n", rc);
7749
7750 /* Disable LLH */
7751 if (!CHIP_IS_E1(bp))
7752 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7753
7754 /* Set "drop all" (stop Rx).
7755 * We need to take a netif_addr_lock() here in order to prevent
7756 * a race between the completion code and this code.
7757 */
7758 netif_addr_lock_bh(bp->dev);
7759 /* Schedule the rx_mode command */
7760 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7761 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7762 else
7763 bnx2x_set_storm_rx_mode(bp);
7764
7765 /* Cleanup multicast configuration */
7766 rparam.mcast_obj = &bp->mcast_obj;
7767 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7768 if (rc < 0)
7769 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7770
7771 netif_addr_unlock_bh(bp->dev);
7772
7773
7774
7775 /*
7776 * Send the UNLOAD_REQUEST to the MCP. This will return if
7777 * this function should perform FUNC, PORT or COMMON HW
7778 * reset.
7779 */
7780 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7781
7782 /*
7783 * (assumption: No Attention from MCP at this stage)
7784 * PMF probably in the middle of TXdisable/enable transaction
7785 */
7786 rc = bnx2x_func_wait_started(bp);
7787 if (rc) {
7788 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7789 #ifdef BNX2X_STOP_ON_ERROR
7790 return;
7791 #endif
7792 }
7793
7794 /* Close multi and leading connections
7795 * Completions for ramrods are collected in a synchronous way
7796 */
7797 for_each_queue(bp, i)
7798 if (bnx2x_stop_queue(bp, i))
7799 #ifdef BNX2X_STOP_ON_ERROR
7800 return;
7801 #else
7802 goto unload_error;
7803 #endif
7804 /* If SP settings didn't get completed so far - something
7805 * very wrong has happen.
7806 */
7807 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7808 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7809
7810 #ifndef BNX2X_STOP_ON_ERROR
7811 unload_error:
7812 #endif
7813 rc = bnx2x_func_stop(bp);
7814 if (rc) {
7815 BNX2X_ERR("Function stop failed!\n");
7816 #ifdef BNX2X_STOP_ON_ERROR
7817 return;
7818 #endif
7819 }
7820
7821 /* Disable HW interrupts, NAPI */
7822 bnx2x_netif_stop(bp, 1);
7823
7824 /* Release IRQs */
7825 bnx2x_free_irq(bp);
7826
7827 /* Reset the chip */
7828 rc = bnx2x_reset_hw(bp, reset_code);
7829 if (rc)
7830 BNX2X_ERR("HW_RESET failed\n");
7831
7832
7833 /* Report UNLOAD_DONE to MCP */
7834 bnx2x_send_unload_done(bp);
7835 }
7836
7837 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7838 {
7839 u32 val;
7840
7841 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7842
7843 if (CHIP_IS_E1(bp)) {
7844 int port = BP_PORT(bp);
7845 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7846 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7847
7848 val = REG_RD(bp, addr);
7849 val &= ~(0x300);
7850 REG_WR(bp, addr, val);
7851 } else {
7852 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7853 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7854 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7855 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7856 }
7857 }
7858
7859 /* Close gates #2, #3 and #4: */
7860 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7861 {
7862 u32 val;
7863
7864 /* Gates #2 and #4a are closed/opened for "not E1" only */
7865 if (!CHIP_IS_E1(bp)) {
7866 /* #4 */
7867 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7868 /* #2 */
7869 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7870 }
7871
7872 /* #3 */
7873 if (CHIP_IS_E1x(bp)) {
7874 /* Prevent interrupts from HC on both ports */
7875 val = REG_RD(bp, HC_REG_CONFIG_1);
7876 REG_WR(bp, HC_REG_CONFIG_1,
7877 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7878 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7879
7880 val = REG_RD(bp, HC_REG_CONFIG_0);
7881 REG_WR(bp, HC_REG_CONFIG_0,
7882 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7883 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7884 } else {
7885 /* Prevent incomming interrupts in IGU */
7886 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7887
7888 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7889 (!close) ?
7890 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7891 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7892 }
7893
7894 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7895 close ? "closing" : "opening");
7896 mmiowb();
7897 }
7898
7899 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7900
7901 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7902 {
7903 /* Do some magic... */
7904 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7905 *magic_val = val & SHARED_MF_CLP_MAGIC;
7906 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7907 }
7908
7909 /**
7910 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7911 *
7912 * @bp: driver handle
7913 * @magic_val: old value of the `magic' bit.
7914 */
7915 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7916 {
7917 /* Restore the `magic' bit value... */
7918 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7919 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7920 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7921 }
7922
7923 /**
7924 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7925 *
7926 * @bp: driver handle
7927 * @magic_val: old value of 'magic' bit.
7928 *
7929 * Takes care of CLP configurations.
7930 */
7931 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7932 {
7933 u32 shmem;
7934 u32 validity_offset;
7935
7936 DP(NETIF_MSG_HW, "Starting\n");
7937
7938 /* Set `magic' bit in order to save MF config */
7939 if (!CHIP_IS_E1(bp))
7940 bnx2x_clp_reset_prep(bp, magic_val);
7941
7942 /* Get shmem offset */
7943 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7944 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7945
7946 /* Clear validity map flags */
7947 if (shmem > 0)
7948 REG_WR(bp, shmem + validity_offset, 0);
7949 }
7950
7951 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7952 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7953
7954 /**
7955 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7956 *
7957 * @bp: driver handle
7958 */
7959 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7960 {
7961 /* special handling for emulation and FPGA,
7962 wait 10 times longer */
7963 if (CHIP_REV_IS_SLOW(bp))
7964 msleep(MCP_ONE_TIMEOUT*10);
7965 else
7966 msleep(MCP_ONE_TIMEOUT);
7967 }
7968
7969 /*
7970 * initializes bp->common.shmem_base and waits for validity signature to appear
7971 */
7972 static int bnx2x_init_shmem(struct bnx2x *bp)
7973 {
7974 int cnt = 0;
7975 u32 val = 0;
7976
7977 do {
7978 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7979 if (bp->common.shmem_base) {
7980 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7981 if (val & SHR_MEM_VALIDITY_MB)
7982 return 0;
7983 }
7984
7985 bnx2x_mcp_wait_one(bp);
7986
7987 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7988
7989 BNX2X_ERR("BAD MCP validity signature\n");
7990
7991 return -ENODEV;
7992 }
7993
7994 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7995 {
7996 int rc = bnx2x_init_shmem(bp);
7997
7998 /* Restore the `magic' bit value */
7999 if (!CHIP_IS_E1(bp))
8000 bnx2x_clp_reset_done(bp, magic_val);
8001
8002 return rc;
8003 }
8004
8005 static void bnx2x_pxp_prep(struct bnx2x *bp)
8006 {
8007 if (!CHIP_IS_E1(bp)) {
8008 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8009 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8010 mmiowb();
8011 }
8012 }
8013
8014 /*
8015 * Reset the whole chip except for:
8016 * - PCIE core
8017 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8018 * one reset bit)
8019 * - IGU
8020 * - MISC (including AEU)
8021 * - GRC
8022 * - RBCN, RBCP
8023 */
8024 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8025 {
8026 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8027 u32 global_bits2, stay_reset2;
8028
8029 /*
8030 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8031 * (per chip) blocks.
8032 */
8033 global_bits2 =
8034 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8035 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8036
8037 /* Don't reset the following blocks */
8038 not_reset_mask1 =
8039 MISC_REGISTERS_RESET_REG_1_RST_HC |
8040 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8041 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8042
8043 not_reset_mask2 =
8044 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8045 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8046 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8047 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8048 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8049 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8050 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8051 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8052 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8053 MISC_REGISTERS_RESET_REG_2_PGLC;
8054
8055 /*
8056 * Keep the following blocks in reset:
8057 * - all xxMACs are handled by the bnx2x_link code.
8058 */
8059 stay_reset2 =
8060 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8061 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8062 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8063 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8064 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8065 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8066 MISC_REGISTERS_RESET_REG_2_XMAC |
8067 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8068
8069 /* Full reset masks according to the chip */
8070 reset_mask1 = 0xffffffff;
8071
8072 if (CHIP_IS_E1(bp))
8073 reset_mask2 = 0xffff;
8074 else if (CHIP_IS_E1H(bp))
8075 reset_mask2 = 0x1ffff;
8076 else if (CHIP_IS_E2(bp))
8077 reset_mask2 = 0xfffff;
8078 else /* CHIP_IS_E3 */
8079 reset_mask2 = 0x3ffffff;
8080
8081 /* Don't reset global blocks unless we need to */
8082 if (!global)
8083 reset_mask2 &= ~global_bits2;
8084
8085 /*
8086 * In case of attention in the QM, we need to reset PXP
8087 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8088 * because otherwise QM reset would release 'close the gates' shortly
8089 * before resetting the PXP, then the PSWRQ would send a write
8090 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8091 * read the payload data from PSWWR, but PSWWR would not
8092 * respond. The write queue in PGLUE would stuck, dmae commands
8093 * would not return. Therefore it's important to reset the second
8094 * reset register (containing the
8095 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8096 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8097 * bit).
8098 */
8099 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8100 reset_mask2 & (~not_reset_mask2));
8101
8102 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8103 reset_mask1 & (~not_reset_mask1));
8104
8105 barrier();
8106 mmiowb();
8107
8108 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8109 reset_mask2 & (~stay_reset2));
8110
8111 barrier();
8112 mmiowb();
8113
8114 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8115 mmiowb();
8116 }
8117
8118 /**
8119 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8120 * It should get cleared in no more than 1s.
8121 *
8122 * @bp: driver handle
8123 *
8124 * It should get cleared in no more than 1s. Returns 0 if
8125 * pending writes bit gets cleared.
8126 */
8127 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8128 {
8129 u32 cnt = 1000;
8130 u32 pend_bits = 0;
8131
8132 do {
8133 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8134
8135 if (pend_bits == 0)
8136 break;
8137
8138 usleep_range(1000, 1000);
8139 } while (cnt-- > 0);
8140
8141 if (cnt <= 0) {
8142 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8143 pend_bits);
8144 return -EBUSY;
8145 }
8146
8147 return 0;
8148 }
8149
8150 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8151 {
8152 int cnt = 1000;
8153 u32 val = 0;
8154 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8155
8156
8157 /* Empty the Tetris buffer, wait for 1s */
8158 do {
8159 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8160 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8161 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8162 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8163 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8164 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8165 ((port_is_idle_0 & 0x1) == 0x1) &&
8166 ((port_is_idle_1 & 0x1) == 0x1) &&
8167 (pgl_exp_rom2 == 0xffffffff))
8168 break;
8169 usleep_range(1000, 1000);
8170 } while (cnt-- > 0);
8171
8172 if (cnt <= 0) {
8173 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8174 " are still"
8175 " outstanding read requests after 1s!\n");
8176 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8177 " port_is_idle_0=0x%08x,"
8178 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8179 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8180 pgl_exp_rom2);
8181 return -EAGAIN;
8182 }
8183
8184 barrier();
8185
8186 /* Close gates #2, #3 and #4 */
8187 bnx2x_set_234_gates(bp, true);
8188
8189 /* Poll for IGU VQs for 57712 and newer chips */
8190 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8191 return -EAGAIN;
8192
8193
8194 /* TBD: Indicate that "process kill" is in progress to MCP */
8195
8196 /* Clear "unprepared" bit */
8197 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8198 barrier();
8199
8200 /* Make sure all is written to the chip before the reset */
8201 mmiowb();
8202
8203 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8204 * PSWHST, GRC and PSWRD Tetris buffer.
8205 */
8206 usleep_range(1000, 1000);
8207
8208 /* Prepare to chip reset: */
8209 /* MCP */
8210 if (global)
8211 bnx2x_reset_mcp_prep(bp, &val);
8212
8213 /* PXP */
8214 bnx2x_pxp_prep(bp);
8215 barrier();
8216
8217 /* reset the chip */
8218 bnx2x_process_kill_chip_reset(bp, global);
8219 barrier();
8220
8221 /* Recover after reset: */
8222 /* MCP */
8223 if (global && bnx2x_reset_mcp_comp(bp, val))
8224 return -EAGAIN;
8225
8226 /* TBD: Add resetting the NO_MCP mode DB here */
8227
8228 /* PXP */
8229 bnx2x_pxp_prep(bp);
8230
8231 /* Open the gates #2, #3 and #4 */
8232 bnx2x_set_234_gates(bp, false);
8233
8234 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8235 * reset state, re-enable attentions. */
8236
8237 return 0;
8238 }
8239
8240 int bnx2x_leader_reset(struct bnx2x *bp)
8241 {
8242 int rc = 0;
8243 bool global = bnx2x_reset_is_global(bp);
8244
8245 /* Try to recover after the failure */
8246 if (bnx2x_process_kill(bp, global)) {
8247 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8248 "Aii!\n", BP_PATH(bp));
8249 rc = -EAGAIN;
8250 goto exit_leader_reset;
8251 }
8252
8253 /*
8254 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8255 * state.
8256 */
8257 bnx2x_set_reset_done(bp);
8258 if (global)
8259 bnx2x_clear_reset_global(bp);
8260
8261 exit_leader_reset:
8262 bp->is_leader = 0;
8263 bnx2x_release_leader_lock(bp);
8264 smp_mb();
8265 return rc;
8266 }
8267
8268 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8269 {
8270 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8271
8272 /* Disconnect this device */
8273 netif_device_detach(bp->dev);
8274
8275 /*
8276 * Block ifup for all function on this engine until "process kill"
8277 * or power cycle.
8278 */
8279 bnx2x_set_reset_in_progress(bp);
8280
8281 /* Shut down the power */
8282 bnx2x_set_power_state(bp, PCI_D3hot);
8283
8284 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8285
8286 smp_mb();
8287 }
8288
8289 /*
8290 * Assumption: runs under rtnl lock. This together with the fact
8291 * that it's called only from bnx2x_sp_rtnl() ensure that it
8292 * will never be called when netif_running(bp->dev) is false.
8293 */
8294 static void bnx2x_parity_recover(struct bnx2x *bp)
8295 {
8296 bool global = false;
8297
8298 DP(NETIF_MSG_HW, "Handling parity\n");
8299 while (1) {
8300 switch (bp->recovery_state) {
8301 case BNX2X_RECOVERY_INIT:
8302 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8303 bnx2x_chk_parity_attn(bp, &global, false);
8304
8305 /* Try to get a LEADER_LOCK HW lock */
8306 if (bnx2x_trylock_leader_lock(bp)) {
8307 bnx2x_set_reset_in_progress(bp);
8308 /*
8309 * Check if there is a global attention and if
8310 * there was a global attention, set the global
8311 * reset bit.
8312 */
8313
8314 if (global)
8315 bnx2x_set_reset_global(bp);
8316
8317 bp->is_leader = 1;
8318 }
8319
8320 /* Stop the driver */
8321 /* If interface has been removed - break */
8322 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8323 return;
8324
8325 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8326
8327 /*
8328 * Reset MCP command sequence number and MCP mail box
8329 * sequence as we are going to reset the MCP.
8330 */
8331 if (global) {
8332 bp->fw_seq = 0;
8333 bp->fw_drv_pulse_wr_seq = 0;
8334 }
8335
8336 /* Ensure "is_leader", MCP command sequence and
8337 * "recovery_state" update values are seen on other
8338 * CPUs.
8339 */
8340 smp_mb();
8341 break;
8342
8343 case BNX2X_RECOVERY_WAIT:
8344 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8345 if (bp->is_leader) {
8346 int other_engine = BP_PATH(bp) ? 0 : 1;
8347 u32 other_load_counter =
8348 bnx2x_get_load_cnt(bp, other_engine);
8349 u32 load_counter =
8350 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8351 global = bnx2x_reset_is_global(bp);
8352
8353 /*
8354 * In case of a parity in a global block, let
8355 * the first leader that performs a
8356 * leader_reset() reset the global blocks in
8357 * order to clear global attentions. Otherwise
8358 * the the gates will remain closed for that
8359 * engine.
8360 */
8361 if (load_counter ||
8362 (global && other_load_counter)) {
8363 /* Wait until all other functions get
8364 * down.
8365 */
8366 schedule_delayed_work(&bp->sp_rtnl_task,
8367 HZ/10);
8368 return;
8369 } else {
8370 /* If all other functions got down -
8371 * try to bring the chip back to
8372 * normal. In any case it's an exit
8373 * point for a leader.
8374 */
8375 if (bnx2x_leader_reset(bp)) {
8376 bnx2x_recovery_failed(bp);
8377 return;
8378 }
8379
8380 /* If we are here, means that the
8381 * leader has succeeded and doesn't
8382 * want to be a leader any more. Try
8383 * to continue as a none-leader.
8384 */
8385 break;
8386 }
8387 } else { /* non-leader */
8388 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8389 /* Try to get a LEADER_LOCK HW lock as
8390 * long as a former leader may have
8391 * been unloaded by the user or
8392 * released a leadership by another
8393 * reason.
8394 */
8395 if (bnx2x_trylock_leader_lock(bp)) {
8396 /* I'm a leader now! Restart a
8397 * switch case.
8398 */
8399 bp->is_leader = 1;
8400 break;
8401 }
8402
8403 schedule_delayed_work(&bp->sp_rtnl_task,
8404 HZ/10);
8405 return;
8406
8407 } else {
8408 /*
8409 * If there was a global attention, wait
8410 * for it to be cleared.
8411 */
8412 if (bnx2x_reset_is_global(bp)) {
8413 schedule_delayed_work(
8414 &bp->sp_rtnl_task,
8415 HZ/10);
8416 return;
8417 }
8418
8419 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8420 bnx2x_recovery_failed(bp);
8421 else {
8422 bp->recovery_state =
8423 BNX2X_RECOVERY_DONE;
8424 smp_mb();
8425 }
8426
8427 return;
8428 }
8429 }
8430 default:
8431 return;
8432 }
8433 }
8434 }
8435
8436 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8437 * scheduled on a general queue in order to prevent a dead lock.
8438 */
8439 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8440 {
8441 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8442
8443 rtnl_lock();
8444
8445 if (!netif_running(bp->dev))
8446 goto sp_rtnl_exit;
8447
8448 /* if stop on error is defined no recovery flows should be executed */
8449 #ifdef BNX2X_STOP_ON_ERROR
8450 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8451 "so reset not done to allow debug dump,\n"
8452 "you will need to reboot when done\n");
8453 goto sp_rtnl_not_reset;
8454 #endif
8455
8456 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8457 /*
8458 * Clear all pending SP commands as we are going to reset the
8459 * function anyway.
8460 */
8461 bp->sp_rtnl_state = 0;
8462 smp_mb();
8463
8464 bnx2x_parity_recover(bp);
8465
8466 goto sp_rtnl_exit;
8467 }
8468
8469 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8470 /*
8471 * Clear all pending SP commands as we are going to reset the
8472 * function anyway.
8473 */
8474 bp->sp_rtnl_state = 0;
8475 smp_mb();
8476
8477 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8478 bnx2x_nic_load(bp, LOAD_NORMAL);
8479
8480 goto sp_rtnl_exit;
8481 }
8482 #ifdef BNX2X_STOP_ON_ERROR
8483 sp_rtnl_not_reset:
8484 #endif
8485 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8486 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8487
8488 sp_rtnl_exit:
8489 rtnl_unlock();
8490 }
8491
8492 /* end of nic load/unload */
8493
8494 static void bnx2x_period_task(struct work_struct *work)
8495 {
8496 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8497
8498 if (!netif_running(bp->dev))
8499 goto period_task_exit;
8500
8501 if (CHIP_REV_IS_SLOW(bp)) {
8502 BNX2X_ERR("period task called on emulation, ignoring\n");
8503 goto period_task_exit;
8504 }
8505
8506 bnx2x_acquire_phy_lock(bp);
8507 /*
8508 * The barrier is needed to ensure the ordering between the writing to
8509 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8510 * the reading here.
8511 */
8512 smp_mb();
8513 if (bp->port.pmf) {
8514 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8515
8516 /* Re-queue task in 1 sec */
8517 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8518 }
8519
8520 bnx2x_release_phy_lock(bp);
8521 period_task_exit:
8522 return;
8523 }
8524
8525 /*
8526 * Init service functions
8527 */
8528
8529 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8530 {
8531 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8532 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8533 return base + (BP_ABS_FUNC(bp)) * stride;
8534 }
8535
8536 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8537 {
8538 u32 reg = bnx2x_get_pretend_reg(bp);
8539
8540 /* Flush all outstanding writes */
8541 mmiowb();
8542
8543 /* Pretend to be function 0 */
8544 REG_WR(bp, reg, 0);
8545 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8546
8547 /* From now we are in the "like-E1" mode */
8548 bnx2x_int_disable(bp);
8549
8550 /* Flush all outstanding writes */
8551 mmiowb();
8552
8553 /* Restore the original function */
8554 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8555 REG_RD(bp, reg);
8556 }
8557
8558 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8559 {
8560 if (CHIP_IS_E1(bp))
8561 bnx2x_int_disable(bp);
8562 else
8563 bnx2x_undi_int_disable_e1h(bp);
8564 }
8565
8566 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8567 {
8568 u32 val;
8569
8570 /* Check if there is any driver already loaded */
8571 val = REG_RD(bp, MISC_REG_UNPREPARED);
8572 if (val == 0x1) {
8573 /* Check if it is the UNDI driver
8574 * UNDI driver initializes CID offset for normal bell to 0x7
8575 */
8576 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8577 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8578 if (val == 0x7) {
8579 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8580 /* save our pf_num */
8581 int orig_pf_num = bp->pf_num;
8582 int port;
8583 u32 swap_en, swap_val, value;
8584
8585 /* clear the UNDI indication */
8586 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8587
8588 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8589
8590 /* try unload UNDI on port 0 */
8591 bp->pf_num = 0;
8592 bp->fw_seq =
8593 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8594 DRV_MSG_SEQ_NUMBER_MASK);
8595 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8596
8597 /* if UNDI is loaded on the other port */
8598 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8599
8600 /* send "DONE" for previous unload */
8601 bnx2x_fw_command(bp,
8602 DRV_MSG_CODE_UNLOAD_DONE, 0);
8603
8604 /* unload UNDI on port 1 */
8605 bp->pf_num = 1;
8606 bp->fw_seq =
8607 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8608 DRV_MSG_SEQ_NUMBER_MASK);
8609 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8610
8611 bnx2x_fw_command(bp, reset_code, 0);
8612 }
8613
8614 /* now it's safe to release the lock */
8615 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8616
8617 bnx2x_undi_int_disable(bp);
8618 port = BP_PORT(bp);
8619
8620 /* close input traffic and wait for it */
8621 /* Do not rcv packets to BRB */
8622 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8623 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8624 /* Do not direct rcv packets that are not for MCP to
8625 * the BRB */
8626 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8627 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8628 /* clear AEU */
8629 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8630 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8631 msleep(10);
8632
8633 /* save NIG port swap info */
8634 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8635 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8636 /* reset device */
8637 REG_WR(bp,
8638 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8639 0xd3ffffff);
8640
8641 value = 0x1400;
8642 if (CHIP_IS_E3(bp)) {
8643 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8644 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8645 }
8646
8647 REG_WR(bp,
8648 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8649 value);
8650
8651 /* take the NIG out of reset and restore swap values */
8652 REG_WR(bp,
8653 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8654 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8655 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8656 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8657
8658 /* send unload done to the MCP */
8659 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8660
8661 /* restore our func and fw_seq */
8662 bp->pf_num = orig_pf_num;
8663 bp->fw_seq =
8664 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8665 DRV_MSG_SEQ_NUMBER_MASK);
8666 } else
8667 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
8668 }
8669 }
8670
8671 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8672 {
8673 u32 val, val2, val3, val4, id;
8674 u16 pmc;
8675
8676 /* Get the chip revision id and number. */
8677 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8678 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8679 id = ((val & 0xffff) << 16);
8680 val = REG_RD(bp, MISC_REG_CHIP_REV);
8681 id |= ((val & 0xf) << 12);
8682 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8683 id |= ((val & 0xff) << 4);
8684 val = REG_RD(bp, MISC_REG_BOND_ID);
8685 id |= (val & 0xf);
8686 bp->common.chip_id = id;
8687
8688 /* Set doorbell size */
8689 bp->db_size = (1 << BNX2X_DB_SHIFT);
8690
8691 if (!CHIP_IS_E1x(bp)) {
8692 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8693 if ((val & 1) == 0)
8694 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8695 else
8696 val = (val >> 1) & 1;
8697 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8698 "2_PORT_MODE");
8699 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8700 CHIP_2_PORT_MODE;
8701
8702 if (CHIP_MODE_IS_4_PORT(bp))
8703 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8704 else
8705 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8706 } else {
8707 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8708 bp->pfid = bp->pf_num; /* 0..7 */
8709 }
8710
8711 bp->link_params.chip_id = bp->common.chip_id;
8712 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8713
8714 val = (REG_RD(bp, 0x2874) & 0x55);
8715 if ((bp->common.chip_id & 0x1) ||
8716 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8717 bp->flags |= ONE_PORT_FLAG;
8718 BNX2X_DEV_INFO("single port device\n");
8719 }
8720
8721 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8722 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8723 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8724 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8725 bp->common.flash_size, bp->common.flash_size);
8726
8727 bnx2x_init_shmem(bp);
8728
8729
8730
8731 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8732 MISC_REG_GENERIC_CR_1 :
8733 MISC_REG_GENERIC_CR_0));
8734
8735 bp->link_params.shmem_base = bp->common.shmem_base;
8736 bp->link_params.shmem2_base = bp->common.shmem2_base;
8737 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8738 bp->common.shmem_base, bp->common.shmem2_base);
8739
8740 if (!bp->common.shmem_base) {
8741 BNX2X_DEV_INFO("MCP not active\n");
8742 bp->flags |= NO_MCP_FLAG;
8743 return;
8744 }
8745
8746 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8747 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8748
8749 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8750 SHARED_HW_CFG_LED_MODE_MASK) >>
8751 SHARED_HW_CFG_LED_MODE_SHIFT);
8752
8753 bp->link_params.feature_config_flags = 0;
8754 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8755 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8756 bp->link_params.feature_config_flags |=
8757 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8758 else
8759 bp->link_params.feature_config_flags &=
8760 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8761
8762 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8763 bp->common.bc_ver = val;
8764 BNX2X_DEV_INFO("bc_ver %X\n", val);
8765 if (val < BNX2X_BC_VER) {
8766 /* for now only warn
8767 * later we might need to enforce this */
8768 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8769 "please upgrade BC\n", BNX2X_BC_VER, val);
8770 }
8771 bp->link_params.feature_config_flags |=
8772 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8773 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8774
8775 bp->link_params.feature_config_flags |=
8776 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8777 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8778
8779 bp->link_params.feature_config_flags |=
8780 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8781 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8782
8783 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8784 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8785
8786 BNX2X_DEV_INFO("%sWoL capable\n",
8787 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8788
8789 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8790 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8791 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8792 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8793
8794 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8795 val, val2, val3, val4);
8796 }
8797
8798 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8799 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8800
8801 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8802 {
8803 int pfid = BP_FUNC(bp);
8804 int igu_sb_id;
8805 u32 val;
8806 u8 fid, igu_sb_cnt = 0;
8807
8808 bp->igu_base_sb = 0xff;
8809 if (CHIP_INT_MODE_IS_BC(bp)) {
8810 int vn = BP_VN(bp);
8811 igu_sb_cnt = bp->igu_sb_cnt;
8812 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8813 FP_SB_MAX_E1x;
8814
8815 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8816 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8817
8818 return;
8819 }
8820
8821 /* IGU in normal mode - read CAM */
8822 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8823 igu_sb_id++) {
8824 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8825 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8826 continue;
8827 fid = IGU_FID(val);
8828 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8829 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8830 continue;
8831 if (IGU_VEC(val) == 0)
8832 /* default status block */
8833 bp->igu_dsb_id = igu_sb_id;
8834 else {
8835 if (bp->igu_base_sb == 0xff)
8836 bp->igu_base_sb = igu_sb_id;
8837 igu_sb_cnt++;
8838 }
8839 }
8840 }
8841
8842 #ifdef CONFIG_PCI_MSI
8843 /*
8844 * It's expected that number of CAM entries for this functions is equal
8845 * to the number evaluated based on the MSI-X table size. We want a
8846 * harsh warning if these values are different!
8847 */
8848 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8849 #endif
8850
8851 if (igu_sb_cnt == 0)
8852 BNX2X_ERR("CAM configuration error\n");
8853 }
8854
8855 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8856 u32 switch_cfg)
8857 {
8858 int cfg_size = 0, idx, port = BP_PORT(bp);
8859
8860 /* Aggregation of supported attributes of all external phys */
8861 bp->port.supported[0] = 0;
8862 bp->port.supported[1] = 0;
8863 switch (bp->link_params.num_phys) {
8864 case 1:
8865 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8866 cfg_size = 1;
8867 break;
8868 case 2:
8869 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8870 cfg_size = 1;
8871 break;
8872 case 3:
8873 if (bp->link_params.multi_phy_config &
8874 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8875 bp->port.supported[1] =
8876 bp->link_params.phy[EXT_PHY1].supported;
8877 bp->port.supported[0] =
8878 bp->link_params.phy[EXT_PHY2].supported;
8879 } else {
8880 bp->port.supported[0] =
8881 bp->link_params.phy[EXT_PHY1].supported;
8882 bp->port.supported[1] =
8883 bp->link_params.phy[EXT_PHY2].supported;
8884 }
8885 cfg_size = 2;
8886 break;
8887 }
8888
8889 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8890 BNX2X_ERR("NVRAM config error. BAD phy config."
8891 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8892 SHMEM_RD(bp,
8893 dev_info.port_hw_config[port].external_phy_config),
8894 SHMEM_RD(bp,
8895 dev_info.port_hw_config[port].external_phy_config2));
8896 return;
8897 }
8898
8899 if (CHIP_IS_E3(bp))
8900 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8901 else {
8902 switch (switch_cfg) {
8903 case SWITCH_CFG_1G:
8904 bp->port.phy_addr = REG_RD(
8905 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8906 break;
8907 case SWITCH_CFG_10G:
8908 bp->port.phy_addr = REG_RD(
8909 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8910 break;
8911 default:
8912 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8913 bp->port.link_config[0]);
8914 return;
8915 }
8916 }
8917 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8918 /* mask what we support according to speed_cap_mask per configuration */
8919 for (idx = 0; idx < cfg_size; idx++) {
8920 if (!(bp->link_params.speed_cap_mask[idx] &
8921 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8922 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8923
8924 if (!(bp->link_params.speed_cap_mask[idx] &
8925 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8926 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8927
8928 if (!(bp->link_params.speed_cap_mask[idx] &
8929 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8930 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8931
8932 if (!(bp->link_params.speed_cap_mask[idx] &
8933 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8934 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8935
8936 if (!(bp->link_params.speed_cap_mask[idx] &
8937 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8938 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8939 SUPPORTED_1000baseT_Full);
8940
8941 if (!(bp->link_params.speed_cap_mask[idx] &
8942 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8943 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8944
8945 if (!(bp->link_params.speed_cap_mask[idx] &
8946 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8947 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8948
8949 }
8950
8951 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8952 bp->port.supported[1]);
8953 }
8954
8955 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8956 {
8957 u32 link_config, idx, cfg_size = 0;
8958 bp->port.advertising[0] = 0;
8959 bp->port.advertising[1] = 0;
8960 switch (bp->link_params.num_phys) {
8961 case 1:
8962 case 2:
8963 cfg_size = 1;
8964 break;
8965 case 3:
8966 cfg_size = 2;
8967 break;
8968 }
8969 for (idx = 0; idx < cfg_size; idx++) {
8970 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8971 link_config = bp->port.link_config[idx];
8972 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8973 case PORT_FEATURE_LINK_SPEED_AUTO:
8974 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8975 bp->link_params.req_line_speed[idx] =
8976 SPEED_AUTO_NEG;
8977 bp->port.advertising[idx] |=
8978 bp->port.supported[idx];
8979 } else {
8980 /* force 10G, no AN */
8981 bp->link_params.req_line_speed[idx] =
8982 SPEED_10000;
8983 bp->port.advertising[idx] |=
8984 (ADVERTISED_10000baseT_Full |
8985 ADVERTISED_FIBRE);
8986 continue;
8987 }
8988 break;
8989
8990 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8991 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8992 bp->link_params.req_line_speed[idx] =
8993 SPEED_10;
8994 bp->port.advertising[idx] |=
8995 (ADVERTISED_10baseT_Full |
8996 ADVERTISED_TP);
8997 } else {
8998 BNX2X_ERR("NVRAM config error. "
8999 "Invalid link_config 0x%x"
9000 " speed_cap_mask 0x%x\n",
9001 link_config,
9002 bp->link_params.speed_cap_mask[idx]);
9003 return;
9004 }
9005 break;
9006
9007 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9008 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9009 bp->link_params.req_line_speed[idx] =
9010 SPEED_10;
9011 bp->link_params.req_duplex[idx] =
9012 DUPLEX_HALF;
9013 bp->port.advertising[idx] |=
9014 (ADVERTISED_10baseT_Half |
9015 ADVERTISED_TP);
9016 } else {
9017 BNX2X_ERR("NVRAM config error. "
9018 "Invalid link_config 0x%x"
9019 " speed_cap_mask 0x%x\n",
9020 link_config,
9021 bp->link_params.speed_cap_mask[idx]);
9022 return;
9023 }
9024 break;
9025
9026 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9027 if (bp->port.supported[idx] &
9028 SUPPORTED_100baseT_Full) {
9029 bp->link_params.req_line_speed[idx] =
9030 SPEED_100;
9031 bp->port.advertising[idx] |=
9032 (ADVERTISED_100baseT_Full |
9033 ADVERTISED_TP);
9034 } else {
9035 BNX2X_ERR("NVRAM config error. "
9036 "Invalid link_config 0x%x"
9037 " speed_cap_mask 0x%x\n",
9038 link_config,
9039 bp->link_params.speed_cap_mask[idx]);
9040 return;
9041 }
9042 break;
9043
9044 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9045 if (bp->port.supported[idx] &
9046 SUPPORTED_100baseT_Half) {
9047 bp->link_params.req_line_speed[idx] =
9048 SPEED_100;
9049 bp->link_params.req_duplex[idx] =
9050 DUPLEX_HALF;
9051 bp->port.advertising[idx] |=
9052 (ADVERTISED_100baseT_Half |
9053 ADVERTISED_TP);
9054 } else {
9055 BNX2X_ERR("NVRAM config error. "
9056 "Invalid link_config 0x%x"
9057 " speed_cap_mask 0x%x\n",
9058 link_config,
9059 bp->link_params.speed_cap_mask[idx]);
9060 return;
9061 }
9062 break;
9063
9064 case PORT_FEATURE_LINK_SPEED_1G:
9065 if (bp->port.supported[idx] &
9066 SUPPORTED_1000baseT_Full) {
9067 bp->link_params.req_line_speed[idx] =
9068 SPEED_1000;
9069 bp->port.advertising[idx] |=
9070 (ADVERTISED_1000baseT_Full |
9071 ADVERTISED_TP);
9072 } else {
9073 BNX2X_ERR("NVRAM config error. "
9074 "Invalid link_config 0x%x"
9075 " speed_cap_mask 0x%x\n",
9076 link_config,
9077 bp->link_params.speed_cap_mask[idx]);
9078 return;
9079 }
9080 break;
9081
9082 case PORT_FEATURE_LINK_SPEED_2_5G:
9083 if (bp->port.supported[idx] &
9084 SUPPORTED_2500baseX_Full) {
9085 bp->link_params.req_line_speed[idx] =
9086 SPEED_2500;
9087 bp->port.advertising[idx] |=
9088 (ADVERTISED_2500baseX_Full |
9089 ADVERTISED_TP);
9090 } else {
9091 BNX2X_ERR("NVRAM config error. "
9092 "Invalid link_config 0x%x"
9093 " speed_cap_mask 0x%x\n",
9094 link_config,
9095 bp->link_params.speed_cap_mask[idx]);
9096 return;
9097 }
9098 break;
9099
9100 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9101 if (bp->port.supported[idx] &
9102 SUPPORTED_10000baseT_Full) {
9103 bp->link_params.req_line_speed[idx] =
9104 SPEED_10000;
9105 bp->port.advertising[idx] |=
9106 (ADVERTISED_10000baseT_Full |
9107 ADVERTISED_FIBRE);
9108 } else {
9109 BNX2X_ERR("NVRAM config error. "
9110 "Invalid link_config 0x%x"
9111 " speed_cap_mask 0x%x\n",
9112 link_config,
9113 bp->link_params.speed_cap_mask[idx]);
9114 return;
9115 }
9116 break;
9117 case PORT_FEATURE_LINK_SPEED_20G:
9118 bp->link_params.req_line_speed[idx] = SPEED_20000;
9119
9120 break;
9121 default:
9122 BNX2X_ERR("NVRAM config error. "
9123 "BAD link speed link_config 0x%x\n",
9124 link_config);
9125 bp->link_params.req_line_speed[idx] =
9126 SPEED_AUTO_NEG;
9127 bp->port.advertising[idx] =
9128 bp->port.supported[idx];
9129 break;
9130 }
9131
9132 bp->link_params.req_flow_ctrl[idx] = (link_config &
9133 PORT_FEATURE_FLOW_CONTROL_MASK);
9134 if ((bp->link_params.req_flow_ctrl[idx] ==
9135 BNX2X_FLOW_CTRL_AUTO) &&
9136 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9137 bp->link_params.req_flow_ctrl[idx] =
9138 BNX2X_FLOW_CTRL_NONE;
9139 }
9140
9141 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9142 " 0x%x advertising 0x%x\n",
9143 bp->link_params.req_line_speed[idx],
9144 bp->link_params.req_duplex[idx],
9145 bp->link_params.req_flow_ctrl[idx],
9146 bp->port.advertising[idx]);
9147 }
9148 }
9149
9150 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9151 {
9152 mac_hi = cpu_to_be16(mac_hi);
9153 mac_lo = cpu_to_be32(mac_lo);
9154 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9155 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9156 }
9157
9158 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9159 {
9160 int port = BP_PORT(bp);
9161 u32 config;
9162 u32 ext_phy_type, ext_phy_config;
9163
9164 bp->link_params.bp = bp;
9165 bp->link_params.port = port;
9166
9167 bp->link_params.lane_config =
9168 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9169
9170 bp->link_params.speed_cap_mask[0] =
9171 SHMEM_RD(bp,
9172 dev_info.port_hw_config[port].speed_capability_mask);
9173 bp->link_params.speed_cap_mask[1] =
9174 SHMEM_RD(bp,
9175 dev_info.port_hw_config[port].speed_capability_mask2);
9176 bp->port.link_config[0] =
9177 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9178
9179 bp->port.link_config[1] =
9180 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9181
9182 bp->link_params.multi_phy_config =
9183 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9184 /* If the device is capable of WoL, set the default state according
9185 * to the HW
9186 */
9187 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9188 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9189 (config & PORT_FEATURE_WOL_ENABLED));
9190
9191 BNX2X_DEV_INFO("lane_config 0x%08x "
9192 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9193 bp->link_params.lane_config,
9194 bp->link_params.speed_cap_mask[0],
9195 bp->port.link_config[0]);
9196
9197 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9198 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9199 bnx2x_phy_probe(&bp->link_params);
9200 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9201
9202 bnx2x_link_settings_requested(bp);
9203
9204 /*
9205 * If connected directly, work with the internal PHY, otherwise, work
9206 * with the external PHY
9207 */
9208 ext_phy_config =
9209 SHMEM_RD(bp,
9210 dev_info.port_hw_config[port].external_phy_config);
9211 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9212 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9213 bp->mdio.prtad = bp->port.phy_addr;
9214
9215 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9216 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9217 bp->mdio.prtad =
9218 XGXS_EXT_PHY_ADDR(ext_phy_config);
9219
9220 /*
9221 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9222 * In MF mode, it is set to cover self test cases
9223 */
9224 if (IS_MF(bp))
9225 bp->port.need_hw_lock = 1;
9226 else
9227 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9228 bp->common.shmem_base,
9229 bp->common.shmem2_base);
9230 }
9231
9232 #ifdef BCM_CNIC
9233 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9234 {
9235 int port = BP_PORT(bp);
9236 int func = BP_ABS_FUNC(bp);
9237
9238 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9239 drv_lic_key[port].max_iscsi_conn);
9240 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9241 drv_lic_key[port].max_fcoe_conn);
9242
9243 /* Get the number of maximum allowed iSCSI and FCoE connections */
9244 bp->cnic_eth_dev.max_iscsi_conn =
9245 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9246 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9247
9248 bp->cnic_eth_dev.max_fcoe_conn =
9249 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9250 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9251
9252 /* Read the WWN: */
9253 if (!IS_MF(bp)) {
9254 /* Port info */
9255 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9256 SHMEM_RD(bp,
9257 dev_info.port_hw_config[port].
9258 fcoe_wwn_port_name_upper);
9259 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9260 SHMEM_RD(bp,
9261 dev_info.port_hw_config[port].
9262 fcoe_wwn_port_name_lower);
9263
9264 /* Node info */
9265 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9266 SHMEM_RD(bp,
9267 dev_info.port_hw_config[port].
9268 fcoe_wwn_node_name_upper);
9269 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9270 SHMEM_RD(bp,
9271 dev_info.port_hw_config[port].
9272 fcoe_wwn_node_name_lower);
9273 } else if (!IS_MF_SD(bp)) {
9274 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9275
9276 /*
9277 * Read the WWN info only if the FCoE feature is enabled for
9278 * this function.
9279 */
9280 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9281 /* Port info */
9282 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9283 MF_CFG_RD(bp, func_ext_config[func].
9284 fcoe_wwn_port_name_upper);
9285 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9286 MF_CFG_RD(bp, func_ext_config[func].
9287 fcoe_wwn_port_name_lower);
9288
9289 /* Node info */
9290 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9291 MF_CFG_RD(bp, func_ext_config[func].
9292 fcoe_wwn_node_name_upper);
9293 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9294 MF_CFG_RD(bp, func_ext_config[func].
9295 fcoe_wwn_node_name_lower);
9296 }
9297 }
9298
9299 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9300 bp->cnic_eth_dev.max_iscsi_conn,
9301 bp->cnic_eth_dev.max_fcoe_conn);
9302
9303 /*
9304 * If maximum allowed number of connections is zero -
9305 * disable the feature.
9306 */
9307 if (!bp->cnic_eth_dev.max_iscsi_conn)
9308 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9309
9310 if (!bp->cnic_eth_dev.max_fcoe_conn)
9311 bp->flags |= NO_FCOE_FLAG;
9312 }
9313 #endif
9314
9315 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9316 {
9317 u32 val, val2;
9318 int func = BP_ABS_FUNC(bp);
9319 int port = BP_PORT(bp);
9320 #ifdef BCM_CNIC
9321 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9322 u8 *fip_mac = bp->fip_mac;
9323 #endif
9324
9325 /* Zero primary MAC configuration */
9326 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9327
9328 if (BP_NOMCP(bp)) {
9329 BNX2X_ERROR("warning: random MAC workaround active\n");
9330 random_ether_addr(bp->dev->dev_addr);
9331 } else if (IS_MF(bp)) {
9332 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9333 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9334 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9335 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9336 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9337
9338 #ifdef BCM_CNIC
9339 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9340 * FCoE MAC then the appropriate feature should be disabled.
9341 */
9342 if (IS_MF_SI(bp)) {
9343 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9344 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9345 val2 = MF_CFG_RD(bp, func_ext_config[func].
9346 iscsi_mac_addr_upper);
9347 val = MF_CFG_RD(bp, func_ext_config[func].
9348 iscsi_mac_addr_lower);
9349 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9350 BNX2X_DEV_INFO("Read iSCSI MAC: "
9351 BNX2X_MAC_FMT"\n",
9352 BNX2X_MAC_PRN_LIST(iscsi_mac));
9353 } else
9354 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9355
9356 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9357 val2 = MF_CFG_RD(bp, func_ext_config[func].
9358 fcoe_mac_addr_upper);
9359 val = MF_CFG_RD(bp, func_ext_config[func].
9360 fcoe_mac_addr_lower);
9361 bnx2x_set_mac_buf(fip_mac, val, val2);
9362 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9363 BNX2X_MAC_FMT"\n",
9364 BNX2X_MAC_PRN_LIST(fip_mac));
9365
9366 } else
9367 bp->flags |= NO_FCOE_FLAG;
9368 }
9369 #endif
9370 } else {
9371 /* in SF read MACs from port configuration */
9372 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9373 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9374 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9375
9376 #ifdef BCM_CNIC
9377 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9378 iscsi_mac_upper);
9379 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9380 iscsi_mac_lower);
9381 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9382
9383 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9384 fcoe_fip_mac_upper);
9385 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9386 fcoe_fip_mac_lower);
9387 bnx2x_set_mac_buf(fip_mac, val, val2);
9388 #endif
9389 }
9390
9391 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9392 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9393
9394 #ifdef BCM_CNIC
9395 /* Set the FCoE MAC in MF_SD mode */
9396 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9397 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9398
9399 /* Disable iSCSI if MAC configuration is
9400 * invalid.
9401 */
9402 if (!is_valid_ether_addr(iscsi_mac)) {
9403 bp->flags |= NO_ISCSI_FLAG;
9404 memset(iscsi_mac, 0, ETH_ALEN);
9405 }
9406
9407 /* Disable FCoE if MAC configuration is
9408 * invalid.
9409 */
9410 if (!is_valid_ether_addr(fip_mac)) {
9411 bp->flags |= NO_FCOE_FLAG;
9412 memset(bp->fip_mac, 0, ETH_ALEN);
9413 }
9414 #endif
9415
9416 if (!is_valid_ether_addr(bp->dev->dev_addr))
9417 dev_err(&bp->pdev->dev,
9418 "bad Ethernet MAC address configuration: "
9419 BNX2X_MAC_FMT", change it manually before bringing up "
9420 "the appropriate network interface\n",
9421 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
9422 }
9423
9424 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9425 {
9426 int /*abs*/func = BP_ABS_FUNC(bp);
9427 int vn;
9428 u32 val = 0;
9429 int rc = 0;
9430
9431 bnx2x_get_common_hwinfo(bp);
9432
9433 /*
9434 * initialize IGU parameters
9435 */
9436 if (CHIP_IS_E1x(bp)) {
9437 bp->common.int_block = INT_BLOCK_HC;
9438
9439 bp->igu_dsb_id = DEF_SB_IGU_ID;
9440 bp->igu_base_sb = 0;
9441 } else {
9442 bp->common.int_block = INT_BLOCK_IGU;
9443 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9444
9445 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9446 int tout = 5000;
9447
9448 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9449
9450 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9451 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9452 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9453
9454 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9455 tout--;
9456 usleep_range(1000, 1000);
9457 }
9458
9459 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9460 dev_err(&bp->pdev->dev,
9461 "FORCING Normal Mode failed!!!\n");
9462 return -EPERM;
9463 }
9464 }
9465
9466 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9467 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9468 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9469 } else
9470 BNX2X_DEV_INFO("IGU Normal Mode\n");
9471
9472 bnx2x_get_igu_cam_info(bp);
9473
9474 }
9475
9476 /*
9477 * set base FW non-default (fast path) status block id, this value is
9478 * used to initialize the fw_sb_id saved on the fp/queue structure to
9479 * determine the id used by the FW.
9480 */
9481 if (CHIP_IS_E1x(bp))
9482 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9483 else /*
9484 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9485 * the same queue are indicated on the same IGU SB). So we prefer
9486 * FW and IGU SBs to be the same value.
9487 */
9488 bp->base_fw_ndsb = bp->igu_base_sb;
9489
9490 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9491 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9492 bp->igu_sb_cnt, bp->base_fw_ndsb);
9493
9494 /*
9495 * Initialize MF configuration
9496 */
9497
9498 bp->mf_ov = 0;
9499 bp->mf_mode = 0;
9500 vn = BP_VN(bp);
9501
9502 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9503 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9504 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9505 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9506
9507 if (SHMEM2_HAS(bp, mf_cfg_addr))
9508 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9509 else
9510 bp->common.mf_cfg_base = bp->common.shmem_base +
9511 offsetof(struct shmem_region, func_mb) +
9512 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9513 /*
9514 * get mf configuration:
9515 * 1. existence of MF configuration
9516 * 2. MAC address must be legal (check only upper bytes)
9517 * for Switch-Independent mode;
9518 * OVLAN must be legal for Switch-Dependent mode
9519 * 3. SF_MODE configures specific MF mode
9520 */
9521 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9522 /* get mf configuration */
9523 val = SHMEM_RD(bp,
9524 dev_info.shared_feature_config.config);
9525 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9526
9527 switch (val) {
9528 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9529 val = MF_CFG_RD(bp, func_mf_config[func].
9530 mac_upper);
9531 /* check for legal mac (upper bytes)*/
9532 if (val != 0xffff) {
9533 bp->mf_mode = MULTI_FUNCTION_SI;
9534 bp->mf_config[vn] = MF_CFG_RD(bp,
9535 func_mf_config[func].config);
9536 } else
9537 BNX2X_DEV_INFO("illegal MAC address "
9538 "for SI\n");
9539 break;
9540 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9541 /* get OV configuration */
9542 val = MF_CFG_RD(bp,
9543 func_mf_config[FUNC_0].e1hov_tag);
9544 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9545
9546 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9547 bp->mf_mode = MULTI_FUNCTION_SD;
9548 bp->mf_config[vn] = MF_CFG_RD(bp,
9549 func_mf_config[func].config);
9550 } else
9551 BNX2X_DEV_INFO("illegal OV for SD\n");
9552 break;
9553 default:
9554 /* Unknown configuration: reset mf_config */
9555 bp->mf_config[vn] = 0;
9556 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9557 }
9558 }
9559
9560 BNX2X_DEV_INFO("%s function mode\n",
9561 IS_MF(bp) ? "multi" : "single");
9562
9563 switch (bp->mf_mode) {
9564 case MULTI_FUNCTION_SD:
9565 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9566 FUNC_MF_CFG_E1HOV_TAG_MASK;
9567 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9568 bp->mf_ov = val;
9569 bp->path_has_ovlan = true;
9570
9571 BNX2X_DEV_INFO("MF OV for func %d is %d "
9572 "(0x%04x)\n", func, bp->mf_ov,
9573 bp->mf_ov);
9574 } else {
9575 dev_err(&bp->pdev->dev,
9576 "No valid MF OV for func %d, "
9577 "aborting\n", func);
9578 return -EPERM;
9579 }
9580 break;
9581 case MULTI_FUNCTION_SI:
9582 BNX2X_DEV_INFO("func %d is in MF "
9583 "switch-independent mode\n", func);
9584 break;
9585 default:
9586 if (vn) {
9587 dev_err(&bp->pdev->dev,
9588 "VN %d is in a single function mode, "
9589 "aborting\n", vn);
9590 return -EPERM;
9591 }
9592 break;
9593 }
9594
9595 /* check if other port on the path needs ovlan:
9596 * Since MF configuration is shared between ports
9597 * Possible mixed modes are only
9598 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9599 */
9600 if (CHIP_MODE_IS_4_PORT(bp) &&
9601 !bp->path_has_ovlan &&
9602 !IS_MF(bp) &&
9603 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9604 u8 other_port = !BP_PORT(bp);
9605 u8 other_func = BP_PATH(bp) + 2*other_port;
9606 val = MF_CFG_RD(bp,
9607 func_mf_config[other_func].e1hov_tag);
9608 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9609 bp->path_has_ovlan = true;
9610 }
9611 }
9612
9613 /* adjust igu_sb_cnt to MF for E1x */
9614 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9615 bp->igu_sb_cnt /= E1HVN_MAX;
9616
9617 /* port info */
9618 bnx2x_get_port_hwinfo(bp);
9619
9620 if (!BP_NOMCP(bp)) {
9621 bp->fw_seq =
9622 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9623 DRV_MSG_SEQ_NUMBER_MASK);
9624 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9625 }
9626
9627 /* Get MAC addresses */
9628 bnx2x_get_mac_hwinfo(bp);
9629
9630 #ifdef BCM_CNIC
9631 bnx2x_get_cnic_info(bp);
9632 #endif
9633
9634 /* Get current FW pulse sequence */
9635 if (!BP_NOMCP(bp)) {
9636 int mb_idx = BP_FW_MB_IDX(bp);
9637
9638 bp->fw_drv_pulse_wr_seq =
9639 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9640 DRV_PULSE_SEQ_MASK);
9641 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9642 }
9643
9644 return rc;
9645 }
9646
9647 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9648 {
9649 int cnt, i, block_end, rodi;
9650 char vpd_data[BNX2X_VPD_LEN+1];
9651 char str_id_reg[VENDOR_ID_LEN+1];
9652 char str_id_cap[VENDOR_ID_LEN+1];
9653 u8 len;
9654
9655 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9656 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9657
9658 if (cnt < BNX2X_VPD_LEN)
9659 goto out_not_found;
9660
9661 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9662 PCI_VPD_LRDT_RO_DATA);
9663 if (i < 0)
9664 goto out_not_found;
9665
9666
9667 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9668 pci_vpd_lrdt_size(&vpd_data[i]);
9669
9670 i += PCI_VPD_LRDT_TAG_SIZE;
9671
9672 if (block_end > BNX2X_VPD_LEN)
9673 goto out_not_found;
9674
9675 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9676 PCI_VPD_RO_KEYWORD_MFR_ID);
9677 if (rodi < 0)
9678 goto out_not_found;
9679
9680 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9681
9682 if (len != VENDOR_ID_LEN)
9683 goto out_not_found;
9684
9685 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9686
9687 /* vendor specific info */
9688 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9689 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9690 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9691 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9692
9693 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9694 PCI_VPD_RO_KEYWORD_VENDOR0);
9695 if (rodi >= 0) {
9696 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9697
9698 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9699
9700 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9701 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9702 bp->fw_ver[len] = ' ';
9703 }
9704 }
9705 return;
9706 }
9707 out_not_found:
9708 return;
9709 }
9710
9711 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9712 {
9713 u32 flags = 0;
9714
9715 if (CHIP_REV_IS_FPGA(bp))
9716 SET_FLAGS(flags, MODE_FPGA);
9717 else if (CHIP_REV_IS_EMUL(bp))
9718 SET_FLAGS(flags, MODE_EMUL);
9719 else
9720 SET_FLAGS(flags, MODE_ASIC);
9721
9722 if (CHIP_MODE_IS_4_PORT(bp))
9723 SET_FLAGS(flags, MODE_PORT4);
9724 else
9725 SET_FLAGS(flags, MODE_PORT2);
9726
9727 if (CHIP_IS_E2(bp))
9728 SET_FLAGS(flags, MODE_E2);
9729 else if (CHIP_IS_E3(bp)) {
9730 SET_FLAGS(flags, MODE_E3);
9731 if (CHIP_REV(bp) == CHIP_REV_Ax)
9732 SET_FLAGS(flags, MODE_E3_A0);
9733 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9734 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9735 }
9736
9737 if (IS_MF(bp)) {
9738 SET_FLAGS(flags, MODE_MF);
9739 switch (bp->mf_mode) {
9740 case MULTI_FUNCTION_SD:
9741 SET_FLAGS(flags, MODE_MF_SD);
9742 break;
9743 case MULTI_FUNCTION_SI:
9744 SET_FLAGS(flags, MODE_MF_SI);
9745 break;
9746 }
9747 } else
9748 SET_FLAGS(flags, MODE_SF);
9749
9750 #if defined(__LITTLE_ENDIAN)
9751 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9752 #else /*(__BIG_ENDIAN)*/
9753 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9754 #endif
9755 INIT_MODE_FLAGS(bp) = flags;
9756 }
9757
9758 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9759 {
9760 int func;
9761 int timer_interval;
9762 int rc;
9763
9764 mutex_init(&bp->port.phy_mutex);
9765 mutex_init(&bp->fw_mb_mutex);
9766 spin_lock_init(&bp->stats_lock);
9767 #ifdef BCM_CNIC
9768 mutex_init(&bp->cnic_mutex);
9769 #endif
9770
9771 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9772 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9773 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9774 rc = bnx2x_get_hwinfo(bp);
9775 if (rc)
9776 return rc;
9777
9778 bnx2x_set_modes_bitmap(bp);
9779
9780 rc = bnx2x_alloc_mem_bp(bp);
9781 if (rc)
9782 return rc;
9783
9784 bnx2x_read_fwinfo(bp);
9785
9786 func = BP_FUNC(bp);
9787
9788 /* need to reset chip if undi was active */
9789 if (!BP_NOMCP(bp))
9790 bnx2x_undi_unload(bp);
9791
9792 if (CHIP_REV_IS_FPGA(bp))
9793 dev_err(&bp->pdev->dev, "FPGA detected\n");
9794
9795 if (BP_NOMCP(bp) && (func == 0))
9796 dev_err(&bp->pdev->dev, "MCP disabled, "
9797 "must load devices in order!\n");
9798
9799 bp->multi_mode = multi_mode;
9800
9801 /* Set TPA flags */
9802 if (disable_tpa) {
9803 bp->flags &= ~TPA_ENABLE_FLAG;
9804 bp->dev->features &= ~NETIF_F_LRO;
9805 } else {
9806 bp->flags |= TPA_ENABLE_FLAG;
9807 bp->dev->features |= NETIF_F_LRO;
9808 }
9809 bp->disable_tpa = disable_tpa;
9810
9811 if (CHIP_IS_E1(bp))
9812 bp->dropless_fc = 0;
9813 else
9814 bp->dropless_fc = dropless_fc;
9815
9816 bp->mrrs = mrrs;
9817
9818 bp->tx_ring_size = MAX_TX_AVAIL;
9819
9820 /* make sure that the numbers are in the right granularity */
9821 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9822 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9823
9824 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9825 bp->current_interval = (poll ? poll : timer_interval);
9826
9827 init_timer(&bp->timer);
9828 bp->timer.expires = jiffies + bp->current_interval;
9829 bp->timer.data = (unsigned long) bp;
9830 bp->timer.function = bnx2x_timer;
9831
9832 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9833 bnx2x_dcbx_init_params(bp);
9834
9835 #ifdef BCM_CNIC
9836 if (CHIP_IS_E1x(bp))
9837 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9838 else
9839 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9840 #endif
9841
9842 /* multiple tx priority */
9843 if (CHIP_IS_E1x(bp))
9844 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9845 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9846 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9847 if (CHIP_IS_E3B0(bp))
9848 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9849
9850 return rc;
9851 }
9852
9853
9854 /****************************************************************************
9855 * General service functions
9856 ****************************************************************************/
9857
9858 /*
9859 * net_device service functions
9860 */
9861
9862 /* called with rtnl_lock */
9863 static int bnx2x_open(struct net_device *dev)
9864 {
9865 struct bnx2x *bp = netdev_priv(dev);
9866 bool global = false;
9867 int other_engine = BP_PATH(bp) ? 0 : 1;
9868 u32 other_load_counter, load_counter;
9869
9870 netif_carrier_off(dev);
9871
9872 bnx2x_set_power_state(bp, PCI_D0);
9873
9874 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9875 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9876
9877 /*
9878 * If parity had happen during the unload, then attentions
9879 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9880 * want the first function loaded on the current engine to
9881 * complete the recovery.
9882 */
9883 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9884 bnx2x_chk_parity_attn(bp, &global, true))
9885 do {
9886 /*
9887 * If there are attentions and they are in a global
9888 * blocks, set the GLOBAL_RESET bit regardless whether
9889 * it will be this function that will complete the
9890 * recovery or not.
9891 */
9892 if (global)
9893 bnx2x_set_reset_global(bp);
9894
9895 /*
9896 * Only the first function on the current engine should
9897 * try to recover in open. In case of attentions in
9898 * global blocks only the first in the chip should try
9899 * to recover.
9900 */
9901 if ((!load_counter &&
9902 (!global || !other_load_counter)) &&
9903 bnx2x_trylock_leader_lock(bp) &&
9904 !bnx2x_leader_reset(bp)) {
9905 netdev_info(bp->dev, "Recovered in open\n");
9906 break;
9907 }
9908
9909 /* recovery has failed... */
9910 bnx2x_set_power_state(bp, PCI_D3hot);
9911 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9912
9913 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9914 " completed yet. Try again later. If u still see this"
9915 " message after a few retries then power cycle is"
9916 " required.\n");
9917
9918 return -EAGAIN;
9919 } while (0);
9920
9921 bp->recovery_state = BNX2X_RECOVERY_DONE;
9922 return bnx2x_nic_load(bp, LOAD_OPEN);
9923 }
9924
9925 /* called with rtnl_lock */
9926 static int bnx2x_close(struct net_device *dev)
9927 {
9928 struct bnx2x *bp = netdev_priv(dev);
9929
9930 /* Unload the driver, release IRQs */
9931 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9932
9933 /* Power off */
9934 bnx2x_set_power_state(bp, PCI_D3hot);
9935
9936 return 0;
9937 }
9938
9939 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9940 struct bnx2x_mcast_ramrod_params *p)
9941 {
9942 int mc_count = netdev_mc_count(bp->dev);
9943 struct bnx2x_mcast_list_elem *mc_mac =
9944 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9945 struct netdev_hw_addr *ha;
9946
9947 if (!mc_mac)
9948 return -ENOMEM;
9949
9950 INIT_LIST_HEAD(&p->mcast_list);
9951
9952 netdev_for_each_mc_addr(ha, bp->dev) {
9953 mc_mac->mac = bnx2x_mc_addr(ha);
9954 list_add_tail(&mc_mac->link, &p->mcast_list);
9955 mc_mac++;
9956 }
9957
9958 p->mcast_list_len = mc_count;
9959
9960 return 0;
9961 }
9962
9963 static inline void bnx2x_free_mcast_macs_list(
9964 struct bnx2x_mcast_ramrod_params *p)
9965 {
9966 struct bnx2x_mcast_list_elem *mc_mac =
9967 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
9968 link);
9969
9970 WARN_ON(!mc_mac);
9971 kfree(mc_mac);
9972 }
9973
9974 /**
9975 * bnx2x_set_uc_list - configure a new unicast MACs list.
9976 *
9977 * @bp: driver handle
9978 *
9979 * We will use zero (0) as a MAC type for these MACs.
9980 */
9981 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
9982 {
9983 int rc;
9984 struct net_device *dev = bp->dev;
9985 struct netdev_hw_addr *ha;
9986 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
9987 unsigned long ramrod_flags = 0;
9988
9989 /* First schedule a cleanup up of old configuration */
9990 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
9991 if (rc < 0) {
9992 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
9993 return rc;
9994 }
9995
9996 netdev_for_each_uc_addr(ha, dev) {
9997 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
9998 BNX2X_UC_LIST_MAC, &ramrod_flags);
9999 if (rc < 0) {
10000 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10001 rc);
10002 return rc;
10003 }
10004 }
10005
10006 /* Execute the pending commands */
10007 __set_bit(RAMROD_CONT, &ramrod_flags);
10008 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10009 BNX2X_UC_LIST_MAC, &ramrod_flags);
10010 }
10011
10012 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10013 {
10014 struct net_device *dev = bp->dev;
10015 struct bnx2x_mcast_ramrod_params rparam = {0};
10016 int rc = 0;
10017
10018 rparam.mcast_obj = &bp->mcast_obj;
10019
10020 /* first, clear all configured multicast MACs */
10021 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10022 if (rc < 0) {
10023 BNX2X_ERR("Failed to clear multicast "
10024 "configuration: %d\n", rc);
10025 return rc;
10026 }
10027
10028 /* then, configure a new MACs list */
10029 if (netdev_mc_count(dev)) {
10030 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10031 if (rc) {
10032 BNX2X_ERR("Failed to create multicast MACs "
10033 "list: %d\n", rc);
10034 return rc;
10035 }
10036
10037 /* Now add the new MACs */
10038 rc = bnx2x_config_mcast(bp, &rparam,
10039 BNX2X_MCAST_CMD_ADD);
10040 if (rc < 0)
10041 BNX2X_ERR("Failed to set a new multicast "
10042 "configuration: %d\n", rc);
10043
10044 bnx2x_free_mcast_macs_list(&rparam);
10045 }
10046
10047 return rc;
10048 }
10049
10050
10051 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10052 void bnx2x_set_rx_mode(struct net_device *dev)
10053 {
10054 struct bnx2x *bp = netdev_priv(dev);
10055 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10056
10057 if (bp->state != BNX2X_STATE_OPEN) {
10058 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10059 return;
10060 }
10061
10062 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10063
10064 if (dev->flags & IFF_PROMISC)
10065 rx_mode = BNX2X_RX_MODE_PROMISC;
10066 else if ((dev->flags & IFF_ALLMULTI) ||
10067 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10068 CHIP_IS_E1(bp)))
10069 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10070 else {
10071 /* some multicasts */
10072 if (bnx2x_set_mc_list(bp) < 0)
10073 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10074
10075 if (bnx2x_set_uc_list(bp) < 0)
10076 rx_mode = BNX2X_RX_MODE_PROMISC;
10077 }
10078
10079 bp->rx_mode = rx_mode;
10080
10081 /* Schedule the rx_mode command */
10082 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10083 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10084 return;
10085 }
10086
10087 bnx2x_set_storm_rx_mode(bp);
10088 }
10089
10090 /* called with rtnl_lock */
10091 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10092 int devad, u16 addr)
10093 {
10094 struct bnx2x *bp = netdev_priv(netdev);
10095 u16 value;
10096 int rc;
10097
10098 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10099 prtad, devad, addr);
10100
10101 /* The HW expects different devad if CL22 is used */
10102 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10103
10104 bnx2x_acquire_phy_lock(bp);
10105 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10106 bnx2x_release_phy_lock(bp);
10107 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10108
10109 if (!rc)
10110 rc = value;
10111 return rc;
10112 }
10113
10114 /* called with rtnl_lock */
10115 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10116 u16 addr, u16 value)
10117 {
10118 struct bnx2x *bp = netdev_priv(netdev);
10119 int rc;
10120
10121 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10122 " value 0x%x\n", prtad, devad, addr, value);
10123
10124 /* The HW expects different devad if CL22 is used */
10125 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10126
10127 bnx2x_acquire_phy_lock(bp);
10128 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10129 bnx2x_release_phy_lock(bp);
10130 return rc;
10131 }
10132
10133 /* called with rtnl_lock */
10134 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10135 {
10136 struct bnx2x *bp = netdev_priv(dev);
10137 struct mii_ioctl_data *mdio = if_mii(ifr);
10138
10139 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10140 mdio->phy_id, mdio->reg_num, mdio->val_in);
10141
10142 if (!netif_running(dev))
10143 return -EAGAIN;
10144
10145 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10146 }
10147
10148 #ifdef CONFIG_NET_POLL_CONTROLLER
10149 static void poll_bnx2x(struct net_device *dev)
10150 {
10151 struct bnx2x *bp = netdev_priv(dev);
10152
10153 disable_irq(bp->pdev->irq);
10154 bnx2x_interrupt(bp->pdev->irq, dev);
10155 enable_irq(bp->pdev->irq);
10156 }
10157 #endif
10158
10159 static const struct net_device_ops bnx2x_netdev_ops = {
10160 .ndo_open = bnx2x_open,
10161 .ndo_stop = bnx2x_close,
10162 .ndo_start_xmit = bnx2x_start_xmit,
10163 .ndo_select_queue = bnx2x_select_queue,
10164 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10165 .ndo_set_mac_address = bnx2x_change_mac_addr,
10166 .ndo_validate_addr = eth_validate_addr,
10167 .ndo_do_ioctl = bnx2x_ioctl,
10168 .ndo_change_mtu = bnx2x_change_mtu,
10169 .ndo_fix_features = bnx2x_fix_features,
10170 .ndo_set_features = bnx2x_set_features,
10171 .ndo_tx_timeout = bnx2x_tx_timeout,
10172 #ifdef CONFIG_NET_POLL_CONTROLLER
10173 .ndo_poll_controller = poll_bnx2x,
10174 #endif
10175 .ndo_setup_tc = bnx2x_setup_tc,
10176
10177 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10178 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10179 #endif
10180 };
10181
10182 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10183 {
10184 struct device *dev = &bp->pdev->dev;
10185
10186 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10187 bp->flags |= USING_DAC_FLAG;
10188 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10189 dev_err(dev, "dma_set_coherent_mask failed, "
10190 "aborting\n");
10191 return -EIO;
10192 }
10193 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10194 dev_err(dev, "System does not support DMA, aborting\n");
10195 return -EIO;
10196 }
10197
10198 return 0;
10199 }
10200
10201 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10202 struct net_device *dev,
10203 unsigned long board_type)
10204 {
10205 struct bnx2x *bp;
10206 int rc;
10207
10208 SET_NETDEV_DEV(dev, &pdev->dev);
10209 bp = netdev_priv(dev);
10210
10211 bp->dev = dev;
10212 bp->pdev = pdev;
10213 bp->flags = 0;
10214 bp->pf_num = PCI_FUNC(pdev->devfn);
10215
10216 rc = pci_enable_device(pdev);
10217 if (rc) {
10218 dev_err(&bp->pdev->dev,
10219 "Cannot enable PCI device, aborting\n");
10220 goto err_out;
10221 }
10222
10223 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10224 dev_err(&bp->pdev->dev,
10225 "Cannot find PCI device base address, aborting\n");
10226 rc = -ENODEV;
10227 goto err_out_disable;
10228 }
10229
10230 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10231 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10232 " base address, aborting\n");
10233 rc = -ENODEV;
10234 goto err_out_disable;
10235 }
10236
10237 if (atomic_read(&pdev->enable_cnt) == 1) {
10238 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10239 if (rc) {
10240 dev_err(&bp->pdev->dev,
10241 "Cannot obtain PCI resources, aborting\n");
10242 goto err_out_disable;
10243 }
10244
10245 pci_set_master(pdev);
10246 pci_save_state(pdev);
10247 }
10248
10249 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10250 if (bp->pm_cap == 0) {
10251 dev_err(&bp->pdev->dev,
10252 "Cannot find power management capability, aborting\n");
10253 rc = -EIO;
10254 goto err_out_release;
10255 }
10256
10257 if (!pci_is_pcie(pdev)) {
10258 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10259 rc = -EIO;
10260 goto err_out_release;
10261 }
10262
10263 rc = bnx2x_set_coherency_mask(bp);
10264 if (rc)
10265 goto err_out_release;
10266
10267 dev->mem_start = pci_resource_start(pdev, 0);
10268 dev->base_addr = dev->mem_start;
10269 dev->mem_end = pci_resource_end(pdev, 0);
10270
10271 dev->irq = pdev->irq;
10272
10273 bp->regview = pci_ioremap_bar(pdev, 0);
10274 if (!bp->regview) {
10275 dev_err(&bp->pdev->dev,
10276 "Cannot map register space, aborting\n");
10277 rc = -ENOMEM;
10278 goto err_out_release;
10279 }
10280
10281 bnx2x_set_power_state(bp, PCI_D0);
10282
10283 /* clean indirect addresses */
10284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10285 PCICFG_VENDOR_ID_OFFSET);
10286 /* Clean the following indirect addresses for all functions since it
10287 * is not used by the driver.
10288 */
10289 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10290 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10291 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10292 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10293 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10294 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10295 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10296 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10297
10298 /*
10299 * Enable internal target-read (in case we are probed after PF FLR).
10300 * Must be done prior to any BAR read access. Only for 57712 and up
10301 */
10302 if (board_type != BCM57710 &&
10303 board_type != BCM57711 &&
10304 board_type != BCM57711E)
10305 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10306
10307 /* Reset the load counter */
10308 bnx2x_clear_load_cnt(bp);
10309
10310 dev->watchdog_timeo = TX_TIMEOUT;
10311
10312 dev->netdev_ops = &bnx2x_netdev_ops;
10313 bnx2x_set_ethtool_ops(dev);
10314
10315 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10316 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10317 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10318
10319 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10320 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10321
10322 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10323 if (bp->flags & USING_DAC_FLAG)
10324 dev->features |= NETIF_F_HIGHDMA;
10325
10326 /* Add Loopback capability to the device */
10327 dev->hw_features |= NETIF_F_LOOPBACK;
10328
10329 #ifdef BCM_DCBNL
10330 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10331 #endif
10332
10333 /* get_port_hwinfo() will set prtad and mmds properly */
10334 bp->mdio.prtad = MDIO_PRTAD_NONE;
10335 bp->mdio.mmds = 0;
10336 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10337 bp->mdio.dev = dev;
10338 bp->mdio.mdio_read = bnx2x_mdio_read;
10339 bp->mdio.mdio_write = bnx2x_mdio_write;
10340
10341 return 0;
10342
10343 err_out_release:
10344 if (atomic_read(&pdev->enable_cnt) == 1)
10345 pci_release_regions(pdev);
10346
10347 err_out_disable:
10348 pci_disable_device(pdev);
10349 pci_set_drvdata(pdev, NULL);
10350
10351 err_out:
10352 return rc;
10353 }
10354
10355 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10356 int *width, int *speed)
10357 {
10358 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10359
10360 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10361
10362 /* return value of 1=2.5GHz 2=5GHz */
10363 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10364 }
10365
10366 static int bnx2x_check_firmware(struct bnx2x *bp)
10367 {
10368 const struct firmware *firmware = bp->firmware;
10369 struct bnx2x_fw_file_hdr *fw_hdr;
10370 struct bnx2x_fw_file_section *sections;
10371 u32 offset, len, num_ops;
10372 u16 *ops_offsets;
10373 int i;
10374 const u8 *fw_ver;
10375
10376 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10377 return -EINVAL;
10378
10379 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10380 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10381
10382 /* Make sure none of the offsets and sizes make us read beyond
10383 * the end of the firmware data */
10384 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10385 offset = be32_to_cpu(sections[i].offset);
10386 len = be32_to_cpu(sections[i].len);
10387 if (offset + len > firmware->size) {
10388 dev_err(&bp->pdev->dev,
10389 "Section %d length is out of bounds\n", i);
10390 return -EINVAL;
10391 }
10392 }
10393
10394 /* Likewise for the init_ops offsets */
10395 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10396 ops_offsets = (u16 *)(firmware->data + offset);
10397 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10398
10399 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10400 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10401 dev_err(&bp->pdev->dev,
10402 "Section offset %d is out of bounds\n", i);
10403 return -EINVAL;
10404 }
10405 }
10406
10407 /* Check FW version */
10408 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10409 fw_ver = firmware->data + offset;
10410 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10411 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10412 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10413 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10414 dev_err(&bp->pdev->dev,
10415 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10416 fw_ver[0], fw_ver[1], fw_ver[2],
10417 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10418 BCM_5710_FW_MINOR_VERSION,
10419 BCM_5710_FW_REVISION_VERSION,
10420 BCM_5710_FW_ENGINEERING_VERSION);
10421 return -EINVAL;
10422 }
10423
10424 return 0;
10425 }
10426
10427 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10428 {
10429 const __be32 *source = (const __be32 *)_source;
10430 u32 *target = (u32 *)_target;
10431 u32 i;
10432
10433 for (i = 0; i < n/4; i++)
10434 target[i] = be32_to_cpu(source[i]);
10435 }
10436
10437 /*
10438 Ops array is stored in the following format:
10439 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10440 */
10441 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10442 {
10443 const __be32 *source = (const __be32 *)_source;
10444 struct raw_op *target = (struct raw_op *)_target;
10445 u32 i, j, tmp;
10446
10447 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10448 tmp = be32_to_cpu(source[j]);
10449 target[i].op = (tmp >> 24) & 0xff;
10450 target[i].offset = tmp & 0xffffff;
10451 target[i].raw_data = be32_to_cpu(source[j + 1]);
10452 }
10453 }
10454
10455 /**
10456 * IRO array is stored in the following format:
10457 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10458 */
10459 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10460 {
10461 const __be32 *source = (const __be32 *)_source;
10462 struct iro *target = (struct iro *)_target;
10463 u32 i, j, tmp;
10464
10465 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10466 target[i].base = be32_to_cpu(source[j]);
10467 j++;
10468 tmp = be32_to_cpu(source[j]);
10469 target[i].m1 = (tmp >> 16) & 0xffff;
10470 target[i].m2 = tmp & 0xffff;
10471 j++;
10472 tmp = be32_to_cpu(source[j]);
10473 target[i].m3 = (tmp >> 16) & 0xffff;
10474 target[i].size = tmp & 0xffff;
10475 j++;
10476 }
10477 }
10478
10479 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10480 {
10481 const __be16 *source = (const __be16 *)_source;
10482 u16 *target = (u16 *)_target;
10483 u32 i;
10484
10485 for (i = 0; i < n/2; i++)
10486 target[i] = be16_to_cpu(source[i]);
10487 }
10488
10489 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10490 do { \
10491 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10492 bp->arr = kmalloc(len, GFP_KERNEL); \
10493 if (!bp->arr) { \
10494 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10495 goto lbl; \
10496 } \
10497 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10498 (u8 *)bp->arr, len); \
10499 } while (0)
10500
10501 int bnx2x_init_firmware(struct bnx2x *bp)
10502 {
10503 const char *fw_file_name;
10504 struct bnx2x_fw_file_hdr *fw_hdr;
10505 int rc;
10506
10507 if (CHIP_IS_E1(bp))
10508 fw_file_name = FW_FILE_NAME_E1;
10509 else if (CHIP_IS_E1H(bp))
10510 fw_file_name = FW_FILE_NAME_E1H;
10511 else if (!CHIP_IS_E1x(bp))
10512 fw_file_name = FW_FILE_NAME_E2;
10513 else {
10514 BNX2X_ERR("Unsupported chip revision\n");
10515 return -EINVAL;
10516 }
10517
10518 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10519
10520 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10521 if (rc) {
10522 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10523 goto request_firmware_exit;
10524 }
10525
10526 rc = bnx2x_check_firmware(bp);
10527 if (rc) {
10528 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10529 goto request_firmware_exit;
10530 }
10531
10532 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10533
10534 /* Initialize the pointers to the init arrays */
10535 /* Blob */
10536 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10537
10538 /* Opcodes */
10539 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10540
10541 /* Offsets */
10542 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10543 be16_to_cpu_n);
10544
10545 /* STORMs firmware */
10546 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10547 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10548 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10549 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10550 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10551 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10552 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10553 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10554 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10555 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10556 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10557 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10558 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10559 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10560 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10561 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10562 /* IRO */
10563 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10564
10565 return 0;
10566
10567 iro_alloc_err:
10568 kfree(bp->init_ops_offsets);
10569 init_offsets_alloc_err:
10570 kfree(bp->init_ops);
10571 init_ops_alloc_err:
10572 kfree(bp->init_data);
10573 request_firmware_exit:
10574 release_firmware(bp->firmware);
10575
10576 return rc;
10577 }
10578
10579 static void bnx2x_release_firmware(struct bnx2x *bp)
10580 {
10581 kfree(bp->init_ops_offsets);
10582 kfree(bp->init_ops);
10583 kfree(bp->init_data);
10584 release_firmware(bp->firmware);
10585 }
10586
10587
10588 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10589 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10590 .init_hw_cmn = bnx2x_init_hw_common,
10591 .init_hw_port = bnx2x_init_hw_port,
10592 .init_hw_func = bnx2x_init_hw_func,
10593
10594 .reset_hw_cmn = bnx2x_reset_common,
10595 .reset_hw_port = bnx2x_reset_port,
10596 .reset_hw_func = bnx2x_reset_func,
10597
10598 .gunzip_init = bnx2x_gunzip_init,
10599 .gunzip_end = bnx2x_gunzip_end,
10600
10601 .init_fw = bnx2x_init_firmware,
10602 .release_fw = bnx2x_release_firmware,
10603 };
10604
10605 void bnx2x__init_func_obj(struct bnx2x *bp)
10606 {
10607 /* Prepare DMAE related driver resources */
10608 bnx2x_setup_dmae(bp);
10609
10610 bnx2x_init_func_obj(bp, &bp->func_obj,
10611 bnx2x_sp(bp, func_rdata),
10612 bnx2x_sp_mapping(bp, func_rdata),
10613 &bnx2x_func_sp_drv);
10614 }
10615
10616 /* must be called after sriov-enable */
10617 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10618 {
10619 int cid_count = BNX2X_L2_CID_COUNT(bp);
10620
10621 #ifdef BCM_CNIC
10622 cid_count += CNIC_CID_MAX;
10623 #endif
10624 return roundup(cid_count, QM_CID_ROUND);
10625 }
10626
10627 /**
10628 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10629 *
10630 * @dev: pci device
10631 *
10632 */
10633 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10634 {
10635 int pos;
10636 u16 control;
10637
10638 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10639
10640 /*
10641 * If MSI-X is not supported - return number of SBs needed to support
10642 * one fast path queue: one FP queue + SB for CNIC
10643 */
10644 if (!pos)
10645 return 1 + CNIC_PRESENT;
10646
10647 /*
10648 * The value in the PCI configuration space is the index of the last
10649 * entry, namely one less than the actual size of the table, which is
10650 * exactly what we want to return from this function: number of all SBs
10651 * without the default SB.
10652 */
10653 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10654 return control & PCI_MSIX_FLAGS_QSIZE;
10655 }
10656
10657 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10658 const struct pci_device_id *ent)
10659 {
10660 struct net_device *dev = NULL;
10661 struct bnx2x *bp;
10662 int pcie_width, pcie_speed;
10663 int rc, max_non_def_sbs;
10664 int rx_count, tx_count, rss_count;
10665 /*
10666 * An estimated maximum supported CoS number according to the chip
10667 * version.
10668 * We will try to roughly estimate the maximum number of CoSes this chip
10669 * may support in order to minimize the memory allocated for Tx
10670 * netdev_queue's. This number will be accurately calculated during the
10671 * initialization of bp->max_cos based on the chip versions AND chip
10672 * revision in the bnx2x_init_bp().
10673 */
10674 u8 max_cos_est = 0;
10675
10676 switch (ent->driver_data) {
10677 case BCM57710:
10678 case BCM57711:
10679 case BCM57711E:
10680 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10681 break;
10682
10683 case BCM57712:
10684 case BCM57712_MF:
10685 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10686 break;
10687
10688 case BCM57800:
10689 case BCM57800_MF:
10690 case BCM57810:
10691 case BCM57810_MF:
10692 case BCM57840:
10693 case BCM57840_MF:
10694 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10695 break;
10696
10697 default:
10698 pr_err("Unknown board_type (%ld), aborting\n",
10699 ent->driver_data);
10700 return -ENODEV;
10701 }
10702
10703 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10704
10705 /* !!! FIXME !!!
10706 * Do not allow the maximum SB count to grow above 16
10707 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10708 * We will use the FP_SB_MAX_E1x macro for this matter.
10709 */
10710 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10711
10712 WARN_ON(!max_non_def_sbs);
10713
10714 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10715 rss_count = max_non_def_sbs - CNIC_PRESENT;
10716
10717 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10718 rx_count = rss_count + FCOE_PRESENT;
10719
10720 /*
10721 * Maximum number of netdev Tx queues:
10722 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10723 */
10724 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10725
10726 /* dev zeroed in init_etherdev */
10727 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10728 if (!dev) {
10729 dev_err(&pdev->dev, "Cannot allocate net device\n");
10730 return -ENOMEM;
10731 }
10732
10733 bp = netdev_priv(dev);
10734
10735 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10736 tx_count, rx_count);
10737
10738 bp->igu_sb_cnt = max_non_def_sbs;
10739 bp->msg_enable = debug;
10740 pci_set_drvdata(pdev, dev);
10741
10742 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10743 if (rc < 0) {
10744 free_netdev(dev);
10745 return rc;
10746 }
10747
10748 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
10749
10750 rc = bnx2x_init_bp(bp);
10751 if (rc)
10752 goto init_one_exit;
10753
10754 /*
10755 * Map doorbels here as we need the real value of bp->max_cos which
10756 * is initialized in bnx2x_init_bp().
10757 */
10758 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10759 min_t(u64, BNX2X_DB_SIZE(bp),
10760 pci_resource_len(pdev, 2)));
10761 if (!bp->doorbells) {
10762 dev_err(&bp->pdev->dev,
10763 "Cannot map doorbell space, aborting\n");
10764 rc = -ENOMEM;
10765 goto init_one_exit;
10766 }
10767
10768 /* calc qm_cid_count */
10769 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10770
10771 #ifdef BCM_CNIC
10772 /* disable FCOE L2 queue for E1x and E3*/
10773 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10774 bp->flags |= NO_FCOE_FLAG;
10775
10776 #endif
10777
10778 /* Configure interrupt mode: try to enable MSI-X/MSI if
10779 * needed, set bp->num_queues appropriately.
10780 */
10781 bnx2x_set_int_mode(bp);
10782
10783 /* Add all NAPI objects */
10784 bnx2x_add_all_napi(bp);
10785
10786 rc = register_netdev(dev);
10787 if (rc) {
10788 dev_err(&pdev->dev, "Cannot register net device\n");
10789 goto init_one_exit;
10790 }
10791
10792 #ifdef BCM_CNIC
10793 if (!NO_FCOE(bp)) {
10794 /* Add storage MAC address */
10795 rtnl_lock();
10796 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10797 rtnl_unlock();
10798 }
10799 #endif
10800
10801 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10802
10803 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10804 " IRQ %d, ", board_info[ent->driver_data].name,
10805 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10806 pcie_width,
10807 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10808 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10809 "5GHz (Gen2)" : "2.5GHz",
10810 dev->base_addr, bp->pdev->irq);
10811 pr_cont("node addr %pM\n", dev->dev_addr);
10812
10813 return 0;
10814
10815 init_one_exit:
10816 if (bp->regview)
10817 iounmap(bp->regview);
10818
10819 if (bp->doorbells)
10820 iounmap(bp->doorbells);
10821
10822 free_netdev(dev);
10823
10824 if (atomic_read(&pdev->enable_cnt) == 1)
10825 pci_release_regions(pdev);
10826
10827 pci_disable_device(pdev);
10828 pci_set_drvdata(pdev, NULL);
10829
10830 return rc;
10831 }
10832
10833 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10834 {
10835 struct net_device *dev = pci_get_drvdata(pdev);
10836 struct bnx2x *bp;
10837
10838 if (!dev) {
10839 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10840 return;
10841 }
10842 bp = netdev_priv(dev);
10843
10844 #ifdef BCM_CNIC
10845 /* Delete storage MAC address */
10846 if (!NO_FCOE(bp)) {
10847 rtnl_lock();
10848 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10849 rtnl_unlock();
10850 }
10851 #endif
10852
10853 #ifdef BCM_DCBNL
10854 /* Delete app tlvs from dcbnl */
10855 bnx2x_dcbnl_update_applist(bp, true);
10856 #endif
10857
10858 unregister_netdev(dev);
10859
10860 /* Delete all NAPI objects */
10861 bnx2x_del_all_napi(bp);
10862
10863 /* Power on: we can't let PCI layer write to us while we are in D3 */
10864 bnx2x_set_power_state(bp, PCI_D0);
10865
10866 /* Disable MSI/MSI-X */
10867 bnx2x_disable_msi(bp);
10868
10869 /* Power off */
10870 bnx2x_set_power_state(bp, PCI_D3hot);
10871
10872 /* Make sure RESET task is not scheduled before continuing */
10873 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10874
10875 if (bp->regview)
10876 iounmap(bp->regview);
10877
10878 if (bp->doorbells)
10879 iounmap(bp->doorbells);
10880
10881 bnx2x_free_mem_bp(bp);
10882
10883 free_netdev(dev);
10884
10885 if (atomic_read(&pdev->enable_cnt) == 1)
10886 pci_release_regions(pdev);
10887
10888 pci_disable_device(pdev);
10889 pci_set_drvdata(pdev, NULL);
10890 }
10891
10892 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10893 {
10894 int i;
10895
10896 bp->state = BNX2X_STATE_ERROR;
10897
10898 bp->rx_mode = BNX2X_RX_MODE_NONE;
10899
10900 #ifdef BCM_CNIC
10901 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10902 #endif
10903 /* Stop Tx */
10904 bnx2x_tx_disable(bp);
10905
10906 bnx2x_netif_stop(bp, 0);
10907
10908 del_timer_sync(&bp->timer);
10909
10910 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10911
10912 /* Release IRQs */
10913 bnx2x_free_irq(bp);
10914
10915 /* Free SKBs, SGEs, TPA pool and driver internals */
10916 bnx2x_free_skbs(bp);
10917
10918 for_each_rx_queue(bp, i)
10919 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10920
10921 bnx2x_free_mem(bp);
10922
10923 bp->state = BNX2X_STATE_CLOSED;
10924
10925 netif_carrier_off(bp->dev);
10926
10927 return 0;
10928 }
10929
10930 static void bnx2x_eeh_recover(struct bnx2x *bp)
10931 {
10932 u32 val;
10933
10934 mutex_init(&bp->port.phy_mutex);
10935
10936 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10937 bp->link_params.shmem_base = bp->common.shmem_base;
10938 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10939
10940 if (!bp->common.shmem_base ||
10941 (bp->common.shmem_base < 0xA0000) ||
10942 (bp->common.shmem_base >= 0xC0000)) {
10943 BNX2X_DEV_INFO("MCP not active\n");
10944 bp->flags |= NO_MCP_FLAG;
10945 return;
10946 }
10947
10948 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10949 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10950 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10951 BNX2X_ERR("BAD MCP validity signature\n");
10952
10953 if (!BP_NOMCP(bp)) {
10954 bp->fw_seq =
10955 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10956 DRV_MSG_SEQ_NUMBER_MASK);
10957 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10958 }
10959 }
10960
10961 /**
10962 * bnx2x_io_error_detected - called when PCI error is detected
10963 * @pdev: Pointer to PCI device
10964 * @state: The current pci connection state
10965 *
10966 * This function is called after a PCI bus error affecting
10967 * this device has been detected.
10968 */
10969 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10970 pci_channel_state_t state)
10971 {
10972 struct net_device *dev = pci_get_drvdata(pdev);
10973 struct bnx2x *bp = netdev_priv(dev);
10974
10975 rtnl_lock();
10976
10977 netif_device_detach(dev);
10978
10979 if (state == pci_channel_io_perm_failure) {
10980 rtnl_unlock();
10981 return PCI_ERS_RESULT_DISCONNECT;
10982 }
10983
10984 if (netif_running(dev))
10985 bnx2x_eeh_nic_unload(bp);
10986
10987 pci_disable_device(pdev);
10988
10989 rtnl_unlock();
10990
10991 /* Request a slot reset */
10992 return PCI_ERS_RESULT_NEED_RESET;
10993 }
10994
10995 /**
10996 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10997 * @pdev: Pointer to PCI device
10998 *
10999 * Restart the card from scratch, as if from a cold-boot.
11000 */
11001 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11002 {
11003 struct net_device *dev = pci_get_drvdata(pdev);
11004 struct bnx2x *bp = netdev_priv(dev);
11005
11006 rtnl_lock();
11007
11008 if (pci_enable_device(pdev)) {
11009 dev_err(&pdev->dev,
11010 "Cannot re-enable PCI device after reset\n");
11011 rtnl_unlock();
11012 return PCI_ERS_RESULT_DISCONNECT;
11013 }
11014
11015 pci_set_master(pdev);
11016 pci_restore_state(pdev);
11017
11018 if (netif_running(dev))
11019 bnx2x_set_power_state(bp, PCI_D0);
11020
11021 rtnl_unlock();
11022
11023 return PCI_ERS_RESULT_RECOVERED;
11024 }
11025
11026 /**
11027 * bnx2x_io_resume - called when traffic can start flowing again
11028 * @pdev: Pointer to PCI device
11029 *
11030 * This callback is called when the error recovery driver tells us that
11031 * its OK to resume normal operation.
11032 */
11033 static void bnx2x_io_resume(struct pci_dev *pdev)
11034 {
11035 struct net_device *dev = pci_get_drvdata(pdev);
11036 struct bnx2x *bp = netdev_priv(dev);
11037
11038 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11039 netdev_err(bp->dev, "Handling parity error recovery. "
11040 "Try again later\n");
11041 return;
11042 }
11043
11044 rtnl_lock();
11045
11046 bnx2x_eeh_recover(bp);
11047
11048 if (netif_running(dev))
11049 bnx2x_nic_load(bp, LOAD_NORMAL);
11050
11051 netif_device_attach(dev);
11052
11053 rtnl_unlock();
11054 }
11055
11056 static struct pci_error_handlers bnx2x_err_handler = {
11057 .error_detected = bnx2x_io_error_detected,
11058 .slot_reset = bnx2x_io_slot_reset,
11059 .resume = bnx2x_io_resume,
11060 };
11061
11062 static struct pci_driver bnx2x_pci_driver = {
11063 .name = DRV_MODULE_NAME,
11064 .id_table = bnx2x_pci_tbl,
11065 .probe = bnx2x_init_one,
11066 .remove = __devexit_p(bnx2x_remove_one),
11067 .suspend = bnx2x_suspend,
11068 .resume = bnx2x_resume,
11069 .err_handler = &bnx2x_err_handler,
11070 };
11071
11072 static int __init bnx2x_init(void)
11073 {
11074 int ret;
11075
11076 pr_info("%s", version);
11077
11078 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11079 if (bnx2x_wq == NULL) {
11080 pr_err("Cannot create workqueue\n");
11081 return -ENOMEM;
11082 }
11083
11084 ret = pci_register_driver(&bnx2x_pci_driver);
11085 if (ret) {
11086 pr_err("Cannot register driver\n");
11087 destroy_workqueue(bnx2x_wq);
11088 }
11089 return ret;
11090 }
11091
11092 static void __exit bnx2x_cleanup(void)
11093 {
11094 pci_unregister_driver(&bnx2x_pci_driver);
11095
11096 destroy_workqueue(bnx2x_wq);
11097 }
11098
11099 void bnx2x_notify_link_changed(struct bnx2x *bp)
11100 {
11101 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11102 }
11103
11104 module_init(bnx2x_init);
11105 module_exit(bnx2x_cleanup);
11106
11107 #ifdef BCM_CNIC
11108 /**
11109 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11110 *
11111 * @bp: driver handle
11112 * @set: set or clear the CAM entry
11113 *
11114 * This function will wait until the ramdord completion returns.
11115 * Return 0 if success, -ENODEV if ramrod doesn't return.
11116 */
11117 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11118 {
11119 unsigned long ramrod_flags = 0;
11120
11121 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11122 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11123 &bp->iscsi_l2_mac_obj, true,
11124 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11125 }
11126
11127 /* count denotes the number of new completions we have seen */
11128 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11129 {
11130 struct eth_spe *spe;
11131
11132 #ifdef BNX2X_STOP_ON_ERROR
11133 if (unlikely(bp->panic))
11134 return;
11135 #endif
11136
11137 spin_lock_bh(&bp->spq_lock);
11138 BUG_ON(bp->cnic_spq_pending < count);
11139 bp->cnic_spq_pending -= count;
11140
11141
11142 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11143 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11144 & SPE_HDR_CONN_TYPE) >>
11145 SPE_HDR_CONN_TYPE_SHIFT;
11146 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11147 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11148
11149 /* Set validation for iSCSI L2 client before sending SETUP
11150 * ramrod
11151 */
11152 if (type == ETH_CONNECTION_TYPE) {
11153 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11154 bnx2x_set_ctx_validation(bp, &bp->context.
11155 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11156 BNX2X_ISCSI_ETH_CID);
11157 }
11158
11159 /*
11160 * There may be not more than 8 L2, not more than 8 L5 SPEs
11161 * and in the air. We also check that number of outstanding
11162 * COMMON ramrods is not more than the EQ and SPQ can
11163 * accommodate.
11164 */
11165 if (type == ETH_CONNECTION_TYPE) {
11166 if (!atomic_read(&bp->cq_spq_left))
11167 break;
11168 else
11169 atomic_dec(&bp->cq_spq_left);
11170 } else if (type == NONE_CONNECTION_TYPE) {
11171 if (!atomic_read(&bp->eq_spq_left))
11172 break;
11173 else
11174 atomic_dec(&bp->eq_spq_left);
11175 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11176 (type == FCOE_CONNECTION_TYPE)) {
11177 if (bp->cnic_spq_pending >=
11178 bp->cnic_eth_dev.max_kwqe_pending)
11179 break;
11180 else
11181 bp->cnic_spq_pending++;
11182 } else {
11183 BNX2X_ERR("Unknown SPE type: %d\n", type);
11184 bnx2x_panic();
11185 break;
11186 }
11187
11188 spe = bnx2x_sp_get_next(bp);
11189 *spe = *bp->cnic_kwq_cons;
11190
11191 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11192 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11193
11194 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11195 bp->cnic_kwq_cons = bp->cnic_kwq;
11196 else
11197 bp->cnic_kwq_cons++;
11198 }
11199 bnx2x_sp_prod_update(bp);
11200 spin_unlock_bh(&bp->spq_lock);
11201 }
11202
11203 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11204 struct kwqe_16 *kwqes[], u32 count)
11205 {
11206 struct bnx2x *bp = netdev_priv(dev);
11207 int i;
11208
11209 #ifdef BNX2X_STOP_ON_ERROR
11210 if (unlikely(bp->panic))
11211 return -EIO;
11212 #endif
11213
11214 spin_lock_bh(&bp->spq_lock);
11215
11216 for (i = 0; i < count; i++) {
11217 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11218
11219 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11220 break;
11221
11222 *bp->cnic_kwq_prod = *spe;
11223
11224 bp->cnic_kwq_pending++;
11225
11226 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11227 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11228 spe->data.update_data_addr.hi,
11229 spe->data.update_data_addr.lo,
11230 bp->cnic_kwq_pending);
11231
11232 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11233 bp->cnic_kwq_prod = bp->cnic_kwq;
11234 else
11235 bp->cnic_kwq_prod++;
11236 }
11237
11238 spin_unlock_bh(&bp->spq_lock);
11239
11240 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11241 bnx2x_cnic_sp_post(bp, 0);
11242
11243 return i;
11244 }
11245
11246 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11247 {
11248 struct cnic_ops *c_ops;
11249 int rc = 0;
11250
11251 mutex_lock(&bp->cnic_mutex);
11252 c_ops = rcu_dereference_protected(bp->cnic_ops,
11253 lockdep_is_held(&bp->cnic_mutex));
11254 if (c_ops)
11255 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11256 mutex_unlock(&bp->cnic_mutex);
11257
11258 return rc;
11259 }
11260
11261 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11262 {
11263 struct cnic_ops *c_ops;
11264 int rc = 0;
11265
11266 rcu_read_lock();
11267 c_ops = rcu_dereference(bp->cnic_ops);
11268 if (c_ops)
11269 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11270 rcu_read_unlock();
11271
11272 return rc;
11273 }
11274
11275 /*
11276 * for commands that have no data
11277 */
11278 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11279 {
11280 struct cnic_ctl_info ctl = {0};
11281
11282 ctl.cmd = cmd;
11283
11284 return bnx2x_cnic_ctl_send(bp, &ctl);
11285 }
11286
11287 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11288 {
11289 struct cnic_ctl_info ctl = {0};
11290
11291 /* first we tell CNIC and only then we count this as a completion */
11292 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11293 ctl.data.comp.cid = cid;
11294 ctl.data.comp.error = err;
11295
11296 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11297 bnx2x_cnic_sp_post(bp, 0);
11298 }
11299
11300
11301 /* Called with netif_addr_lock_bh() taken.
11302 * Sets an rx_mode config for an iSCSI ETH client.
11303 * Doesn't block.
11304 * Completion should be checked outside.
11305 */
11306 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11307 {
11308 unsigned long accept_flags = 0, ramrod_flags = 0;
11309 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11310 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11311
11312 if (start) {
11313 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11314 * because it's the only way for UIO Queue to accept
11315 * multicasts (in non-promiscuous mode only one Queue per
11316 * function will receive multicast packets (leading in our
11317 * case).
11318 */
11319 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11320 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11321 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11322 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11323
11324 /* Clear STOP_PENDING bit if START is requested */
11325 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11326
11327 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11328 } else
11329 /* Clear START_PENDING bit if STOP is requested */
11330 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11331
11332 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11333 set_bit(sched_state, &bp->sp_state);
11334 else {
11335 __set_bit(RAMROD_RX, &ramrod_flags);
11336 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11337 ramrod_flags);
11338 }
11339 }
11340
11341
11342 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11343 {
11344 struct bnx2x *bp = netdev_priv(dev);
11345 int rc = 0;
11346
11347 switch (ctl->cmd) {
11348 case DRV_CTL_CTXTBL_WR_CMD: {
11349 u32 index = ctl->data.io.offset;
11350 dma_addr_t addr = ctl->data.io.dma_addr;
11351
11352 bnx2x_ilt_wr(bp, index, addr);
11353 break;
11354 }
11355
11356 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11357 int count = ctl->data.credit.credit_count;
11358
11359 bnx2x_cnic_sp_post(bp, count);
11360 break;
11361 }
11362
11363 /* rtnl_lock is held. */
11364 case DRV_CTL_START_L2_CMD: {
11365 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11366 unsigned long sp_bits = 0;
11367
11368 /* Configure the iSCSI classification object */
11369 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11370 cp->iscsi_l2_client_id,
11371 cp->iscsi_l2_cid, BP_FUNC(bp),
11372 bnx2x_sp(bp, mac_rdata),
11373 bnx2x_sp_mapping(bp, mac_rdata),
11374 BNX2X_FILTER_MAC_PENDING,
11375 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11376 &bp->macs_pool);
11377
11378 /* Set iSCSI MAC address */
11379 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11380 if (rc)
11381 break;
11382
11383 mmiowb();
11384 barrier();
11385
11386 /* Start accepting on iSCSI L2 ring */
11387
11388 netif_addr_lock_bh(dev);
11389 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11390 netif_addr_unlock_bh(dev);
11391
11392 /* bits to wait on */
11393 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11394 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11395
11396 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11397 BNX2X_ERR("rx_mode completion timed out!\n");
11398
11399 break;
11400 }
11401
11402 /* rtnl_lock is held. */
11403 case DRV_CTL_STOP_L2_CMD: {
11404 unsigned long sp_bits = 0;
11405
11406 /* Stop accepting on iSCSI L2 ring */
11407 netif_addr_lock_bh(dev);
11408 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11409 netif_addr_unlock_bh(dev);
11410
11411 /* bits to wait on */
11412 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11413 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11414
11415 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11416 BNX2X_ERR("rx_mode completion timed out!\n");
11417
11418 mmiowb();
11419 barrier();
11420
11421 /* Unset iSCSI L2 MAC */
11422 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11423 BNX2X_ISCSI_ETH_MAC, true);
11424 break;
11425 }
11426 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11427 int count = ctl->data.credit.credit_count;
11428
11429 smp_mb__before_atomic_inc();
11430 atomic_add(count, &bp->cq_spq_left);
11431 smp_mb__after_atomic_inc();
11432 break;
11433 }
11434
11435 default:
11436 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11437 rc = -EINVAL;
11438 }
11439
11440 return rc;
11441 }
11442
11443 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11444 {
11445 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11446
11447 if (bp->flags & USING_MSIX_FLAG) {
11448 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11449 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11450 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11451 } else {
11452 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11453 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11454 }
11455 if (!CHIP_IS_E1x(bp))
11456 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11457 else
11458 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11459
11460 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11461 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11462 cp->irq_arr[1].status_blk = bp->def_status_blk;
11463 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11464 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11465
11466 cp->num_irq = 2;
11467 }
11468
11469 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11470 void *data)
11471 {
11472 struct bnx2x *bp = netdev_priv(dev);
11473 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11474
11475 if (ops == NULL)
11476 return -EINVAL;
11477
11478 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11479 if (!bp->cnic_kwq)
11480 return -ENOMEM;
11481
11482 bp->cnic_kwq_cons = bp->cnic_kwq;
11483 bp->cnic_kwq_prod = bp->cnic_kwq;
11484 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11485
11486 bp->cnic_spq_pending = 0;
11487 bp->cnic_kwq_pending = 0;
11488
11489 bp->cnic_data = data;
11490
11491 cp->num_irq = 0;
11492 cp->drv_state |= CNIC_DRV_STATE_REGD;
11493 cp->iro_arr = bp->iro_arr;
11494
11495 bnx2x_setup_cnic_irq_info(bp);
11496
11497 rcu_assign_pointer(bp->cnic_ops, ops);
11498
11499 return 0;
11500 }
11501
11502 static int bnx2x_unregister_cnic(struct net_device *dev)
11503 {
11504 struct bnx2x *bp = netdev_priv(dev);
11505 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11506
11507 mutex_lock(&bp->cnic_mutex);
11508 cp->drv_state = 0;
11509 rcu_assign_pointer(bp->cnic_ops, NULL);
11510 mutex_unlock(&bp->cnic_mutex);
11511 synchronize_rcu();
11512 kfree(bp->cnic_kwq);
11513 bp->cnic_kwq = NULL;
11514
11515 return 0;
11516 }
11517
11518 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11519 {
11520 struct bnx2x *bp = netdev_priv(dev);
11521 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11522
11523 /* If both iSCSI and FCoE are disabled - return NULL in
11524 * order to indicate CNIC that it should not try to work
11525 * with this device.
11526 */
11527 if (NO_ISCSI(bp) && NO_FCOE(bp))
11528 return NULL;
11529
11530 cp->drv_owner = THIS_MODULE;
11531 cp->chip_id = CHIP_ID(bp);
11532 cp->pdev = bp->pdev;
11533 cp->io_base = bp->regview;
11534 cp->io_base2 = bp->doorbells;
11535 cp->max_kwqe_pending = 8;
11536 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11537 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11538 bnx2x_cid_ilt_lines(bp);
11539 cp->ctx_tbl_len = CNIC_ILT_LINES;
11540 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11541 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11542 cp->drv_ctl = bnx2x_drv_ctl;
11543 cp->drv_register_cnic = bnx2x_register_cnic;
11544 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11545 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11546 cp->iscsi_l2_client_id =
11547 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11548 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11549
11550 if (NO_ISCSI_OOO(bp))
11551 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11552
11553 if (NO_ISCSI(bp))
11554 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11555
11556 if (NO_FCOE(bp))
11557 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11558
11559 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11560 "starting cid %d\n",
11561 cp->ctx_blk_size,
11562 cp->ctx_tbl_offset,
11563 cp->ctx_tbl_len,
11564 cp->starting_cid);
11565 return cp;
11566 }
11567 EXPORT_SYMBOL(bnx2x_cnic_probe);
11568
11569 #endif /* BCM_CNIC */
11570
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