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[media] m88ds3103: improve ts clock setting
[linux-2.6/btrfs-unstable.git] / drivers / media / dvb-frontends / m88ds3103.c
blobfae92515cf51a65be24b3acc4da2cdb06a5407ee
1 /*
2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "m88ds3103_priv.h"
18
19 static struct dvb_frontend_ops m88ds3103_ops;
20
21 /* write single register with mask */
22 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
23 u8 reg, u8 mask, u8 val)
24 {
25 int ret;
26 u8 tmp;
27
28 /* no need for read if whole reg is written */
29 if (mask != 0xff) {
30 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
31 if (ret)
32 return ret;
33
34 val &= mask;
35 tmp &= ~mask;
36 val |= tmp;
37 }
38
39 return regmap_bulk_write(dev->regmap, reg, &val, 1);
40 }
41
42 /* write reg val table using reg addr auto increment */
43 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
44 const struct m88ds3103_reg_val *tab, int tab_len)
45 {
46 struct i2c_client *client = dev->client;
47 int ret, i, j;
48 u8 buf[83];
49
50 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
51
52 if (tab_len > 86) {
53 ret = -EINVAL;
54 goto err;
55 }
56
57 for (i = 0, j = 0; i < tab_len; i++, j++) {
58 buf[j] = tab[i].val;
59
60 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
61 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
62 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
63 if (ret)
64 goto err;
65
66 j = -1;
67 }
68 }
69
70 return 0;
71 err:
72 dev_dbg(&client->dev, "failed=%d\n", ret);
73 return ret;
74 }
75
76 /*
77 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
78 */
79 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
80 {
81 struct m88ds3103_dev *dev = fe->demodulator_priv;
82 unsigned tmp;
83 int ret;
84
85 ret = regmap_read(dev->regmap, 0x3f, &tmp);
86 if (ret == 0)
87 *_agc_pwm = tmp;
88 return ret;
89 }
90 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
91
92 static int m88ds3103_read_status(struct dvb_frontend *fe,
93 enum fe_status *status)
94 {
95 struct m88ds3103_dev *dev = fe->demodulator_priv;
96 struct i2c_client *client = dev->client;
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
98 int ret, i, itmp;
99 unsigned int utmp;
100 u8 buf[3];
101
102 *status = 0;
103
104 if (!dev->warm) {
105 ret = -EAGAIN;
106 goto err;
107 }
108
109 switch (c->delivery_system) {
110 case SYS_DVBS:
111 ret = regmap_read(dev->regmap, 0xd1, &utmp);
112 if (ret)
113 goto err;
114
115 if ((utmp & 0x07) == 0x07)
116 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
117 FE_HAS_VITERBI | FE_HAS_SYNC |
118 FE_HAS_LOCK;
119 break;
120 case SYS_DVBS2:
121 ret = regmap_read(dev->regmap, 0x0d, &utmp);
122 if (ret)
123 goto err;
124
125 if ((utmp & 0x8f) == 0x8f)
126 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
127 FE_HAS_VITERBI | FE_HAS_SYNC |
128 FE_HAS_LOCK;
129 break;
130 default:
131 dev_dbg(&client->dev, "invalid delivery_system\n");
132 ret = -EINVAL;
133 goto err;
134 }
135
136 dev->fe_status = *status;
137 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
138
139 /* CNR */
140 if (dev->fe_status & FE_HAS_VITERBI) {
141 unsigned int cnr, noise, signal, noise_tot, signal_tot;
142
143 cnr = 0;
144 /* more iterations for more accurate estimation */
145 #define M88DS3103_SNR_ITERATIONS 3
146
147 switch (c->delivery_system) {
148 case SYS_DVBS:
149 itmp = 0;
150
151 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
152 ret = regmap_read(dev->regmap, 0xff, &utmp);
153 if (ret)
154 goto err;
155
156 itmp += utmp;
157 }
158
159 /* use of single register limits max value to 15 dB */
160 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
161 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
162 if (itmp)
163 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
164 break;
165 case SYS_DVBS2:
166 noise_tot = 0;
167 signal_tot = 0;
168
169 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
170 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
171 if (ret)
172 goto err;
173
174 noise = buf[1] << 6; /* [13:6] */
175 noise |= buf[0] & 0x3f; /* [5:0] */
176 noise >>= 2;
177 signal = buf[2] * buf[2];
178 signal >>= 1;
179
180 noise_tot += noise;
181 signal_tot += signal;
182 }
183
184 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
185 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
186
187 /* SNR(X) dB = 10 * log10(X) dB */
188 if (signal > noise) {
189 itmp = signal / noise;
190 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
191 }
192 break;
193 default:
194 dev_dbg(&client->dev, "invalid delivery_system\n");
195 ret = -EINVAL;
196 goto err;
197 }
198
199 if (cnr) {
200 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
201 c->cnr.stat[0].svalue = cnr;
202 } else {
203 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
204 }
205 } else {
206 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
207 }
208
209 /* BER */
210 if (dev->fe_status & FE_HAS_LOCK) {
211 unsigned int utmp, post_bit_error, post_bit_count;
212
213 switch (c->delivery_system) {
214 case SYS_DVBS:
215 ret = regmap_write(dev->regmap, 0xf9, 0x04);
216 if (ret)
217 goto err;
218
219 ret = regmap_read(dev->regmap, 0xf8, &utmp);
220 if (ret)
221 goto err;
222
223 /* measurement ready? */
224 if (!(utmp & 0x10)) {
225 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
226 if (ret)
227 goto err;
228
229 post_bit_error = buf[1] << 8 | buf[0] << 0;
230 post_bit_count = 0x800000;
231 dev->post_bit_error += post_bit_error;
232 dev->post_bit_count += post_bit_count;
233 dev->dvbv3_ber = post_bit_error;
234
235 /* restart measurement */
236 utmp |= 0x10;
237 ret = regmap_write(dev->regmap, 0xf8, utmp);
238 if (ret)
239 goto err;
240 }
241 break;
242 case SYS_DVBS2:
243 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
244 if (ret)
245 goto err;
246
247 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
248
249 /* enough data? */
250 if (utmp > 4000) {
251 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
252 if (ret)
253 goto err;
254
255 post_bit_error = buf[1] << 8 | buf[0] << 0;
256 post_bit_count = 32 * utmp; /* TODO: FEC */
257 dev->post_bit_error += post_bit_error;
258 dev->post_bit_count += post_bit_count;
259 dev->dvbv3_ber = post_bit_error;
260
261 /* restart measurement */
262 ret = regmap_write(dev->regmap, 0xd1, 0x01);
263 if (ret)
264 goto err;
265
266 ret = regmap_write(dev->regmap, 0xf9, 0x01);
267 if (ret)
268 goto err;
269
270 ret = regmap_write(dev->regmap, 0xf9, 0x00);
271 if (ret)
272 goto err;
273
274 ret = regmap_write(dev->regmap, 0xd1, 0x00);
275 if (ret)
276 goto err;
277 }
278 break;
279 default:
280 dev_dbg(&client->dev, "invalid delivery_system\n");
281 ret = -EINVAL;
282 goto err;
283 }
284
285 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
286 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
287 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
288 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
289 } else {
290 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
291 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
292 }
293
294 return 0;
295 err:
296 dev_dbg(&client->dev, "failed=%d\n", ret);
297 return ret;
298 }
299
300 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
301 {
302 struct m88ds3103_dev *dev = fe->demodulator_priv;
303 struct i2c_client *client = dev->client;
304 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
305 int ret, len;
306 const struct m88ds3103_reg_val *init;
307 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
308 u8 buf[3];
309 u16 u16tmp;
310 u32 tuner_frequency, target_mclk;
311 s32 s32tmp;
312
313 dev_dbg(&client->dev,
314 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
315 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
316 c->inversion, c->pilot, c->rolloff);
317
318 if (!dev->warm) {
319 ret = -EAGAIN;
320 goto err;
321 }
322
323 /* reset */
324 ret = regmap_write(dev->regmap, 0x07, 0x80);
325 if (ret)
326 goto err;
327
328 ret = regmap_write(dev->regmap, 0x07, 0x00);
329 if (ret)
330 goto err;
331
332 /* Disable demod clock path */
333 if (dev->chip_id == M88RS6000_CHIP_ID) {
334 ret = regmap_write(dev->regmap, 0x06, 0xe0);
335 if (ret)
336 goto err;
337 }
338
339 /* program tuner */
340 if (fe->ops.tuner_ops.set_params) {
341 ret = fe->ops.tuner_ops.set_params(fe);
342 if (ret)
343 goto err;
344 }
345
346 if (fe->ops.tuner_ops.get_frequency) {
347 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
348 if (ret)
349 goto err;
350 } else {
351 /*
352 * Use nominal target frequency as tuner driver does not provide
353 * actual frequency used. Carrier offset calculation is not
354 * valid.
355 */
356 tuner_frequency = c->frequency;
357 }
358
359 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
360 if (dev->chip_id == M88RS6000_CHIP_ID) {
361 if (c->symbol_rate > 45010000)
362 dev->mclk_khz = 110250;
363 else
364 dev->mclk_khz = 96000;
365
366 if (c->delivery_system == SYS_DVBS)
367 target_mclk = 96000;
368 else
369 target_mclk = 144000;
370
371 /* Enable demod clock path */
372 ret = regmap_write(dev->regmap, 0x06, 0x00);
373 if (ret)
374 goto err;
375 usleep_range(10000, 20000);
376 } else {
377 /* set M88DS3103 mclk and ts mclk. */
378 dev->mclk_khz = 96000;
379
380 switch (dev->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 target_mclk = dev->cfg->ts_clk;
384 break;
385 case M88DS3103_TS_PARALLEL:
386 case M88DS3103_TS_CI:
387 if (c->delivery_system == SYS_DVBS)
388 target_mclk = 96000;
389 else {
390 if (c->symbol_rate < 18000000)
391 target_mclk = 96000;
392 else if (c->symbol_rate < 28000000)
393 target_mclk = 144000;
394 else
395 target_mclk = 192000;
396 }
397 break;
398 default:
399 dev_dbg(&client->dev, "invalid ts_mode\n");
400 ret = -EINVAL;
401 goto err;
402 }
403
404 switch (target_mclk) {
405 case 96000:
406 u8tmp1 = 0x02; /* 0b10 */
407 u8tmp2 = 0x01; /* 0b01 */
408 break;
409 case 144000:
410 u8tmp1 = 0x00; /* 0b00 */
411 u8tmp2 = 0x01; /* 0b01 */
412 break;
413 case 192000:
414 u8tmp1 = 0x03; /* 0b11 */
415 u8tmp2 = 0x00; /* 0b00 */
416 break;
417 }
418 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
419 if (ret)
420 goto err;
421 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
422 if (ret)
423 goto err;
424 }
425
426 ret = regmap_write(dev->regmap, 0xb2, 0x01);
427 if (ret)
428 goto err;
429
430 ret = regmap_write(dev->regmap, 0x00, 0x01);
431 if (ret)
432 goto err;
433
434 switch (c->delivery_system) {
435 case SYS_DVBS:
436 if (dev->chip_id == M88RS6000_CHIP_ID) {
437 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
438 init = m88rs6000_dvbs_init_reg_vals;
439 } else {
440 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
441 init = m88ds3103_dvbs_init_reg_vals;
442 }
443 break;
444 case SYS_DVBS2:
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
447 init = m88rs6000_dvbs2_init_reg_vals;
448 } else {
449 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
450 init = m88ds3103_dvbs2_init_reg_vals;
451 }
452 break;
453 default:
454 dev_dbg(&client->dev, "invalid delivery_system\n");
455 ret = -EINVAL;
456 goto err;
457 }
458
459 /* program init table */
460 if (c->delivery_system != dev->delivery_system) {
461 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
462 if (ret)
463 goto err;
464 }
465
466 if (dev->chip_id == M88RS6000_CHIP_ID) {
467 if ((c->delivery_system == SYS_DVBS2)
468 && ((c->symbol_rate / 1000) <= 5000)) {
469 ret = regmap_write(dev->regmap, 0xc0, 0x04);
470 if (ret)
471 goto err;
472 buf[0] = 0x09;
473 buf[1] = 0x22;
474 buf[2] = 0x88;
475 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
476 if (ret)
477 goto err;
478 }
479 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
480 if (ret)
481 goto err;
482 ret = regmap_write(dev->regmap, 0xf1, 0x01);
483 if (ret)
484 goto err;
485 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
486 if (ret)
487 goto err;
488 }
489
490 switch (dev->cfg->ts_mode) {
491 case M88DS3103_TS_SERIAL:
492 u8tmp1 = 0x00;
493 u8tmp = 0x06;
494 break;
495 case M88DS3103_TS_SERIAL_D7:
496 u8tmp1 = 0x20;
497 u8tmp = 0x06;
498 break;
499 case M88DS3103_TS_PARALLEL:
500 u8tmp = 0x02;
501 break;
502 case M88DS3103_TS_CI:
503 u8tmp = 0x03;
504 break;
505 default:
506 dev_dbg(&client->dev, "invalid ts_mode\n");
507 ret = -EINVAL;
508 goto err;
509 }
510
511 if (dev->cfg->ts_clk_pol)
512 u8tmp |= 0x40;
513
514 /* TS mode */
515 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
516 if (ret)
517 goto err;
518
519 switch (dev->cfg->ts_mode) {
520 case M88DS3103_TS_SERIAL:
521 case M88DS3103_TS_SERIAL_D7:
522 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
523 if (ret)
524 goto err;
525 u16tmp = 0;
526 u8tmp1 = 0x3f;
527 u8tmp2 = 0x3f;
528 break;
529 default:
530 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
531 u8tmp1 = u16tmp / 2 - 1;
532 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
533 }
534
535 dev_dbg(&client->dev, "target_mclk=%d ts_clk=%d ts_clk_divide_ratio=%u\n",
536 target_mclk, dev->cfg->ts_clk, u16tmp);
537
538 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
539 /* u8tmp2[5:0] => ea[5:0] */
540 u8tmp = (u8tmp1 >> 2) & 0x0f;
541 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
542 if (ret)
543 goto err;
544 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
545 ret = regmap_write(dev->regmap, 0xea, u8tmp);
546 if (ret)
547 goto err;
548
549 if (c->symbol_rate <= 3000000)
550 u8tmp = 0x20;
551 else if (c->symbol_rate <= 10000000)
552 u8tmp = 0x10;
553 else
554 u8tmp = 0x06;
555
556 ret = regmap_write(dev->regmap, 0xc3, 0x08);
557 if (ret)
558 goto err;
559
560 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
561 if (ret)
562 goto err;
563
564 ret = regmap_write(dev->regmap, 0xc4, 0x08);
565 if (ret)
566 goto err;
567
568 ret = regmap_write(dev->regmap, 0xc7, 0x00);
569 if (ret)
570 goto err;
571
572 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2);
573 buf[0] = (u16tmp >> 0) & 0xff;
574 buf[1] = (u16tmp >> 8) & 0xff;
575 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
576 if (ret)
577 goto err;
578
579 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
580 if (ret)
581 goto err;
582
583 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
584 if (ret)
585 goto err;
586
587 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
588 if (ret)
589 goto err;
590
591 dev_dbg(&client->dev, "carrier offset=%d\n",
592 (tuner_frequency - c->frequency));
593
594 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
595 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz);
596 buf[0] = (s32tmp >> 0) & 0xff;
597 buf[1] = (s32tmp >> 8) & 0xff;
598 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
599 if (ret)
600 goto err;
601
602 ret = regmap_write(dev->regmap, 0x00, 0x00);
603 if (ret)
604 goto err;
605
606 ret = regmap_write(dev->regmap, 0xb2, 0x00);
607 if (ret)
608 goto err;
609
610 dev->delivery_system = c->delivery_system;
611
612 return 0;
613 err:
614 dev_dbg(&client->dev, "failed=%d\n", ret);
615 return ret;
616 }
617
618 static int m88ds3103_init(struct dvb_frontend *fe)
619 {
620 struct m88ds3103_dev *dev = fe->demodulator_priv;
621 struct i2c_client *client = dev->client;
622 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
623 int ret, len, remaining;
624 unsigned int utmp;
625 const struct firmware *fw = NULL;
626 u8 *fw_file;
627
628 dev_dbg(&client->dev, "\n");
629
630 /* set cold state by default */
631 dev->warm = false;
632
633 /* wake up device from sleep */
634 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
635 if (ret)
636 goto err;
637 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
638 if (ret)
639 goto err;
640 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
641 if (ret)
642 goto err;
643
644 /* firmware status */
645 ret = regmap_read(dev->regmap, 0xb9, &utmp);
646 if (ret)
647 goto err;
648
649 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
650
651 if (utmp)
652 goto skip_fw_download;
653
654 /* global reset, global diseqc reset, golbal fec reset */
655 ret = regmap_write(dev->regmap, 0x07, 0xe0);
656 if (ret)
657 goto err;
658 ret = regmap_write(dev->regmap, 0x07, 0x00);
659 if (ret)
660 goto err;
661
662 /* cold state - try to download firmware */
663 dev_info(&client->dev, "found a '%s' in cold state\n",
664 m88ds3103_ops.info.name);
665
666 if (dev->chip_id == M88RS6000_CHIP_ID)
667 fw_file = M88RS6000_FIRMWARE;
668 else
669 fw_file = M88DS3103_FIRMWARE;
670 /* request the firmware, this will block and timeout */
671 ret = request_firmware(&fw, fw_file, &client->dev);
672 if (ret) {
673 dev_err(&client->dev, "firmware file '%s' not found\n", fw_file);
674 goto err;
675 }
676
677 dev_info(&client->dev, "downloading firmware from file '%s'\n",
678 fw_file);
679
680 ret = regmap_write(dev->regmap, 0xb2, 0x01);
681 if (ret)
682 goto error_fw_release;
683
684 for (remaining = fw->size; remaining > 0;
685 remaining -= (dev->cfg->i2c_wr_max - 1)) {
686 len = remaining;
687 if (len > (dev->cfg->i2c_wr_max - 1))
688 len = (dev->cfg->i2c_wr_max - 1);
689
690 ret = regmap_bulk_write(dev->regmap, 0xb0,
691 &fw->data[fw->size - remaining], len);
692 if (ret) {
693 dev_err(&client->dev, "firmware download failed=%d\n",
694 ret);
695 goto error_fw_release;
696 }
697 }
698
699 ret = regmap_write(dev->regmap, 0xb2, 0x00);
700 if (ret)
701 goto error_fw_release;
702
703 release_firmware(fw);
704 fw = NULL;
705
706 ret = regmap_read(dev->regmap, 0xb9, &utmp);
707 if (ret)
708 goto err;
709
710 if (!utmp) {
711 dev_info(&client->dev, "firmware did not run\n");
712 ret = -EFAULT;
713 goto err;
714 }
715
716 dev_info(&client->dev, "found a '%s' in warm state\n",
717 m88ds3103_ops.info.name);
718 dev_info(&client->dev, "firmware version: %X.%X\n",
719 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
720
721 skip_fw_download:
722 /* warm state */
723 dev->warm = true;
724
725 /* init stats here in order signal app which stats are supported */
726 c->cnr.len = 1;
727 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
728 c->post_bit_error.len = 1;
729 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
730 c->post_bit_count.len = 1;
731 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
732
733 return 0;
734 error_fw_release:
735 release_firmware(fw);
736 err:
737 dev_dbg(&client->dev, "failed=%d\n", ret);
738 return ret;
739 }
740
741 static int m88ds3103_sleep(struct dvb_frontend *fe)
742 {
743 struct m88ds3103_dev *dev = fe->demodulator_priv;
744 struct i2c_client *client = dev->client;
745 int ret;
746 unsigned int utmp;
747
748 dev_dbg(&client->dev, "\n");
749
750 dev->fe_status = 0;
751 dev->delivery_system = SYS_UNDEFINED;
752
753 /* TS Hi-Z */
754 if (dev->chip_id == M88RS6000_CHIP_ID)
755 utmp = 0x29;
756 else
757 utmp = 0x27;
758 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
759 if (ret)
760 goto err;
761
762 /* sleep */
763 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
764 if (ret)
765 goto err;
766 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
767 if (ret)
768 goto err;
769 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
770 if (ret)
771 goto err;
772
773 return 0;
774 err:
775 dev_dbg(&client->dev, "failed=%d\n", ret);
776 return ret;
777 }
778
779 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
780 struct dtv_frontend_properties *c)
781 {
782 struct m88ds3103_dev *dev = fe->demodulator_priv;
783 struct i2c_client *client = dev->client;
784 int ret;
785 u8 buf[3];
786
787 dev_dbg(&client->dev, "\n");
788
789 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
790 ret = 0;
791 goto err;
792 }
793
794 switch (c->delivery_system) {
795 case SYS_DVBS:
796 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
797 if (ret)
798 goto err;
799
800 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
801 if (ret)
802 goto err;
803
804 switch ((buf[0] >> 2) & 0x01) {
805 case 0:
806 c->inversion = INVERSION_OFF;
807 break;
808 case 1:
809 c->inversion = INVERSION_ON;
810 break;
811 }
812
813 switch ((buf[1] >> 5) & 0x07) {
814 case 0:
815 c->fec_inner = FEC_7_8;
816 break;
817 case 1:
818 c->fec_inner = FEC_5_6;
819 break;
820 case 2:
821 c->fec_inner = FEC_3_4;
822 break;
823 case 3:
824 c->fec_inner = FEC_2_3;
825 break;
826 case 4:
827 c->fec_inner = FEC_1_2;
828 break;
829 default:
830 dev_dbg(&client->dev, "invalid fec_inner\n");
831 }
832
833 c->modulation = QPSK;
834
835 break;
836 case SYS_DVBS2:
837 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
838 if (ret)
839 goto err;
840
841 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
842 if (ret)
843 goto err;
844
845 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
846 if (ret)
847 goto err;
848
849 switch ((buf[0] >> 0) & 0x0f) {
850 case 2:
851 c->fec_inner = FEC_2_5;
852 break;
853 case 3:
854 c->fec_inner = FEC_1_2;
855 break;
856 case 4:
857 c->fec_inner = FEC_3_5;
858 break;
859 case 5:
860 c->fec_inner = FEC_2_3;
861 break;
862 case 6:
863 c->fec_inner = FEC_3_4;
864 break;
865 case 7:
866 c->fec_inner = FEC_4_5;
867 break;
868 case 8:
869 c->fec_inner = FEC_5_6;
870 break;
871 case 9:
872 c->fec_inner = FEC_8_9;
873 break;
874 case 10:
875 c->fec_inner = FEC_9_10;
876 break;
877 default:
878 dev_dbg(&client->dev, "invalid fec_inner\n");
879 }
880
881 switch ((buf[0] >> 5) & 0x01) {
882 case 0:
883 c->pilot = PILOT_OFF;
884 break;
885 case 1:
886 c->pilot = PILOT_ON;
887 break;
888 }
889
890 switch ((buf[0] >> 6) & 0x07) {
891 case 0:
892 c->modulation = QPSK;
893 break;
894 case 1:
895 c->modulation = PSK_8;
896 break;
897 case 2:
898 c->modulation = APSK_16;
899 break;
900 case 3:
901 c->modulation = APSK_32;
902 break;
903 default:
904 dev_dbg(&client->dev, "invalid modulation\n");
905 }
906
907 switch ((buf[1] >> 7) & 0x01) {
908 case 0:
909 c->inversion = INVERSION_OFF;
910 break;
911 case 1:
912 c->inversion = INVERSION_ON;
913 break;
914 }
915
916 switch ((buf[2] >> 0) & 0x03) {
917 case 0:
918 c->rolloff = ROLLOFF_35;
919 break;
920 case 1:
921 c->rolloff = ROLLOFF_25;
922 break;
923 case 2:
924 c->rolloff = ROLLOFF_20;
925 break;
926 default:
927 dev_dbg(&client->dev, "invalid rolloff\n");
928 }
929 break;
930 default:
931 dev_dbg(&client->dev, "invalid delivery_system\n");
932 ret = -EINVAL;
933 goto err;
934 }
935
936 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
937 if (ret)
938 goto err;
939
940 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
941 dev->mclk_khz * 1000 / 0x10000;
942
943 return 0;
944 err:
945 dev_dbg(&client->dev, "failed=%d\n", ret);
946 return ret;
947 }
948
949 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
950 {
951 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
952
953 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
954 *snr = div_s64(c->cnr.stat[0].svalue, 100);
955 else
956 *snr = 0;
957
958 return 0;
959 }
960
961 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
962 {
963 struct m88ds3103_dev *dev = fe->demodulator_priv;
964
965 *ber = dev->dvbv3_ber;
966
967 return 0;
968 }
969
970 static int m88ds3103_set_tone(struct dvb_frontend *fe,
971 enum fe_sec_tone_mode fe_sec_tone_mode)
972 {
973 struct m88ds3103_dev *dev = fe->demodulator_priv;
974 struct i2c_client *client = dev->client;
975 int ret;
976 unsigned int utmp, tone, reg_a1_mask;
977
978 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
979
980 if (!dev->warm) {
981 ret = -EAGAIN;
982 goto err;
983 }
984
985 switch (fe_sec_tone_mode) {
986 case SEC_TONE_ON:
987 tone = 0;
988 reg_a1_mask = 0x47;
989 break;
990 case SEC_TONE_OFF:
991 tone = 1;
992 reg_a1_mask = 0x00;
993 break;
994 default:
995 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
996 ret = -EINVAL;
997 goto err;
998 }
999
1000 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1001 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1002 if (ret)
1003 goto err;
1004
1005 utmp = 1 << 2;
1006 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1007 if (ret)
1008 goto err;
1009
1010 return 0;
1011 err:
1012 dev_dbg(&client->dev, "failed=%d\n", ret);
1013 return ret;
1014 }
1015
1016 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1017 enum fe_sec_voltage fe_sec_voltage)
1018 {
1019 struct m88ds3103_dev *dev = fe->demodulator_priv;
1020 struct i2c_client *client = dev->client;
1021 int ret;
1022 unsigned int utmp;
1023 bool voltage_sel, voltage_dis;
1024
1025 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1026
1027 if (!dev->warm) {
1028 ret = -EAGAIN;
1029 goto err;
1030 }
1031
1032 switch (fe_sec_voltage) {
1033 case SEC_VOLTAGE_18:
1034 voltage_sel = true;
1035 voltage_dis = false;
1036 break;
1037 case SEC_VOLTAGE_13:
1038 voltage_sel = false;
1039 voltage_dis = false;
1040 break;
1041 case SEC_VOLTAGE_OFF:
1042 voltage_sel = false;
1043 voltage_dis = true;
1044 break;
1045 default:
1046 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1047 ret = -EINVAL;
1048 goto err;
1049 }
1050
1051 /* output pin polarity */
1052 voltage_sel ^= dev->cfg->lnb_hv_pol;
1053 voltage_dis ^= dev->cfg->lnb_en_pol;
1054
1055 utmp = voltage_dis << 1 | voltage_sel << 0;
1056 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1057 if (ret)
1058 goto err;
1059
1060 return 0;
1061 err:
1062 dev_dbg(&client->dev, "failed=%d\n", ret);
1063 return ret;
1064 }
1065
1066 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1067 struct dvb_diseqc_master_cmd *diseqc_cmd)
1068 {
1069 struct m88ds3103_dev *dev = fe->demodulator_priv;
1070 struct i2c_client *client = dev->client;
1071 int ret;
1072 unsigned int utmp;
1073 unsigned long timeout;
1074
1075 dev_dbg(&client->dev, "msg=%*ph\n",
1076 diseqc_cmd->msg_len, diseqc_cmd->msg);
1077
1078 if (!dev->warm) {
1079 ret = -EAGAIN;
1080 goto err;
1081 }
1082
1083 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1084 ret = -EINVAL;
1085 goto err;
1086 }
1087
1088 utmp = dev->cfg->envelope_mode << 5;
1089 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1090 if (ret)
1091 goto err;
1092
1093 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1094 diseqc_cmd->msg_len);
1095 if (ret)
1096 goto err;
1097
1098 ret = regmap_write(dev->regmap, 0xa1,
1099 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1100 if (ret)
1101 goto err;
1102
1103 /* wait DiSEqC TX ready */
1104 #define SEND_MASTER_CMD_TIMEOUT 120
1105 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1106
1107 /* DiSEqC message period is 13.5 ms per byte */
1108 utmp = diseqc_cmd->msg_len * 13500;
1109 usleep_range(utmp - 4000, utmp);
1110
1111 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1112 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1113 if (ret)
1114 goto err;
1115 utmp = (utmp >> 6) & 0x1;
1116 }
1117
1118 if (utmp == 0) {
1119 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1120 jiffies_to_msecs(jiffies) -
1121 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1122 } else {
1123 dev_dbg(&client->dev, "diseqc tx timeout\n");
1124
1125 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1126 if (ret)
1127 goto err;
1128 }
1129
1130 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1131 if (ret)
1132 goto err;
1133
1134 if (utmp == 1) {
1135 ret = -ETIMEDOUT;
1136 goto err;
1137 }
1138
1139 return 0;
1140 err:
1141 dev_dbg(&client->dev, "failed=%d\n", ret);
1142 return ret;
1143 }
1144
1145 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1146 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1147 {
1148 struct m88ds3103_dev *dev = fe->demodulator_priv;
1149 struct i2c_client *client = dev->client;
1150 int ret;
1151 unsigned int utmp, burst;
1152 unsigned long timeout;
1153
1154 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1155
1156 if (!dev->warm) {
1157 ret = -EAGAIN;
1158 goto err;
1159 }
1160
1161 utmp = dev->cfg->envelope_mode << 5;
1162 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1163 if (ret)
1164 goto err;
1165
1166 switch (fe_sec_mini_cmd) {
1167 case SEC_MINI_A:
1168 burst = 0x02;
1169 break;
1170 case SEC_MINI_B:
1171 burst = 0x01;
1172 break;
1173 default:
1174 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1175 ret = -EINVAL;
1176 goto err;
1177 }
1178
1179 ret = regmap_write(dev->regmap, 0xa1, burst);
1180 if (ret)
1181 goto err;
1182
1183 /* wait DiSEqC TX ready */
1184 #define SEND_BURST_TIMEOUT 40
1185 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1186
1187 /* DiSEqC ToneBurst period is 12.5 ms */
1188 usleep_range(8500, 12500);
1189
1190 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1191 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1192 if (ret)
1193 goto err;
1194 utmp = (utmp >> 6) & 0x1;
1195 }
1196
1197 if (utmp == 0) {
1198 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1199 jiffies_to_msecs(jiffies) -
1200 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1201 } else {
1202 dev_dbg(&client->dev, "diseqc tx timeout\n");
1203
1204 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1205 if (ret)
1206 goto err;
1207 }
1208
1209 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1210 if (ret)
1211 goto err;
1212
1213 if (utmp == 1) {
1214 ret = -ETIMEDOUT;
1215 goto err;
1216 }
1217
1218 return 0;
1219 err:
1220 dev_dbg(&client->dev, "failed=%d\n", ret);
1221 return ret;
1222 }
1223
1224 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1225 struct dvb_frontend_tune_settings *s)
1226 {
1227 s->min_delay_ms = 3000;
1228
1229 return 0;
1230 }
1231
1232 static void m88ds3103_release(struct dvb_frontend *fe)
1233 {
1234 struct m88ds3103_dev *dev = fe->demodulator_priv;
1235 struct i2c_client *client = dev->client;
1236
1237 i2c_unregister_device(client);
1238 }
1239
1240 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1241 {
1242 struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1243 struct i2c_client *client = dev->client;
1244 int ret;
1245 struct i2c_msg msg = {
1246 .addr = client->addr,
1247 .flags = 0,
1248 .len = 2,
1249 .buf = "\x03\x11",
1250 };
1251
1252 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1253 ret = __i2c_transfer(client->adapter, &msg, 1);
1254 if (ret != 1) {
1255 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1256 if (ret >= 0)
1257 ret = -EREMOTEIO;
1258 return ret;
1259 }
1260
1261 return 0;
1262 }
1263
1264 /*
1265 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1266 * proper I2C client for legacy media attach binding.
1267 * New users must use I2C client binding directly!
1268 */
1269 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1270 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1271 {
1272 struct i2c_client *client;
1273 struct i2c_board_info board_info;
1274 struct m88ds3103_platform_data pdata;
1275
1276 pdata.clk = cfg->clock;
1277 pdata.i2c_wr_max = cfg->i2c_wr_max;
1278 pdata.ts_mode = cfg->ts_mode;
1279 pdata.ts_clk = cfg->ts_clk;
1280 pdata.ts_clk_pol = cfg->ts_clk_pol;
1281 pdata.spec_inv = cfg->spec_inv;
1282 pdata.agc = cfg->agc;
1283 pdata.agc_inv = cfg->agc_inv;
1284 pdata.clk_out = cfg->clock_out;
1285 pdata.envelope_mode = cfg->envelope_mode;
1286 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1287 pdata.lnb_en_pol = cfg->lnb_en_pol;
1288 pdata.attach_in_use = true;
1289
1290 memset(&board_info, 0, sizeof(board_info));
1291 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1292 board_info.addr = cfg->i2c_addr;
1293 board_info.platform_data = &pdata;
1294 client = i2c_new_device(i2c, &board_info);
1295 if (!client || !client->dev.driver)
1296 return NULL;
1297
1298 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1299 return pdata.get_dvb_frontend(client);
1300 }
1301 EXPORT_SYMBOL(m88ds3103_attach);
1302
1303 static struct dvb_frontend_ops m88ds3103_ops = {
1304 .delsys = {SYS_DVBS, SYS_DVBS2},
1305 .info = {
1306 .name = "Montage Technology M88DS3103",
1307 .frequency_min = 950000,
1308 .frequency_max = 2150000,
1309 .frequency_tolerance = 5000,
1310 .symbol_rate_min = 1000000,
1311 .symbol_rate_max = 45000000,
1312 .caps = FE_CAN_INVERSION_AUTO |
1313 FE_CAN_FEC_1_2 |
1314 FE_CAN_FEC_2_3 |
1315 FE_CAN_FEC_3_4 |
1316 FE_CAN_FEC_4_5 |
1317 FE_CAN_FEC_5_6 |
1318 FE_CAN_FEC_6_7 |
1319 FE_CAN_FEC_7_8 |
1320 FE_CAN_FEC_8_9 |
1321 FE_CAN_FEC_AUTO |
1322 FE_CAN_QPSK |
1323 FE_CAN_RECOVER |
1324 FE_CAN_2G_MODULATION
1325 },
1326
1327 .release = m88ds3103_release,
1328
1329 .get_tune_settings = m88ds3103_get_tune_settings,
1330
1331 .init = m88ds3103_init,
1332 .sleep = m88ds3103_sleep,
1333
1334 .set_frontend = m88ds3103_set_frontend,
1335 .get_frontend = m88ds3103_get_frontend,
1336
1337 .read_status = m88ds3103_read_status,
1338 .read_snr = m88ds3103_read_snr,
1339 .read_ber = m88ds3103_read_ber,
1340
1341 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1342 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1343
1344 .set_tone = m88ds3103_set_tone,
1345 .set_voltage = m88ds3103_set_voltage,
1346 };
1347
1348 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1349 {
1350 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1351
1352 dev_dbg(&client->dev, "\n");
1353
1354 return &dev->fe;
1355 }
1356
1357 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1358 {
1359 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1360
1361 dev_dbg(&client->dev, "\n");
1362
1363 return dev->muxc->adapter[0];
1364 }
1365
1366 static int m88ds3103_probe(struct i2c_client *client,
1367 const struct i2c_device_id *id)
1368 {
1369 struct m88ds3103_dev *dev;
1370 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1371 int ret;
1372 unsigned int utmp;
1373
1374 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1375 if (!dev) {
1376 ret = -ENOMEM;
1377 goto err;
1378 }
1379
1380 dev->client = client;
1381 dev->config.clock = pdata->clk;
1382 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1383 dev->config.ts_mode = pdata->ts_mode;
1384 dev->config.ts_clk = pdata->ts_clk;
1385 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1386 dev->config.spec_inv = pdata->spec_inv;
1387 dev->config.agc_inv = pdata->agc_inv;
1388 dev->config.clock_out = pdata->clk_out;
1389 dev->config.envelope_mode = pdata->envelope_mode;
1390 dev->config.agc = pdata->agc;
1391 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1392 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1393 dev->cfg = &dev->config;
1394 /* create regmap */
1395 dev->regmap_config.reg_bits = 8,
1396 dev->regmap_config.val_bits = 8,
1397 dev->regmap_config.lock_arg = dev,
1398 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1399 if (IS_ERR(dev->regmap)) {
1400 ret = PTR_ERR(dev->regmap);
1401 goto err_kfree;
1402 }
1403
1404 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1405 ret = regmap_read(dev->regmap, 0x00, &utmp);
1406 if (ret)
1407 goto err_kfree;
1408
1409 dev->chip_id = utmp >> 1;
1410 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1411
1412 switch (dev->chip_id) {
1413 case M88RS6000_CHIP_ID:
1414 case M88DS3103_CHIP_ID:
1415 break;
1416 default:
1417 goto err_kfree;
1418 }
1419
1420 switch (dev->cfg->clock_out) {
1421 case M88DS3103_CLOCK_OUT_DISABLED:
1422 utmp = 0x80;
1423 break;
1424 case M88DS3103_CLOCK_OUT_ENABLED:
1425 utmp = 0x00;
1426 break;
1427 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1428 utmp = 0x10;
1429 break;
1430 default:
1431 ret = -EINVAL;
1432 goto err_kfree;
1433 }
1434
1435 if (!pdata->ts_clk) {
1436 ret = -EINVAL;
1437 goto err_kfree;
1438 }
1439
1440 /* 0x29 register is defined differently for m88rs6000. */
1441 /* set internal tuner address to 0x21 */
1442 if (dev->chip_id == M88RS6000_CHIP_ID)
1443 utmp = 0x00;
1444
1445 ret = regmap_write(dev->regmap, 0x29, utmp);
1446 if (ret)
1447 goto err_kfree;
1448
1449 /* sleep */
1450 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1451 if (ret)
1452 goto err_kfree;
1453 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1454 if (ret)
1455 goto err_kfree;
1456 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1457 if (ret)
1458 goto err_kfree;
1459
1460 /* create mux i2c adapter for tuner */
1461 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1462 m88ds3103_select, NULL);
1463 if (!dev->muxc) {
1464 ret = -ENOMEM;
1465 goto err_kfree;
1466 }
1467 dev->muxc->priv = dev;
1468 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1469 if (ret)
1470 goto err_kfree;
1471
1472 /* create dvb_frontend */
1473 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1474 if (dev->chip_id == M88RS6000_CHIP_ID)
1475 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1476 sizeof(dev->fe.ops.info.name));
1477 if (!pdata->attach_in_use)
1478 dev->fe.ops.release = NULL;
1479 dev->fe.demodulator_priv = dev;
1480 i2c_set_clientdata(client, dev);
1481
1482 /* setup callbacks */
1483 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1484 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1485 return 0;
1486 err_kfree:
1487 kfree(dev);
1488 err:
1489 dev_dbg(&client->dev, "failed=%d\n", ret);
1490 return ret;
1491 }
1492
1493 static int m88ds3103_remove(struct i2c_client *client)
1494 {
1495 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1496
1497 dev_dbg(&client->dev, "\n");
1498
1499 i2c_mux_del_adapters(dev->muxc);
1500
1501 kfree(dev);
1502 return 0;
1503 }
1504
1505 static const struct i2c_device_id m88ds3103_id_table[] = {
1506 {"m88ds3103", 0},
1507 {}
1508 };
1509 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1510
1511 static struct i2c_driver m88ds3103_driver = {
1512 .driver = {
1513 .name = "m88ds3103",
1514 .suppress_bind_attrs = true,
1515 },
1516 .probe = m88ds3103_probe,
1517 .remove = m88ds3103_remove,
1518 .id_table = m88ds3103_id_table,
1519 };
1520
1521 module_i2c_driver(m88ds3103_driver);
1522
1523 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1524 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1525 MODULE_LICENSE("GPL");
1526 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1527 MODULE_FIRMWARE(M88RS6000_FIRMWARE);
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