?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: integrator: delete static UART1 mapping
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-integrator / integrator_ap.c
blob771cbe44b66243c5a000d287384c2fce59375f20
1 /*
2 * linux/arch/arm/mach-integrator/integrator_ap.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/mtd/physmap.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/clk-integrator.h>
37 #include <linux/of_irq.h>
38 #include <linux/of_address.h>
39 #include <linux/of_platform.h>
40 #include <linux/stat.h>
41 #include <linux/sys_soc.h>
42 #include <video/vga.h>
43
44 #include <mach/hardware.h>
45 #include <mach/platform.h>
46 #include <asm/hardware/arm_timer.h>
47 #include <asm/setup.h>
48 #include <asm/param.h> /* HZ */
49 #include <asm/mach-types.h>
50 #include <asm/sched_clock.h>
51
52 #include <mach/lm.h>
53 #include <mach/irqs.h>
54
55 #include <asm/mach/arch.h>
56 #include <asm/mach/irq.h>
57 #include <asm/mach/map.h>
58 #include <asm/mach/pci.h>
59 #include <asm/mach/time.h>
60
61 #include <plat/fpga-irq.h>
62
63 #include "common.h"
64
65 /* Base address to the AP system controller */
66 static void __iomem *ap_syscon_base;
67
68 /*
69 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
70 * is the (PA >> 12).
71 *
72 * Setup a VA for the Integrator interrupt controller (for header #0,
73 * just for now).
74 */
75 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
76 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
77 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
78
79 /*
80 * Logical Physical
81 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
82 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
83 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
84 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
85 * ef000000 Cache flush
86 * f1000000 10000000 Core module registers
87 * f1100000 11000000 System controller registers
88 * f1200000 12000000 EBI registers
89 * f1300000 13000000 Counter/Timer
90 * f1400000 14000000 Interrupt controller
91 * f1600000 16000000 UART 0
92 * f1700000 17000000 UART 1
93 * f1a00000 1a000000 Debug LEDs
94 * f1b00000 1b000000 GPIO
95 */
96
97 static struct map_desc ap_io_desc[] __initdata = {
98 {
99 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
129 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
130 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }, {
134 .virtual = (unsigned long)PCI_MEMORY_VADDR,
135 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
136 .length = SZ_16M,
137 .type = MT_DEVICE
138 }, {
139 .virtual = (unsigned long)PCI_CONFIG_VADDR,
140 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
141 .length = SZ_16M,
142 .type = MT_DEVICE
143 }, {
144 .virtual = (unsigned long)PCI_V3_VADDR,
145 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
146 .length = SZ_64K,
147 .type = MT_DEVICE
148 }
149 };
150
151 static void __init ap_map_io(void)
152 {
153 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
154 vga_base = (unsigned long)PCI_MEMORY_VADDR;
155 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
156 }
157
158 #ifdef CONFIG_PM
159 static unsigned long ic_irq_enable;
160
161 static int irq_suspend(void)
162 {
163 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
164 return 0;
165 }
166
167 static void irq_resume(void)
168 {
169 /* disable all irq sources */
170 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
171 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
172 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
173
174 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
175 }
176 #else
177 #define irq_suspend NULL
178 #define irq_resume NULL
179 #endif
180
181 static struct syscore_ops irq_syscore_ops = {
182 .suspend = irq_suspend,
183 .resume = irq_resume,
184 };
185
186 static int __init irq_syscore_init(void)
187 {
188 register_syscore_ops(&irq_syscore_ops);
189
190 return 0;
191 }
192
193 device_initcall(irq_syscore_init);
194
195 /*
196 * Flash handling.
197 */
198 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
199 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
200
201 static int ap_flash_init(struct platform_device *dev)
202 {
203 u32 tmp;
204
205 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
206 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
207
208 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
209 writel(tmp, EBI_CSR1);
210
211 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
212 writel(0xa05f, EBI_LOCK);
213 writel(tmp, EBI_CSR1);
214 writel(0, EBI_LOCK);
215 }
216 return 0;
217 }
218
219 static void ap_flash_exit(struct platform_device *dev)
220 {
221 u32 tmp;
222
223 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
224 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
225
226 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
227 writel(tmp, EBI_CSR1);
228
229 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
230 writel(0xa05f, EBI_LOCK);
231 writel(tmp, EBI_CSR1);
232 writel(0, EBI_LOCK);
233 }
234 }
235
236 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
237 {
238 if (on)
239 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
240 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
241 else
242 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
243 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
244 }
245
246 static struct physmap_flash_data ap_flash_data = {
247 .width = 4,
248 .init = ap_flash_init,
249 .exit = ap_flash_exit,
250 .set_vpp = ap_flash_set_vpp,
251 };
252
253 /*
254 * Where is the timer (VA)?
255 */
256 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
257 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
258 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
259
260 static unsigned long timer_reload;
261
262 static u32 notrace integrator_read_sched_clock(void)
263 {
264 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
265 }
266
267 static void integrator_clocksource_init(unsigned long inrate,
268 void __iomem *base)
269 {
270 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
271 unsigned long rate = inrate;
272
273 if (rate >= 1500000) {
274 rate /= 16;
275 ctrl |= TIMER_CTRL_DIV16;
276 }
277
278 writel(0xffff, base + TIMER_LOAD);
279 writel(ctrl, base + TIMER_CTRL);
280
281 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
282 rate, 200, 16, clocksource_mmio_readl_down);
283 setup_sched_clock(integrator_read_sched_clock, 16, rate);
284 }
285
286 static void __iomem * clkevt_base;
287
288 /*
289 * IRQ handler for the timer
290 */
291 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
292 {
293 struct clock_event_device *evt = dev_id;
294
295 /* clear the interrupt */
296 writel(1, clkevt_base + TIMER_INTCLR);
297
298 evt->event_handler(evt);
299
300 return IRQ_HANDLED;
301 }
302
303 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
304 {
305 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
306
307 /* Disable timer */
308 writel(ctrl, clkevt_base + TIMER_CTRL);
309
310 switch (mode) {
311 case CLOCK_EVT_MODE_PERIODIC:
312 /* Enable the timer and start the periodic tick */
313 writel(timer_reload, clkevt_base + TIMER_LOAD);
314 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
315 writel(ctrl, clkevt_base + TIMER_CTRL);
316 break;
317 case CLOCK_EVT_MODE_ONESHOT:
318 /* Leave the timer disabled, .set_next_event will enable it */
319 ctrl &= ~TIMER_CTRL_PERIODIC;
320 writel(ctrl, clkevt_base + TIMER_CTRL);
321 break;
322 case CLOCK_EVT_MODE_UNUSED:
323 case CLOCK_EVT_MODE_SHUTDOWN:
324 case CLOCK_EVT_MODE_RESUME:
325 default:
326 /* Just leave in disabled state */
327 break;
328 }
329
330 }
331
332 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
333 {
334 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
335
336 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
337 writel(next, clkevt_base + TIMER_LOAD);
338 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
339
340 return 0;
341 }
342
343 static struct clock_event_device integrator_clockevent = {
344 .name = "timer1",
345 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
346 .set_mode = clkevt_set_mode,
347 .set_next_event = clkevt_set_next_event,
348 .rating = 300,
349 };
350
351 static struct irqaction integrator_timer_irq = {
352 .name = "timer",
353 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
354 .handler = integrator_timer_interrupt,
355 .dev_id = &integrator_clockevent,
356 };
357
358 static void integrator_clockevent_init(unsigned long inrate,
359 void __iomem *base, int irq)
360 {
361 unsigned long rate = inrate;
362 unsigned int ctrl = 0;
363
364 clkevt_base = base;
365 /* Calculate and program a divisor */
366 if (rate > 0x100000 * HZ) {
367 rate /= 256;
368 ctrl |= TIMER_CTRL_DIV256;
369 } else if (rate > 0x10000 * HZ) {
370 rate /= 16;
371 ctrl |= TIMER_CTRL_DIV16;
372 }
373 timer_reload = rate / HZ;
374 writel(ctrl, clkevt_base + TIMER_CTRL);
375
376 setup_irq(irq, &integrator_timer_irq);
377 clockevents_config_and_register(&integrator_clockevent,
378 rate,
379 1,
380 0xffffU);
381 }
382
383 void __init ap_init_early(void)
384 {
385 }
386
387 #ifdef CONFIG_OF
388
389 static void __init ap_init_timer_of(void)
390 {
391 struct device_node *node;
392 const char *path;
393 void __iomem *base;
394 int err;
395 int irq;
396 struct clk *clk;
397 unsigned long rate;
398
399 clk = clk_get_sys("ap_timer", NULL);
400 BUG_ON(IS_ERR(clk));
401 clk_prepare_enable(clk);
402 rate = clk_get_rate(clk);
403
404 err = of_property_read_string(of_aliases,
405 "arm,timer-primary", &path);
406 if (WARN_ON(err))
407 return;
408 node = of_find_node_by_path(path);
409 base = of_iomap(node, 0);
410 if (WARN_ON(!base))
411 return;
412 writel(0, base + TIMER_CTRL);
413 integrator_clocksource_init(rate, base);
414
415 err = of_property_read_string(of_aliases,
416 "arm,timer-secondary", &path);
417 if (WARN_ON(err))
418 return;
419 node = of_find_node_by_path(path);
420 base = of_iomap(node, 0);
421 if (WARN_ON(!base))
422 return;
423 irq = irq_of_parse_and_map(node, 0);
424 writel(0, base + TIMER_CTRL);
425 integrator_clockevent_init(rate, base, irq);
426 }
427
428 static struct sys_timer ap_of_timer = {
429 .init = ap_init_timer_of,
430 };
431
432 static const struct of_device_id fpga_irq_of_match[] __initconst = {
433 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
434 { /* Sentinel */ }
435 };
436
437 static void __init ap_init_irq_of(void)
438 {
439 /* disable core module IRQs */
440 writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
441 of_irq_init(fpga_irq_of_match);
442 integrator_clk_init(false);
443 }
444
445 /* For the Device Tree, add in the UART callbacks as AUXDATA */
446 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
447 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
448 "rtc", NULL),
449 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
450 "uart0", &integrator_uart_data),
451 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
452 "uart1", &integrator_uart_data),
453 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
454 "kmi0", NULL),
455 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
456 "kmi1", NULL),
457 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
458 "physmap-flash", &ap_flash_data),
459 { /* sentinel */ },
460 };
461
462 static void __init ap_init_of(void)
463 {
464 unsigned long sc_dec;
465 struct device_node *root;
466 struct device_node *syscon;
467 struct device *parent;
468 struct soc_device *soc_dev;
469 struct soc_device_attribute *soc_dev_attr;
470 u32 ap_sc_id;
471 int err;
472 int i;
473
474 /* Here we create an SoC device for the root node */
475 root = of_find_node_by_path("/");
476 if (!root)
477 return;
478 syscon = of_find_node_by_path("/syscon");
479 if (!syscon)
480 return;
481
482 ap_syscon_base = of_iomap(syscon, 0);
483 if (!ap_syscon_base)
484 return;
485
486 ap_sc_id = readl(ap_syscon_base);
487
488 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
489 if (!soc_dev_attr)
490 return;
491
492 err = of_property_read_string(root, "compatible",
493 &soc_dev_attr->soc_id);
494 if (err)
495 return;
496 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
497 if (err)
498 return;
499 soc_dev_attr->family = "Integrator";
500 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
501 'A' + (ap_sc_id & 0x0f));
502
503 soc_dev = soc_device_register(soc_dev_attr);
504 if (IS_ERR_OR_NULL(soc_dev)) {
505 kfree(soc_dev_attr->revision);
506 kfree(soc_dev_attr);
507 return;
508 }
509
510 parent = soc_device_to_device(soc_dev);
511
512 if (!IS_ERR_OR_NULL(parent))
513 integrator_init_sysfs(parent, ap_sc_id);
514
515 of_platform_populate(root, of_default_bus_match_table,
516 ap_auxdata_lookup, parent);
517
518 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
519 for (i = 0; i < 4; i++) {
520 struct lm_device *lmdev;
521
522 if ((sc_dec & (16 << i)) == 0)
523 continue;
524
525 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
526 if (!lmdev)
527 continue;
528
529 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
530 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
531 lmdev->resource.flags = IORESOURCE_MEM;
532 lmdev->irq = IRQ_AP_EXPINT0 + i;
533 lmdev->id = i;
534
535 lm_device_register(lmdev);
536 }
537 }
538
539 static const char * ap_dt_board_compat[] = {
540 "arm,integrator-ap",
541 NULL,
542 };
543
544 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
545 .reserve = integrator_reserve,
546 .map_io = ap_map_io,
547 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
548 .init_early = ap_init_early,
549 .init_irq = ap_init_irq_of,
550 .handle_irq = fpga_handle_irq,
551 .timer = &ap_of_timer,
552 .init_machine = ap_init_of,
553 .restart = integrator_restart,
554 .dt_compat = ap_dt_board_compat,
555 MACHINE_END
556
557 #endif
558
559 #ifdef CONFIG_ATAGS
560
561 /*
562 * For the ATAG boot some static mappings are needed. This will
563 * go away with the ATAG support down the road.
564 */
565
566 static struct map_desc ap_io_desc_atag[] __initdata = {
567 {
568 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
569 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
570 .length = SZ_4K,
571 .type = MT_DEVICE
572 },
573 };
574
575 static void __init ap_map_io_atag(void)
576 {
577 iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
578 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
579 ap_map_io();
580 }
581
582 /*
583 * This is where non-devicetree initialization code is collected and stashed
584 * for eventual deletion.
585 */
586
587 static struct resource cfi_flash_resource = {
588 .start = INTEGRATOR_FLASH_BASE,
589 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
590 .flags = IORESOURCE_MEM,
591 };
592
593 static struct platform_device cfi_flash_device = {
594 .name = "physmap-flash",
595 .id = 0,
596 .dev = {
597 .platform_data = &ap_flash_data,
598 },
599 .num_resources = 1,
600 .resource = &cfi_flash_resource,
601 };
602
603 static void __init ap_init_timer(void)
604 {
605 struct clk *clk;
606 unsigned long rate;
607
608 clk = clk_get_sys("ap_timer", NULL);
609 BUG_ON(IS_ERR(clk));
610 clk_prepare_enable(clk);
611 rate = clk_get_rate(clk);
612
613 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
614 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
615 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
616
617 integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
618 integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
619 IRQ_TIMERINT1);
620 }
621
622 static struct sys_timer ap_timer = {
623 .init = ap_init_timer,
624 };
625
626 #define INTEGRATOR_SC_VALID_INT 0x003fffff
627
628 static void __init ap_init_irq(void)
629 {
630 /* Disable all interrupts initially. */
631 /* Do the core module ones */
632 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
633
634 /* do the header card stuff next */
635 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
636 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
637
638 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
639 -1, INTEGRATOR_SC_VALID_INT, NULL);
640 integrator_clk_init(false);
641 }
642
643 static void __init ap_init(void)
644 {
645 unsigned long sc_dec;
646 int i;
647
648 platform_device_register(&cfi_flash_device);
649
650 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
651 for (i = 0; i < 4; i++) {
652 struct lm_device *lmdev;
653
654 if ((sc_dec & (16 << i)) == 0)
655 continue;
656
657 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
658 if (!lmdev)
659 continue;
660
661 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
662 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
663 lmdev->resource.flags = IORESOURCE_MEM;
664 lmdev->irq = IRQ_AP_EXPINT0 + i;
665 lmdev->id = i;
666
667 lm_device_register(lmdev);
668 }
669
670 integrator_init(false);
671 }
672
673 MACHINE_START(INTEGRATOR, "ARM-Integrator")
674 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
675 .atag_offset = 0x100,
676 .reserve = integrator_reserve,
677 .map_io = ap_map_io_atag,
678 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
679 .init_early = ap_init_early,
680 .init_irq = ap_init_irq,
681 .handle_irq = fpga_handle_irq,
682 .timer = &ap_timer,
683 .init_machine = ap_init,
684 .restart = integrator_restart,
685 MACHINE_END
686
687 #endif
(deprecated) Btrfs devel tree