1 /****************************************************************************
2 * Driver for Solarflare 802.3an compliant PHY
3 * Copyright 2007 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/seq_file.h>
17 #include "falcon_hwdefs.h"
21 /* We expect these MMDs to be in the package */
22 /* AN not here as mdio_check_mmds() requires STAT2 support */
23 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
24 MDIO_MMDREG_DEVS0_PCS | \
25 MDIO_MMDREG_DEVS0_PHYXS)
27 #define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
28 (1 << LOOPBACK_PCS) | \
29 (1 << LOOPBACK_PMAPMD) | \
30 (1 << LOOPBACK_NETWORK))
32 /* We complain if we fail to see the link partner as 10G capable this many
33 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
35 #define MAX_BAD_LP_TRIES (5)
37 /* Extended control register */
38 #define PMA_PMD_XCONTROL_REG 0xc000
39 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8
40 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
42 /* extended status register */
43 #define PMA_PMD_XSTATUS_REG 0xc001
44 #define PMA_PMD_XSTAT_FLP_LBN (12)
46 /* LED control register */
47 #define PMA_PMD_LED_CTRL_REG (0xc007)
48 #define PMA_PMA_LED_ACTIVITY_LBN (3)
50 /* LED function override register */
51 #define PMA_PMD_LED_OVERR_REG (0xc009)
52 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
53 #define PMA_PMD_LED_LINK_LBN (0)
54 #define PMA_PMD_LED_SPEED_LBN (2)
55 #define PMA_PMD_LED_TX_LBN (4)
56 #define PMA_PMD_LED_RX_LBN (6)
57 /* Override settings */
58 #define PMA_PMD_LED_AUTO (0) /* H/W control */
59 #define PMA_PMD_LED_ON (1)
60 #define PMA_PMD_LED_OFF (2)
61 #define PMA_PMD_LED_FLASH (3)
62 /* All LEDs under hardware control */
63 #define PMA_PMD_LED_FULL_AUTO (0)
64 /* Green and Amber under hardware control, Red off */
65 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
68 /* Self test (BIST) control register */
69 #define PMA_PMD_BIST_CTRL_REG (0xc014)
70 #define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */
71 #define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */
72 #define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */
73 /* Self test status register */
74 #define PMA_PMD_BIST_STAT_REG (0xc015)
75 #define PMA_PMD_BIST_ENX_LBN (3)
76 #define PMA_PMD_BIST_PMA_LBN (2)
77 #define PMA_PMD_BIST_RXD_LBN (1)
78 #define PMA_PMD_BIST_AFE_LBN (0)
80 /* Special Software reset register */
81 #define PMA_PMD_EXT_CTRL_REG 49152
82 #define PMA_PMD_EXT_SSR_LBN 15
84 #define BIST_MAX_DELAY (1000)
85 #define BIST_POLL_DELAY (10)
87 /* Misc register defines */
88 #define PCS_CLOCK_CTRL_REG 0xd801
89 #define PLL312_RST_N_LBN 2
91 #define PCS_SOFT_RST2_REG 0xd806
92 #define SERDES_RST_N_LBN 13
93 #define XGXS_RST_N_LBN 12
95 #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
96 #define CLK312_EN_LBN 3
99 #define PHYXS_TEST1 (49162)
100 #define LOOPBACK_NEAR_LBN (8)
101 #define LOOPBACK_NEAR_WIDTH (1)
103 /* Boot status register */
104 #define PCS_BOOT_STATUS_REG (0xd000)
105 #define PCS_BOOT_FATAL_ERR_LBN (0)
106 #define PCS_BOOT_PROGRESS_LBN (1)
107 #define PCS_BOOT_PROGRESS_WIDTH (2)
108 #define PCS_BOOT_COMPLETE_LBN (3)
109 #define PCS_BOOT_MAX_DELAY (100)
110 #define PCS_BOOT_POLL_DELAY (10)
112 /* Time to wait between powering down the LNPGA and turning off the power
114 #define LNPGA_PDOWN_WAIT (HZ / 5)
116 static int crc_error_reset_threshold
= 100;
117 module_param(crc_error_reset_threshold
, int, 0644);
118 MODULE_PARM_DESC(crc_error_reset_threshold
,
119 "Max number of CRC errors before XAUI reset");
121 struct tenxpress_phy_data
{
122 enum tenxpress_state state
;
123 enum efx_loopback_mode loopback_mode
;
124 atomic_t bad_crc_count
;
129 static int tenxpress_state_is(struct efx_nic
*efx
, int state
)
131 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
132 return (phy_data
!= NULL
) && (state
== phy_data
->state
);
135 void tenxpress_set_state(struct efx_nic
*efx
,
136 enum tenxpress_state state
)
138 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
139 if (phy_data
!= NULL
)
140 phy_data
->state
= state
;
143 void tenxpress_crc_err(struct efx_nic
*efx
)
145 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
146 if (phy_data
!= NULL
)
147 atomic_inc(&phy_data
->bad_crc_count
);
150 /* Check that the C166 has booted successfully */
151 static int tenxpress_phy_check(struct efx_nic
*efx
)
153 int phy_id
= efx
->mii
.phy_id
;
154 int count
= PCS_BOOT_MAX_DELAY
/ PCS_BOOT_POLL_DELAY
;
157 /* Wait for the boot to complete (or not) */
159 boot_stat
= mdio_clause45_read(efx
, phy_id
,
161 PCS_BOOT_STATUS_REG
);
162 if (boot_stat
& (1 << PCS_BOOT_COMPLETE_LBN
))
165 udelay(PCS_BOOT_POLL_DELAY
);
169 EFX_ERR(efx
, "%s: PHY boot timed out. Last status "
171 (boot_stat
>> PCS_BOOT_PROGRESS_LBN
) &
172 ((1 << PCS_BOOT_PROGRESS_WIDTH
) - 1));
179 static void tenxpress_reset_xaui(struct efx_nic
*efx
);
181 static int tenxpress_init(struct efx_nic
*efx
)
185 /* Turn on the clock */
186 reg
= (1 << CLK312_EN_LBN
);
187 mdio_clause45_write(efx
, efx
->mii
.phy_id
,
188 MDIO_MMD_PCS
, PCS_TEST_SELECT_REG
, reg
);
190 rc
= tenxpress_phy_check(efx
);
194 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
195 reg
= mdio_clause45_read(efx
, efx
->mii
.phy_id
,
196 MDIO_MMD_PMAPMD
, PMA_PMD_LED_CTRL_REG
);
197 reg
|= (1 << PMA_PMA_LED_ACTIVITY_LBN
);
198 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
199 PMA_PMD_LED_CTRL_REG
, reg
);
201 reg
= PMA_PMD_LED_DEFAULT
;
202 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
203 PMA_PMD_LED_OVERR_REG
, reg
);
208 static int tenxpress_phy_init(struct efx_nic
*efx
)
210 struct tenxpress_phy_data
*phy_data
;
213 phy_data
= kzalloc(sizeof(*phy_data
), GFP_KERNEL
);
214 efx
->phy_data
= phy_data
;
216 tenxpress_set_state(efx
, TENXPRESS_STATUS_NORMAL
);
218 if (!sfe4001_phy_flash_cfg
) {
219 rc
= mdio_clause45_wait_reset_mmds(efx
,
220 TENXPRESS_REQUIRED_DEVS
);
225 rc
= mdio_clause45_check_mmds(efx
, TENXPRESS_REQUIRED_DEVS
, 0);
229 rc
= tenxpress_init(efx
);
233 schedule_timeout_uninterruptible(HZ
/ 5); /* 200ms */
235 /* Let XGXS and SerDes out of reset and resets 10XPress */
236 falcon_reset_xaui(efx
);
241 kfree(efx
->phy_data
);
242 efx
->phy_data
= NULL
;
246 static int tenxpress_special_reset(struct efx_nic
*efx
)
250 EFX_TRACE(efx
, "%s\n", __func__
);
253 reg
= mdio_clause45_read(efx
, efx
->mii
.phy_id
,
254 MDIO_MMD_PMAPMD
, PMA_PMD_EXT_CTRL_REG
);
255 reg
|= (1 << PMA_PMD_EXT_SSR_LBN
);
256 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
257 PMA_PMD_EXT_CTRL_REG
, reg
);
261 /* Wait for the blocks to come out of reset */
262 rc
= mdio_clause45_wait_reset_mmds(efx
,
263 TENXPRESS_REQUIRED_DEVS
);
267 /* Try and reconfigure the device */
268 rc
= tenxpress_init(efx
);
275 static void tenxpress_set_bad_lp(struct efx_nic
*efx
, int bad_lp
)
277 struct tenxpress_phy_data
*pd
= efx
->phy_data
;
280 /* Nothing to do if all is well and was previously so. */
281 if (!(bad_lp
|| pd
->bad_lp_tries
))
284 reg
= mdio_clause45_read(efx
, efx
->mii
.phy_id
,
285 MDIO_MMD_PMAPMD
, PMA_PMD_LED_OVERR_REG
);
290 pd
->bad_lp_tries
= 0;
292 if (pd
->bad_lp_tries
== MAX_BAD_LP_TRIES
) {
293 pd
->bad_lp_tries
= 0; /* Restart count */
294 reg
&= ~(PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
);
295 reg
|= (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
);
296 EFX_ERR(efx
, "This NIC appears to be plugged into"
297 " a port that is not 10GBASE-T capable.\n"
298 " This PHY is 10GBASE-T ONLY, so no link can"
299 " be established.\n");
301 reg
|= (PMA_PMD_LED_OFF
<< PMA_PMD_LED_RX_LBN
);
303 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
304 PMA_PMD_LED_OVERR_REG
, reg
);
307 /* Check link status and return a boolean OK value. If the link is NOT
308 * OK we have a quick rummage round to see if we appear to be plugged
309 * into a non-10GBT port and if so warn the user that they won't get
310 * link any time soon as we are 10GBT only, unless caller specified
311 * not to do this check (it isn't useful in loopback) */
312 static int tenxpress_link_ok(struct efx_nic
*efx
, int check_lp
)
314 int ok
= mdio_clause45_links_ok(efx
, TENXPRESS_REQUIRED_DEVS
);
317 tenxpress_set_bad_lp(efx
, 0);
318 } else if (check_lp
) {
319 /* Are we plugged into the wrong sort of link? */
321 int phy_id
= efx
->mii
.phy_id
;
322 int an_stat
= mdio_clause45_read(efx
, phy_id
, MDIO_MMD_AN
,
324 int xphy_stat
= mdio_clause45_read(efx
, phy_id
,
326 PMA_PMD_XSTATUS_REG
);
327 /* Are we plugged into anything that sends FLPs? If
328 * not we can't distinguish between not being plugged
329 * in and being plugged into a non-AN antique. The FLP
330 * bit has the advantage of not clearing when autoneg
332 if (!(xphy_stat
& (1 << PMA_PMD_XSTAT_FLP_LBN
))) {
333 tenxpress_set_bad_lp(efx
, 0);
337 /* If it can do 10GBT it must be XNP capable */
338 bad_lp
= !(an_stat
& (1 << MDIO_AN_STATUS_XNP_LBN
));
339 if (!bad_lp
&& (an_stat
& (1 << MDIO_AN_STATUS_PAGE_LBN
))) {
340 bad_lp
= !(mdio_clause45_read(efx
, phy_id
,
341 MDIO_MMD_AN
, MDIO_AN_10GBT_STATUS
) &
342 (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN
));
344 tenxpress_set_bad_lp(efx
, bad_lp
);
349 static void tenxpress_phyxs_loopback(struct efx_nic
*efx
)
351 int phy_id
= efx
->mii
.phy_id
;
354 ctrl1
= ctrl2
= mdio_clause45_read(efx
, phy_id
, MDIO_MMD_PHYXS
,
356 if (efx
->loopback_mode
== LOOPBACK_PHYXS
)
357 ctrl2
|= (1 << LOOPBACK_NEAR_LBN
);
359 ctrl2
&= ~(1 << LOOPBACK_NEAR_LBN
);
361 mdio_clause45_write(efx
, phy_id
, MDIO_MMD_PHYXS
,
365 static void tenxpress_phy_reconfigure(struct efx_nic
*efx
)
367 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
368 int loop_change
= LOOPBACK_OUT_OF(phy_data
, efx
,
369 TENXPRESS_LOOPBACKS
);
371 if (!tenxpress_state_is(efx
, TENXPRESS_STATUS_NORMAL
))
374 /* When coming out of transmit disable, coming out of low power
375 * mode, or moving out of any PHY internal loopback mode,
376 * perform a special software reset */
377 if ((phy_data
->tx_disabled
&& !efx
->tx_disabled
) ||
379 (void) tenxpress_special_reset(efx
);
380 falcon_reset_xaui(efx
);
383 mdio_clause45_transmit_disable(efx
);
384 mdio_clause45_phy_reconfigure(efx
);
385 tenxpress_phyxs_loopback(efx
);
387 phy_data
->tx_disabled
= efx
->tx_disabled
;
388 phy_data
->loopback_mode
= efx
->loopback_mode
;
389 efx
->link_up
= tenxpress_link_ok(efx
, 0);
390 efx
->link_options
= GM_LPA_10000FULL
;
393 static void tenxpress_phy_clear_interrupt(struct efx_nic
*efx
)
395 /* Nothing done here - LASI interrupts aren't reliable so poll */
399 /* Poll PHY for interrupt */
400 static int tenxpress_phy_check_hw(struct efx_nic
*efx
)
402 struct tenxpress_phy_data
*phy_data
= efx
->phy_data
;
403 int phy_up
= tenxpress_state_is(efx
, TENXPRESS_STATUS_NORMAL
);
406 link_ok
= phy_up
&& tenxpress_link_ok(efx
, 1);
408 if (link_ok
!= efx
->link_up
)
409 falcon_xmac_sim_phy_event(efx
);
411 /* Nothing to check if we've already shut down the PHY */
415 if (atomic_read(&phy_data
->bad_crc_count
) > crc_error_reset_threshold
) {
416 EFX_ERR(efx
, "Resetting XAUI due to too many CRC errors\n");
417 falcon_reset_xaui(efx
);
418 atomic_set(&phy_data
->bad_crc_count
, 0);
424 static void tenxpress_phy_fini(struct efx_nic
*efx
)
428 /* Power down the LNPGA */
429 reg
= (1 << PMA_PMD_LNPGA_POWERDOWN_LBN
);
430 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
431 PMA_PMD_XCONTROL_REG
, reg
);
433 /* Waiting here ensures that the board fini, which can turn off the
434 * power to the PHY, won't get run until the LNPGA powerdown has been
435 * given long enough to complete. */
436 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT
); /* 200 ms */
438 kfree(efx
->phy_data
);
439 efx
->phy_data
= NULL
;
443 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
444 * (which probably aren't wired anyway) are left in AUTO mode */
445 void tenxpress_phy_blink(struct efx_nic
*efx
, int blink
)
450 reg
= (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_TX_LBN
) |
451 (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_RX_LBN
) |
452 (PMA_PMD_LED_FLASH
<< PMA_PMD_LED_LINK_LBN
);
454 reg
= PMA_PMD_LED_DEFAULT
;
456 mdio_clause45_write(efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
457 PMA_PMD_LED_OVERR_REG
, reg
);
460 static void tenxpress_reset_xaui(struct efx_nic
*efx
)
462 int phy
= efx
->mii
.phy_id
;
463 int clk_ctrl
, test_select
, soft_rst2
;
465 /* Real work is done on clock_ctrl other resets are thought to be
466 * optional but make the reset more reliable
470 clk_ctrl
= mdio_clause45_read(efx
, phy
, MDIO_MMD_PCS
,
472 test_select
= mdio_clause45_read(efx
, phy
, MDIO_MMD_PCS
,
473 PCS_TEST_SELECT_REG
);
474 soft_rst2
= mdio_clause45_read(efx
, phy
, MDIO_MMD_PCS
,
478 test_select
&= ~(1 << CLK312_EN_LBN
);
479 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
480 PCS_TEST_SELECT_REG
, test_select
);
482 soft_rst2
&= ~((1 << XGXS_RST_N_LBN
) | (1 << SERDES_RST_N_LBN
));
483 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
484 PCS_SOFT_RST2_REG
, soft_rst2
);
486 clk_ctrl
&= ~(1 << PLL312_RST_N_LBN
);
487 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
488 PCS_CLOCK_CTRL_REG
, clk_ctrl
);
492 clk_ctrl
|= (1 << PLL312_RST_N_LBN
);
493 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
494 PCS_CLOCK_CTRL_REG
, clk_ctrl
);
497 soft_rst2
|= ((1 << XGXS_RST_N_LBN
) | (1 << SERDES_RST_N_LBN
));
498 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
499 PCS_SOFT_RST2_REG
, soft_rst2
);
502 test_select
|= (1 << CLK312_EN_LBN
);
503 mdio_clause45_write(efx
, phy
, MDIO_MMD_PCS
,
504 PCS_TEST_SELECT_REG
, test_select
);
508 struct efx_phy_operations falcon_tenxpress_phy_ops
= {
509 .init
= tenxpress_phy_init
,
510 .reconfigure
= tenxpress_phy_reconfigure
,
511 .check_hw
= tenxpress_phy_check_hw
,
512 .fini
= tenxpress_phy_fini
,
513 .clear_interrupt
= tenxpress_phy_clear_interrupt
,
514 .reset_xaui
= tenxpress_reset_xaui
,
515 .mmds
= TENXPRESS_REQUIRED_DEVS
,
516 .loopbacks
= TENXPRESS_LOOPBACKS
,