drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #include <linux/version.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/timer.h>
  22 #include <linux/mii.h>
  23 #include <linux/list.h>
  24 #include <linux/pci.h>
  25 #include <linux/device.h>
  26 #include <linux/highmem.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/inet_lro.h>
  29
  30 #include "enum.h"
  31 #include "bitfield.h"
  32 #include "i2c-direct.h"
  33
  34 #define EFX_MAX_LRO_DESCRIPTORS 8
  35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
  36
  37 /**************************************************************************
  38  *
  39  * Build definitions
  40  *
  41  **************************************************************************/
  42 #ifndef EFX_DRIVER_NAME
  43 #define EFX_DRIVER_NAME "sfc"
  44 #endif
  45 #define EFX_DRIVER_VERSION      "2.2.0136"
  46
  47 #ifdef EFX_ENABLE_DEBUG
  48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  50 #else
  51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  53 #endif
  54
  55 #define NET_DEV_REGISTERED(efx)                                 \
  56         ((efx)->net_dev->reg_state == NETREG_REGISTERED)
  57
  58 /* Include net device name in log messages if it has been registered.
  59  * Use efx->name not efx->net_dev->name so that races with (un)registration
  60  * are harmless.
  61  */
  62 #define NET_DEV_NAME(efx) (NET_DEV_REGISTERED(efx) ? (efx)->name : "")
  63
  64 /* Un-rate-limited logging */
  65 #define EFX_ERR(efx, fmt, args...) \
  66 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, NET_DEV_NAME(efx), ##args)
  67
  68 #define EFX_INFO(efx, fmt, args...) \
  69 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, NET_DEV_NAME(efx), ##args)
  70
  71 #ifdef EFX_ENABLE_DEBUG
  72 #define EFX_LOG(efx, fmt, args...) \
  73 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  74 #else
  75 #define EFX_LOG(efx, fmt, args...) \
  76 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  77 #endif
  78
  79 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  80
  81 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  82
  83 /* Rate-limited logging */
  84 #define EFX_ERR_RL(efx, fmt, args...) \
  85 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  86
  87 #define EFX_INFO_RL(efx, fmt, args...) \
  88 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  89
  90 #define EFX_LOG_RL(efx, fmt, args...) \
  91 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  92
  93 /* Kernel headers may redefine inline anyway */
  94 #ifndef inline
  95 #define inline inline __attribute__ ((always_inline))
  96 #endif
  97
  98 /**************************************************************************
  99  *
 100  * Efx data structures
 101  *
 102  **************************************************************************/
 103
 104 #define EFX_MAX_CHANNELS 32
 105 #define EFX_MAX_TX_QUEUES 1
 106 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
 107
 108 /**
 109  * struct efx_special_buffer - An Efx special buffer
 110  * @addr: CPU base address of the buffer
 111  * @dma_addr: DMA base address of the buffer
 112  * @len: Buffer length, in bytes
 113  * @index: Buffer index within controller;s buffer table
 114  * @entries: Number of buffer table entries
 115  *
 116  * Special buffers are used for the event queues and the TX and RX
 117  * descriptor queues for each channel.  They are *not* used for the
 118  * actual transmit and receive buffers.
 119  *
 120  * Note that for Falcon, TX and RX descriptor queues live in host memory.
 121  * Allocation and freeing procedures must take this into account.
 122  */
 123 struct efx_special_buffer {
 124         void *addr;
 125         dma_addr_t dma_addr;
 126         unsigned int len;
 127         int index;
 128         int entries;
 129 };
 130
 131 /**
 132  * struct efx_tx_buffer - An Efx TX buffer
 133  * @skb: The associated socket buffer.
 134  *      Set only on the final fragment of a packet; %NULL for all other
 135  *      fragments.  When this fragment completes, then we can free this
 136  *      skb.
 137  * @tsoh: The associated TSO header structure, or %NULL if this
 138  *      buffer is not a TSO header.
 139  * @dma_addr: DMA address of the fragment.
 140  * @len: Length of this fragment.
 141  *      This field is zero when the queue slot is empty.
 142  * @continuation: True if this fragment is not the end of a packet.
 143  * @unmap_single: True if pci_unmap_single should be used.
 144  * @unmap_addr: DMA address to unmap
 145  * @unmap_len: Length of this fragment to unmap
 146  */
 147 struct efx_tx_buffer {
 148         const struct sk_buff *skb;
 149         struct efx_tso_header *tsoh;
 150         dma_addr_t dma_addr;
 151         unsigned short len;
 152         unsigned char continuation;
 153         unsigned char unmap_single;
 154         dma_addr_t unmap_addr;
 155         unsigned short unmap_len;
 156 };
 157
 158 /**
 159  * struct efx_tx_queue - An Efx TX queue
 160  *
 161  * This is a ring buffer of TX fragments.
 162  * Since the TX completion path always executes on the same
 163  * CPU and the xmit path can operate on different CPUs,
 164  * performance is increased by ensuring that the completion
 165  * path and the xmit path operate on different cache lines.
 166  * This is particularly important if the xmit path is always
 167  * executing on one CPU which is different from the completion
 168  * path.  There is also a cache line for members which are
 169  * read but not written on the fast path.
 170  *
 171  * @efx: The associated Efx NIC
 172  * @queue: DMA queue number
 173  * @used: Queue is used by net driver
 174  * @channel: The associated channel
 175  * @buffer: The software buffer ring
 176  * @txd: The hardware descriptor ring
 177  * @read_count: Current read pointer.
 178  *      This is the number of buffers that have been removed from both rings.
 179  * @stopped: Stopped flag.
 180  *      Set if this TX queue is currently stopping its port.
 181  * @insert_count: Current insert pointer
 182  *      This is the number of buffers that have been added to the
 183  *      software ring.
 184  * @write_count: Current write pointer
 185  *      This is the number of buffers that have been added to the
 186  *      hardware ring.
 187  * @old_read_count: The value of read_count when last checked.
 188  *      This is here for performance reasons.  The xmit path will
 189  *      only get the up-to-date value of read_count if this
 190  *      variable indicates that the queue is full.  This is to
 191  *      avoid cache-line ping-pong between the xmit path and the
 192  *      completion path.
 193  * @tso_headers_free: A list of TSO headers allocated for this TX queue
 194  *      that are not in use, and so available for new TSO sends. The list
 195  *      is protected by the TX queue lock.
 196  * @tso_bursts: Number of times TSO xmit invoked by kernel
 197  * @tso_long_headers: Number of packets with headers too long for standard
 198  *      blocks
 199  * @tso_packets: Number of packets via the TSO xmit path
 200  */
 201 struct efx_tx_queue {
 202         /* Members which don't change on the fast path */
 203         struct efx_nic *efx ____cacheline_aligned_in_smp;
 204         int queue;
 205         int used;
 206         struct efx_channel *channel;
 207         struct efx_nic *nic;
 208         struct efx_tx_buffer *buffer;
 209         struct efx_special_buffer txd;
 210
 211         /* Members used mainly on the completion path */
 212         unsigned int read_count ____cacheline_aligned_in_smp;
 213         int stopped;
 214
 215         /* Members used only on the xmit path */
 216         unsigned int insert_count ____cacheline_aligned_in_smp;
 217         unsigned int write_count;
 218         unsigned int old_read_count;
 219         struct efx_tso_header *tso_headers_free;
 220         unsigned int tso_bursts;
 221         unsigned int tso_long_headers;
 222         unsigned int tso_packets;
 223 };
 224
 225 /**
 226  * struct efx_rx_buffer - An Efx RX data buffer
 227  * @dma_addr: DMA base address of the buffer
 228  * @skb: The associated socket buffer, if any.
 229  *      If both this and page are %NULL, the buffer slot is currently free.
 230  * @page: The associated page buffer, if any.
 231  *      If both this and skb are %NULL, the buffer slot is currently free.
 232  * @data: Pointer to ethernet header
 233  * @len: Buffer length, in bytes.
 234  * @unmap_addr: DMA address to unmap
 235  */
 236 struct efx_rx_buffer {
 237         dma_addr_t dma_addr;
 238         struct sk_buff *skb;
 239         struct page *page;
 240         char *data;
 241         unsigned int len;
 242         dma_addr_t unmap_addr;
 243 };
 244
 245 /**
 246  * struct efx_rx_queue - An Efx RX queue
 247  * @efx: The associated Efx NIC
 248  * @queue: DMA queue number
 249  * @used: Queue is used by net driver
 250  * @channel: The associated channel
 251  * @buffer: The software buffer ring
 252  * @rxd: The hardware descriptor ring
 253  * @added_count: Number of buffers added to the receive queue.
 254  * @notified_count: Number of buffers given to NIC (<= @added_count).
 255  * @removed_count: Number of buffers removed from the receive queue.
 256  * @add_lock: Receive queue descriptor add spin lock.
 257  *      This lock must be held in order to add buffers to the RX
 258  *      descriptor ring (rxd and buffer) and to update added_count (but
 259  *      not removed_count).
 260  * @max_fill: RX descriptor maximum fill level (<= ring size)
 261  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 262  *      (<= @max_fill)
 263  * @fast_fill_limit: The level to which a fast fill will fill
 264  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 265  * @min_fill: RX descriptor minimum non-zero fill level.
 266  *      This records the minimum fill level observed when a ring
 267  *      refill was triggered.
 268  * @min_overfill: RX descriptor minimum overflow fill level.
 269  *      This records the minimum fill level at which RX queue
 270  *      overflow was observed.  It should never be set.
 271  * @alloc_page_count: RX allocation strategy counter.
 272  * @alloc_skb_count: RX allocation strategy counter.
 273  * @work: Descriptor push work thread
 274  * @buf_page: Page for next RX buffer.
 275  *      We can use a single page for multiple RX buffers. This tracks
 276  *      the remaining space in the allocation.
 277  * @buf_dma_addr: Page's DMA address.
 278  * @buf_data: Page's host address.
 279  */
 280 struct efx_rx_queue {
 281         struct efx_nic *efx;
 282         int queue;
 283         int used;
 284         struct efx_channel *channel;
 285         struct efx_rx_buffer *buffer;
 286         struct efx_special_buffer rxd;
 287
 288         int added_count;
 289         int notified_count;
 290         int removed_count;
 291         spinlock_t add_lock;
 292         unsigned int max_fill;
 293         unsigned int fast_fill_trigger;
 294         unsigned int fast_fill_limit;
 295         unsigned int min_fill;
 296         unsigned int min_overfill;
 297         unsigned int alloc_page_count;
 298         unsigned int alloc_skb_count;
 299         struct delayed_work work;
 300         unsigned int slow_fill_count;
 301
 302         struct page *buf_page;
 303         dma_addr_t buf_dma_addr;
 304         char *buf_data;
 305 };
 306
 307 /**
 308  * struct efx_buffer - An Efx general-purpose buffer
 309  * @addr: host base address of the buffer
 310  * @dma_addr: DMA base address of the buffer
 311  * @len: Buffer length, in bytes
 312  *
 313  * Falcon uses these buffers for its interrupt status registers and
 314  * MAC stats dumps.
 315  */
 316 struct efx_buffer {
 317         void *addr;
 318         dma_addr_t dma_addr;
 319         unsigned int len;
 320 };
 321
 322
 323 /* Flags for channel->used_flags */
 324 #define EFX_USED_BY_RX 1
 325 #define EFX_USED_BY_TX 2
 326 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
 327
 328 enum efx_rx_alloc_method {
 329         RX_ALLOC_METHOD_AUTO = 0,
 330         RX_ALLOC_METHOD_SKB = 1,
 331         RX_ALLOC_METHOD_PAGE = 2,
 332 };
 333
 334 /**
 335  * struct efx_channel - An Efx channel
 336  *
 337  * A channel comprises an event queue, at least one TX queue, at least
 338  * one RX queue, and an associated tasklet for processing the event
 339  * queue.
 340  *
 341  * @efx: Associated Efx NIC
 342  * @evqnum: Event queue number
 343  * @channel: Channel instance number
 344  * @used_flags: Channel is used by net driver
 345  * @enabled: Channel enabled indicator
 346  * @irq: IRQ number (MSI and MSI-X only)
 347  * @has_interrupt: Channel has an interrupt
 348  * @irq_moderation: IRQ moderation value (in us)
 349  * @napi_dev: Net device used with NAPI
 350  * @napi_str: NAPI control structure
 351  * @reset_work: Scheduled reset work thread
 352  * @work_pending: Is work pending via NAPI?
 353  * @eventq: Event queue buffer
 354  * @eventq_read_ptr: Event queue read pointer
 355  * @last_eventq_read_ptr: Last event queue read pointer value.
 356  * @eventq_magic: Event queue magic value for driver-generated test events
 357  * @lro_mgr: LRO state
 358  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 359  *      and diagnostic counters
 360  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 361  *      descriptors
 362  * @rx_alloc_pop_pages: RX allocation method currently in use for popping
 363  *      descriptors
 364  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 365  * @n_rx_ip_frag_err: Count of RX IP fragment errors
 366  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 367  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 368  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 369  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 370  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 371  */
 372 struct efx_channel {
 373         struct efx_nic *efx;
 374         int evqnum;
 375         int channel;
 376         int used_flags;
 377         int enabled;
 378         int irq;
 379         unsigned int has_interrupt;
 380         unsigned int irq_moderation;
 381         struct net_device *napi_dev;
 382         struct napi_struct napi_str;
 383         struct work_struct reset_work;
 384         int work_pending;
 385         struct efx_special_buffer eventq;
 386         unsigned int eventq_read_ptr;
 387         unsigned int last_eventq_read_ptr;
 388         unsigned int eventq_magic;
 389
 390         struct net_lro_mgr lro_mgr;
 391         int rx_alloc_level;
 392         int rx_alloc_push_pages;
 393         int rx_alloc_pop_pages;
 394
 395         unsigned n_rx_tobe_disc;
 396         unsigned n_rx_ip_frag_err;
 397         unsigned n_rx_ip_hdr_chksum_err;
 398         unsigned n_rx_tcp_udp_chksum_err;
 399         unsigned n_rx_frm_trunc;
 400         unsigned n_rx_overlength;
 401         unsigned n_skbuff_leaks;
 402
 403         /* Used to pipeline received packets in order to optimise memory
 404          * access with prefetches.
 405          */
 406         struct efx_rx_buffer *rx_pkt;
 407         int rx_pkt_csummed;
 408
 409 };
 410
 411 /**
 412  * struct efx_blinker - S/W LED blinking context
 413  * @led_num: LED ID (board-specific meaning)
 414  * @state: Current state - on or off
 415  * @resubmit: Timer resubmission flag
 416  * @timer: Control timer for blinking
 417  */
 418 struct efx_blinker {
 419         int led_num;
 420         int state;
 421         int resubmit;
 422         struct timer_list timer;
 423 };
 424
 425
 426 /**
 427  * struct efx_board - board information
 428  * @type: Board model type
 429  * @major: Major rev. ('A', 'B' ...)
 430  * @minor: Minor rev. (0, 1, ...)
 431  * @init: Initialisation function
 432  * @init_leds: Sets up board LEDs
 433  * @set_fault_led: Turns the fault LED on or off
 434  * @blink: Starts/stops blinking
 435  * @blinker: used to blink LEDs in software
 436  */
 437 struct efx_board {
 438         int type;
 439         int major;
 440         int minor;
 441         int (*init) (struct efx_nic *nic);
 442         /* As the LEDs are typically attached to the PHY, LEDs
 443          * have a separate init callback that happens later than
 444          * board init. */
 445         int (*init_leds)(struct efx_nic *efx);
 446         void (*set_fault_led) (struct efx_nic *efx, int state);
 447         void (*blink) (struct efx_nic *efx, int start);
 448         struct efx_blinker blinker;
 449 };
 450
 451 #define STRING_TABLE_LOOKUP(val, member)        \
 452         member ## _names[val]
 453
 454 enum efx_int_mode {
 455         /* Be careful if altering to correct macro below */
 456         EFX_INT_MODE_MSIX = 0,
 457         EFX_INT_MODE_MSI = 1,
 458         EFX_INT_MODE_LEGACY = 2,
 459         EFX_INT_MODE_MAX        /* Insert any new items before this */
 460 };
 461 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 462
 463 enum phy_type {
 464         PHY_TYPE_NONE = 0,
 465         PHY_TYPE_CX4_RTMR = 1,
 466         PHY_TYPE_1G_ALASKA = 2,
 467         PHY_TYPE_10XPRESS = 3,
 468         PHY_TYPE_XFP = 4,
 469         PHY_TYPE_PM8358 = 6,
 470         PHY_TYPE_MAX    /* Insert any new items before this */
 471 };
 472
 473 #define PHY_ADDR_INVALID 0xff
 474
 475 enum nic_state {
 476         STATE_INIT = 0,
 477         STATE_RUNNING = 1,
 478         STATE_FINI = 2,
 479         STATE_RESETTING = 3, /* rtnl_lock always held */
 480         STATE_DISABLED = 4,
 481         STATE_MAX,
 482 };
 483
 484 /*
 485  * Alignment of page-allocated RX buffers
 486  *
 487  * Controls the number of bytes inserted at the start of an RX buffer.
 488  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 489  * of the skb->head for hardware DMA].
 490  */
 491 #if defined(__i386__) || defined(__x86_64__)
 492 #define EFX_PAGE_IP_ALIGN 0
 493 #else
 494 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 495 #endif
 496
 497 /*
 498  * Alignment of the skb->head which wraps a page-allocated RX buffer
 499  *
 500  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 501  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 502  * EFX_PAGE_IP_ALIGN.
 503  */
 504 #define EFX_PAGE_SKB_ALIGN 2
 505
 506 /* Forward declaration */
 507 struct efx_nic;
 508
 509 /* Pseudo bit-mask flow control field */
 510 enum efx_fc_type {
 511         EFX_FC_RX = 1,
 512         EFX_FC_TX = 2,
 513         EFX_FC_AUTO = 4,
 514 };
 515
 516 /**
 517  * struct efx_phy_operations - Efx PHY operations table
 518  * @init: Initialise PHY
 519  * @fini: Shut down PHY
 520  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 521  * @clear_interrupt: Clear down interrupt
 522  * @blink: Blink LEDs
 523  * @check_hw: Check hardware
 524  * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset)
 525  * @mmds: MMD presence mask
 526  * @loopbacks: Supported loopback modes mask
 527  */
 528 struct efx_phy_operations {
 529         int (*init) (struct efx_nic *efx);
 530         void (*fini) (struct efx_nic *efx);
 531         void (*reconfigure) (struct efx_nic *efx);
 532         void (*clear_interrupt) (struct efx_nic *efx);
 533         int (*check_hw) (struct efx_nic *efx);
 534         void (*reset_xaui) (struct efx_nic *efx);
 535         int mmds;
 536         unsigned loopbacks;
 537 };
 538
 539 /*
 540  * Efx extended statistics
 541  *
 542  * Not all statistics are provided by all supported MACs.  The purpose
 543  * is this structure is to contain the raw statistics provided by each
 544  * MAC.
 545  */
 546 struct efx_mac_stats {
 547         u64 tx_bytes;
 548         u64 tx_good_bytes;
 549         u64 tx_bad_bytes;
 550         unsigned long tx_packets;
 551         unsigned long tx_bad;
 552         unsigned long tx_pause;
 553         unsigned long tx_control;
 554         unsigned long tx_unicast;
 555         unsigned long tx_multicast;
 556         unsigned long tx_broadcast;
 557         unsigned long tx_lt64;
 558         unsigned long tx_64;
 559         unsigned long tx_65_to_127;
 560         unsigned long tx_128_to_255;
 561         unsigned long tx_256_to_511;
 562         unsigned long tx_512_to_1023;
 563         unsigned long tx_1024_to_15xx;
 564         unsigned long tx_15xx_to_jumbo;
 565         unsigned long tx_gtjumbo;
 566         unsigned long tx_collision;
 567         unsigned long tx_single_collision;
 568         unsigned long tx_multiple_collision;
 569         unsigned long tx_excessive_collision;
 570         unsigned long tx_deferred;
 571         unsigned long tx_late_collision;
 572         unsigned long tx_excessive_deferred;
 573         unsigned long tx_non_tcpudp;
 574         unsigned long tx_mac_src_error;
 575         unsigned long tx_ip_src_error;
 576         u64 rx_bytes;
 577         u64 rx_good_bytes;
 578         u64 rx_bad_bytes;
 579         unsigned long rx_packets;
 580         unsigned long rx_good;
 581         unsigned long rx_bad;
 582         unsigned long rx_pause;
 583         unsigned long rx_control;
 584         unsigned long rx_unicast;
 585         unsigned long rx_multicast;
 586         unsigned long rx_broadcast;
 587         unsigned long rx_lt64;
 588         unsigned long rx_64;
 589         unsigned long rx_65_to_127;
 590         unsigned long rx_128_to_255;
 591         unsigned long rx_256_to_511;
 592         unsigned long rx_512_to_1023;
 593         unsigned long rx_1024_to_15xx;
 594         unsigned long rx_15xx_to_jumbo;
 595         unsigned long rx_gtjumbo;
 596         unsigned long rx_bad_lt64;
 597         unsigned long rx_bad_64_to_15xx;
 598         unsigned long rx_bad_15xx_to_jumbo;
 599         unsigned long rx_bad_gtjumbo;
 600         unsigned long rx_overflow;
 601         unsigned long rx_missed;
 602         unsigned long rx_false_carrier;
 603         unsigned long rx_symbol_error;
 604         unsigned long rx_align_error;
 605         unsigned long rx_length_error;
 606         unsigned long rx_internal_error;
 607         unsigned long rx_good_lt64;
 608 };
 609
 610 /* Number of bits used in a multicast filter hash address */
 611 #define EFX_MCAST_HASH_BITS 8
 612
 613 /* Number of (single-bit) entries in a multicast filter hash */
 614 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 615
 616 /* An Efx multicast filter hash */
 617 union efx_multicast_hash {
 618         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 619         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 620 };
 621
 622 /**
 623  * struct efx_nic - an Efx NIC
 624  * @name: Device name (net device name or bus id before net device registered)
 625  * @pci_dev: The PCI device
 626  * @type: Controller type attributes
 627  * @legacy_irq: IRQ number
 628  * @workqueue: Workqueue for resets, port reconfigures and the HW monitor
 629  * @reset_work: Scheduled reset workitem
 630  * @monitor_work: Hardware monitor workitem
 631  * @membase_phys: Memory BAR value as physical address
 632  * @membase: Memory BAR value
 633  * @biu_lock: BIU (bus interface unit) lock
 634  * @interrupt_mode: Interrupt mode
 635  * @i2c: I2C interface
 636  * @board_info: Board-level information
 637  * @state: Device state flag. Serialised by the rtnl_lock.
 638  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 639  * @tx_queue: TX DMA queues
 640  * @rx_queue: RX DMA queues
 641  * @channel: Channels
 642  * @rss_queues: Number of RSS queues
 643  * @rx_buffer_len: RX buffer length
 644  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 645  * @irq_status: Interrupt status buffer
 646  * @last_irq_cpu: Last CPU to handle interrupt.
 647  *      This register is written with the SMP processor ID whenever an
 648  *      interrupt is handled.  It is used by falcon_test_interrupt()
 649  *      to verify that an interrupt has occurred.
 650  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 651  * @nic_data: Hardware dependant state
 652  * @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
 653  *      efx_reconfigure_port()
 654  * @port_enabled: Port enabled indicator.
 655  *      Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
 656  *      efx_reconfigure_work with kernel interfaces. Safe to read under any
 657  *      one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
 658  *      be held to modify it.
 659  * @port_initialized: Port initialized?
 660  * @net_dev: Operating system network device. Consider holding the rtnl lock
 661  * @rx_checksum_enabled: RX checksumming enabled
 662  * @netif_stop_count: Port stop count
 663  * @netif_stop_lock: Port stop lock
 664  * @mac_stats: MAC statistics. These include all statistics the MACs
 665  *      can provide.  Generic code converts these into a standard
 666  *      &struct net_device_stats.
 667  * @stats_buffer: DMA buffer for statistics
 668  * @stats_lock: Statistics update lock
 669  * @mac_address: Permanent MAC address
 670  * @phy_type: PHY type
 671  * @phy_lock: PHY access lock
 672  * @phy_op: PHY interface
 673  * @phy_data: PHY private data (including PHY-specific stats)
 674  * @mii: PHY interface
 675  * @tx_disabled: PHY transmitter turned off
 676  * @link_up: Link status
 677  * @link_options: Link options (MII/GMII format)
 678  * @n_link_state_changes: Number of times the link has changed state
 679  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 680  * @multicast_hash: Multicast hash table
 681  * @flow_control: Flow control flags - separate RX/TX so can't use link_options
 682  * @reconfigure_work: work item for dealing with PHY events
 683  * @loopback_mode: Loopback status
 684  * @loopback_modes: Supported loopback mode bitmask
 685  * @loopback_selftest: Offline self-test private state
 686  *
 687  * The @priv field of the corresponding &struct net_device points to
 688  * this.
 689  */
 690 struct efx_nic {
 691         char name[IFNAMSIZ];
 692         struct pci_dev *pci_dev;
 693         const struct efx_nic_type *type;
 694         int legacy_irq;
 695         struct workqueue_struct *workqueue;
 696         struct work_struct reset_work;
 697         struct delayed_work monitor_work;
 698         unsigned long membase_phys;
 699         void __iomem *membase;
 700         spinlock_t biu_lock;
 701         enum efx_int_mode interrupt_mode;
 702
 703         struct efx_i2c_interface i2c;
 704         struct efx_board board_info;
 705
 706         enum nic_state state;
 707         enum reset_type reset_pending;
 708
 709         struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
 710         struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
 711         struct efx_channel channel[EFX_MAX_CHANNELS];
 712
 713         int rss_queues;
 714         unsigned int rx_buffer_len;
 715         unsigned int rx_buffer_order;
 716
 717         struct efx_buffer irq_status;
 718         volatile signed int last_irq_cpu;
 719
 720         unsigned n_rx_nodesc_drop_cnt;
 721
 722         void *nic_data;
 723
 724         struct mutex mac_lock;
 725         int port_enabled;
 726
 727         int port_initialized;
 728         struct net_device *net_dev;
 729         int rx_checksum_enabled;
 730
 731         atomic_t netif_stop_count;
 732         spinlock_t netif_stop_lock;
 733
 734         struct efx_mac_stats mac_stats;
 735         struct efx_buffer stats_buffer;
 736         spinlock_t stats_lock;
 737
 738         unsigned char mac_address[ETH_ALEN];
 739
 740         enum phy_type phy_type;
 741         spinlock_t phy_lock;
 742         struct efx_phy_operations *phy_op;
 743         void *phy_data;
 744         struct mii_if_info mii;
 745         unsigned tx_disabled;
 746
 747         int link_up;
 748         unsigned int link_options;
 749         unsigned int n_link_state_changes;
 750
 751         int promiscuous;
 752         union efx_multicast_hash multicast_hash;
 753         enum efx_fc_type flow_control;
 754         struct work_struct reconfigure_work;
 755
 756         atomic_t rx_reset;
 757         enum efx_loopback_mode loopback_mode;
 758         unsigned int loopback_modes;
 759
 760         void *loopback_selftest;
 761 };
 762
 763 /**
 764  * struct efx_nic_type - Efx device type definition
 765  * @mem_bar: Memory BAR number
 766  * @mem_map_size: Memory BAR mapped size
 767  * @txd_ptr_tbl_base: TX descriptor ring base address
 768  * @rxd_ptr_tbl_base: RX descriptor ring base address
 769  * @buf_tbl_base: Buffer table base address
 770  * @evq_ptr_tbl_base: Event queue pointer table base address
 771  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 772  * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
 773  * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
 774  * @evq_size: Event queue size (must be a power of two)
 775  * @max_dma_mask: Maximum possible DMA mask
 776  * @tx_dma_mask: TX DMA mask
 777  * @bug5391_mask: Address mask for bug 5391 workaround
 778  * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
 779  * @rx_xon_thresh: RX FIFO XON watermark (bytes)
 780  * @rx_buffer_padding: Padding added to each RX buffer
 781  * @max_interrupt_mode: Highest capability interrupt mode supported
 782  *      from &enum efx_init_mode.
 783  * @phys_addr_channels: Number of channels with physically addressed
 784  *      descriptors
 785  */
 786 struct efx_nic_type {
 787         unsigned int mem_bar;
 788         unsigned int mem_map_size;
 789         unsigned int txd_ptr_tbl_base;
 790         unsigned int rxd_ptr_tbl_base;
 791         unsigned int buf_tbl_base;
 792         unsigned int evq_ptr_tbl_base;
 793         unsigned int evq_rptr_tbl_base;
 794
 795         unsigned int txd_ring_mask;
 796         unsigned int rxd_ring_mask;
 797         unsigned int evq_size;
 798         dma_addr_t max_dma_mask;
 799         unsigned int tx_dma_mask;
 800         unsigned bug5391_mask;
 801
 802         int rx_xoff_thresh;
 803         int rx_xon_thresh;
 804         unsigned int rx_buffer_padding;
 805         unsigned int max_interrupt_mode;
 806         unsigned int phys_addr_channels;
 807 };
 808
 809 /**************************************************************************
 810  *
 811  * Prototypes and inline functions
 812  *
 813  *************************************************************************/
 814
 815 /* Iterate over all used channels */
 816 #define efx_for_each_channel(_channel, _efx)                            \
 817         for (_channel = &_efx->channel[0];                              \
 818              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 819              _channel++)                                                \
 820                 if (!_channel->used_flags)                              \
 821                         continue;                                       \
 822                 else
 823
 824 /* Iterate over all used channels with interrupts */
 825 #define efx_for_each_channel_with_interrupt(_channel, _efx)             \
 826         for (_channel = &_efx->channel[0];                              \
 827              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 828              _channel++)                                                \
 829                 if (!(_channel->used_flags && _channel->has_interrupt)) \
 830                         continue;                                       \
 831                 else
 832
 833 /* Iterate over all used TX queues */
 834 #define efx_for_each_tx_queue(_tx_queue, _efx)                          \
 835         for (_tx_queue = &_efx->tx_queue[0];                            \
 836              _tx_queue < &_efx->tx_queue[EFX_MAX_TX_QUEUES];            \
 837              _tx_queue++)                                               \
 838                 if (!_tx_queue->used)                                   \
 839                         continue;                                       \
 840                 else
 841
 842 /* Iterate over all TX queues belonging to a channel */
 843 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 844         for (_tx_queue = &_channel->efx->tx_queue[0];                   \
 845              _tx_queue < &_channel->efx->tx_queue[EFX_MAX_TX_QUEUES];   \
 846              _tx_queue++)                                               \
 847                 if ((!_tx_queue->used) ||                               \
 848                     (_tx_queue->channel != _channel))                   \
 849                         continue;                                       \
 850                 else
 851
 852 /* Iterate over all used RX queues */
 853 #define efx_for_each_rx_queue(_rx_queue, _efx)                          \
 854         for (_rx_queue = &_efx->rx_queue[0];                            \
 855              _rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES];            \
 856              _rx_queue++)                                               \
 857                 if (!_rx_queue->used)                                   \
 858                         continue;                                       \
 859                 else
 860
 861 /* Iterate over all RX queues belonging to a channel */
 862 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 863         for (_rx_queue = &_channel->efx->rx_queue[0];                   \
 864              _rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES];   \
 865              _rx_queue++)                                               \
 866                 if ((!_rx_queue->used) ||                               \
 867                     (_rx_queue->channel != _channel))                   \
 868                         continue;                                       \
 869                 else
 870
 871 /* Returns a pointer to the specified receive buffer in the RX
 872  * descriptor queue.
 873  */
 874 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 875                                                   unsigned int index)
 876 {
 877         return (&rx_queue->buffer[index]);
 878 }
 879
 880 /* Set bit in a little-endian bitfield */
 881 static inline void set_bit_le(int nr, unsigned char *addr)
 882 {
 883         addr[nr / 8] |= (1 << (nr % 8));
 884 }
 885
 886 /* Clear bit in a little-endian bitfield */
 887 static inline void clear_bit_le(int nr, unsigned char *addr)
 888 {
 889         addr[nr / 8] &= ~(1 << (nr % 8));
 890 }
 891
 892
 893 /**
 894  * EFX_MAX_FRAME_LEN - calculate maximum frame length
 895  *
 896  * This calculates the maximum frame length that will be used for a
 897  * given MTU.  The frame length will be equal to the MTU plus a
 898  * constant amount of header space and padding.  This is the quantity
 899  * that the net driver will program into the MAC as the maximum frame
 900  * length.
 901  *
 902  * The 10G MAC used in Falcon requires 8-byte alignment on the frame
 903  * length, so we round up to the nearest 8.
 904  */
 905 #define EFX_MAX_FRAME_LEN(mtu) \
 906         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
 907
 908
 909 #endif /* EFX_NET_DRIVER_H */