drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include <net/switchdev.h>
  48 #include "wq.h"
  49 #include "mlx5_core.h"
  50 #include "en_stats.h"
  51
  52 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
  53
  54 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  55 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
  56
  57 #define MLX5E_MAX_NUM_TC        8
  58
  59 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  60 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  61 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  62
  63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  66
  67 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW            0x1
  68 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW            0x3
  69 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW            0x6
  70
  71 #define MLX5_RX_HEADROOM NET_SKB_PAD
  72
  73 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
  74         (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
  75 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
  76         max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
  77 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
  78 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
  79
  80 #define MLX5_MPWRQ_LOG_WQE_SZ                   18
  81 #define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
  82                                     MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
  83 #define MLX5_MPWRQ_PAGES_PER_WQE                BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
  84 #define MLX5_MPWRQ_STRIDES_PER_PAGE             (MLX5_MPWRQ_NUM_STRIDES >> \
  85                                                  MLX5_MPWRQ_WQE_PAGE_ORDER)
  86
  87 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
  88 #define MLX5E_REQUIRED_MTTS(wqes)               \
  89         (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
  90 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
  91
  92 #define MLX5_UMR_ALIGN                          (2048)
  93 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD       (128)
  94
  95 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  96 #define MLX5E_DEFAULT_LRO_TIMEOUT                       32
  97 #define MLX5E_LRO_TIMEOUT_ARR_SIZE                      4
  98
  99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
 100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
 101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
 102 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
 103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
 104 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
 105 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW            0x2
 106
 107 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
 108 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
 109 #define MLX5E_MIN_NUM_CHANNELS         0x1
 110 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
 111 #define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
 112 #define MLX5E_TX_CQ_POLL_BUDGET        128
 113 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
 114
 115 #define MLX5E_ICOSQ_MAX_WQEBBS \
 116         (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
 117
 118 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
 119 #define MLX5E_XDP_IHS_DS_COUNT \
 120         DIV_ROUND_UP(MLX5E_XDP_MIN_INLINE - 2, MLX5_SEND_WQE_DS)
 121 #define MLX5E_XDP_TX_DS_COUNT \
 122         ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
 123 #define MLX5E_XDP_TX_WQEBBS \
 124         DIV_ROUND_UP(MLX5E_XDP_TX_DS_COUNT, MLX5_SEND_WQEBB_NUM_DS)
 125
 126 #define MLX5E_NUM_MAIN_GROUPS 9
 127
 128 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
 129 {
 130         switch (wq_type) {
 131         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 132                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
 133                              wq_size / 2);
 134         default:
 135                 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
 136                              wq_size / 2);
 137         }
 138 }
 139
 140 static inline int mlx5_min_log_rq_size(int wq_type)
 141 {
 142         switch (wq_type) {
 143         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 144                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 145         default:
 146                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 147         }
 148 }
 149
 150 static inline int mlx5_max_log_rq_size(int wq_type)
 151 {
 152         switch (wq_type) {
 153         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 154                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
 155         default:
 156                 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
 157         }
 158 }
 159
 160 struct mlx5e_tx_wqe {
 161         struct mlx5_wqe_ctrl_seg ctrl;
 162         struct mlx5_wqe_eth_seg  eth;
 163 };
 164
 165 struct mlx5e_rx_wqe {
 166         struct mlx5_wqe_srq_next_seg  next;
 167         struct mlx5_wqe_data_seg      data;
 168 };
 169
 170 struct mlx5e_umr_wqe {
 171         struct mlx5_wqe_ctrl_seg       ctrl;
 172         struct mlx5_wqe_umr_ctrl_seg   uctrl;
 173         struct mlx5_mkey_seg           mkc;
 174         struct mlx5_wqe_data_seg       data;
 175 };
 176
 177 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
 178
 179 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
 180         "rx_cqe_moder",
 181         "rx_cqe_compress",
 182 };
 183
 184 enum mlx5e_priv_flag {
 185         MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
 186         MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
 187 };
 188
 189 #define MLX5E_SET_PFLAG(priv, pflag, enable)                    \
 190         do {                                                    \
 191                 if (enable)                                     \
 192                         (priv)->params.pflags |= (pflag);       \
 193                 else                                            \
 194                         (priv)->params.pflags &= ~(pflag);      \
 195         } while (0)
 196
 197 #define MLX5E_GET_PFLAG(priv, pflag) (!!((priv)->params.pflags & (pflag)))
 198
 199 #ifdef CONFIG_MLX5_CORE_EN_DCB
 200 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
 201 #endif
 202
 203 struct mlx5e_cq_moder {
 204         u16 usec;
 205         u16 pkts;
 206 };
 207
 208 struct mlx5e_params {
 209         u8  log_sq_size;
 210         u8  rq_wq_type;
 211         u8  mpwqe_log_stride_sz;
 212         u8  mpwqe_log_num_strides;
 213         u8  log_rq_size;
 214         u16 num_channels;
 215         u8  num_tc;
 216         u8  rx_cq_period_mode;
 217         bool rx_cqe_compress_def;
 218         struct mlx5e_cq_moder rx_cq_moderation;
 219         struct mlx5e_cq_moder tx_cq_moderation;
 220         u16 min_rx_wqes;
 221         bool lro_en;
 222         u32 lro_wqe_sz;
 223         u16 tx_max_inline;
 224         u8  tx_min_inline_mode;
 225         u8  rss_hfunc;
 226         u8  toeplitz_hash_key[40];
 227         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 228         bool vlan_strip_disable;
 229         bool rx_am_enabled;
 230         u32 lro_timeout;
 231         u32 pflags;
 232 };
 233
 234 #ifdef CONFIG_MLX5_CORE_EN_DCB
 235 struct mlx5e_cee_config {
 236         /* bw pct for priority group */
 237         u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];
 238         u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];
 239         bool                       pfc_setting[CEE_DCBX_MAX_PRIO];
 240         bool                       pfc_enable;
 241 };
 242
 243 enum {
 244         MLX5_DCB_CHG_RESET,
 245         MLX5_DCB_NO_CHG,
 246         MLX5_DCB_CHG_NO_RESET,
 247 };
 248
 249 struct mlx5e_dcbx {
 250         enum mlx5_dcbx_oper_mode   mode;
 251         struct mlx5e_cee_config    cee_cfg; /* pending configuration */
 252
 253         /* The only setting that cannot be read from FW */
 254         u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];
 255 };
 256 #endif
 257
 258 struct mlx5e_tstamp {
 259         rwlock_t                   lock;
 260         struct cyclecounter        cycles;
 261         struct timecounter         clock;
 262         struct hwtstamp_config     hwtstamp_config;
 263         u32                        nominal_c_mult;
 264         unsigned long              overflow_period;
 265         struct delayed_work        overflow_work;
 266         struct mlx5_core_dev      *mdev;
 267         struct ptp_clock          *ptp;
 268         struct ptp_clock_info      ptp_info;
 269         u8                        *pps_pin_caps;
 270 };
 271
 272 enum {
 273         MLX5E_RQ_STATE_ENABLED,
 274         MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
 275         MLX5E_RQ_STATE_AM,
 276 };
 277
 278 struct mlx5e_cq {
 279         /* data path - accessed per cqe */
 280         struct mlx5_cqwq           wq;
 281
 282         /* data path - accessed per napi poll */
 283         u16                        event_ctr;
 284         struct napi_struct        *napi;
 285         struct mlx5_core_cq        mcq;
 286         struct mlx5e_channel      *channel;
 287         struct mlx5e_priv         *priv;
 288
 289         /* cqe decompression */
 290         struct mlx5_cqe64          title;
 291         struct mlx5_mini_cqe8      mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
 292         u8                         mini_arr_idx;
 293         u16                        decmprs_left;
 294         u16                        decmprs_wqe_counter;
 295
 296         /* control */
 297         struct mlx5_frag_wq_ctrl   wq_ctrl;
 298 } ____cacheline_aligned_in_smp;
 299
 300 struct mlx5e_tx_wqe_info {
 301         u32 num_bytes;
 302         u8  num_wqebbs;
 303         u8  num_dma;
 304 };
 305
 306 enum mlx5e_dma_map_type {
 307         MLX5E_DMA_MAP_SINGLE,
 308         MLX5E_DMA_MAP_PAGE
 309 };
 310
 311 struct mlx5e_sq_dma {
 312         dma_addr_t              addr;
 313         u32                     size;
 314         enum mlx5e_dma_map_type type;
 315 };
 316
 317 enum {
 318         MLX5E_SQ_STATE_ENABLED,
 319 };
 320
 321 struct mlx5e_sq_wqe_info {
 322         u8  opcode;
 323         u8  num_wqebbs;
 324 };
 325
 326 enum mlx5e_sq_type {
 327         MLX5E_SQ_TXQ,
 328         MLX5E_SQ_ICO,
 329         MLX5E_SQ_XDP
 330 };
 331
 332 struct mlx5e_sq {
 333         /* data path */
 334
 335         /* dirtied @completion */
 336         u16                        cc;
 337         u32                        dma_fifo_cc;
 338
 339         /* dirtied @xmit */
 340         u16                        pc ____cacheline_aligned_in_smp;
 341         u32                        dma_fifo_pc;
 342         struct mlx5e_sq_stats      stats;
 343
 344         struct mlx5e_cq            cq;
 345
 346         /* pointers to per tx element info: write@xmit, read@completion */
 347         union {
 348                 struct {
 349                         struct sk_buff           **skb;
 350                         struct mlx5e_sq_dma       *dma_fifo;
 351                         struct mlx5e_tx_wqe_info  *wqe_info;
 352                 } txq;
 353                 struct mlx5e_sq_wqe_info *ico_wqe;
 354                 struct {
 355                         struct mlx5e_sq_wqe_info  *wqe_info;
 356                         struct mlx5e_dma_info     *di;
 357                         bool                       doorbell;
 358                 } xdp;
 359         } db;
 360
 361         /* read only */
 362         struct mlx5_wq_cyc         wq;
 363         u32                        dma_fifo_mask;
 364         void __iomem              *uar_map;
 365         struct netdev_queue       *txq;
 366         u32                        sqn;
 367         u16                        max_inline;
 368         u8                         min_inline_mode;
 369         u16                        edge;
 370         struct device             *pdev;
 371         struct mlx5e_tstamp       *tstamp;
 372         __be32                     mkey_be;
 373         unsigned long              state;
 374
 375         /* control path */
 376         struct mlx5_wq_ctrl        wq_ctrl;
 377         struct mlx5e_channel      *channel;
 378         int                        tc;
 379         u32                        rate_limit;
 380         u8                         type;
 381 } ____cacheline_aligned_in_smp;
 382
 383 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 384 {
 385         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 386                 (sq->cc  == sq->pc));
 387 }
 388
 389 struct mlx5e_dma_info {
 390         struct page     *page;
 391         dma_addr_t      addr;
 392 };
 393
 394 struct mlx5e_umr_dma_info {
 395         __be64                *mtt;
 396         dma_addr_t             mtt_addr;
 397         struct mlx5e_dma_info  dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
 398         struct mlx5e_umr_wqe   wqe;
 399 };
 400
 401 struct mlx5e_mpw_info {
 402         struct mlx5e_umr_dma_info umr;
 403         u16 consumed_strides;
 404         u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
 405 };
 406
 407 struct mlx5e_rx_am_stats {
 408         int ppms; /* packets per msec */
 409         int epms; /* events per msec */
 410 };
 411
 412 struct mlx5e_rx_am_sample {
 413         ktime_t         time;
 414         unsigned int    pkt_ctr;
 415         u16             event_ctr;
 416 };
 417
 418 struct mlx5e_rx_am { /* Adaptive Moderation */
 419         u8                                      state;
 420         struct mlx5e_rx_am_stats                prev_stats;
 421         struct mlx5e_rx_am_sample               start_sample;
 422         struct work_struct                      work;
 423         u8                                      profile_ix;
 424         u8                                      mode;
 425         u8                                      tune_state;
 426         u8                                      steps_right;
 427         u8                                      steps_left;
 428         u8                                      tired;
 429 };
 430
 431 /* a single cache unit is capable to serve one napi call (for non-striding rq)
 432  * or a MPWQE (for striding rq).
 433  */
 434 #define MLX5E_CACHE_UNIT        (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
 435                                  MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
 436 #define MLX5E_CACHE_SIZE        (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
 437 struct mlx5e_page_cache {
 438         u32 head;
 439         u32 tail;
 440         struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
 441 };
 442
 443 struct mlx5e_rq;
 444 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
 445 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);
 446 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
 447
 448 struct mlx5e_rq {
 449         /* data path */
 450         struct mlx5_wq_ll      wq;
 451
 452         union {
 453                 struct mlx5e_dma_info *dma_info;
 454                 struct {
 455                         struct mlx5e_mpw_info *info;
 456                         void                  *mtt_no_align;
 457                 } mpwqe;
 458         };
 459         struct {
 460                 u8             page_order;
 461                 u32            wqe_sz;    /* wqe data buffer size */
 462                 u8             map_dir;   /* dma map direction */
 463         } buff;
 464         __be32                 mkey_be;
 465
 466         struct device         *pdev;
 467         struct net_device     *netdev;
 468         struct mlx5e_tstamp   *tstamp;
 469         struct mlx5e_rq_stats  stats;
 470         struct mlx5e_cq        cq;
 471         struct mlx5e_page_cache page_cache;
 472
 473         mlx5e_fp_handle_rx_cqe handle_rx_cqe;
 474         mlx5e_fp_alloc_wqe     alloc_wqe;
 475         mlx5e_fp_dealloc_wqe   dealloc_wqe;
 476
 477         unsigned long          state;
 478         int                    ix;
 479         u16                    rx_headroom;
 480
 481         struct mlx5e_rx_am     am; /* Adaptive Moderation */
 482
 483         /* XDP */
 484         struct bpf_prog       *xdp_prog;
 485         struct mlx5e_sq        xdpsq;
 486
 487         /* control */
 488         struct mlx5_wq_ctrl    wq_ctrl;
 489         u8                     wq_type;
 490         u32                    mpwqe_stride_sz;
 491         u32                    mpwqe_num_strides;
 492         u32                    rqn;
 493         struct mlx5e_channel  *channel;
 494         struct mlx5e_priv     *priv;
 495         struct mlx5_core_mkey  umr_mkey;
 496 } ____cacheline_aligned_in_smp;
 497
 498 enum channel_flags {
 499         MLX5E_CHANNEL_NAPI_SCHED = 1,
 500 };
 501
 502 struct mlx5e_channel {
 503         /* data path */
 504         struct mlx5e_rq            rq;
 505         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 506         struct mlx5e_sq            icosq;   /* internal control operations */
 507         bool                       xdp;
 508         struct napi_struct         napi;
 509         struct device             *pdev;
 510         struct net_device         *netdev;
 511         __be32                     mkey_be;
 512         u8                         num_tc;
 513         unsigned long              flags;
 514
 515         /* control */
 516         struct mlx5e_priv         *priv;
 517         int                        ix;
 518         int                        cpu;
 519 };
 520
 521 enum mlx5e_traffic_types {
 522         MLX5E_TT_IPV4_TCP,
 523         MLX5E_TT_IPV6_TCP,
 524         MLX5E_TT_IPV4_UDP,
 525         MLX5E_TT_IPV6_UDP,
 526         MLX5E_TT_IPV4_IPSEC_AH,
 527         MLX5E_TT_IPV6_IPSEC_AH,
 528         MLX5E_TT_IPV4_IPSEC_ESP,
 529         MLX5E_TT_IPV6_IPSEC_ESP,
 530         MLX5E_TT_IPV4,
 531         MLX5E_TT_IPV6,
 532         MLX5E_TT_ANY,
 533         MLX5E_NUM_TT,
 534         MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
 535 };
 536
 537 enum {
 538         MLX5E_STATE_ASYNC_EVENTS_ENABLED,
 539         MLX5E_STATE_OPENED,
 540         MLX5E_STATE_DESTROYING,
 541 };
 542
 543 struct mlx5e_vxlan_db {
 544         spinlock_t                      lock; /* protect vxlan table */
 545         struct radix_tree_root          tree;
 546 };
 547
 548 struct mlx5e_l2_rule {
 549         u8  addr[ETH_ALEN + 2];
 550         struct mlx5_flow_handle *rule;
 551 };
 552
 553 struct mlx5e_flow_table {
 554         int num_groups;
 555         struct mlx5_flow_table *t;
 556         struct mlx5_flow_group **g;
 557 };
 558
 559 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
 560
 561 struct mlx5e_tc_table {
 562         struct mlx5_flow_table          *t;
 563
 564         struct rhashtable_params        ht_params;
 565         struct rhashtable               ht;
 566 };
 567
 568 struct mlx5e_vlan_table {
 569         struct mlx5e_flow_table         ft;
 570         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 571         struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
 572         struct mlx5_flow_handle *untagged_rule;
 573         struct mlx5_flow_handle *any_cvlan_rule;
 574         struct mlx5_flow_handle *any_svlan_rule;
 575         bool                    filter_disabled;
 576 };
 577
 578 struct mlx5e_l2_table {
 579         struct mlx5e_flow_table    ft;
 580         struct hlist_head          netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
 581         struct hlist_head          netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
 582         struct mlx5e_l2_rule       broadcast;
 583         struct mlx5e_l2_rule       allmulti;
 584         struct mlx5e_l2_rule       promisc;
 585         bool                       broadcast_enabled;
 586         bool                       allmulti_enabled;
 587         bool                       promisc_enabled;
 588 };
 589
 590 /* L3/L4 traffic type classifier */
 591 struct mlx5e_ttc_table {
 592         struct mlx5e_flow_table  ft;
 593         struct mlx5_flow_handle  *rules[MLX5E_NUM_TT];
 594 };
 595
 596 #define ARFS_HASH_SHIFT BITS_PER_BYTE
 597 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
 598 struct arfs_table {
 599         struct mlx5e_flow_table  ft;
 600         struct mlx5_flow_handle  *default_rule;
 601         struct hlist_head        rules_hash[ARFS_HASH_SIZE];
 602 };
 603
 604 enum  arfs_type {
 605         ARFS_IPV4_TCP,
 606         ARFS_IPV6_TCP,
 607         ARFS_IPV4_UDP,
 608         ARFS_IPV6_UDP,
 609         ARFS_NUM_TYPES,
 610 };
 611
 612 struct mlx5e_arfs_tables {
 613         struct arfs_table arfs_tables[ARFS_NUM_TYPES];
 614         /* Protect aRFS rules list */
 615         spinlock_t                     arfs_lock;
 616         struct list_head               rules;
 617         int                            last_filter_id;
 618         struct workqueue_struct        *wq;
 619 };
 620
 621 /* NIC prio FTS */
 622 enum {
 623         MLX5E_VLAN_FT_LEVEL = 0,
 624         MLX5E_L2_FT_LEVEL,
 625         MLX5E_TTC_FT_LEVEL,
 626         MLX5E_ARFS_FT_LEVEL
 627 };
 628
 629 struct mlx5e_ethtool_table {
 630         struct mlx5_flow_table *ft;
 631         int                    num_rules;
 632 };
 633
 634 #define ETHTOOL_NUM_L3_L4_FTS 7
 635 #define ETHTOOL_NUM_L2_FTS 4
 636
 637 struct mlx5e_ethtool_steering {
 638         struct mlx5e_ethtool_table      l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
 639         struct mlx5e_ethtool_table      l2_ft[ETHTOOL_NUM_L2_FTS];
 640         struct list_head                rules;
 641         int                             tot_num_rules;
 642 };
 643
 644 struct mlx5e_flow_steering {
 645         struct mlx5_flow_namespace      *ns;
 646         struct mlx5e_ethtool_steering   ethtool;
 647         struct mlx5e_tc_table           tc;
 648         struct mlx5e_vlan_table         vlan;
 649         struct mlx5e_l2_table           l2;
 650         struct mlx5e_ttc_table          ttc;
 651         struct mlx5e_arfs_tables        arfs;
 652 };
 653
 654 struct mlx5e_rqt {
 655         u32              rqtn;
 656         bool             enabled;
 657 };
 658
 659 struct mlx5e_tir {
 660         u32               tirn;
 661         struct mlx5e_rqt  rqt;
 662         struct list_head  list;
 663 };
 664
 665 enum {
 666         MLX5E_TC_PRIO = 0,
 667         MLX5E_NIC_PRIO
 668 };
 669
 670 struct mlx5e_profile {
 671         void    (*init)(struct mlx5_core_dev *mdev,
 672                         struct net_device *netdev,
 673                         const struct mlx5e_profile *profile, void *ppriv);
 674         void    (*cleanup)(struct mlx5e_priv *priv);
 675         int     (*init_rx)(struct mlx5e_priv *priv);
 676         void    (*cleanup_rx)(struct mlx5e_priv *priv);
 677         int     (*init_tx)(struct mlx5e_priv *priv);
 678         void    (*cleanup_tx)(struct mlx5e_priv *priv);
 679         void    (*enable)(struct mlx5e_priv *priv);
 680         void    (*disable)(struct mlx5e_priv *priv);
 681         void    (*update_stats)(struct mlx5e_priv *priv);
 682         int     (*max_nch)(struct mlx5_core_dev *mdev);
 683         int     max_tc;
 684 };
 685
 686 struct mlx5e_priv {
 687         /* priv data path fields - start */
 688         struct mlx5e_sq            **txq_to_sq_map;
 689         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 690         struct bpf_prog *xdp_prog;
 691         /* priv data path fields - end */
 692
 693         unsigned long              state;
 694         struct mutex               state_lock; /* Protects Interface state */
 695         struct mlx5e_rq            drop_rq;
 696
 697         struct mlx5e_channel     **channel;
 698         u32                        tisn[MLX5E_MAX_NUM_TC];
 699         struct mlx5e_rqt           indir_rqt;
 700         struct mlx5e_tir           indir_tir[MLX5E_NUM_INDIR_TIRS];
 701         struct mlx5e_tir           direct_tir[MLX5E_MAX_NUM_CHANNELS];
 702         u32                        tx_rates[MLX5E_MAX_NUM_SQS];
 703
 704         struct mlx5e_flow_steering fs;
 705         struct mlx5e_vxlan_db      vxlan;
 706
 707         struct mlx5e_params        params;
 708         struct workqueue_struct    *wq;
 709         struct work_struct         update_carrier_work;
 710         struct work_struct         set_rx_mode_work;
 711         struct work_struct         tx_timeout_work;
 712         struct delayed_work        update_stats_work;
 713
 714         struct mlx5_core_dev      *mdev;
 715         struct net_device         *netdev;
 716         struct mlx5e_stats         stats;
 717         struct mlx5e_tstamp        tstamp;
 718         u16 q_counter;
 719 #ifdef CONFIG_MLX5_CORE_EN_DCB
 720         struct mlx5e_dcbx          dcbx;
 721 #endif
 722
 723         const struct mlx5e_profile *profile;
 724         void                      *ppriv;
 725 };
 726
 727 void mlx5e_build_ptys2ethtool_map(void);
 728
 729 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 730 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 731                        void *accel_priv, select_queue_fallback_t fallback);
 732 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 733
 734 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 735 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 736 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 737 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 738 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 739 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
 740 void mlx5e_free_xdpsq_descs(struct mlx5e_sq *sq);
 741 void mlx5e_free_sq_descs(struct mlx5e_sq *sq);
 742
 743 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 744                         bool recycle);
 745 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 746 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 747 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 748 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 749 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
 750 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
 751 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
 752 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
 753 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
 754 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 755
 756 void mlx5e_rx_am(struct mlx5e_rq *rq);
 757 void mlx5e_rx_am_work(struct work_struct *work);
 758 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
 759
 760 void mlx5e_update_stats(struct mlx5e_priv *priv);
 761
 762 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
 763 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
 764 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
 765 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
 766 int mlx5e_self_test_num(struct mlx5e_priv *priv);
 767 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
 768                      u64 *buf);
 769 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
 770                            int location);
 771 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
 772                                 struct ethtool_rxnfc *info, u32 *rule_locs);
 773 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
 774                                struct ethtool_rx_flow_spec *fs);
 775 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
 776                               int location);
 777 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
 778 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
 779 void mlx5e_set_rx_mode_work(struct work_struct *work);
 780
 781 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 782                         struct skb_shared_hwtstamps *hwts);
 783 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 784 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 785 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
 786                              struct ptp_clock_event *event);
 787 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 788 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 789 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
 790
 791 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 792                           u16 vid);
 793 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 794                            u16 vid);
 795 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 796 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 797
 798 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
 799
 800 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
 801 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv *priv, void *tirc,
 802                                     enum mlx5e_traffic_types tt);
 803
 804 int mlx5e_open_locked(struct net_device *netdev);
 805 int mlx5e_close_locked(struct net_device *netdev);
 806 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
 807                                    u32 *indirection_rqt, int len,
 808                                    int num_channels);
 809 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 810
 811 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
 812                                  u8 cq_period_mode);
 813 void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type);
 814
 815 static inline void
 816 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, struct mlx5_wqe_ctrl_seg *ctrl)
 817 {
 818         /* ensure wqe is visible to device before updating doorbell record */
 819         dma_wmb();
 820
 821         *sq->wq.db = cpu_to_be32(sq->pc);
 822
 823         /* ensure doorbell record is visible to device before ringing the
 824          * doorbell
 825          */
 826         wmb();
 827
 828         mlx5_write64((__be32 *)ctrl, sq->uar_map, NULL);
 829 }
 830
 831 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 832 {
 833         struct mlx5_core_cq *mcq;
 834
 835         mcq = &cq->mcq;
 836         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
 837 }
 838
 839 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 840 {
 841         return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
 842 }
 843
 844 extern const struct ethtool_ops mlx5e_ethtool_ops;
 845 #ifdef CONFIG_MLX5_CORE_EN_DCB
 846 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 847 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 848 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
 849 #endif
 850
 851 #ifndef CONFIG_RFS_ACCEL
 852 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
 853 {
 854         return 0;
 855 }
 856
 857 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
 858
 859 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
 860 {
 861         return -EOPNOTSUPP;
 862 }
 863
 864 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
 865 {
 866         return -EOPNOTSUPP;
 867 }
 868 #else
 869 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
 870 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
 871 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
 872 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
 873 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
 874                         u16 rxq_index, u32 flow_id);
 875 #endif
 876
 877 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 878 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
 879                      struct mlx5e_tir *tir, u32 *in, int inlen);
 880 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
 881                        struct mlx5e_tir *tir);
 882 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
 883 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
 884 int mlx5e_refresh_tirs_self_loopback(struct mlx5_core_dev *mdev,
 885                                      bool enable_uc_lb);
 886
 887 struct mlx5_eswitch_rep;
 888 int mlx5e_vport_rep_load(struct mlx5_eswitch *esw,
 889                          struct mlx5_eswitch_rep *rep);
 890 void mlx5e_vport_rep_unload(struct mlx5_eswitch *esw,
 891                             struct mlx5_eswitch_rep *rep);
 892 int mlx5e_nic_rep_load(struct mlx5_eswitch *esw, struct mlx5_eswitch_rep *rep);
 893 void mlx5e_nic_rep_unload(struct mlx5_eswitch *esw,
 894                           struct mlx5_eswitch_rep *rep);
 895 int mlx5e_add_sqs_fwd_rules(struct mlx5e_priv *priv);
 896 void mlx5e_remove_sqs_fwd_rules(struct mlx5e_priv *priv);
 897 int mlx5e_attr_get(struct net_device *dev, struct switchdev_attr *attr);
 898 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
 899 void mlx5e_update_hw_rep_counters(struct mlx5e_priv *priv);
 900
 901 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
 902 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
 903 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
 904 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
 905 int mlx5e_create_tises(struct mlx5e_priv *priv);
 906 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
 907 int mlx5e_close(struct net_device *netdev);
 908 int mlx5e_open(struct net_device *netdev);
 909 void mlx5e_update_stats_work(struct work_struct *work);
 910 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
 911                                        const struct mlx5e_profile *profile,
 912                                        void *ppriv);
 913 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv);
 914 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 915 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev);
 916 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
 917
 918 int mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
 919                             void *sp);
 920 bool mlx5e_has_offload_stats(const struct net_device *dev, int attr_id);
 921
 922 bool mlx5e_is_uplink_rep(struct mlx5e_priv *priv);
 923 bool mlx5e_is_vf_vport_rep(struct mlx5e_priv *priv);
 924 #endif /* __MLX5_EN_H__ */