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KVM: MMU: fix forgot flush tlbs on sync_page path
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / paging_tmpl.h
blobca0e5e834724afc4c737b2669736af84437a2c51
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #ifdef CONFIG_X86_64
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
39 #else
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
42 #endif
43 #elif PTTYPE == 32
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
55 #else
56 #error Invalid PTTYPE value
57 #endif
58
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61
62 /*
63 * The guest_walker structure emulates the behavior of the hardware page
64 * table walker.
65 */
66 struct guest_walker {
67 int level;
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
72 unsigned pt_access;
73 unsigned pte_access;
74 gfn_t gfn;
75 u32 error_code;
76 };
77
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
79 {
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 }
82
83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
86 {
87 pt_element_t ret;
88 pt_element_t *table;
89 struct page *page;
90
91 page = gfn_to_page(kvm, table_gfn);
92
93 table = kmap_atomic(page, KM_USER0);
94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
95 kunmap_atomic(table, KM_USER0);
96
97 kvm_release_page_dirty(page);
98
99 return (ret != orig_pte);
100 }
101
102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
103 {
104 unsigned access;
105
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107 #if PTTYPE == 64
108 if (vcpu->arch.mmu.nx)
109 access &= ~(gpte >> PT64_NX_SHIFT);
110 #endif
111 return access;
112 }
113
114 /*
115 * Fetch a guest pte for a guest virtual address
116 */
117 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
119 gva_t addr, u32 access)
120 {
121 pt_element_t pte;
122 gfn_t table_gfn;
123 unsigned index, pt_access, uninitialized_var(pte_access);
124 gpa_t pte_gpa;
125 bool eperm, present, rsvd_fault;
126 int offset, write_fault, user_fault, fetch_fault;
127
128 write_fault = access & PFERR_WRITE_MASK;
129 user_fault = access & PFERR_USER_MASK;
130 fetch_fault = access & PFERR_FETCH_MASK;
131
132 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
133 fetch_fault);
134 walk:
135 present = true;
136 eperm = rsvd_fault = false;
137 walker->level = mmu->root_level;
138 pte = mmu->get_cr3(vcpu);
139
140 #if PTTYPE == 64
141 if (walker->level == PT32E_ROOT_LEVEL) {
142 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
143 trace_kvm_mmu_paging_element(pte, walker->level);
144 if (!is_present_gpte(pte)) {
145 present = false;
146 goto error;
147 }
148 --walker->level;
149 }
150 #endif
151 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
152 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
153
154 pt_access = ACC_ALL;
155
156 for (;;) {
157 index = PT_INDEX(addr, walker->level);
158
159 table_gfn = gpte_to_gfn(pte);
160 offset = index * sizeof(pt_element_t);
161 pte_gpa = gfn_to_gpa(table_gfn) + offset;
162 walker->table_gfn[walker->level - 1] = table_gfn;
163 walker->pte_gpa[walker->level - 1] = pte_gpa;
164
165 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
166 offset, sizeof(pte),
167 PFERR_USER_MASK|PFERR_WRITE_MASK)) {
168 present = false;
169 break;
170 }
171
172 trace_kvm_mmu_paging_element(pte, walker->level);
173
174 if (!is_present_gpte(pte)) {
175 present = false;
176 break;
177 }
178
179 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
180 rsvd_fault = true;
181 break;
182 }
183
184 if (write_fault && !is_writable_pte(pte))
185 if (user_fault || is_write_protection(vcpu))
186 eperm = true;
187
188 if (user_fault && !(pte & PT_USER_MASK))
189 eperm = true;
190
191 #if PTTYPE == 64
192 if (fetch_fault && (pte & PT64_NX_MASK))
193 eperm = true;
194 #endif
195
196 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
197 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
198 sizeof(pte));
199 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
200 index, pte, pte|PT_ACCESSED_MASK))
201 goto walk;
202 mark_page_dirty(vcpu->kvm, table_gfn);
203 pte |= PT_ACCESSED_MASK;
204 }
205
206 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
207
208 walker->ptes[walker->level - 1] = pte;
209
210 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
211 ((walker->level == PT_DIRECTORY_LEVEL) &&
212 is_large_pte(pte) &&
213 (PTTYPE == 64 || is_pse(vcpu))) ||
214 ((walker->level == PT_PDPE_LEVEL) &&
215 is_large_pte(pte) &&
216 mmu->root_level == PT64_ROOT_LEVEL)) {
217 int lvl = walker->level;
218 gpa_t real_gpa;
219 gfn_t gfn;
220 u32 ac;
221
222 gfn = gpte_to_gfn_lvl(pte, lvl);
223 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
224
225 if (PTTYPE == 32 &&
226 walker->level == PT_DIRECTORY_LEVEL &&
227 is_cpuid_PSE36())
228 gfn += pse36_gfn_delta(pte);
229
230 ac = write_fault | fetch_fault | user_fault;
231
232 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
233 ac);
234 if (real_gpa == UNMAPPED_GVA)
235 return 0;
236
237 walker->gfn = real_gpa >> PAGE_SHIFT;
238
239 break;
240 }
241
242 pt_access = pte_access;
243 --walker->level;
244 }
245
246 if (!present || eperm || rsvd_fault)
247 goto error;
248
249 if (write_fault && !is_dirty_gpte(pte)) {
250 bool ret;
251
252 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
253 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
254 pte|PT_DIRTY_MASK);
255 if (ret)
256 goto walk;
257 mark_page_dirty(vcpu->kvm, table_gfn);
258 pte |= PT_DIRTY_MASK;
259 walker->ptes[walker->level - 1] = pte;
260 }
261
262 walker->pt_access = pt_access;
263 walker->pte_access = pte_access;
264 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
265 __func__, (u64)pte, pte_access, pt_access);
266 return 1;
267
268 error:
269 walker->error_code = 0;
270 if (present)
271 walker->error_code |= PFERR_PRESENT_MASK;
272
273 walker->error_code |= write_fault | user_fault;
274
275 if (fetch_fault && mmu->nx)
276 walker->error_code |= PFERR_FETCH_MASK;
277 if (rsvd_fault)
278 walker->error_code |= PFERR_RSVD_MASK;
279
280 vcpu->arch.fault.address = addr;
281 vcpu->arch.fault.error_code = walker->error_code;
282
283 trace_kvm_mmu_walker_error(walker->error_code);
284 return 0;
285 }
286
287 static int FNAME(walk_addr)(struct guest_walker *walker,
288 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
289 {
290 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
291 access);
292 }
293
294 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
295 struct kvm_vcpu *vcpu, gva_t addr,
296 u32 access)
297 {
298 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
299 addr, access);
300 }
301
302 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
303 u64 *spte, const void *pte)
304 {
305 pt_element_t gpte;
306 unsigned pte_access;
307 pfn_t pfn;
308 u64 new_spte;
309
310 gpte = *(const pt_element_t *)pte;
311 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
312 if (!is_present_gpte(gpte)) {
313 if (sp->unsync)
314 new_spte = shadow_trap_nonpresent_pte;
315 else
316 new_spte = shadow_notrap_nonpresent_pte;
317 __set_spte(spte, new_spte);
318 }
319 return;
320 }
321 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
322 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
323 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
324 return;
325 pfn = vcpu->arch.update_pte.pfn;
326 if (is_error_pfn(pfn))
327 return;
328 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
329 return;
330 kvm_get_pfn(pfn);
331 /*
332 * we call mmu_set_spte() with reset_host_protection = true beacuse that
333 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
334 */
335 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
336 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
337 gpte_to_gfn(gpte), pfn, true, true);
338 }
339
340 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
341 struct guest_walker *gw, int level)
342 {
343 pt_element_t curr_pte;
344 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
345 u64 mask;
346 int r, index;
347
348 if (level == PT_PAGE_TABLE_LEVEL) {
349 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
350 base_gpa = pte_gpa & ~mask;
351 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
352
353 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
354 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
355 curr_pte = gw->prefetch_ptes[index];
356 } else
357 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
358 &curr_pte, sizeof(curr_pte));
359
360 return r || curr_pte != gw->ptes[level - 1];
361 }
362
363 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
364 u64 *sptep)
365 {
366 struct kvm_mmu_page *sp;
367 struct kvm_mmu *mmu = &vcpu->arch.mmu;
368 pt_element_t *gptep = gw->prefetch_ptes;
369 u64 *spte;
370 int i;
371
372 sp = page_header(__pa(sptep));
373
374 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
375 return;
376
377 if (sp->role.direct)
378 return __direct_pte_prefetch(vcpu, sp, sptep);
379
380 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
381 spte = sp->spt + i;
382
383 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
384 pt_element_t gpte;
385 unsigned pte_access;
386 gfn_t gfn;
387 pfn_t pfn;
388 bool dirty;
389
390 if (spte == sptep)
391 continue;
392
393 if (*spte != shadow_trap_nonpresent_pte)
394 continue;
395
396 gpte = gptep[i];
397
398 if (is_rsvd_bits_set(mmu, gpte, PT_PAGE_TABLE_LEVEL))
399 continue;
400
401 if (!is_present_gpte(gpte)) {
402 if (!sp->unsync)
403 __set_spte(spte, shadow_notrap_nonpresent_pte);
404 continue;
405 }
406
407 if (!(gpte & PT_ACCESSED_MASK))
408 continue;
409
410 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
411 gfn = gpte_to_gfn(gpte);
412 dirty = is_dirty_gpte(gpte);
413 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
414 (pte_access & ACC_WRITE_MASK) && dirty);
415 if (is_error_pfn(pfn)) {
416 kvm_release_pfn_clean(pfn);
417 break;
418 }
419
420 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
421 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
422 pfn, true, true);
423 }
424 }
425
426 /*
427 * Fetch a shadow pte for a specific level in the paging hierarchy.
428 */
429 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
430 struct guest_walker *gw,
431 int user_fault, int write_fault, int hlevel,
432 int *ptwrite, pfn_t pfn, bool map_writable)
433 {
434 unsigned access = gw->pt_access;
435 struct kvm_mmu_page *sp = NULL;
436 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
437 int top_level;
438 unsigned direct_access;
439 struct kvm_shadow_walk_iterator it;
440
441 if (!is_present_gpte(gw->ptes[gw->level - 1]))
442 return NULL;
443
444 direct_access = gw->pt_access & gw->pte_access;
445 if (!dirty)
446 direct_access &= ~ACC_WRITE_MASK;
447
448 top_level = vcpu->arch.mmu.root_level;
449 if (top_level == PT32E_ROOT_LEVEL)
450 top_level = PT32_ROOT_LEVEL;
451 /*
452 * Verify that the top-level gpte is still there. Since the page
453 * is a root page, it is either write protected (and cannot be
454 * changed from now on) or it is invalid (in which case, we don't
455 * really care if it changes underneath us after this point).
456 */
457 if (FNAME(gpte_changed)(vcpu, gw, top_level))
458 goto out_gpte_changed;
459
460 for (shadow_walk_init(&it, vcpu, addr);
461 shadow_walk_okay(&it) && it.level > gw->level;
462 shadow_walk_next(&it)) {
463 gfn_t table_gfn;
464
465 drop_large_spte(vcpu, it.sptep);
466
467 sp = NULL;
468 if (!is_shadow_present_pte(*it.sptep)) {
469 table_gfn = gw->table_gfn[it.level - 2];
470 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
471 false, access, it.sptep);
472 }
473
474 /*
475 * Verify that the gpte in the page we've just write
476 * protected is still there.
477 */
478 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
479 goto out_gpte_changed;
480
481 if (sp)
482 link_shadow_page(it.sptep, sp);
483 }
484
485 for (;
486 shadow_walk_okay(&it) && it.level > hlevel;
487 shadow_walk_next(&it)) {
488 gfn_t direct_gfn;
489
490 validate_direct_spte(vcpu, it.sptep, direct_access);
491
492 drop_large_spte(vcpu, it.sptep);
493
494 if (is_shadow_present_pte(*it.sptep))
495 continue;
496
497 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
498
499 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
500 true, direct_access, it.sptep);
501 link_shadow_page(it.sptep, sp);
502 }
503
504 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
505 user_fault, write_fault, dirty, ptwrite, it.level,
506 gw->gfn, pfn, false, map_writable);
507 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
508
509 return it.sptep;
510
511 out_gpte_changed:
512 if (sp)
513 kvm_mmu_put_page(sp, it.sptep);
514 kvm_release_pfn_clean(pfn);
515 return NULL;
516 }
517
518 /*
519 * Page fault handler. There are several causes for a page fault:
520 * - there is no shadow pte for the guest pte
521 * - write access through a shadow pte marked read only so that we can set
522 * the dirty bit
523 * - write access to a shadow pte marked read only so we can update the page
524 * dirty bitmap, when userspace requests it
525 * - mmio access; in this case we will never install a present shadow pte
526 * - normal guest page fault due to the guest pte marked not present, not
527 * writable, or not executable
528 *
529 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
530 * a negative value on error.
531 */
532 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
533 bool no_apf)
534 {
535 int write_fault = error_code & PFERR_WRITE_MASK;
536 int user_fault = error_code & PFERR_USER_MASK;
537 struct guest_walker walker;
538 u64 *sptep;
539 int write_pt = 0;
540 int r;
541 pfn_t pfn;
542 int level = PT_PAGE_TABLE_LEVEL;
543 unsigned long mmu_seq;
544 bool map_writable;
545
546 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
547
548 r = mmu_topup_memory_caches(vcpu);
549 if (r)
550 return r;
551
552 /*
553 * Look up the guest pte for the faulting address.
554 */
555 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
556
557 /*
558 * The page is not mapped by the guest. Let the guest handle it.
559 */
560 if (!r) {
561 pgprintk("%s: guest page fault\n", __func__);
562 inject_page_fault(vcpu);
563 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
564 return 0;
565 }
566
567 if (walker.level >= PT_DIRECTORY_LEVEL) {
568 level = min(walker.level, mapping_level(vcpu, walker.gfn));
569 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
570 }
571
572 mmu_seq = vcpu->kvm->mmu_notifier_seq;
573 smp_rmb();
574
575 if (try_async_pf(vcpu, no_apf, walker.gfn, addr, &pfn, write_fault,
576 &map_writable))
577 return 0;
578
579 /* mmio */
580 if (is_error_pfn(pfn))
581 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
582
583 if (!map_writable)
584 walker.pte_access &= ~ACC_WRITE_MASK;
585
586 spin_lock(&vcpu->kvm->mmu_lock);
587 if (mmu_notifier_retry(vcpu, mmu_seq))
588 goto out_unlock;
589
590 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
591 kvm_mmu_free_some_pages(vcpu);
592 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
593 level, &write_pt, pfn, map_writable);
594 (void)sptep;
595 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
596 sptep, *sptep, write_pt);
597
598 if (!write_pt)
599 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
600
601 ++vcpu->stat.pf_fixed;
602 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
603 spin_unlock(&vcpu->kvm->mmu_lock);
604
605 return write_pt;
606
607 out_unlock:
608 spin_unlock(&vcpu->kvm->mmu_lock);
609 kvm_release_pfn_clean(pfn);
610 return 0;
611 }
612
613 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
614 {
615 struct kvm_shadow_walk_iterator iterator;
616 struct kvm_mmu_page *sp;
617 gpa_t pte_gpa = -1;
618 int level;
619 u64 *sptep;
620 int need_flush = 0;
621
622 spin_lock(&vcpu->kvm->mmu_lock);
623
624 for_each_shadow_entry(vcpu, gva, iterator) {
625 level = iterator.level;
626 sptep = iterator.sptep;
627
628 sp = page_header(__pa(sptep));
629 if (is_last_spte(*sptep, level)) {
630 int offset, shift;
631
632 if (!sp->unsync)
633 break;
634
635 shift = PAGE_SHIFT -
636 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
637 offset = sp->role.quadrant << shift;
638
639 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
640 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
641
642 if (is_shadow_present_pte(*sptep)) {
643 if (is_large_pte(*sptep))
644 --vcpu->kvm->stat.lpages;
645 drop_spte(vcpu->kvm, sptep,
646 shadow_trap_nonpresent_pte);
647 need_flush = 1;
648 } else
649 __set_spte(sptep, shadow_trap_nonpresent_pte);
650 break;
651 }
652
653 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
654 break;
655 }
656
657 if (need_flush)
658 kvm_flush_remote_tlbs(vcpu->kvm);
659
660 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
661
662 spin_unlock(&vcpu->kvm->mmu_lock);
663
664 if (pte_gpa == -1)
665 return;
666
667 if (mmu_topup_memory_caches(vcpu))
668 return;
669 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
670 }
671
672 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
673 u32 *error)
674 {
675 struct guest_walker walker;
676 gpa_t gpa = UNMAPPED_GVA;
677 int r;
678
679 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
680
681 if (r) {
682 gpa = gfn_to_gpa(walker.gfn);
683 gpa |= vaddr & ~PAGE_MASK;
684 } else if (error)
685 *error = walker.error_code;
686
687 return gpa;
688 }
689
690 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
691 u32 access, u32 *error)
692 {
693 struct guest_walker walker;
694 gpa_t gpa = UNMAPPED_GVA;
695 int r;
696
697 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
698
699 if (r) {
700 gpa = gfn_to_gpa(walker.gfn);
701 gpa |= vaddr & ~PAGE_MASK;
702 } else if (error)
703 *error = walker.error_code;
704
705 return gpa;
706 }
707
708 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
709 struct kvm_mmu_page *sp)
710 {
711 int i, j, offset, r;
712 pt_element_t pt[256 / sizeof(pt_element_t)];
713 gpa_t pte_gpa;
714
715 if (sp->role.direct
716 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
717 nonpaging_prefetch_page(vcpu, sp);
718 return;
719 }
720
721 pte_gpa = gfn_to_gpa(sp->gfn);
722 if (PTTYPE == 32) {
723 offset = sp->role.quadrant << PT64_LEVEL_BITS;
724 pte_gpa += offset * sizeof(pt_element_t);
725 }
726
727 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
728 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
729 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
730 for (j = 0; j < ARRAY_SIZE(pt); ++j)
731 if (r || is_present_gpte(pt[j]))
732 sp->spt[i+j] = shadow_trap_nonpresent_pte;
733 else
734 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
735 }
736 }
737
738 /*
739 * Using the cached information from sp->gfns is safe because:
740 * - The spte has a reference to the struct page, so the pfn for a given gfn
741 * can't change unless all sptes pointing to it are nuked first.
742 */
743 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
744 bool clear_unsync)
745 {
746 int i, offset, nr_present;
747 bool reset_host_protection;
748 gpa_t first_pte_gpa;
749
750 offset = nr_present = 0;
751
752 /* direct kvm_mmu_page can not be unsync. */
753 BUG_ON(sp->role.direct);
754
755 if (PTTYPE == 32)
756 offset = sp->role.quadrant << PT64_LEVEL_BITS;
757
758 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
759
760 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
761 unsigned pte_access;
762 pt_element_t gpte;
763 gpa_t pte_gpa;
764 gfn_t gfn;
765 bool rsvd_bits_set;
766
767 if (!is_shadow_present_pte(sp->spt[i]))
768 continue;
769
770 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
771
772 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
773 sizeof(pt_element_t)))
774 return -EINVAL;
775
776 gfn = gpte_to_gfn(gpte);
777 rsvd_bits_set = is_rsvd_bits_set(&vcpu->arch.mmu, gpte,
778 PT_PAGE_TABLE_LEVEL);
779 if (rsvd_bits_set || gfn != sp->gfns[i] ||
780 !is_present_gpte(gpte) || !(gpte & PT_ACCESSED_MASK)) {
781 u64 nonpresent;
782
783 if (rsvd_bits_set || is_present_gpte(gpte) ||
784 !clear_unsync)
785 nonpresent = shadow_trap_nonpresent_pte;
786 else
787 nonpresent = shadow_notrap_nonpresent_pte;
788 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
789 kvm_flush_remote_tlbs(vcpu->kvm);
790 continue;
791 }
792
793 nr_present++;
794 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
795 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
796 pte_access &= ~ACC_WRITE_MASK;
797 reset_host_protection = 0;
798 } else {
799 reset_host_protection = 1;
800 }
801 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
802 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
803 spte_to_pfn(sp->spt[i]), true, false,
804 reset_host_protection);
805 }
806
807 return !nr_present;
808 }
809
810 #undef pt_element_t
811 #undef guest_walker
812 #undef FNAME
813 #undef PT_BASE_ADDR_MASK
814 #undef PT_INDEX
815 #undef PT_LEVEL_MASK
816 #undef PT_LVL_ADDR_MASK
817 #undef PT_LVL_OFFSET_MASK
818 #undef PT_LEVEL_BITS
819 #undef PT_MAX_FULL_LEVELS
820 #undef gpte_to_gfn
821 #undef gpte_to_gfn_lvl
822 #undef CMPXCHG
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