drivers/staging/silicom/bp_mod.h

   1 /******************************************************************************/
   2 /*                                                                            */
   3 /* Bypass Control utility, Copyright (c) 2005 Silicom                         */
   4 /*                                                                            */
   5 /* This program is free software; you can redistribute it and/or modify       */
   6 /* it under the terms of the GNU General Public License as published by       */
   7 /* the Free Software Foundation, located in the file LICENSE.                 */
   8 /*                                                                            */
   9 /*                                                                            */
  10 /* bp_mod.h                                                                   */
  11 /*                                                                            */
  12 /******************************************************************************/
  13
  14 #ifndef BP_MOD_H
  15 #define BP_MOD_H
  16 #include "bits.h"
  17
  18 #define usec_delay(x) udelay(x)
  19 #ifndef msec_delay_bp
  20 #define msec_delay_bp(x)                        \
  21 do {                                            \
  22         int  i;                                 \
  23         if (1) {                                \
  24                 for (i = 0; i < 1000; i++) {    \
  25                         udelay(x);              \
  26                 }                               \
  27         } else {                                \
  28                 msleep(x);                      \
  29         }                                       \
  30 } while (0)
  31
  32 #endif
  33
  34 #include <linux/param.h>
  35
  36 #ifndef jiffies_to_msecs
  37 #define jiffies_to_msecs(x) _kc_jiffies_to_msecs(x)
  38 static inline unsigned int jiffies_to_msecs(const unsigned long j)
  39 {
  40 #if HZ <= 1000 && !(1000 % HZ)
  41         return (1000 / HZ) * j;
  42 #elif HZ > 1000 && !(HZ % 1000)
  43         return (j + (HZ / 1000) - 1) / (HZ / 1000);
  44 #else
  45         return (j * 1000) / HZ;
  46 #endif
  47 }
  48 #endif
  49
  50 #define SILICOM_VID              0x1374
  51 #define SILICOM_SVID             0x1374
  52
  53 #define SILICOM_PXG2BPFI_SSID    0x0026
  54 #define SILICOM_PXG2BPFILX_SSID  0x0027
  55 #define SILICOM_PXGBPI_SSID      0x0028
  56 #define SILICOM_PXGBPIG_SSID     0x0029
  57 #define SILICOM_PXG2TBFI_SSID    0x002a
  58 #define SILICOM_PXG4BPI_SSID     0x002c
  59 #define SILICOM_PXG4BPFI_SSID    0x002d
  60 #define SILICOM_PXG4BPFILX_SSID  0x002e
  61 #define SILICOM_PXG2BPFIL_SSID   0x002F
  62 #define SILICOM_PXG2BPFILLX_SSID 0x0030
  63 #define SILICOM_PEG4BPI_SSID     0x0031
  64 #define SILICOM_PEG2BPI_SSID     0x0037
  65 #define SILICOM_PEG4BPIN_SSID    0x0038
  66 #define SILICOM_PEG2BPFI_SSID    0x0039
  67 #define SILICOM_PEG2BPFILX_SSID  0x003A
  68 #define SILICOM_PMCXG2BPFI_SSID  0x003B
  69 #define NOKIA_PMCXG2BPFIN_SSID   0x0510
  70 #define NOKIA_PMCXG2BPIN_SSID    0x0513
  71 #define NOKIA_PMCXG4BPIN_SSID    0x0514
  72 #define NOKIA_PMCXG2BPFIN_SVID   0x13B8
  73 #define NOKIA_PMCXG2BPIN2_SSID    0x0515
  74 #define NOKIA_PMCXG4BPIN2_SSID    0x0516
  75 #define SILICOM_PMCX2BPI_SSID       0x041
  76 #define SILICOM_PMCX4BPI_SSID       0x042
  77 #define SILICOM_PXG2BISC1_SSID   0x003d
  78 #define SILICOM_PEG2TBFI_SSID    0x003E
  79 #define SILICOM_PXG2TBI_SSID     0x003f
  80 #define SILICOM_PXG4BPFID_SSID   0x0043
  81 #define SILICOM_PEG4BPFI_SSID    0x0040
  82 #define SILICOM_PEG4BPIPT_SSID   0x0044
  83 #define SILICOM_PXG6BPI_SSID     0x0045
  84 #define SILICOM_PEG4BPIL_SSID    0x0046
  85 #define SILICOM_PEG2BPI5_SSID    0x0052
  86 #define SILICOM_PEG6BPI_SSID    0x0053
  87 #define SILICOM_PEG4BPFI5_SSID   0x0050
  88 #define SILICOM_PEG4BPFI5LX_SSID   0x0051
  89 #define SILICOM_PEG2BISC6_SSID 0x54
  90
  91 #define SILICOM_PEG6BPIFC_SSID 0x55
  92
  93 #define SILICOM_PEG2BPFI5_SSID   0x0056
  94 #define SILICOM_PEG2BPFI5LX_SSID   0x0057
  95
  96 #define SILICOM_PXEG4BPFI_SSID    0x0058
  97
  98 #define SILICOM_PEG2BPFID_SSID   0x0047
  99 #define SILICOM_PEG2BPFIDLX_SSID  0x004C
 100 #define SILICOM_MEG2BPFILN_SSID  0x0048
 101 #define SILICOM_MEG2BPFINX_SSID  0x0049
 102 #define SILICOM_PEG4BPFILX_SSID  0x004A
 103 #define SILICOM_MHIO8AD_SSID    0x004F
 104
 105 #define SILICOM_MEG2BPFILXLN_SSID 0x004b
 106 #define SILICOM_PEG2BPIX1_SSID    0x004d
 107 #define SILICOM_MEG2BPFILXNX_SSID 0x004e
 108
 109 #define SILICOM_PE10G2BPISR_SSID  0x0102
 110 #define SILICOM_PE10G2BPILR_SSID  0x0103
 111 #define SILICOM_PE10G2BPICX4_SSID  0x0101
 112
 113 #define SILICOM_XE10G2BPILR_SSID 0x0163
 114 #define SILICOM_XE10G2BPISR_SSID 0x0162
 115 #define SILICOM_XE10G2BPICX4_SSID 0x0161
 116 #define SILICOM_XE10G2BPIT_SSID   0x0160
 117
 118 #define SILICOM_PE10GDBISR_SSID   0x0181
 119 #define SILICOM_PE10GDBILR_SSID   0x0182
 120
 121 #define SILICOM_PE210G2DBi9SR_SSID          0x0188
 122 #define SILICOM_PE210G2DBi9SRRB_SSID    0x0188
 123 #define SILICOM_PE210G2DBi9LR_SSID          0x0189
 124 #define SILICOM_PE210G2DBi9LRRB_SSID    0x0189
 125 #define SILICOM_PE310G4DBi940SR_SSID    0x018C
 126
 127 #define SILICOM_PE310G4BPi9T_SSID       0x130
 128 #define SILICOM_PE310G4BPi9SR_SSID        0x132
 129 #define SILICOM_PE310G4BPi9LR_SSID        0x133
 130
 131 #define NOKIA_XE10G2BPIXR_SVID   0x13B8
 132 #define NOKIA_XE10G2BPIXR_SSID   0x051C
 133
 134 #define INTEL_PEG4BPII_PID   0x10A0
 135 #define INTEL_PEG4BPFII_PID   0x10A1
 136 #define INTEL_PEG4BPII_SSID   0x11A0
 137 #define INTEL_PEG4BPFII_SSID   0x11A1
 138
 139 #define INTEL_PEG4BPIIO_SSID   0x10A0
 140 #define INTEL_PEG4BPIIO_PID   0x105e
 141
 142 #define BROADCOM_VID         0x14e4
 143 #define BROADCOM_PE10G2_PID  0x164e
 144
 145 #define SILICOM_PE10G2BPTCX4_SSID 0x0141
 146 #define SILICOM_PE10G2BPTSR_SSID  0x0142
 147 #define SILICOM_PE10G2BPTLR_SSID  0x0143
 148 #define SILICOM_PE10G2BPTT_SSID   0x0140
 149
 150 #define SILICOM_PEG4BPI6_SSID     0x0320
 151 #define SILICOM_PEG4BPFI6_SSID    0x0321
 152 #define SILICOM_PEG4BPFI6LX_SSID    0x0322
 153 #define SILICOM_PEG4BPFI6ZX_SSID    0x0323
 154
 155 #define SILICOM_PEG2BPI6_SSID    0x0300
 156 #define SILICOM_PEG2BPFI6_SSID    0x0301
 157 #define SILICOM_PEG2BPFI6LX_SSID    0x0302
 158 #define SILICOM_PEG2BPFI6ZX_SSID    0x0303
 159 #define SILICOM_PEG2BPFI6FLXM_SSID  0x0304
 160
 161 #define SILICOM_PEG2DBI6_SSID    0x0308
 162 #define SILICOM_PEG2DBFI6_SSID    0x0309
 163 #define SILICOM_PEG2DBFI6LX_SSID    0x030A
 164 #define SILICOM_PEG2DBFI6ZX_SSID    0x030B
 165
 166 #define SILICOM_MEG2BPI6_SSID     0x0310
 167 #define SILICOM_XEG2BPI6_SSID    0x0318
 168 #define SILICOM_PEG4BPI6FC_SSID     0x0328
 169 #define SILICOM_PEG4BPFI6FC_SSID    0x0329
 170 #define SILICOM_PEG4BPFI6FCLX_SSID    0x032A
 171 #define SILICOM_PEG4BPFI6FCZX_SSID    0x032B
 172
 173 #define SILICOM_PEG6BPI6_SSID     0x0340
 174
 175 #define SILICOM_PEG2BPI6SC6_SSID     0x0360
 176
 177 #define SILICOM_MEG2BPI6_SSID     0x0310
 178 #define SILICOM_XEG2BPI6_SSID     0x0318
 179 #define SILICOM_MEG4BPI6_SSID     0x0330
 180
 181 #define SILICOM_PE2G4BPi80L_SSID    0x0380
 182
 183 #define SILICOM_M6E2G8BPi80A_SSID    0x0474
 184
 185 #define SILICOM_PE2G4BPi35_SSID    0x03d8
 186
 187 #define SILICOM_PE2G4BPFi80_SSID    0x0381
 188 #define SILICOM_PE2G4BPFi80LX_SSID    0x0382
 189 #define SILICOM_PE2G4BPFi80ZX_SSID    0x0383
 190
 191 #define SILICOM_PE2G4BPi80_SSID    0x0388
 192
 193 #define SILICOM_PE2G2BPi80_SSID    0x0390
 194 #define SILICOM_PE2G2BPFi80_SSID    0x0391
 195 #define SILICOM_PE2G2BPFi80LX_SSID    0x0392
 196 #define SILICOM_PE2G2BPFi80ZX_SSID    0x0393
 197
 198 #define SILICOM_PE2G4BPi35L_SSID    0x03D0
 199 #define SILICOM_PE2G4BPFi35_SSID    0x03D1
 200 #define SILICOM_PE2G4BPFi35LX_SSID    0x03D2
 201 #define SILICOM_PE2G4BPFi35ZX_SSID    0x03D3
 202
 203 #define SILICOM_PE2G2BPi35_SSID    0x03c0
 204 #define SILICOM_PAC1200BPi35_SSID    0x03cc
 205 #define SILICOM_PE2G2BPFi35_SSID    0x03C1
 206 #define SILICOM_PE2G2BPFi35LX_SSID    0x03C2
 207 #define SILICOM_PE2G2BPFi35ZX_SSID    0x03C3
 208
 209 #define SILICOM_PE2G6BPi35_SSID    0x03E0
 210 #define SILICOM_PE2G6BPi35CX_SSID  0x0AA0
 211
 212 #define INTEL_PE210G2SPI9_SSID     0x00C
 213
 214 #define SILICOM_M1EG2BPI6_SSID     0x400
 215
 216 #define SILICOM_M1EG2BPFI6_SSID     0x0401
 217 #define SILICOM_M1EG2BPFI6LX_SSID     0x0402
 218 #define SILICOM_M1EG2BPFI6ZX_SSID     0x0403
 219
 220 #define SILICOM_M1EG4BPI6_SSID     0x0420
 221
 222 #define SILICOM_M1EG4BPFI6_SSID       0x0421
 223 #define SILICOM_M1EG4BPFI6LX_SSID     0x0422
 224 #define SILICOM_M1EG4BPFI6ZX_SSID     0x0423
 225
 226 #define SILICOM_M1EG6BPI6_SSID     0x0440
 227
 228 #define SILICOM_M1E2G4BPi80_SSID     0x0460
 229 #define SILICOM_M1E2G4BPFi80_SSID       0x0461
 230 #define SILICOM_M1E2G4BPFi80LX_SSID     0x0462
 231 #define SILICOM_M1E2G4BPFi80ZX_SSID     0x0463
 232
 233 #define SILICOM_M6E2G8BPi80_SSID        0x0470
 234 #define SILICOM_PE210G2BPi40_SSID       0x01a0
 235
 236 #define PEG540_IF_SERIES(pid) \
 237         ((pid == SILICOM_PE210G2BPi40_SSID))
 238
 239 #define OLD_IF_SERIES(pid)\
 240         ((pid == SILICOM_PXG2BPFI_SSID) || \
 241          (pid == SILICOM_PXG2BPFILX_SSID))
 242
 243 #define P2BPFI_IF_SERIES(pid) \
 244         ((pid == SILICOM_PXG2BPFI_SSID) || \
 245          (pid == SILICOM_PXG2BPFILX_SSID) || \
 246          (pid == SILICOM_PEG2BPFI_SSID) || \
 247          (pid == SILICOM_PEG2BPFID_SSID) || \
 248          (pid == SILICOM_PEG2BPFIDLX_SSID) || \
 249          (pid == SILICOM_MEG2BPFILN_SSID) || \
 250          (pid == SILICOM_MEG2BPFINX_SSID) || \
 251          (pid == SILICOM_PEG4BPFILX_SSID) || \
 252          (pid == SILICOM_PEG4BPFI_SSID) || \
 253          (pid == SILICOM_PXEG4BPFI_SSID) || \
 254          (pid == SILICOM_PXG4BPFID_SSID) || \
 255          (pid == SILICOM_PEG2TBFI_SSID) || \
 256          (pid == SILICOM_PE10G2BPISR_SSID) || \
 257          (pid == SILICOM_PE10G2BPILR_SSID) || \
 258          (pid == SILICOM_PEG2BPFILX_SSID) || \
 259          (pid == SILICOM_PMCXG2BPFI_SSID) || \
 260          (pid == SILICOM_MHIO8AD_SSID) || \
 261          (pid == SILICOM_PEG4BPFI5LX_SSID) || \
 262          (pid == SILICOM_PEG4BPFI5_SSID) || \
 263          (pid == SILICOM_PEG4BPFI6FC_SSID) || \
 264          (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
 265          (pid == SILICOM_PEG4BPFI6FCZX_SSID) || \
 266          (pid == NOKIA_PMCXG2BPFIN_SSID) || \
 267          (pid == SILICOM_MEG2BPFILXLN_SSID) || \
 268          (pid == SILICOM_MEG2BPFILXNX_SSID) || \
 269          (pid == SILICOM_XE10G2BPIT_SSID) || \
 270          (pid == SILICOM_XE10G2BPICX4_SSID) || \
 271          (pid == SILICOM_XE10G2BPISR_SSID) || \
 272          (pid == NOKIA_XE10G2BPIXR_SSID) || \
 273          (pid == SILICOM_PE10GDBISR_SSID) || \
 274          (pid == SILICOM_PE10GDBILR_SSID) || \
 275          (pid == SILICOM_XE10G2BPILR_SSID))
 276
 277 #define INTEL_IF_SERIES(pid) \
 278         ((pid == INTEL_PEG4BPII_SSID) || \
 279          (pid == INTEL_PEG4BPIIO_SSID) || \
 280          (pid == INTEL_PEG4BPFII_SSID))
 281
 282 #define NOKIA_SERIES(pid) \
 283         ((pid == NOKIA_PMCXG2BPIN_SSID) || \
 284          (pid == NOKIA_PMCXG4BPIN_SSID) || \
 285          (pid == SILICOM_PMCX4BPI_SSID) || \
 286          (pid == NOKIA_PMCXG2BPFIN_SSID) || \
 287          (pid == SILICOM_PMCXG2BPFI_SSID) || \
 288          (pid == NOKIA_PMCXG2BPIN2_SSID) || \
 289          (pid == NOKIA_PMCXG4BPIN2_SSID) || \
 290          (pid == SILICOM_PMCX2BPI_SSID))
 291
 292 #define DISCF_IF_SERIES(pid) \
 293         (pid == SILICOM_PEG2TBFI_SSID)
 294
 295 #define PEGF_IF_SERIES(pid) \
 296         ((pid == SILICOM_PEG2BPFI_SSID) || \
 297          (pid == SILICOM_PEG2BPFID_SSID) || \
 298          (pid == SILICOM_PEG2BPFIDLX_SSID) || \
 299          (pid == SILICOM_PEG2BPFILX_SSID) || \
 300          (pid == SILICOM_PEG4BPFI_SSID) || \
 301          (pid == SILICOM_PXEG4BPFI_SSID) || \
 302          (pid == SILICOM_MEG2BPFILN_SSID) || \
 303          (pid == SILICOM_MEG2BPFINX_SSID) || \
 304          (pid == SILICOM_PEG4BPFILX_SSID) || \
 305          (pid == SILICOM_PEG2TBFI_SSID) || \
 306          (pid == SILICOM_MEG2BPFILXLN_SSID) || \
 307          (pid == SILICOM_MEG2BPFILXNX_SSID))
 308
 309 #define TPL_IF_SERIES(pid) \
 310         ((pid == SILICOM_PXG2BPFIL_SSID) || \
 311          (pid == SILICOM_PXG2BPFILLX_SSID) || \
 312          (pid == SILICOM_PXG2TBFI_SSID) || \
 313          (pid == SILICOM_PXG4BPFID_SSID) || \
 314          (pid == SILICOM_PXG4BPFI_SSID))
 315
 316 #define BP10G_IF_SERIES(pid) \
 317         ((pid == SILICOM_PE10G2BPISR_SSID) || \
 318          (pid == SILICOM_PE10G2BPICX4_SSID) || \
 319          (pid == SILICOM_PE10G2BPILR_SSID) || \
 320          (pid == SILICOM_XE10G2BPIT_SSID) || \
 321          (pid == SILICOM_XE10G2BPICX4_SSID) || \
 322          (pid == SILICOM_XE10G2BPISR_SSID) || \
 323          (pid == NOKIA_XE10G2BPIXR_SSID) || \
 324          (pid == SILICOM_PE10GDBISR_SSID) || \
 325          (pid == SILICOM_PE10GDBILR_SSID) || \
 326          (pid == SILICOM_XE10G2BPILR_SSID))
 327
 328 #define BP10GB_IF_SERIES(pid) \
 329         ((pid == SILICOM_PE10G2BPTCX4_SSID) || \
 330          (pid == SILICOM_PE10G2BPTSR_SSID) || \
 331          (pid == SILICOM_PE10G2BPTLR_SSID) || \
 332          (pid == SILICOM_PE10G2BPTT_SSID))
 333
 334 #define BP10G_CX4_SERIES(pid) \
 335         (pid == SILICOM_PE10G2BPICX4_SSID)
 336
 337 #define BP10GB_CX4_SERIES(pid) \
 338         (pid == SILICOM_PE10G2BPTCX4_SSID)
 339
 340 #define SILICOM_M2EG2BPFI6_SSID       0x0501
 341 #define SILICOM_M2EG2BPFI6LX_SSID     0x0502
 342 #define SILICOM_M2EG2BPFI6ZX_SSID     0x0503
 343 #define SILICOM_M2EG4BPI6_SSID        0x0520
 344
 345 #define SILICOM_M2EG4BPFI6_SSID       0x0521
 346 #define SILICOM_M2EG4BPFI6LX_SSID     0x0522
 347 #define SILICOM_M2EG4BPFI6ZX_SSID     0x0523
 348
 349 #define SILICOM_M2EG6BPI6_SSID     0x0540
 350
 351 #define SILICOM_M1E10G2BPI9CX4_SSID  0x481
 352 #define SILICOM_M1E10G2BPI9SR_SSID   0x482
 353 #define SILICOM_M1E10G2BPI9LR_SSID   0x483
 354 #define SILICOM_M1E10G2BPI9T_SSID    0x480
 355
 356 #define SILICOM_M2E10G2BPI9CX4_SSID  0x581
 357 #define SILICOM_M2E10G2BPI9SR_SSID   0x582
 358 #define SILICOM_M2E10G2BPI9LR_SSID   0x583
 359 #define SILICOM_M2E10G2BPI9T_SSID    0x580
 360
 361 #define SILICOM_PE210G2BPI9CX4_SSID  0x121
 362 #define SILICOM_PE210G2BPI9SR_SSID   0x122
 363 #define SILICOM_PE210G2BPI9LR_SSID   0x123
 364 #define SILICOM_PE210G2BPI9T_SSID    0x120
 365
 366 #define DBI_IF_SERIES(pid) \
 367         ((pid == SILICOM_PE10GDBISR_SSID) || \
 368          (pid == SILICOM_PE10GDBILR_SSID) || \
 369          (pid == SILICOM_XE10G2BPILR_SSID) || \
 370          (pid == SILICOM_PE210G2DBi9LR_SSID))
 371
 372 #define PEGF5_IF_SERIES(pid) \
 373         ((pid == SILICOM_PEG2BPFI5_SSID) || \
 374          (pid == SILICOM_PEG2BPFI5LX_SSID) || \
 375          (pid == SILICOM_PEG4BPFI6_SSID) || \
 376          (pid == SILICOM_PEG4BPFI6LX_SSID) || \
 377          (pid == SILICOM_PEG4BPFI6ZX_SSID) || \
 378          (pid == SILICOM_PEG2BPFI6_SSID) || \
 379          (pid == SILICOM_PEG2BPFI6LX_SSID) || \
 380          (pid == SILICOM_PEG2BPFI6ZX_SSID) || \
 381          (pid == SILICOM_PEG2BPFI6FLXM_SSID) || \
 382          (pid == SILICOM_PEG2DBFI6_SSID) || \
 383          (pid == SILICOM_PEG2DBFI6LX_SSID) || \
 384          (pid == SILICOM_PEG2DBFI6ZX_SSID) || \
 385          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 386          (pid == SILICOM_PEG4BPFI6FCLX_SSID) || \
 387          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 388          (pid == SILICOM_M1EG2BPFI6_SSID) || \
 389          (pid == SILICOM_M1EG2BPFI6LX_SSID) || \
 390          (pid == SILICOM_M1EG2BPFI6ZX_SSID) || \
 391          (pid == SILICOM_M1EG4BPFI6_SSID) || \
 392          (pid == SILICOM_M1EG4BPFI6LX_SSID) || \
 393          (pid == SILICOM_M1EG4BPFI6ZX_SSID) || \
 394          (pid == SILICOM_M2EG2BPFI6_SSID) || \
 395          (pid == SILICOM_M2EG2BPFI6LX_SSID) || \
 396          (pid == SILICOM_M2EG2BPFI6ZX_SSID) || \
 397          (pid == SILICOM_M2EG4BPFI6_SSID) || \
 398          (pid == SILICOM_M2EG4BPFI6LX_SSID) || \
 399          (pid == SILICOM_M2EG4BPFI6ZX_SSID) || \
 400          (pid == SILICOM_PEG4BPFI6FCZX_SSID))
 401
 402 #define PEG5_IF_SERIES(pid) \
 403         ((pid == SILICOM_PEG4BPI6_SSID) || \
 404          (pid == SILICOM_PEG2BPI6_SSID) || \
 405          (pid == SILICOM_PEG4BPI6FC_SSID) || \
 406          (pid == SILICOM_PEG6BPI6_SSID) || \
 407          (pid == SILICOM_PEG2BPI6SC6_SSID) || \
 408          (pid == SILICOM_MEG2BPI6_SSID) || \
 409          (pid == SILICOM_XEG2BPI6_SSID) || \
 410          (pid == SILICOM_MEG4BPI6_SSID) || \
 411          (pid == SILICOM_M1EG2BPI6_SSID) || \
 412          (pid == SILICOM_M1EG4BPI6_SSID) || \
 413          (pid == SILICOM_M1EG6BPI6_SSID) || \
 414          (pid == SILICOM_PEG6BPI_SSID) || \
 415          (pid == SILICOM_PEG4BPIL_SSID) || \
 416          (pid == SILICOM_PEG2BISC6_SSID) || \
 417          (pid == SILICOM_PEG2BPI5_SSID))
 418
 419 #define PEG80_IF_SERIES(pid) \
 420         ((pid == SILICOM_M1E2G4BPi80_SSID) || \
 421          (pid == SILICOM_M6E2G8BPi80_SSID) || \
 422          (pid == SILICOM_PE2G4BPi80L_SSID) || \
 423          (pid == SILICOM_M6E2G8BPi80A_SSID) || \
 424          (pid == SILICOM_PE2G2BPi35_SSID) || \
 425          (pid == SILICOM_PAC1200BPi35_SSID) || \
 426          (pid == SILICOM_PE2G4BPi35_SSID) || \
 427          (pid == SILICOM_PE2G4BPi35L_SSID) || \
 428          (pid == SILICOM_PE2G6BPi35_SSID) || \
 429          (pid == SILICOM_PE2G2BPi80_SSID) || \
 430          (pid == SILICOM_PE2G4BPi80_SSID) || \
 431          (pid == SILICOM_PE2G4BPFi80_SSID) || \
 432          (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
 433          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 434          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 435          (pid == SILICOM_PE2G2BPFi80_SSID) || \
 436          (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
 437          (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
 438          (pid == SILICOM_PE2G2BPFi35_SSID) || \
 439          (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
 440          (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
 441          (pid == SILICOM_PE2G4BPFi35_SSID) || \
 442          (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
 443          (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 444
 445 #define PEGF80_IF_SERIES(pid) \
 446         ((pid == SILICOM_PE2G4BPFi80_SSID) || \
 447          (pid == SILICOM_PE2G4BPFi80LX_SSID) || \
 448          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 449          (pid == SILICOM_PE2G4BPFi80ZX_SSID) || \
 450          (pid == SILICOM_M1E2G4BPFi80_SSID) || \
 451          (pid == SILICOM_M1E2G4BPFi80LX_SSID) || \
 452          (pid == SILICOM_M1E2G4BPFi80ZX_SSID) || \
 453          (pid == SILICOM_PE2G2BPFi80_SSID) || \
 454          (pid == SILICOM_PE2G2BPFi80LX_SSID) || \
 455          (pid == SILICOM_PE2G2BPFi80ZX_SSID) || \
 456          (pid == SILICOM_PE2G2BPFi35_SSID) || \
 457          (pid == SILICOM_PE2G2BPFi35LX_SSID) || \
 458          (pid == SILICOM_PE2G2BPFi35ZX_SSID) || \
 459          (pid == SILICOM_PE2G4BPFi35_SSID) || \
 460          (pid == SILICOM_PE2G4BPFi35LX_SSID) || \
 461          (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 462
 463 #define BP10G9_IF_SERIES(pid) \
 464         ((pid == INTEL_PE210G2SPI9_SSID) || \
 465          (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \
 466          (pid == SILICOM_M1E10G2BPI9SR_SSID) || \
 467          (pid == SILICOM_M1E10G2BPI9LR_SSID) || \
 468          (pid == SILICOM_M1E10G2BPI9T_SSID) || \
 469          (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \
 470          (pid == SILICOM_M2E10G2BPI9SR_SSID) || \
 471          (pid == SILICOM_M2E10G2BPI9LR_SSID) || \
 472          (pid == SILICOM_M2E10G2BPI9T_SSID) || \
 473          (pid == SILICOM_PE210G2BPI9CX4_SSID) || \
 474          (pid == SILICOM_PE210G2BPI9SR_SSID) || \
 475          (pid == SILICOM_PE210G2BPI9LR_SSID) || \
 476          (pid == SILICOM_PE210G2DBi9SR_SSID) || \
 477          (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \
 478          (pid == SILICOM_PE210G2DBi9LR_SSID) || \
 479          (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \
 480          (pid == SILICOM_PE310G4DBi940SR_SSID) || \
 481          (pid == SILICOM_PEG2BISC6_SSID) || \
 482          (pid == SILICOM_PE310G4BPi9T_SSID) || \
 483          (pid == SILICOM_PE310G4BPi9SR_SSID) || \
 484          (pid == SILICOM_PE310G4BPi9LR_SSID) || \
 485          (pid == SILICOM_PE210G2BPI9T_SSID))
 486
 487 /*******************************************************/
 488 /* 1G INTERFACE ****************************************/
 489 /*******************************************************/
 490
 491 /* Intel Registers */
 492 #define BPCTLI_CTRL          0x00000
 493 #define BPCTLI_CTRL_SWDPIO0  0x00400000
 494 #define BPCTLI_CTRL_SWDPIN0  0x00040000
 495
 496 #define BPCTLI_CTRL_EXT 0x00018 /* Extended Device Control - RW */
 497 #define BPCTLI_STATUS   0x00008 /* Device Status - RO */
 498
 499 /* HW related */
 500 #define BPCTLI_CTRL_EXT_SDP6_DATA 0x00000040    /* Value of SW
 501                                                                                      * Defineable Pin 6
 502                                                                                      */
 503 #define BPCTLI_CTRL_EXT_SDP7_DATA 0x00000080    /* Value of SW
 504                                                                                      * Defineable Pin 7
 505                                                                                      */
 506 #define BPCTLI_CTRL_SDP0_DATA     0x00040000    /* SWDPIN 0 value */
 507 #define BPCTLI_CTRL_EXT_SDP6_DIR  0x00000400    /* Direction of SDP6
 508                                                                                    * 0=in 1=out
 509                                                                                    */
 510 #define BPCTLI_CTRL_EXT_SDP7_DIR  0x00000800    /* Direction of SDP7
 511                                                                                    * 0=in 1=out
 512                                                                                    */
 513 #define BPCTLI_CTRL_SDP0_DIR      0x00400000    /* SDP0 Input or output */
 514 #define BPCTLI_CTRL_SWDPIN1       0x00080000
 515 #define BPCTLI_CTRL_SDP1_DIR      0x00800000
 516
 517 #define BPCTLI_STATUS_LU          0x00000002    /* Link up.0=no,1=link */
 518
 519 #define BPCTLI_CTRL_SDP0_SHIFT     18
 520 #define BPCTLI_CTRL_EXT_SDP6_SHIFT 6
 521
 522 #define BPCTLI_STATUS_TBIMODE     0x00000020
 523 #define BPCTLI_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
 524 #define BPCTLI_CTRL_EXT_LINK_MODE_MASK         0x00C00000
 525
 526 #define BPCTLI_CTRL_EXT_MCLK_DIR  BPCTLI_CTRL_EXT_SDP7_DIR
 527 #define BPCTLI_CTRL_EXT_MCLK_DATA BPCTLI_CTRL_EXT_SDP7_DATA
 528 #define BPCTLI_CTRL_EXT_MDIO_DIR  BPCTLI_CTRL_EXT_SDP6_DIR
 529 #define BPCTLI_CTRL_EXT_MDIO_DATA BPCTLI_CTRL_EXT_SDP6_DATA
 530
 531 #define BPCTLI_CTRL_EXT_MCLK_DIR5  BPCTLI_CTRL_SDP1_DIR
 532 #define BPCTLI_CTRL_EXT_MCLK_DATA5 BPCTLI_CTRL_SWDPIN1
 533 #define BPCTLI_CTRL_EXT_MCLK_DIR80  BPCTLI_CTRL_EXT_SDP6_DIR
 534 #define BPCTLI_CTRL_EXT_MCLK_DATA80 BPCTLI_CTRL_EXT_SDP6_DATA
 535 #define BPCTLI_CTRL_EXT_MDIO_DIR5  BPCTLI_CTRL_SWDPIO0
 536 #define BPCTLI_CTRL_EXT_MDIO_DATA5 BPCTLI_CTRL_SWDPIN0
 537 #define BPCTLI_CTRL_EXT_MDIO_DIR80  BPCTLI_CTRL_SWDPIO0
 538 #define BPCTLI_CTRL_EXT_MDIO_DATA80 BPCTLI_CTRL_SWDPIN0
 539
 540 #define BPCTL_WRITE_REG(a, reg, value) \
 541         (writel((value), (void *)(((a)->mem_map) + BPCTLI_##reg)))
 542
 543 #define BPCTL_READ_REG(a, reg) ( \
 544         readl((void *)((a)->mem_map) + BPCTLI_##reg))
 545
 546 #define BPCTL_WRITE_FLUSH(a) BPCTL_READ_REG(a, STATUS)
 547
 548 #define BPCTL_BP_WRITE_REG(a, reg, value) ({ \
 549         BPCTL_WRITE_REG(a, reg, value); \
 550         BPCTL_WRITE_FLUSH(a); })
 551
 552 /**************************************************************/
 553 /************** 82575 Interface********************************/
 554 /**************************************************************/
 555
 556 #define BPCTLI_MII_CR_POWER_DOWN       0x0800
 557 #define BPCTLI_PHY_CONTROL      0x00    /* Control Register */
 558 #define BPCTLI_MDIC     0x00020 /* MDI Control - RW */
 559 #define BPCTLI_IGP01E1000_PHY_PAGE_SELECT        0x1F   /* Page Select */
 560 #define BPCTLI_MAX_PHY_REG_ADDRESS    0x1F      /* 5 bit address bus (0-0x1F) */
 561
 562 #define BPCTLI_MDIC_DATA_MASK 0x0000FFFF
 563 #define BPCTLI_MDIC_REG_MASK  0x001F0000
 564 #define BPCTLI_MDIC_REG_SHIFT 16
 565 #define BPCTLI_MDIC_PHY_MASK  0x03E00000
 566 #define BPCTLI_MDIC_PHY_SHIFT 21
 567 #define BPCTLI_MDIC_OP_WRITE  0x04000000
 568 #define BPCTLI_MDIC_OP_READ   0x08000000
 569 #define BPCTLI_MDIC_READY     0x10000000
 570 #define BPCTLI_MDIC_INT_EN    0x20000000
 571 #define BPCTLI_MDIC_ERROR     0x40000000
 572
 573 #define BPCTLI_SWFW_PHY0_SM  0x02
 574 #define BPCTLI_SWFW_PHY1_SM  0x04
 575
 576 #define BPCTLI_SW_FW_SYNC  0x05B5C      /* Software-Firmware
 577                                                                      * Synchronization - RW
 578                                                                      */
 579
 580 #define BPCTLI_SWSM      0x05B50        /* SW Semaphore */
 581 #define BPCTLI_FWSM      0x05B54        /* FW Semaphore */
 582
 583 #define BPCTLI_SWSM_SMBI         0x00000001     /* Driver Semaphore bit */
 584 #define BPCTLI_SWSM_SWESMBI      0x00000002     /* FW Semaphore bit */
 585 #define BPCTLI_MAX_PHY_MULTI_PAGE_REG 0xF
 586 #define BPCTLI_GEN_POLL_TIMEOUT          640
 587
 588 /********************************************************/
 589
 590 /********************************************************/
 591 /* 10G INTERFACE ****************************************/
 592 /********************************************************/
 593
 594 #define BP10G_I2CCTL              0x28
 595
 596 /* I2CCTL Bit Masks */
 597 #define BP10G_I2C_CLK_IN    0x00000001
 598 #define BP10G_I2C_CLK_OUT   0x00000002
 599 #define BP10G_I2C_DATA_IN   0x00000004
 600 #define BP10G_I2C_DATA_OUT  0x00000008
 601
 602 #define BP10G_ESDP                0x20
 603
 604 #define BP10G_SDP0_DIR            0x100
 605 #define BP10G_SDP1_DIR            0x200
 606 #define BP10G_SDP3_DIR            0x800
 607 #define BP10G_SDP4_DIR            BIT_12
 608 #define BP10G_SDP5_DIR            0x2000
 609 #define BP10G_SDP0_DATA           0x001
 610 #define BP10G_SDP1_DATA           0x002
 611 #define BP10G_SDP3_DATA           0x008
 612 #define BP10G_SDP4_DATA           0x010
 613 #define BP10G_SDP5_DATA           0x020
 614
 615 #define BP10G_SDP2_DIR            0x400
 616 #define BP10G_SDP2_DATA            0x4
 617
 618 #define BP10G_EODSDP              0x28
 619
 620 #define BP10G_SDP6_DATA_IN        0x001
 621 #define BP10G_SDP6_DATA_OUT       0x002
 622
 623 #define BP10G_SDP7_DATA_IN        0x004
 624 #define BP10G_SDP7_DATA_OUT       0x008
 625
 626 #define BP10G_MCLK_DATA_OUT       BP10G_SDP7_DATA_OUT
 627 #define BP10G_MDIO_DATA_OUT       BP10G_SDP6_DATA_OUT
 628 #define BP10G_MDIO_DATA_IN        BP10G_SDP6_DATA_IN
 629
 630 #define BP10G_MDIO_DATA           /*BP10G_SDP5_DATA*/ BP10G_SDP3_DATA
 631 #define BP10G_MDIO_DIR            /*BP10G_SDP5_DIR*/  BP10G_SDP3_DATA
 632
 633 /*#define BP10G_MCLK_DATA_OUT9       BP10G_I2C_CLK_OUT
 634 #define BP10G_MDIO_DATA_OUT9       BP10G_I2C_DATA_OUT*/
 635
 636                                        /*#define BP10G_MCLK_DATA_OUT9*/
 637                                         /*BP10G_I2C_DATA_OUT */
 638 #define BP10G_MDIO_DATA_OUT9           BP10G_I2C_DATA_OUT       /*BP10G_I2C_CLK_OUT */
 639
 640 /* VIA EOSDP ! */
 641 #define BP10G_MCLK_DATA_OUT9           BP10G_SDP4_DATA
 642 #define BP10G_MCLK_DIR_OUT9            BP10G_SDP4_DIR
 643
 644 /*#define BP10G_MDIO_DATA_IN9        BP10G_I2C_DATA_IN*/
 645
 646 #define BP10G_MDIO_DATA_IN9           BP10G_I2C_DATA_IN /*BP10G_I2C_CLK_IN */
 647
 648 #define BP540_MDIO_DATA           /*BP10G_SDP5_DATA*/ BP10G_SDP0_DATA
 649 #define BP540_MDIO_DIR            /*BP10G_SDP5_DIR*/  BP10G_SDP0_DIR
 650 #define BP540_MCLK_DATA       BP10G_SDP2_DATA
 651 #define BP540_MCLK_DIR       BP10G_SDP2_DIR
 652
 653 #define BP10G_WRITE_REG(a, reg, value) \
 654         (writel((value), (void *)(((a)->mem_map) + BP10G_##reg)))
 655
 656 #define BP10G_READ_REG(a, reg) ( \
 657         readl((void *)((a)->mem_map) + BP10G_##reg))
 658
 659 /*****BROADCOM*******************************************/
 660
 661 #define BP10GB_MISC_REG_GPIO                                             0xa490
 662 #define BP10GB_GPIO3_P0                              BIT_3
 663 #define BP10GB_GPIO3_P1                              BIT_7
 664
 665 #define BP10GB_GPIO3_SET_P0                          BIT_11
 666 #define BP10GB_GPIO3_CLR_P0                          BIT_19
 667 #define BP10GB_GPIO3_OE_P0                           BIT_27
 668
 669 #define BP10GB_GPIO3_SET_P1                          BIT_15
 670 #define BP10GB_GPIO3_CLR_P1                          BIT_23
 671 #define BP10GB_GPIO3_OE_P1                           BIT_31
 672
 673 #define BP10GB_GPIO0_P1                              0x10
 674 #define BP10GB_GPIO0_P0                              0x1
 675 #define BP10GB_GPIO0_CLR_P0                          0x10000
 676 #define BP10GB_GPIO0_CLR_P1                          0x100000
 677 #define BP10GB_GPIO0_SET_P0                          0x100
 678 #define BP10GB_GPIO0_SET_P1                          0x1000
 679
 680 #define BP10GB_GPIO0_OE_P1                           0x10000000
 681 #define BP10GB_GPIO0_OE_P0                           0x1000000
 682
 683 #define BP10GB_MISC_REG_SPIO                                             0xa4fc
 684 #define BP10GB_GPIO4_OE                              BIT_28
 685 #define BP10GB_GPIO5_OE                              BIT_29
 686 #define BP10GB_GPIO4_CLR                             BIT_20
 687 #define BP10GB_GPIO5_CLR                             BIT_21
 688 #define BP10GB_GPIO4_SET                             BIT_12
 689 #define BP10GB_GPIO5_SET                             BIT_13
 690 #define BP10GB_GPIO4                                 BIT_4
 691 #define BP10GB_GPIO5                                 BIT_5
 692
 693 #define BP10GB_MCLK_DIR  BP10GB_GPIO5_OE
 694 #define BP10GB_MDIO_DIR  BP10GB_GPIO4_OE
 695
 696 #define BP10GB_MCLK_DATA BP10GB_GPIO5
 697 #define BP10GB_MDIO_DATA BP10GB_GPIO4
 698
 699 #define BP10GB_MCLK_SET BP10GB_GPIO5_SET
 700 #define BP10GB_MDIO_SET BP10GB_GPIO4_SET
 701
 702 #define BP10GB_MCLK_CLR BP10GB_GPIO5_CLR
 703 #define BP10GB_MDIO_CLR BP10GB_GPIO4_CLR
 704
 705 #define BP10GB_WRITE_REG(a, reg, value) \
 706         (writel((value), (void *)(((a)->mem_map) + BP10GB_##reg)))
 707
 708 #define BP10GB_READ_REG(a, reg) ( \
 709         readl((void *)((a)->mem_map) + BP10GB_##reg))
 710
 711 #endif