drivers/cpufreq/s5pv210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * CPU frequency scaling for S5PC110/S5PV210
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/cpufreq.h>
  19 #include <linux/reboot.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #include <mach/map.h>
  23 #include <mach/regs-clock.h>
  24
  25 static struct clk *dmc0_clk;
  26 static struct clk *dmc1_clk;
  27 static DEFINE_MUTEX(set_freq_lock);
  28
  29 /* APLL M,P,S values for 1G/800Mhz */
  30 #define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  31 #define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  32
  33 /* Use 800MHz when entering sleep mode */
  34 #define SLEEP_FREQ      (800 * 1000)
  35
  36 /* Tracks if cpu freqency can be updated anymore */
  37 static bool no_cpufreq_access;
  38
  39 /*
  40  * DRAM configurations to calculate refresh counter for changing
  41  * frequency of memory.
  42  */
  43 struct dram_conf {
  44         unsigned long freq;     /* HZ */
  45         unsigned long refresh;  /* DRAM refresh counter * 1000 */
  46 };
  47
  48 /* DRAM configuration (DMC0 and DMC1) */
  49 static struct dram_conf s5pv210_dram_conf[2];
  50
  51 enum perf_level {
  52         L0, L1, L2, L3, L4,
  53 };
  54
  55 enum s5pv210_mem_type {
  56         LPDDR   = 0x1,
  57         LPDDR2  = 0x2,
  58         DDR2    = 0x4,
  59 };
  60
  61 enum s5pv210_dmc_port {
  62         DMC0 = 0,
  63         DMC1,
  64 };
  65
  66 static struct cpufreq_frequency_table s5pv210_freq_table[] = {
  67         {0, L0, 1000*1000},
  68         {0, L1, 800*1000},
  69         {0, L2, 400*1000},
  70         {0, L3, 200*1000},
  71         {0, L4, 100*1000},
  72         {0, 0, CPUFREQ_TABLE_END},
  73 };
  74
  75 static struct regulator *arm_regulator;
  76 static struct regulator *int_regulator;
  77
  78 struct s5pv210_dvs_conf {
  79         int arm_volt;   /* uV */
  80         int int_volt;   /* uV */
  81 };
  82
  83 static const int arm_volt_max = 1350000;
  84 static const int int_volt_max = 1250000;
  85
  86 static struct s5pv210_dvs_conf dvs_conf[] = {
  87         [L0] = {
  88                 .arm_volt       = 1250000,
  89                 .int_volt       = 1100000,
  90         },
  91         [L1] = {
  92                 .arm_volt       = 1200000,
  93                 .int_volt       = 1100000,
  94         },
  95         [L2] = {
  96                 .arm_volt       = 1050000,
  97                 .int_volt       = 1100000,
  98         },
  99         [L3] = {
 100                 .arm_volt       = 950000,
 101                 .int_volt       = 1100000,
 102         },
 103         [L4] = {
 104                 .arm_volt       = 950000,
 105                 .int_volt       = 1000000,
 106         },
 107 };
 108
 109 static u32 clkdiv_val[5][11] = {
 110         /*
 111          * Clock divider value for following
 112          * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
 113          *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
 114          *   ONEDRAM, MFC, G3D }
 115          */
 116
 117         /* L0 : [1000/200/100][166/83][133/66][200/200] */
 118         {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
 119
 120         /* L1 : [800/200/100][166/83][133/66][200/200] */
 121         {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
 122
 123         /* L2 : [400/200/100][166/83][133/66][200/200] */
 124         {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 125
 126         /* L3 : [200/200/100][166/83][133/66][200/200] */
 127         {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 128
 129         /* L4 : [100/100/100][83/83][66/66][100/100] */
 130         {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
 131 };
 132
 133 /*
 134  * This function set DRAM refresh counter
 135  * accoriding to operating frequency of DRAM
 136  * ch: DMC port number 0 or 1
 137  * freq: Operating frequency of DRAM(KHz)
 138  */
 139 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
 140 {
 141         unsigned long tmp, tmp1;
 142         void __iomem *reg = NULL;
 143
 144         if (ch == DMC0) {
 145                 reg = (S5P_VA_DMC0 + 0x30);
 146         } else if (ch == DMC1) {
 147                 reg = (S5P_VA_DMC1 + 0x30);
 148         } else {
 149                 printk(KERN_ERR "Cannot find DMC port\n");
 150                 return;
 151         }
 152
 153         /* Find current DRAM frequency */
 154         tmp = s5pv210_dram_conf[ch].freq;
 155
 156         do_div(tmp, freq);
 157
 158         tmp1 = s5pv210_dram_conf[ch].refresh;
 159
 160         do_div(tmp1, tmp);
 161
 162         __raw_writel(tmp1, reg);
 163 }
 164
 165 static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 166 {
 167         unsigned long reg;
 168         unsigned int priv_index;
 169         unsigned int pll_changing = 0;
 170         unsigned int bus_speed_changing = 0;
 171         unsigned int old_freq, new_freq;
 172         int arm_volt, int_volt;
 173         int ret = 0;
 174
 175         mutex_lock(&set_freq_lock);
 176
 177         if (no_cpufreq_access) {
 178 #ifdef CONFIG_PM_VERBOSE
 179                 pr_err("%s:%d denied access to %s as it is disabled"
 180                                 "temporarily\n", __FILE__, __LINE__, __func__);
 181 #endif
 182                 ret = -EINVAL;
 183                 goto exit;
 184         }
 185
 186         old_freq = policy->cur;
 187         new_freq = s5pv210_freq_table[index].frequency;
 188
 189         /* Finding current running level index */
 190         if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 191                                            old_freq, CPUFREQ_RELATION_H,
 192                                            &priv_index)) {
 193                 ret = -EINVAL;
 194                 goto exit;
 195         }
 196
 197         arm_volt = dvs_conf[index].arm_volt;
 198         int_volt = dvs_conf[index].int_volt;
 199
 200         if (new_freq > old_freq) {
 201                 ret = regulator_set_voltage(arm_regulator,
 202                                 arm_volt, arm_volt_max);
 203                 if (ret)
 204                         goto exit;
 205
 206                 ret = regulator_set_voltage(int_regulator,
 207                                 int_volt, int_volt_max);
 208                 if (ret)
 209                         goto exit;
 210         }
 211
 212         /* Check if there need to change PLL */
 213         if ((index == L0) || (priv_index == L0))
 214                 pll_changing = 1;
 215
 216         /* Check if there need to change System bus clock */
 217         if ((index == L4) || (priv_index == L4))
 218                 bus_speed_changing = 1;
 219
 220         if (bus_speed_changing) {
 221                 /*
 222                  * Reconfigure DRAM refresh counter value for minimum
 223                  * temporary clock while changing divider.
 224                  * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
 225                  */
 226                 if (pll_changing)
 227                         s5pv210_set_refresh(DMC1, 83000);
 228                 else
 229                         s5pv210_set_refresh(DMC1, 100000);
 230
 231                 s5pv210_set_refresh(DMC0, 83000);
 232         }
 233
 234         /*
 235          * APLL should be changed in this level
 236          * APLL -> MPLL(for stable transition) -> APLL
 237          * Some clock source's clock API are not prepared.
 238          * Do not use clock API in below code.
 239          */
 240         if (pll_changing) {
 241                 /*
 242                  * 1. Temporary Change divider for MFC and G3D
 243                  * SCLKA2M(200/1=200)->(200/4=50)Mhz
 244                  */
 245                 reg = __raw_readl(S5P_CLK_DIV2);
 246                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 247                 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
 248                         (3 << S5P_CLKDIV2_MFC_SHIFT);
 249                 __raw_writel(reg, S5P_CLK_DIV2);
 250
 251                 /* For MFC, G3D dividing */
 252                 do {
 253                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 254                 } while (reg & ((1 << 16) | (1 << 17)));
 255
 256                 /*
 257                  * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
 258                  * (200/4=50)->(667/4=166)Mhz
 259                  */
 260                 reg = __raw_readl(S5P_CLK_SRC2);
 261                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 262                 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
 263                         (1 << S5P_CLKSRC2_MFC_SHIFT);
 264                 __raw_writel(reg, S5P_CLK_SRC2);
 265
 266                 do {
 267                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 268                 } while (reg & ((1 << 7) | (1 << 3)));
 269
 270                 /*
 271                  * 3. DMC1 refresh count for 133Mhz if (index == L4) is
 272                  * true refresh counter is already programed in upper
 273                  * code. 0x287@83Mhz
 274                  */
 275                 if (!bus_speed_changing)
 276                         s5pv210_set_refresh(DMC1, 133000);
 277
 278                 /* 4. SCLKAPLL -> SCLKMPLL */
 279                 reg = __raw_readl(S5P_CLK_SRC0);
 280                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 281                 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
 282                 __raw_writel(reg, S5P_CLK_SRC0);
 283
 284                 do {
 285                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 286                 } while (reg & (0x1 << 18));
 287
 288         }
 289
 290         /* Change divider */
 291         reg = __raw_readl(S5P_CLK_DIV0);
 292
 293         reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
 294                 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
 295                 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
 296                 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
 297
 298         reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
 299                 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
 300                 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
 301                 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
 302                 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
 303                 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
 304                 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
 305                 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
 306
 307         __raw_writel(reg, S5P_CLK_DIV0);
 308
 309         do {
 310                 reg = __raw_readl(S5P_CLKDIV_STAT0);
 311         } while (reg & 0xff);
 312
 313         /* ARM MCS value changed */
 314         reg = __raw_readl(S5P_ARM_MCS_CON);
 315         reg &= ~0x3;
 316         if (index >= L3)
 317                 reg |= 0x3;
 318         else
 319                 reg |= 0x1;
 320
 321         __raw_writel(reg, S5P_ARM_MCS_CON);
 322
 323         if (pll_changing) {
 324                 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
 325                 __raw_writel(0x2cf, S5P_APLL_LOCK);
 326
 327                 /*
 328                  * 6. Turn on APLL
 329                  * 6-1. Set PMS values
 330                  * 6-2. Wait untile the PLL is locked
 331                  */
 332                 if (index == L0)
 333                         __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
 334                 else
 335                         __raw_writel(APLL_VAL_800, S5P_APLL_CON);
 336
 337                 do {
 338                         reg = __raw_readl(S5P_APLL_CON);
 339                 } while (!(reg & (0x1 << 29)));
 340
 341                 /*
 342                  * 7. Change souce clock from SCLKMPLL(667Mhz)
 343                  * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 344                  * (667/4=166)->(200/4=50)Mhz
 345                  */
 346                 reg = __raw_readl(S5P_CLK_SRC2);
 347                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 348                 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
 349                         (0 << S5P_CLKSRC2_MFC_SHIFT);
 350                 __raw_writel(reg, S5P_CLK_SRC2);
 351
 352                 do {
 353                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 354                 } while (reg & ((1 << 7) | (1 << 3)));
 355
 356                 /*
 357                  * 8. Change divider for MFC and G3D
 358                  * (200/4=50)->(200/1=200)Mhz
 359                  */
 360                 reg = __raw_readl(S5P_CLK_DIV2);
 361                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 362                 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
 363                         (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
 364                 __raw_writel(reg, S5P_CLK_DIV2);
 365
 366                 /* For MFC, G3D dividing */
 367                 do {
 368                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 369                 } while (reg & ((1 << 16) | (1 << 17)));
 370
 371                 /* 9. Change MPLL to APLL in MSYS_MUX */
 372                 reg = __raw_readl(S5P_CLK_SRC0);
 373                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 374                 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
 375                 __raw_writel(reg, S5P_CLK_SRC0);
 376
 377                 do {
 378                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 379                 } while (reg & (0x1 << 18));
 380
 381                 /*
 382                  * 10. DMC1 refresh counter
 383                  * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
 384                  * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
 385                  */
 386                 if (!bus_speed_changing)
 387                         s5pv210_set_refresh(DMC1, 200000);
 388         }
 389
 390         /*
 391          * L4 level need to change memory bus speed, hence onedram clock divier
 392          * and memory refresh parameter should be changed
 393          */
 394         if (bus_speed_changing) {
 395                 reg = __raw_readl(S5P_CLK_DIV6);
 396                 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
 397                 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
 398                 __raw_writel(reg, S5P_CLK_DIV6);
 399
 400                 do {
 401                         reg = __raw_readl(S5P_CLKDIV_STAT1);
 402                 } while (reg & (1 << 15));
 403
 404                 /* Reconfigure DRAM refresh counter value */
 405                 if (index != L4) {
 406                         /*
 407                          * DMC0 : 166Mhz
 408                          * DMC1 : 200Mhz
 409                          */
 410                         s5pv210_set_refresh(DMC0, 166000);
 411                         s5pv210_set_refresh(DMC1, 200000);
 412                 } else {
 413                         /*
 414                          * DMC0 : 83Mhz
 415                          * DMC1 : 100Mhz
 416                          */
 417                         s5pv210_set_refresh(DMC0, 83000);
 418                         s5pv210_set_refresh(DMC1, 100000);
 419                 }
 420         }
 421
 422         if (new_freq < old_freq) {
 423                 regulator_set_voltage(int_regulator,
 424                                 int_volt, int_volt_max);
 425
 426                 regulator_set_voltage(arm_regulator,
 427                                 arm_volt, arm_volt_max);
 428         }
 429
 430         printk(KERN_DEBUG "Perf changed[L%d]\n", index);
 431
 432 exit:
 433         mutex_unlock(&set_freq_lock);
 434         return ret;
 435 }
 436
 437 static int check_mem_type(void __iomem *dmc_reg)
 438 {
 439         unsigned long val;
 440
 441         val = __raw_readl(dmc_reg + 0x4);
 442         val = (val & (0xf << 8));
 443
 444         return val >> 8;
 445 }
 446
 447 static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
 448 {
 449         unsigned long mem_type;
 450         int ret;
 451
 452         policy->clk = clk_get(NULL, "armclk");
 453         if (IS_ERR(policy->clk))
 454                 return PTR_ERR(policy->clk);
 455
 456         dmc0_clk = clk_get(NULL, "sclk_dmc0");
 457         if (IS_ERR(dmc0_clk)) {
 458                 ret = PTR_ERR(dmc0_clk);
 459                 goto out_dmc0;
 460         }
 461
 462         dmc1_clk = clk_get(NULL, "hclk_msys");
 463         if (IS_ERR(dmc1_clk)) {
 464                 ret = PTR_ERR(dmc1_clk);
 465                 goto out_dmc1;
 466         }
 467
 468         if (policy->cpu != 0) {
 469                 ret = -EINVAL;
 470                 goto out_dmc1;
 471         }
 472
 473         /*
 474          * check_mem_type : This driver only support LPDDR & LPDDR2.
 475          * other memory type is not supported.
 476          */
 477         mem_type = check_mem_type(S5P_VA_DMC0);
 478
 479         if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
 480                 printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
 481                 ret = -EINVAL;
 482                 goto out_dmc1;
 483         }
 484
 485         /* Find current refresh counter and frequency each DMC */
 486         s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
 487         s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
 488
 489         s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
 490         s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
 491
 492         policy->suspend_freq = SLEEP_FREQ;
 493         return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
 494
 495 out_dmc1:
 496         clk_put(dmc0_clk);
 497 out_dmc0:
 498         clk_put(policy->clk);
 499         return ret;
 500 }
 501
 502 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
 503                                                  unsigned long event, void *ptr)
 504 {
 505         int ret;
 506
 507         ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
 508         if (ret < 0)
 509                 return NOTIFY_BAD;
 510
 511         no_cpufreq_access = true;
 512         return NOTIFY_DONE;
 513 }
 514
 515 static struct cpufreq_driver s5pv210_driver = {
 516         .flags          = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 517         .verify         = cpufreq_generic_frequency_table_verify,
 518         .target_index   = s5pv210_target,
 519         .get            = cpufreq_generic_get,
 520         .init           = s5pv210_cpu_init,
 521         .name           = "s5pv210",
 522 #ifdef CONFIG_PM
 523         .suspend        = cpufreq_generic_suspend,
 524         .resume         = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
 525 #endif
 526 };
 527
 528 static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
 529         .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
 530 };
 531
 532 static int __init s5pv210_cpufreq_init(void)
 533 {
 534         arm_regulator = regulator_get(NULL, "vddarm");
 535         if (IS_ERR(arm_regulator)) {
 536                 pr_err("failed to get regulator vddarm");
 537                 return PTR_ERR(arm_regulator);
 538         }
 539
 540         int_regulator = regulator_get(NULL, "vddint");
 541         if (IS_ERR(int_regulator)) {
 542                 pr_err("failed to get regulator vddint");
 543                 regulator_put(arm_regulator);
 544                 return PTR_ERR(int_regulator);
 545         }
 546
 547         register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
 548
 549         return cpufreq_register_driver(&s5pv210_driver);
 550 }
 551
 552 late_initcall(s5pv210_cpufreq_init);