?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
pinctrl: remove remaining users of gpiochip_remove() retval
[linux-2.6/btrfs-unstable.git] / drivers / pinctrl / nomadik / pinctrl-nomadik.c
blob4332b38c52aba87d404a46b0071664bec269b459
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/of_device.h>
26 #include <linux/of_address.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include "pinctrl-nomadik.h"
34 #include "../core.h"
35
36 /*
37 * The GPIO module in the Nomadik family of Systems-on-Chip is an
38 * AMBA device, managing 32 pins and alternate functions. The logic block
39 * is currently used in the Nomadik and ux500.
40 *
41 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
42 */
43
44 /*
45 * pin configurations are represented by 32-bit integers:
46 *
47 * bit 0.. 8 - Pin Number (512 Pins Maximum)
48 * bit 9..10 - Alternate Function Selection
49 * bit 11..12 - Pull up/down state
50 * bit 13 - Sleep mode behaviour
51 * bit 14 - Direction
52 * bit 15 - Value (if output)
53 * bit 16..18 - SLPM pull up/down state
54 * bit 19..20 - SLPM direction
55 * bit 21..22 - SLPM Value (if output)
56 * bit 23..25 - PDIS value (if input)
57 * bit 26 - Gpio mode
58 * bit 27 - Sleep mode
59 *
60 * to facilitate the definition, the following macros are provided
61 *
62 * PIN_CFG_DEFAULT - default config (0):
63 * pull up/down = disabled
64 * sleep mode = input/wakeup
65 * direction = input
66 * value = low
67 * SLPM direction = same as normal
68 * SLPM pull = same as normal
69 * SLPM value = same as normal
70 *
71 * PIN_CFG - default config with alternate function
72 */
73
74 typedef unsigned long pin_cfg_t;
75
76 #define PIN_NUM_MASK 0x1ff
77 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
78
79 #define PIN_ALT_SHIFT 9
80 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
81 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
82 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
83 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
84 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
85 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
86
87 #define PIN_PULL_SHIFT 11
88 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
89 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
90 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
91 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
92 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
93
94 #define PIN_SLPM_SHIFT 13
95 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
96 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
97 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
98 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
99 /* These two replace the above in DB8500v2+ */
100 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
101 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
102 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
103
104 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
105 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
106
107 #define PIN_DIR_SHIFT 14
108 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
109 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
110 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
111 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
112
113 #define PIN_VAL_SHIFT 15
114 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
115 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
116 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
117 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
118
119 #define PIN_SLPM_PULL_SHIFT 16
120 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
121 #define PIN_SLPM_PULL(x) \
122 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL_NONE \
124 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_UP \
126 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
127 #define PIN_SLPM_PULL_DOWN \
128 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
129
130 #define PIN_SLPM_DIR_SHIFT 19
131 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
132 #define PIN_SLPM_DIR(x) \
133 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
134 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
136
137 #define PIN_SLPM_VAL_SHIFT 21
138 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
139 #define PIN_SLPM_VAL(x) \
140 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
141 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
143
144 #define PIN_SLPM_PDIS_SHIFT 23
145 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
146 #define PIN_SLPM_PDIS(x) \
147 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
149 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
150 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
151
152 #define PIN_LOWEMI_SHIFT 25
153 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
154 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
155 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
156 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
157
158 #define PIN_GPIOMODE_SHIFT 26
159 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
160 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
161 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
162 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
163
164 #define PIN_SLEEPMODE_SHIFT 27
165 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
166 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
167 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
168 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
169
170
171 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
172 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
173 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
174 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
175 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
176 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
177
178 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
179 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
180 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
181 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
182 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
183
184 #define PIN_CFG_DEFAULT (0)
185
186 #define PIN_CFG(num, alt) \
187 (PIN_CFG_DEFAULT |\
188 (PIN_NUM(num) | PIN_##alt))
189
190 #define PIN_CFG_INPUT(num, alt, pull) \
191 (PIN_CFG_DEFAULT |\
192 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
193
194 #define PIN_CFG_OUTPUT(num, alt, val) \
195 (PIN_CFG_DEFAULT |\
196 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
197
198 /*
199 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
200 * the "gpio" namespace for generic and cross-machine functions
201 */
202
203 #define GPIO_BLOCK_SHIFT 5
204 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
205
206 /* Register in the logic block */
207 #define NMK_GPIO_DAT 0x00
208 #define NMK_GPIO_DATS 0x04
209 #define NMK_GPIO_DATC 0x08
210 #define NMK_GPIO_PDIS 0x0c
211 #define NMK_GPIO_DIR 0x10
212 #define NMK_GPIO_DIRS 0x14
213 #define NMK_GPIO_DIRC 0x18
214 #define NMK_GPIO_SLPC 0x1c
215 #define NMK_GPIO_AFSLA 0x20
216 #define NMK_GPIO_AFSLB 0x24
217 #define NMK_GPIO_LOWEMI 0x28
218
219 #define NMK_GPIO_RIMSC 0x40
220 #define NMK_GPIO_FIMSC 0x44
221 #define NMK_GPIO_IS 0x48
222 #define NMK_GPIO_IC 0x4c
223 #define NMK_GPIO_RWIMSC 0x50
224 #define NMK_GPIO_FWIMSC 0x54
225 #define NMK_GPIO_WKS 0x58
226 /* These appear in DB8540 and later ASICs */
227 #define NMK_GPIO_EDGELEVEL 0x5C
228 #define NMK_GPIO_LEVEL 0x60
229
230
231 /* Pull up/down values */
232 enum nmk_gpio_pull {
233 NMK_GPIO_PULL_NONE,
234 NMK_GPIO_PULL_UP,
235 NMK_GPIO_PULL_DOWN,
236 };
237
238 /* Sleep mode */
239 enum nmk_gpio_slpm {
240 NMK_GPIO_SLPM_INPUT,
241 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
242 NMK_GPIO_SLPM_NOCHANGE,
243 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
244 };
245
246 struct nmk_gpio_chip {
247 struct gpio_chip chip;
248 void __iomem *addr;
249 struct clk *clk;
250 unsigned int bank;
251 unsigned int parent_irq;
252 int latent_parent_irq;
253 u32 (*get_latent_status)(unsigned int bank);
254 void (*set_ioforce)(bool enable);
255 spinlock_t lock;
256 bool sleepmode;
257 /* Keep track of configured edges */
258 u32 edge_rising;
259 u32 edge_falling;
260 u32 real_wake;
261 u32 rwimsc;
262 u32 fwimsc;
263 u32 rimsc;
264 u32 fimsc;
265 u32 pull_up;
266 u32 lowemi;
267 };
268
269 /**
270 * struct nmk_pinctrl - state container for the Nomadik pin controller
271 * @dev: containing device pointer
272 * @pctl: corresponding pin controller device
273 * @soc: SoC data for this specific chip
274 * @prcm_base: PRCM register range virtual base
275 */
276 struct nmk_pinctrl {
277 struct device *dev;
278 struct pinctrl_dev *pctl;
279 const struct nmk_pinctrl_soc_data *soc;
280 void __iomem *prcm_base;
281 };
282
283 static struct nmk_gpio_chip *
284 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
285
286 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
287
288 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
289
290 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
291 unsigned offset, int gpio_mode)
292 {
293 u32 bit = 1 << offset;
294 u32 afunc, bfunc;
295
296 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
297 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
298 if (gpio_mode & NMK_GPIO_ALT_A)
299 afunc |= bit;
300 if (gpio_mode & NMK_GPIO_ALT_B)
301 bfunc |= bit;
302 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
303 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
304 }
305
306 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
307 unsigned offset, enum nmk_gpio_slpm mode)
308 {
309 u32 bit = 1 << offset;
310 u32 slpm;
311
312 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
313 if (mode == NMK_GPIO_SLPM_NOCHANGE)
314 slpm |= bit;
315 else
316 slpm &= ~bit;
317 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
318 }
319
320 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
321 unsigned offset, enum nmk_gpio_pull pull)
322 {
323 u32 bit = 1 << offset;
324 u32 pdis;
325
326 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
327 if (pull == NMK_GPIO_PULL_NONE) {
328 pdis |= bit;
329 nmk_chip->pull_up &= ~bit;
330 } else {
331 pdis &= ~bit;
332 }
333
334 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
335
336 if (pull == NMK_GPIO_PULL_UP) {
337 nmk_chip->pull_up |= bit;
338 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
339 } else if (pull == NMK_GPIO_PULL_DOWN) {
340 nmk_chip->pull_up &= ~bit;
341 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
342 }
343 }
344
345 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
346 unsigned offset, bool lowemi)
347 {
348 u32 bit = BIT(offset);
349 bool enabled = nmk_chip->lowemi & bit;
350
351 if (lowemi == enabled)
352 return;
353
354 if (lowemi)
355 nmk_chip->lowemi |= bit;
356 else
357 nmk_chip->lowemi &= ~bit;
358
359 writel_relaxed(nmk_chip->lowemi,
360 nmk_chip->addr + NMK_GPIO_LOWEMI);
361 }
362
363 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
364 unsigned offset)
365 {
366 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
367 }
368
369 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
370 unsigned offset, int val)
371 {
372 if (val)
373 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
374 else
375 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
376 }
377
378 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
379 unsigned offset, int val)
380 {
381 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
382 __nmk_gpio_set_output(nmk_chip, offset, val);
383 }
384
385 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
386 unsigned offset, int gpio_mode,
387 bool glitch)
388 {
389 u32 rwimsc = nmk_chip->rwimsc;
390 u32 fwimsc = nmk_chip->fwimsc;
391
392 if (glitch && nmk_chip->set_ioforce) {
393 u32 bit = BIT(offset);
394
395 /* Prevent spurious wakeups */
396 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
397 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
398
399 nmk_chip->set_ioforce(true);
400 }
401
402 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
403
404 if (glitch && nmk_chip->set_ioforce) {
405 nmk_chip->set_ioforce(false);
406
407 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
408 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
409 }
410 }
411
412 static void
413 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
414 {
415 u32 falling = nmk_chip->fimsc & BIT(offset);
416 u32 rising = nmk_chip->rimsc & BIT(offset);
417 int gpio = nmk_chip->chip.base + offset;
418 int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset);
419 struct irq_data *d = irq_get_irq_data(irq);
420
421 if (!rising && !falling)
422 return;
423
424 if (!d || !irqd_irq_disabled(d))
425 return;
426
427 if (rising) {
428 nmk_chip->rimsc &= ~BIT(offset);
429 writel_relaxed(nmk_chip->rimsc,
430 nmk_chip->addr + NMK_GPIO_RIMSC);
431 }
432
433 if (falling) {
434 nmk_chip->fimsc &= ~BIT(offset);
435 writel_relaxed(nmk_chip->fimsc,
436 nmk_chip->addr + NMK_GPIO_FIMSC);
437 }
438
439 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
440 }
441
442 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
443 {
444 u32 val;
445
446 val = readl(reg);
447 val = ((val & ~mask) | (value & mask));
448 writel(val, reg);
449 }
450
451 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
452 unsigned offset, unsigned alt_num)
453 {
454 int i;
455 u16 reg;
456 u8 bit;
457 u8 alt_index;
458 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
459 const u16 *gpiocr_regs;
460
461 if (!npct->prcm_base)
462 return;
463
464 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
465 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
466 alt_num);
467 return;
468 }
469
470 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
471 if (npct->soc->altcx_pins[i].pin == offset)
472 break;
473 }
474 if (i == npct->soc->npins_altcx) {
475 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
476 offset);
477 return;
478 }
479
480 pin_desc = npct->soc->altcx_pins + i;
481 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
482
483 /*
484 * If alt_num is NULL, just clear current ALTCx selection
485 * to make sure we come back to a pure ALTC selection
486 */
487 if (!alt_num) {
488 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
489 if (pin_desc->altcx[i].used == true) {
490 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
491 bit = pin_desc->altcx[i].control_bit;
492 if (readl(npct->prcm_base + reg) & BIT(bit)) {
493 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
494 dev_dbg(npct->dev,
495 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
496 offset, i+1);
497 }
498 }
499 }
500 return;
501 }
502
503 alt_index = alt_num - 1;
504 if (pin_desc->altcx[alt_index].used == false) {
505 dev_warn(npct->dev,
506 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
507 offset, alt_num);
508 return;
509 }
510
511 /*
512 * Check if any other ALTCx functions are activated on this pin
513 * and disable it first.
514 */
515 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
516 if (i == alt_index)
517 continue;
518 if (pin_desc->altcx[i].used == true) {
519 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
520 bit = pin_desc->altcx[i].control_bit;
521 if (readl(npct->prcm_base + reg) & BIT(bit)) {
522 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
523 dev_dbg(npct->dev,
524 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
525 offset, i+1);
526 }
527 }
528 }
529
530 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
531 bit = pin_desc->altcx[alt_index].control_bit;
532 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
533 offset, alt_index+1);
534 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
535 }
536
537 /*
538 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
539 * - Save SLPM registers
540 * - Set SLPM=0 for the IOs you want to switch and others to 1
541 * - Configure the GPIO registers for the IOs that are being switched
542 * - Set IOFORCE=1
543 * - Modify the AFLSA/B registers for the IOs that are being switched
544 * - Set IOFORCE=0
545 * - Restore SLPM registers
546 * - Any spurious wake up event during switch sequence to be ignored and
547 * cleared
548 */
549 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
550 {
551 int i;
552
553 for (i = 0; i < NUM_BANKS; i++) {
554 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
555 unsigned int temp = slpm[i];
556
557 if (!chip)
558 break;
559
560 clk_enable(chip->clk);
561
562 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
563 writel(temp, chip->addr + NMK_GPIO_SLPC);
564 }
565 }
566
567 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
568 {
569 int i;
570
571 for (i = 0; i < NUM_BANKS; i++) {
572 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
573
574 if (!chip)
575 break;
576
577 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
578
579 clk_disable(chip->clk);
580 }
581 }
582
583 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
584 {
585 int i;
586 u16 reg;
587 u8 bit;
588 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
589 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
590 const u16 *gpiocr_regs;
591
592 if (!npct->prcm_base)
593 return NMK_GPIO_ALT_C;
594
595 for (i = 0; i < npct->soc->npins_altcx; i++) {
596 if (npct->soc->altcx_pins[i].pin == gpio)
597 break;
598 }
599 if (i == npct->soc->npins_altcx)
600 return NMK_GPIO_ALT_C;
601
602 pin_desc = npct->soc->altcx_pins + i;
603 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
604 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
605 if (pin_desc->altcx[i].used == true) {
606 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
607 bit = pin_desc->altcx[i].control_bit;
608 if (readl(npct->prcm_base + reg) & BIT(bit))
609 return NMK_GPIO_ALT_C+i+1;
610 }
611 }
612 return NMK_GPIO_ALT_C;
613 }
614
615 int nmk_gpio_get_mode(int gpio)
616 {
617 struct nmk_gpio_chip *nmk_chip;
618 u32 afunc, bfunc, bit;
619
620 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
621 if (!nmk_chip)
622 return -EINVAL;
623
624 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
625
626 clk_enable(nmk_chip->clk);
627
628 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
629 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
630
631 clk_disable(nmk_chip->clk);
632
633 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
634 }
635 EXPORT_SYMBOL(nmk_gpio_get_mode);
636
637
638 /* IRQ functions */
639 static inline int nmk_gpio_get_bitmask(int gpio)
640 {
641 return 1 << (gpio % NMK_GPIO_PER_CHIP);
642 }
643
644 static void nmk_gpio_irq_ack(struct irq_data *d)
645 {
646 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
647 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
648
649 clk_enable(nmk_chip->clk);
650 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
651 clk_disable(nmk_chip->clk);
652 }
653
654 enum nmk_gpio_irq_type {
655 NORMAL,
656 WAKE,
657 };
658
659 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
660 int gpio, enum nmk_gpio_irq_type which,
661 bool enable)
662 {
663 u32 bitmask = nmk_gpio_get_bitmask(gpio);
664 u32 *rimscval;
665 u32 *fimscval;
666 u32 rimscreg;
667 u32 fimscreg;
668
669 if (which == NORMAL) {
670 rimscreg = NMK_GPIO_RIMSC;
671 fimscreg = NMK_GPIO_FIMSC;
672 rimscval = &nmk_chip->rimsc;
673 fimscval = &nmk_chip->fimsc;
674 } else {
675 rimscreg = NMK_GPIO_RWIMSC;
676 fimscreg = NMK_GPIO_FWIMSC;
677 rimscval = &nmk_chip->rwimsc;
678 fimscval = &nmk_chip->fwimsc;
679 }
680
681 /* we must individually set/clear the two edges */
682 if (nmk_chip->edge_rising & bitmask) {
683 if (enable)
684 *rimscval |= bitmask;
685 else
686 *rimscval &= ~bitmask;
687 writel(*rimscval, nmk_chip->addr + rimscreg);
688 }
689 if (nmk_chip->edge_falling & bitmask) {
690 if (enable)
691 *fimscval |= bitmask;
692 else
693 *fimscval &= ~bitmask;
694 writel(*fimscval, nmk_chip->addr + fimscreg);
695 }
696 }
697
698 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
699 int gpio, bool on)
700 {
701 /*
702 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
703 * disabled, since setting SLPM to 1 increases power consumption, and
704 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
705 */
706 if (nmk_chip->sleepmode && on) {
707 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
708 NMK_GPIO_SLPM_WAKEUP_ENABLE);
709 }
710
711 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
712 }
713
714 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
715 {
716 struct nmk_gpio_chip *nmk_chip;
717 unsigned long flags;
718 u32 bitmask;
719
720 nmk_chip = irq_data_get_irq_chip_data(d);
721 bitmask = nmk_gpio_get_bitmask(d->hwirq);
722 if (!nmk_chip)
723 return -EINVAL;
724
725 clk_enable(nmk_chip->clk);
726 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
727 spin_lock(&nmk_chip->lock);
728
729 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
730
731 if (!(nmk_chip->real_wake & bitmask))
732 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
733
734 spin_unlock(&nmk_chip->lock);
735 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
736 clk_disable(nmk_chip->clk);
737
738 return 0;
739 }
740
741 static void nmk_gpio_irq_mask(struct irq_data *d)
742 {
743 nmk_gpio_irq_maskunmask(d, false);
744 }
745
746 static void nmk_gpio_irq_unmask(struct irq_data *d)
747 {
748 nmk_gpio_irq_maskunmask(d, true);
749 }
750
751 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
752 {
753 struct nmk_gpio_chip *nmk_chip;
754 unsigned long flags;
755 u32 bitmask;
756
757 nmk_chip = irq_data_get_irq_chip_data(d);
758 if (!nmk_chip)
759 return -EINVAL;
760 bitmask = nmk_gpio_get_bitmask(d->hwirq);
761
762 clk_enable(nmk_chip->clk);
763 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
764 spin_lock(&nmk_chip->lock);
765
766 if (irqd_irq_disabled(d))
767 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
768
769 if (on)
770 nmk_chip->real_wake |= bitmask;
771 else
772 nmk_chip->real_wake &= ~bitmask;
773
774 spin_unlock(&nmk_chip->lock);
775 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
776 clk_disable(nmk_chip->clk);
777
778 return 0;
779 }
780
781 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
782 {
783 bool enabled = !irqd_irq_disabled(d);
784 bool wake = irqd_is_wakeup_set(d);
785 struct nmk_gpio_chip *nmk_chip;
786 unsigned long flags;
787 u32 bitmask;
788
789 nmk_chip = irq_data_get_irq_chip_data(d);
790 bitmask = nmk_gpio_get_bitmask(d->hwirq);
791 if (!nmk_chip)
792 return -EINVAL;
793 if (type & IRQ_TYPE_LEVEL_HIGH)
794 return -EINVAL;
795 if (type & IRQ_TYPE_LEVEL_LOW)
796 return -EINVAL;
797
798 clk_enable(nmk_chip->clk);
799 spin_lock_irqsave(&nmk_chip->lock, flags);
800
801 if (enabled)
802 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
803
804 if (enabled || wake)
805 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
806
807 nmk_chip->edge_rising &= ~bitmask;
808 if (type & IRQ_TYPE_EDGE_RISING)
809 nmk_chip->edge_rising |= bitmask;
810
811 nmk_chip->edge_falling &= ~bitmask;
812 if (type & IRQ_TYPE_EDGE_FALLING)
813 nmk_chip->edge_falling |= bitmask;
814
815 if (enabled)
816 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
817
818 if (enabled || wake)
819 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
820
821 spin_unlock_irqrestore(&nmk_chip->lock, flags);
822 clk_disable(nmk_chip->clk);
823
824 return 0;
825 }
826
827 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
828 {
829 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
830
831 clk_enable(nmk_chip->clk);
832 nmk_gpio_irq_unmask(d);
833 return 0;
834 }
835
836 static void nmk_gpio_irq_shutdown(struct irq_data *d)
837 {
838 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
839
840 nmk_gpio_irq_mask(d);
841 clk_disable(nmk_chip->clk);
842 }
843
844 static struct irq_chip nmk_gpio_irq_chip = {
845 .name = "Nomadik-GPIO",
846 .irq_ack = nmk_gpio_irq_ack,
847 .irq_mask = nmk_gpio_irq_mask,
848 .irq_unmask = nmk_gpio_irq_unmask,
849 .irq_set_type = nmk_gpio_irq_set_type,
850 .irq_set_wake = nmk_gpio_irq_set_wake,
851 .irq_startup = nmk_gpio_irq_startup,
852 .irq_shutdown = nmk_gpio_irq_shutdown,
853 .flags = IRQCHIP_MASK_ON_SUSPEND,
854 };
855
856 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
857 u32 status)
858 {
859 struct irq_chip *host_chip = irq_get_chip(irq);
860 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
861
862 chained_irq_enter(host_chip, desc);
863
864 while (status) {
865 int bit = __ffs(status);
866
867 generic_handle_irq(irq_find_mapping(chip->irqdomain, bit));
868 status &= ~BIT(bit);
869 }
870
871 chained_irq_exit(host_chip, desc);
872 }
873
874 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
875 {
876 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
877 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
878 u32 status;
879
880 clk_enable(nmk_chip->clk);
881 status = readl(nmk_chip->addr + NMK_GPIO_IS);
882 clk_disable(nmk_chip->clk);
883
884 __nmk_gpio_irq_handler(irq, desc, status);
885 }
886
887 static void nmk_gpio_latent_irq_handler(unsigned int irq,
888 struct irq_desc *desc)
889 {
890 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
891 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
892 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
893
894 __nmk_gpio_irq_handler(irq, desc, status);
895 }
896
897 /* I/O Functions */
898
899 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
900 {
901 /*
902 * Map back to global GPIO space and request muxing, the direction
903 * parameter does not matter for this controller.
904 */
905 int gpio = chip->base + offset;
906
907 return pinctrl_request_gpio(gpio);
908 }
909
910 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
911 {
912 int gpio = chip->base + offset;
913
914 pinctrl_free_gpio(gpio);
915 }
916
917 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
918 {
919 struct nmk_gpio_chip *nmk_chip =
920 container_of(chip, struct nmk_gpio_chip, chip);
921
922 clk_enable(nmk_chip->clk);
923
924 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
925
926 clk_disable(nmk_chip->clk);
927
928 return 0;
929 }
930
931 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
932 {
933 struct nmk_gpio_chip *nmk_chip =
934 container_of(chip, struct nmk_gpio_chip, chip);
935 u32 bit = 1 << offset;
936 int value;
937
938 clk_enable(nmk_chip->clk);
939
940 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
941
942 clk_disable(nmk_chip->clk);
943
944 return value;
945 }
946
947 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
948 int val)
949 {
950 struct nmk_gpio_chip *nmk_chip =
951 container_of(chip, struct nmk_gpio_chip, chip);
952
953 clk_enable(nmk_chip->clk);
954
955 __nmk_gpio_set_output(nmk_chip, offset, val);
956
957 clk_disable(nmk_chip->clk);
958 }
959
960 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
961 int val)
962 {
963 struct nmk_gpio_chip *nmk_chip =
964 container_of(chip, struct nmk_gpio_chip, chip);
965
966 clk_enable(nmk_chip->clk);
967
968 __nmk_gpio_make_output(nmk_chip, offset, val);
969
970 clk_disable(nmk_chip->clk);
971
972 return 0;
973 }
974
975 #ifdef CONFIG_DEBUG_FS
976
977 #include <linux/seq_file.h>
978
979 static void nmk_gpio_dbg_show_one(struct seq_file *s,
980 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
981 unsigned offset, unsigned gpio)
982 {
983 const char *label = gpiochip_is_requested(chip, offset);
984 struct nmk_gpio_chip *nmk_chip =
985 container_of(chip, struct nmk_gpio_chip, chip);
986 int mode;
987 bool is_out;
988 bool pull;
989 u32 bit = 1 << offset;
990 const char *modes[] = {
991 [NMK_GPIO_ALT_GPIO] = "gpio",
992 [NMK_GPIO_ALT_A] = "altA",
993 [NMK_GPIO_ALT_B] = "altB",
994 [NMK_GPIO_ALT_C] = "altC",
995 [NMK_GPIO_ALT_C+1] = "altC1",
996 [NMK_GPIO_ALT_C+2] = "altC2",
997 [NMK_GPIO_ALT_C+3] = "altC3",
998 [NMK_GPIO_ALT_C+4] = "altC4",
999 };
1000
1001 clk_enable(nmk_chip->clk);
1002 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1003 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1004 mode = nmk_gpio_get_mode(gpio);
1005 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1006 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1007
1008 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1009 gpio, label ?: "(none)",
1010 is_out ? "out" : "in ",
1011 chip->get
1012 ? (chip->get(chip, offset) ? "hi" : "lo")
1013 : "? ",
1014 (mode < 0) ? "unknown" : modes[mode],
1015 pull ? "pull" : "none");
1016
1017 if (!is_out) {
1018 int irq = gpio_to_irq(gpio);
1019 struct irq_desc *desc = irq_to_desc(irq);
1020
1021 /* This races with request_irq(), set_irq_type(),
1022 * and set_irq_wake() ... but those are "rare".
1023 */
1024 if (irq > 0 && desc && desc->action) {
1025 char *trigger;
1026 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1027
1028 if (nmk_chip->edge_rising & bitmask)
1029 trigger = "edge-rising";
1030 else if (nmk_chip->edge_falling & bitmask)
1031 trigger = "edge-falling";
1032 else
1033 trigger = "edge-undefined";
1034
1035 seq_printf(s, " irq-%d %s%s",
1036 irq, trigger,
1037 irqd_is_wakeup_set(&desc->irq_data)
1038 ? " wakeup" : "");
1039 }
1040 }
1041 clk_disable(nmk_chip->clk);
1042 }
1043
1044 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1045 {
1046 unsigned i;
1047 unsigned gpio = chip->base;
1048
1049 for (i = 0; i < chip->ngpio; i++, gpio++) {
1050 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1051 seq_printf(s, "\n");
1052 }
1053 }
1054
1055 #else
1056 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1057 struct pinctrl_dev *pctldev,
1058 struct gpio_chip *chip,
1059 unsigned offset, unsigned gpio)
1060 {
1061 }
1062 #define nmk_gpio_dbg_show NULL
1063 #endif
1064
1065 /* This structure is replicated for each GPIO block allocated at probe time */
1066 static struct gpio_chip nmk_gpio_template = {
1067 .request = nmk_gpio_request,
1068 .free = nmk_gpio_free,
1069 .direction_input = nmk_gpio_make_input,
1070 .get = nmk_gpio_get_input,
1071 .direction_output = nmk_gpio_make_output,
1072 .set = nmk_gpio_set_output,
1073 .dbg_show = nmk_gpio_dbg_show,
1074 .can_sleep = false,
1075 };
1076
1077 void nmk_gpio_clocks_enable(void)
1078 {
1079 int i;
1080
1081 for (i = 0; i < NUM_BANKS; i++) {
1082 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1083
1084 if (!chip)
1085 continue;
1086
1087 clk_enable(chip->clk);
1088 }
1089 }
1090
1091 void nmk_gpio_clocks_disable(void)
1092 {
1093 int i;
1094
1095 for (i = 0; i < NUM_BANKS; i++) {
1096 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1097
1098 if (!chip)
1099 continue;
1100
1101 clk_disable(chip->clk);
1102 }
1103 }
1104
1105 /*
1106 * Called from the suspend/resume path to only keep the real wakeup interrupts
1107 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1108 * and not the rest of the interrupts which we needed to have as wakeups for
1109 * cpuidle.
1110 *
1111 * PM ops are not used since this needs to be done at the end, after all the
1112 * other drivers are done with their suspend callbacks.
1113 */
1114 void nmk_gpio_wakeups_suspend(void)
1115 {
1116 int i;
1117
1118 for (i = 0; i < NUM_BANKS; i++) {
1119 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1120
1121 if (!chip)
1122 break;
1123
1124 clk_enable(chip->clk);
1125
1126 writel(chip->rwimsc & chip->real_wake,
1127 chip->addr + NMK_GPIO_RWIMSC);
1128 writel(chip->fwimsc & chip->real_wake,
1129 chip->addr + NMK_GPIO_FWIMSC);
1130
1131 clk_disable(chip->clk);
1132 }
1133 }
1134
1135 void nmk_gpio_wakeups_resume(void)
1136 {
1137 int i;
1138
1139 for (i = 0; i < NUM_BANKS; i++) {
1140 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1141
1142 if (!chip)
1143 break;
1144
1145 clk_enable(chip->clk);
1146
1147 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1148 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1149
1150 clk_disable(chip->clk);
1151 }
1152 }
1153
1154 /*
1155 * Read the pull up/pull down status.
1156 * A bit set in 'pull_up' means that pull up
1157 * is selected if pull is enabled in PDIS register.
1158 * Note: only pull up/down set via this driver can
1159 * be detected due to HW limitations.
1160 */
1161 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1162 {
1163 if (gpio_bank < NUM_BANKS) {
1164 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1165
1166 if (!chip)
1167 return;
1168
1169 *pull_up = chip->pull_up;
1170 }
1171 }
1172
1173 static int nmk_gpio_probe(struct platform_device *dev)
1174 {
1175 struct device_node *np = dev->dev.of_node;
1176 struct nmk_gpio_chip *nmk_chip;
1177 struct gpio_chip *chip;
1178 struct resource *res;
1179 struct clk *clk;
1180 int latent_irq;
1181 bool supports_sleepmode;
1182 void __iomem *base;
1183 int irq;
1184 int ret;
1185
1186 if (of_get_property(np, "st,supports-sleepmode", NULL))
1187 supports_sleepmode = true;
1188 else
1189 supports_sleepmode = false;
1190
1191 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1192 dev_err(&dev->dev, "gpio-bank property not found\n");
1193 return -EINVAL;
1194 }
1195
1196 irq = platform_get_irq(dev, 0);
1197 if (irq < 0)
1198 return irq;
1199
1200 /* It's OK for this IRQ not to be present */
1201 latent_irq = platform_get_irq(dev, 1);
1202
1203 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1204 base = devm_ioremap_resource(&dev->dev, res);
1205 if (IS_ERR(base))
1206 return PTR_ERR(base);
1207
1208 clk = devm_clk_get(&dev->dev, NULL);
1209 if (IS_ERR(clk))
1210 return PTR_ERR(clk);
1211 clk_prepare(clk);
1212
1213 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1214 if (!nmk_chip)
1215 return -ENOMEM;
1216
1217 /*
1218 * The virt address in nmk_chip->addr is in the nomadik register space,
1219 * so we can simply convert the resource address, without remapping
1220 */
1221 nmk_chip->bank = dev->id;
1222 nmk_chip->clk = clk;
1223 nmk_chip->addr = base;
1224 nmk_chip->chip = nmk_gpio_template;
1225 nmk_chip->parent_irq = irq;
1226 nmk_chip->latent_parent_irq = latent_irq;
1227 nmk_chip->sleepmode = supports_sleepmode;
1228 spin_lock_init(&nmk_chip->lock);
1229
1230 chip = &nmk_chip->chip;
1231 chip->base = dev->id * NMK_GPIO_PER_CHIP;
1232 chip->ngpio = NMK_GPIO_PER_CHIP;
1233 chip->label = dev_name(&dev->dev);
1234 chip->dev = &dev->dev;
1235 chip->owner = THIS_MODULE;
1236
1237 clk_enable(nmk_chip->clk);
1238 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1239 clk_disable(nmk_chip->clk);
1240 chip->of_node = np;
1241
1242 ret = gpiochip_add(&nmk_chip->chip);
1243 if (ret)
1244 return ret;
1245
1246 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1247
1248 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1249
1250 platform_set_drvdata(dev, nmk_chip);
1251
1252 /*
1253 * Let the generic code handle this edge IRQ, the the chained
1254 * handler will perform the actual work of handling the parent
1255 * interrupt.
1256 */
1257 ret = gpiochip_irqchip_add(&nmk_chip->chip,
1258 &nmk_gpio_irq_chip,
1259 0,
1260 handle_edge_irq,
1261 IRQ_TYPE_EDGE_FALLING);
1262 if (ret) {
1263 dev_err(&dev->dev, "could not add irqchip\n");
1264 gpiochip_remove(&nmk_chip->chip);
1265 return -ENODEV;
1266 }
1267 /* Then register the chain on the parent IRQ */
1268 gpiochip_set_chained_irqchip(&nmk_chip->chip,
1269 &nmk_gpio_irq_chip,
1270 nmk_chip->parent_irq,
1271 nmk_gpio_irq_handler);
1272 if (nmk_chip->latent_parent_irq > 0)
1273 gpiochip_set_chained_irqchip(&nmk_chip->chip,
1274 &nmk_gpio_irq_chip,
1275 nmk_chip->latent_parent_irq,
1276 nmk_gpio_latent_irq_handler);
1277
1278 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1279
1280 return 0;
1281 }
1282
1283 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1284 {
1285 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1286
1287 return npct->soc->ngroups;
1288 }
1289
1290 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1291 unsigned selector)
1292 {
1293 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1294
1295 return npct->soc->groups[selector].name;
1296 }
1297
1298 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1299 const unsigned **pins,
1300 unsigned *num_pins)
1301 {
1302 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1303
1304 *pins = npct->soc->groups[selector].pins;
1305 *num_pins = npct->soc->groups[selector].npins;
1306 return 0;
1307 }
1308
1309 static struct pinctrl_gpio_range *
1310 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1311 {
1312 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1313 int i;
1314
1315 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1316 struct pinctrl_gpio_range *range;
1317
1318 range = &npct->soc->gpio_ranges[i];
1319 if (offset >= range->pin_base &&
1320 offset <= (range->pin_base + range->npins - 1))
1321 return range;
1322 }
1323 return NULL;
1324 }
1325
1326 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1327 unsigned offset)
1328 {
1329 struct pinctrl_gpio_range *range;
1330 struct gpio_chip *chip;
1331
1332 range = nmk_match_gpio_range(pctldev, offset);
1333 if (!range || !range->gc) {
1334 seq_printf(s, "invalid pin offset");
1335 return;
1336 }
1337 chip = range->gc;
1338 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1339 }
1340
1341 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1342 struct pinctrl_map *map, unsigned num_maps)
1343 {
1344 int i;
1345
1346 for (i = 0; i < num_maps; i++)
1347 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1348 kfree(map[i].data.configs.configs);
1349 kfree(map);
1350 }
1351
1352 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1353 unsigned *num_maps, unsigned reserve)
1354 {
1355 unsigned old_num = *reserved_maps;
1356 unsigned new_num = *num_maps + reserve;
1357 struct pinctrl_map *new_map;
1358
1359 if (old_num >= new_num)
1360 return 0;
1361
1362 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1363 if (!new_map)
1364 return -ENOMEM;
1365
1366 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1367
1368 *map = new_map;
1369 *reserved_maps = new_num;
1370
1371 return 0;
1372 }
1373
1374 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1375 unsigned *num_maps, const char *group,
1376 const char *function)
1377 {
1378 if (*num_maps == *reserved_maps)
1379 return -ENOSPC;
1380
1381 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1382 (*map)[*num_maps].data.mux.group = group;
1383 (*map)[*num_maps].data.mux.function = function;
1384 (*num_maps)++;
1385
1386 return 0;
1387 }
1388
1389 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1390 unsigned *reserved_maps,
1391 unsigned *num_maps, const char *group,
1392 unsigned long *configs, unsigned num_configs)
1393 {
1394 unsigned long *dup_configs;
1395
1396 if (*num_maps == *reserved_maps)
1397 return -ENOSPC;
1398
1399 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1400 GFP_KERNEL);
1401 if (!dup_configs)
1402 return -ENOMEM;
1403
1404 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1405
1406 (*map)[*num_maps].data.configs.group_or_pin = group;
1407 (*map)[*num_maps].data.configs.configs = dup_configs;
1408 (*map)[*num_maps].data.configs.num_configs = num_configs;
1409 (*num_maps)++;
1410
1411 return 0;
1412 }
1413
1414 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1415 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1416 .size = ARRAY_SIZE(y), }
1417
1418 static const unsigned long nmk_pin_input_modes[] = {
1419 PIN_INPUT_NOPULL,
1420 PIN_INPUT_PULLUP,
1421 PIN_INPUT_PULLDOWN,
1422 };
1423
1424 static const unsigned long nmk_pin_output_modes[] = {
1425 PIN_OUTPUT_LOW,
1426 PIN_OUTPUT_HIGH,
1427 PIN_DIR_OUTPUT,
1428 };
1429
1430 static const unsigned long nmk_pin_sleep_modes[] = {
1431 PIN_SLEEPMODE_DISABLED,
1432 PIN_SLEEPMODE_ENABLED,
1433 };
1434
1435 static const unsigned long nmk_pin_sleep_input_modes[] = {
1436 PIN_SLPM_INPUT_NOPULL,
1437 PIN_SLPM_INPUT_PULLUP,
1438 PIN_SLPM_INPUT_PULLDOWN,
1439 PIN_SLPM_DIR_INPUT,
1440 };
1441
1442 static const unsigned long nmk_pin_sleep_output_modes[] = {
1443 PIN_SLPM_OUTPUT_LOW,
1444 PIN_SLPM_OUTPUT_HIGH,
1445 PIN_SLPM_DIR_OUTPUT,
1446 };
1447
1448 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1449 PIN_SLPM_WAKEUP_DISABLE,
1450 PIN_SLPM_WAKEUP_ENABLE,
1451 };
1452
1453 static const unsigned long nmk_pin_gpio_modes[] = {
1454 PIN_GPIOMODE_DISABLED,
1455 PIN_GPIOMODE_ENABLED,
1456 };
1457
1458 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1459 PIN_SLPM_PDIS_DISABLED,
1460 PIN_SLPM_PDIS_ENABLED,
1461 };
1462
1463 struct nmk_cfg_param {
1464 const char *property;
1465 unsigned long config;
1466 const unsigned long *choice;
1467 int size;
1468 };
1469
1470 static const struct nmk_cfg_param nmk_cfg_params[] = {
1471 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1472 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1473 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1474 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1475 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1476 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1477 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1478 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1479 };
1480
1481 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1482 {
1483 int ret = 0;
1484
1485 if (nmk_cfg_params[index].choice == NULL)
1486 *config = nmk_cfg_params[index].config;
1487 else {
1488 /* test if out of range */
1489 if (val < nmk_cfg_params[index].size) {
1490 *config = nmk_cfg_params[index].config |
1491 nmk_cfg_params[index].choice[val];
1492 }
1493 }
1494 return ret;
1495 }
1496
1497 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1498 {
1499 int i, pin_number;
1500 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1501
1502 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1503 for (i = 0; i < npct->soc->npins; i++)
1504 if (npct->soc->pins[i].number == pin_number)
1505 return npct->soc->pins[i].name;
1506 return NULL;
1507 }
1508
1509 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1510 unsigned long *configs)
1511 {
1512 bool has_config = 0;
1513 unsigned long cfg = 0;
1514 int i, val, ret;
1515
1516 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1517 ret = of_property_read_u32(np,
1518 nmk_cfg_params[i].property, &val);
1519 if (ret != -EINVAL) {
1520 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1521 *configs |= cfg;
1522 has_config = 1;
1523 }
1524 }
1525 }
1526
1527 return has_config;
1528 }
1529
1530 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1531 struct device_node *np,
1532 struct pinctrl_map **map,
1533 unsigned *reserved_maps,
1534 unsigned *num_maps)
1535 {
1536 int ret;
1537 const char *function = NULL;
1538 unsigned long configs = 0;
1539 bool has_config = 0;
1540 unsigned reserve = 0;
1541 struct property *prop;
1542 const char *group, *gpio_name;
1543 struct device_node *np_config;
1544
1545 ret = of_property_read_string(np, "ste,function", &function);
1546 if (ret >= 0)
1547 reserve = 1;
1548
1549 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1550
1551 np_config = of_parse_phandle(np, "ste,config", 0);
1552 if (np_config)
1553 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1554
1555 ret = of_property_count_strings(np, "ste,pins");
1556 if (ret < 0)
1557 goto exit;
1558
1559 if (has_config)
1560 reserve++;
1561
1562 reserve *= ret;
1563
1564 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1565 if (ret < 0)
1566 goto exit;
1567
1568 of_property_for_each_string(np, "ste,pins", prop, group) {
1569 if (function) {
1570 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1571 group, function);
1572 if (ret < 0)
1573 goto exit;
1574 }
1575 if (has_config) {
1576 gpio_name = nmk_find_pin_name(pctldev, group);
1577
1578 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1579 gpio_name, &configs, 1);
1580 if (ret < 0)
1581 goto exit;
1582 }
1583
1584 }
1585 exit:
1586 return ret;
1587 }
1588
1589 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1590 struct device_node *np_config,
1591 struct pinctrl_map **map, unsigned *num_maps)
1592 {
1593 unsigned reserved_maps;
1594 struct device_node *np;
1595 int ret;
1596
1597 reserved_maps = 0;
1598 *map = NULL;
1599 *num_maps = 0;
1600
1601 for_each_child_of_node(np_config, np) {
1602 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1603 &reserved_maps, num_maps);
1604 if (ret < 0) {
1605 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1606 return ret;
1607 }
1608 }
1609
1610 return 0;
1611 }
1612
1613 static const struct pinctrl_ops nmk_pinctrl_ops = {
1614 .get_groups_count = nmk_get_groups_cnt,
1615 .get_group_name = nmk_get_group_name,
1616 .get_group_pins = nmk_get_group_pins,
1617 .pin_dbg_show = nmk_pin_dbg_show,
1618 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1619 .dt_free_map = nmk_pinctrl_dt_free_map,
1620 };
1621
1622 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1623 {
1624 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1625
1626 return npct->soc->nfunctions;
1627 }
1628
1629 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1630 unsigned function)
1631 {
1632 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1633
1634 return npct->soc->functions[function].name;
1635 }
1636
1637 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1638 unsigned function,
1639 const char * const **groups,
1640 unsigned * const num_groups)
1641 {
1642 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1643
1644 *groups = npct->soc->functions[function].groups;
1645 *num_groups = npct->soc->functions[function].ngroups;
1646
1647 return 0;
1648 }
1649
1650 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1651 unsigned group)
1652 {
1653 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1654 const struct nmk_pingroup *g;
1655 static unsigned int slpm[NUM_BANKS];
1656 unsigned long flags = 0;
1657 bool glitch;
1658 int ret = -EINVAL;
1659 int i;
1660
1661 g = &npct->soc->groups[group];
1662
1663 if (g->altsetting < 0)
1664 return -EINVAL;
1665
1666 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1667
1668 /*
1669 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1670 * we may pass through an undesired state. In this case we take
1671 * some extra care.
1672 *
1673 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1674 * - Save SLPM registers (since we have a shadow register in the
1675 * nmk_chip we're using that as backup)
1676 * - Set SLPM=0 for the IOs you want to switch and others to 1
1677 * - Configure the GPIO registers for the IOs that are being switched
1678 * - Set IOFORCE=1
1679 * - Modify the AFLSA/B registers for the IOs that are being switched
1680 * - Set IOFORCE=0
1681 * - Restore SLPM registers
1682 * - Any spurious wake up event during switch sequence to be ignored
1683 * and cleared
1684 *
1685 * We REALLY need to save ALL slpm registers, because the external
1686 * IOFORCE will switch *all* ports to their sleepmode setting to as
1687 * to avoid glitches. (Not just one port!)
1688 */
1689 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1690
1691 if (glitch) {
1692 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1693
1694 /* Initially don't put any pins to sleep when switching */
1695 memset(slpm, 0xff, sizeof(slpm));
1696
1697 /*
1698 * Then mask the pins that need to be sleeping now when we're
1699 * switching to the ALT C function.
1700 */
1701 for (i = 0; i < g->npins; i++)
1702 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1703 nmk_gpio_glitch_slpm_init(slpm);
1704 }
1705
1706 for (i = 0; i < g->npins; i++) {
1707 struct pinctrl_gpio_range *range;
1708 struct nmk_gpio_chip *nmk_chip;
1709 struct gpio_chip *chip;
1710 unsigned bit;
1711
1712 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1713 if (!range) {
1714 dev_err(npct->dev,
1715 "invalid pin offset %d in group %s at index %d\n",
1716 g->pins[i], g->name, i);
1717 goto out_glitch;
1718 }
1719 if (!range->gc) {
1720 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1721 g->pins[i], g->name, i);
1722 goto out_glitch;
1723 }
1724 chip = range->gc;
1725 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1726 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1727
1728 clk_enable(nmk_chip->clk);
1729 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1730 /*
1731 * If the pin is switching to altfunc, and there was an
1732 * interrupt installed on it which has been lazy disabled,
1733 * actually mask the interrupt to prevent spurious interrupts
1734 * that would occur while the pin is under control of the
1735 * peripheral. Only SKE does this.
1736 */
1737 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1738
1739 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1740 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1741 clk_disable(nmk_chip->clk);
1742
1743 /*
1744 * Call PRCM GPIOCR config function in case ALTC
1745 * has been selected:
1746 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1747 * must be set.
1748 * - If selection is pure ALTC and previous selection was ALTCx,
1749 * then some bits in PRCM GPIOCR registers must be cleared.
1750 */
1751 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1752 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1753 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1754 }
1755
1756 /* When all pins are successfully reconfigured we get here */
1757 ret = 0;
1758
1759 out_glitch:
1760 if (glitch) {
1761 nmk_gpio_glitch_slpm_restore(slpm);
1762 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1763 }
1764
1765 return ret;
1766 }
1767
1768 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1769 struct pinctrl_gpio_range *range,
1770 unsigned offset)
1771 {
1772 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1773 struct nmk_gpio_chip *nmk_chip;
1774 struct gpio_chip *chip;
1775 unsigned bit;
1776
1777 if (!range) {
1778 dev_err(npct->dev, "invalid range\n");
1779 return -EINVAL;
1780 }
1781 if (!range->gc) {
1782 dev_err(npct->dev, "missing GPIO chip in range\n");
1783 return -EINVAL;
1784 }
1785 chip = range->gc;
1786 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1787
1788 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1789
1790 clk_enable(nmk_chip->clk);
1791 bit = offset % NMK_GPIO_PER_CHIP;
1792 /* There is no glitch when converting any pin to GPIO */
1793 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1794 clk_disable(nmk_chip->clk);
1795
1796 return 0;
1797 }
1798
1799 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1800 struct pinctrl_gpio_range *range,
1801 unsigned offset)
1802 {
1803 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1804
1805 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1806 /* Set the pin to some default state, GPIO is usually default */
1807 }
1808
1809 static const struct pinmux_ops nmk_pinmux_ops = {
1810 .get_functions_count = nmk_pmx_get_funcs_cnt,
1811 .get_function_name = nmk_pmx_get_func_name,
1812 .get_function_groups = nmk_pmx_get_func_groups,
1813 .enable = nmk_pmx_enable,
1814 .gpio_request_enable = nmk_gpio_request_enable,
1815 .gpio_disable_free = nmk_gpio_disable_free,
1816 };
1817
1818 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1819 unsigned long *config)
1820 {
1821 /* Not implemented */
1822 return -EINVAL;
1823 }
1824
1825 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1826 unsigned long *configs, unsigned num_configs)
1827 {
1828 static const char *pullnames[] = {
1829 [NMK_GPIO_PULL_NONE] = "none",
1830 [NMK_GPIO_PULL_UP] = "up",
1831 [NMK_GPIO_PULL_DOWN] = "down",
1832 [3] /* illegal */ = "??"
1833 };
1834 static const char *slpmnames[] = {
1835 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1836 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1837 };
1838 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1839 struct nmk_gpio_chip *nmk_chip;
1840 struct pinctrl_gpio_range *range;
1841 struct gpio_chip *chip;
1842 unsigned bit;
1843 pin_cfg_t cfg;
1844 int pull, slpm, output, val, i;
1845 bool lowemi, gpiomode, sleep;
1846
1847 range = nmk_match_gpio_range(pctldev, pin);
1848 if (!range) {
1849 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1850 return -EINVAL;
1851 }
1852 if (!range->gc) {
1853 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1854 pin);
1855 return -EINVAL;
1856 }
1857 chip = range->gc;
1858 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1859
1860 for (i = 0; i < num_configs; i++) {
1861 /*
1862 * The pin config contains pin number and altfunction fields,
1863 * here we just ignore that part. It's being handled by the
1864 * framework and pinmux callback respectively.
1865 */
1866 cfg = (pin_cfg_t) configs[i];
1867 pull = PIN_PULL(cfg);
1868 slpm = PIN_SLPM(cfg);
1869 output = PIN_DIR(cfg);
1870 val = PIN_VAL(cfg);
1871 lowemi = PIN_LOWEMI(cfg);
1872 gpiomode = PIN_GPIOMODE(cfg);
1873 sleep = PIN_SLEEPMODE(cfg);
1874
1875 if (sleep) {
1876 int slpm_pull = PIN_SLPM_PULL(cfg);
1877 int slpm_output = PIN_SLPM_DIR(cfg);
1878 int slpm_val = PIN_SLPM_VAL(cfg);
1879
1880 /* All pins go into GPIO mode at sleep */
1881 gpiomode = true;
1882
1883 /*
1884 * The SLPM_* values are normal values + 1 to allow zero
1885 * to mean "same as normal".
1886 */
1887 if (slpm_pull)
1888 pull = slpm_pull - 1;
1889 if (slpm_output)
1890 output = slpm_output - 1;
1891 if (slpm_val)
1892 val = slpm_val - 1;
1893
1894 dev_dbg(nmk_chip->chip.dev,
1895 "pin %d: sleep pull %s, dir %s, val %s\n",
1896 pin,
1897 slpm_pull ? pullnames[pull] : "same",
1898 slpm_output ? (output ? "output" : "input")
1899 : "same",
1900 slpm_val ? (val ? "high" : "low") : "same");
1901 }
1902
1903 dev_dbg(nmk_chip->chip.dev,
1904 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1905 pin, cfg, pullnames[pull], slpmnames[slpm],
1906 output ? "output " : "input",
1907 output ? (val ? "high" : "low") : "",
1908 lowemi ? "on" : "off");
1909
1910 clk_enable(nmk_chip->clk);
1911 bit = pin % NMK_GPIO_PER_CHIP;
1912 if (gpiomode)
1913 /* No glitch when going to GPIO mode */
1914 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1915 if (output)
1916 __nmk_gpio_make_output(nmk_chip, bit, val);
1917 else {
1918 __nmk_gpio_make_input(nmk_chip, bit);
1919 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1920 }
1921 /* TODO: isn't this only applicable on output pins? */
1922 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1923
1924 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1925 clk_disable(nmk_chip->clk);
1926 } /* for each config */
1927
1928 return 0;
1929 }
1930
1931 static const struct pinconf_ops nmk_pinconf_ops = {
1932 .pin_config_get = nmk_pin_config_get,
1933 .pin_config_set = nmk_pin_config_set,
1934 };
1935
1936 static struct pinctrl_desc nmk_pinctrl_desc = {
1937 .name = "pinctrl-nomadik",
1938 .pctlops = &nmk_pinctrl_ops,
1939 .pmxops = &nmk_pinmux_ops,
1940 .confops = &nmk_pinconf_ops,
1941 .owner = THIS_MODULE,
1942 };
1943
1944 static const struct of_device_id nmk_pinctrl_match[] = {
1945 {
1946 .compatible = "stericsson,stn8815-pinctrl",
1947 .data = (void *)PINCTRL_NMK_STN8815,
1948 },
1949 {
1950 .compatible = "stericsson,db8500-pinctrl",
1951 .data = (void *)PINCTRL_NMK_DB8500,
1952 },
1953 {
1954 .compatible = "stericsson,db8540-pinctrl",
1955 .data = (void *)PINCTRL_NMK_DB8540,
1956 },
1957 {},
1958 };
1959
1960 #ifdef CONFIG_PM_SLEEP
1961 static int nmk_pinctrl_suspend(struct device *dev)
1962 {
1963 struct nmk_pinctrl *npct;
1964
1965 npct = dev_get_drvdata(dev);
1966 if (!npct)
1967 return -EINVAL;
1968
1969 return pinctrl_force_sleep(npct->pctl);
1970 }
1971
1972 static int nmk_pinctrl_resume(struct device *dev)
1973 {
1974 struct nmk_pinctrl *npct;
1975
1976 npct = dev_get_drvdata(dev);
1977 if (!npct)
1978 return -EINVAL;
1979
1980 return pinctrl_force_default(npct->pctl);
1981 }
1982 #endif
1983
1984 static int nmk_pinctrl_probe(struct platform_device *pdev)
1985 {
1986 const struct of_device_id *match;
1987 struct device_node *np = pdev->dev.of_node;
1988 struct device_node *prcm_np;
1989 struct nmk_pinctrl *npct;
1990 unsigned int version = 0;
1991 int i;
1992
1993 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1994 if (!npct)
1995 return -ENOMEM;
1996
1997 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1998 if (!match)
1999 return -ENODEV;
2000 version = (unsigned int) match->data;
2001
2002 /* Poke in other ASIC variants here */
2003 if (version == PINCTRL_NMK_STN8815)
2004 nmk_pinctrl_stn8815_init(&npct->soc);
2005 if (version == PINCTRL_NMK_DB8500)
2006 nmk_pinctrl_db8500_init(&npct->soc);
2007 if (version == PINCTRL_NMK_DB8540)
2008 nmk_pinctrl_db8540_init(&npct->soc);
2009
2010 prcm_np = of_parse_phandle(np, "prcm", 0);
2011 if (prcm_np)
2012 npct->prcm_base = of_iomap(prcm_np, 0);
2013 if (!npct->prcm_base) {
2014 if (version == PINCTRL_NMK_STN8815) {
2015 dev_info(&pdev->dev,
2016 "No PRCM base, "
2017 "assuming no ALT-Cx control is available\n");
2018 } else {
2019 dev_err(&pdev->dev, "missing PRCM base address\n");
2020 return -EINVAL;
2021 }
2022 }
2023
2024 /*
2025 * We need all the GPIO drivers to probe FIRST, or we will not be able
2026 * to obtain references to the struct gpio_chip * for them, and we
2027 * need this to proceed.
2028 */
2029 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2030 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2031 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2032 return -EPROBE_DEFER;
2033 }
2034 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2035 }
2036
2037 nmk_pinctrl_desc.pins = npct->soc->pins;
2038 nmk_pinctrl_desc.npins = npct->soc->npins;
2039 npct->dev = &pdev->dev;
2040
2041 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2042 if (!npct->pctl) {
2043 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2044 return -EINVAL;
2045 }
2046
2047 /* We will handle a range of GPIO pins */
2048 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2049 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2050
2051 platform_set_drvdata(pdev, npct);
2052 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2053
2054 return 0;
2055 }
2056
2057 static const struct of_device_id nmk_gpio_match[] = {
2058 { .compatible = "st,nomadik-gpio", },
2059 {}
2060 };
2061
2062 static struct platform_driver nmk_gpio_driver = {
2063 .driver = {
2064 .owner = THIS_MODULE,
2065 .name = "gpio",
2066 .of_match_table = nmk_gpio_match,
2067 },
2068 .probe = nmk_gpio_probe,
2069 };
2070
2071 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
2072 nmk_pinctrl_suspend,
2073 nmk_pinctrl_resume);
2074
2075 static struct platform_driver nmk_pinctrl_driver = {
2076 .driver = {
2077 .owner = THIS_MODULE,
2078 .name = "pinctrl-nomadik",
2079 .of_match_table = nmk_pinctrl_match,
2080 .pm = &nmk_pinctrl_pm_ops,
2081 },
2082 .probe = nmk_pinctrl_probe,
2083 };
2084
2085 static int __init nmk_gpio_init(void)
2086 {
2087 int ret;
2088
2089 ret = platform_driver_register(&nmk_gpio_driver);
2090 if (ret)
2091 return ret;
2092 return platform_driver_register(&nmk_pinctrl_driver);
2093 }
2094
2095 core_initcall(nmk_gpio_init);
2096
2097 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2098 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2099 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree