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pinctrl: sh-pfc: r8a7792: Add EtherAVB pin groups
[linux-2.6/btrfs-unstable.git] / drivers / pinctrl / sh-pfc / pfc-r8a7792.c
blobd51695d0d05f318f2cae32a7d548e6cf9300319e
1 /*
2 * r8a7792 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13
14 #include "core.h"
15 #include "sh_pfc.h"
16
17 #define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_29(0, fn, sfx), \
19 PORT_GP_23(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_28(3, fn, sfx), \
22 PORT_GP_17(4, fn, sfx), \
23 PORT_GP_17(5, fn, sfx), \
24 PORT_GP_17(6, fn, sfx), \
25 PORT_GP_17(7, fn, sfx), \
26 PORT_GP_17(8, fn, sfx), \
27 PORT_GP_17(9, fn, sfx), \
28 PORT_GP_32(10, fn, sfx), \
29 PORT_GP_30(11, fn, sfx)
30
31 enum {
32 PINMUX_RESERVED = 0,
33
34 PINMUX_DATA_BEGIN,
35 GP_ALL(DATA),
36 PINMUX_DATA_END,
37
38 PINMUX_FUNCTION_BEGIN,
39 GP_ALL(FN),
40
41 /* GPSR0 */
42 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
43 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
44 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
45 FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
46 FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
47 FN_IP1_3, FN_IP1_4,
48
49 /* GPSR1 */
50 FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
51 FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
52 FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
53 FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
54 FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
55 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
56
57 /* GPSR2 */
58 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
59 FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
60 FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
61 FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
62
63 /* GPSR3 */
64 FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
65 FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
66 FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
67 FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
68 FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
69
70 /* GPSR4 */
71 FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
72 FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
73 FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
74 FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
75 FN_VI0_FIELD,
76
77 /* GPSR5 */
78 FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
79 FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
80 FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
81 FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
82 FN_VI1_FIELD,
83
84 /* GPSR6 */
85 FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
86 FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
87 FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
88
89 /* GPSR7 */
90 FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
91 FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
92 FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
93
94 /* GPSR8 */
95 FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
96 FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
97 FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
98
99 /* GPSR9 */
100 FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
101 FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
102 FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
103
104 /* GPSR10 */
105 FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
106 FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
107 FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
108 FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
109 FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
110 FN_CAN1_TX, FN_CAN1_RX,
111
112 /* GPSR11 */
113 FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
114 FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
115 FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
116 FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
117 FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
118 FN_ADICHS2, FN_AVS1, FN_AVS2,
119
120 /* IPSR0 */
121 FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
122 FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
123 FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
124 FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
125 FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
126 FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
127 FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
128 FN_DU0_DB7_C5,
129
130 /* IPSR1 */
131 FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
132 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
133 FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
134 FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
135 FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
136 FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
137 FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
138 FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
139
140 /* IPSR2 */
141 FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
142 FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
143 FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
144 FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
145 FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
146 FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
147 FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
148 FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
149 FN_VI2_FIELD, FN_AVB_TXD2,
150
151 /* IPSR3 */
152 FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
153 FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
154 FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
155 FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
156 FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
157 FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
158 FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
159 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
160
161 /* IPSR4 */
162 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
163 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
164 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
165 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
166 FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
167 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
168 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
169 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
170 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
171 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
172 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
173 FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
174 FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
175
176 /* IPSR5 */
177 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
178 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
179 FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
180 FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
181 FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
182 FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
183
184 /* IPSR6 */
185 FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
186 FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
187 FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
188 FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
189 FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
190 FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
191
192 /* IPSR7 */
193 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
194 FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
195 FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
196 FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
197 FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
198 FN_AUDIO_CLKA, FN_AUDIO_CLKB,
199
200 /* MOD_SEL */
201 FN_SEL_VI1_0, FN_SEL_VI1_1,
202 PINMUX_FUNCTION_END,
203
204 PINMUX_MARK_BEGIN,
205 DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
206 DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
207 DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
208 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
209 DU1_DISP_MARK, DU1_CDE_MARK,
210
211 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
212 D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
213 D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
214 A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
215 A12_MARK, A13_MARK, A14_MARK, A15_MARK,
216
217 A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
218 EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
219 EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
220 WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
221 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
222
223 VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
224 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
225 VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
226 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
227 VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
228 VI0_FIELD_MARK,
229
230 VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
231 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
232 VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
233 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
234 VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
235 VI1_FIELD_MARK,
236
237 VI3_D10_Y2_MARK, VI3_FIELD_MARK,
238
239 VI4_CLK_MARK,
240
241 VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
242 VI5_FIELD_MARK,
243
244 HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
245 TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
246 TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
247 CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
248
249 SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
250 SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
251 ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
252 ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
253
254 /* IPSR0 */
255 DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
256 DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
257 DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
258 DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
259 DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
260 DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
261 DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
262 DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
263
264 /* IPSR1 */
265 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
266 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
267 DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
268 DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
269 DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
270 DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
271 A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
272 A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
273
274 /* IPSR2 */
275 VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
276 VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
277 VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
278 VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
279 VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
280 VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
281 VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
282 VI2_D10_Y2_MARK, AVB_TXD0_MARK,
283 VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
284
285 /* IPSR3 */
286 VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
287 VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
288 VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
289 VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
290 VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
291 VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
292 VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
293 VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
294
295 /* IPSR4 */
296 VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
297 VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
298 RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
299 VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
300 VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
301 VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
302 VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
303 VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
304 VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
305 VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
306 VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
307
308 /* IPSR5 */
309 VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
310 VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
311 VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
312 VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
313 VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
314 VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
315 VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
316
317 /* IPSR6 */
318 MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
319 MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
320 MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
321 MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
322 DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
323 RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
324 RX3_MARK,
325
326 /* IPSR7 */
327 PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
328 FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
329 PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
330 SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
331 SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
332 AUDIO_CLKB_MARK,
333 PINMUX_MARK_END,
334 };
335
336 static const u16 pinmux_data[] = {
337 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
338
339 PINMUX_SINGLE(DU1_DB2_C0_DATA12),
340 PINMUX_SINGLE(DU1_DB3_C1_DATA13),
341 PINMUX_SINGLE(DU1_DB4_C2_DATA14),
342 PINMUX_SINGLE(DU1_DB5_C3_DATA15),
343 PINMUX_SINGLE(DU1_DB6_C4),
344 PINMUX_SINGLE(DU1_DB7_C5),
345 PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
346 PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
347 PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
348 PINMUX_SINGLE(DU1_DISP),
349 PINMUX_SINGLE(DU1_CDE),
350 PINMUX_SINGLE(D0),
351 PINMUX_SINGLE(D1),
352 PINMUX_SINGLE(D2),
353 PINMUX_SINGLE(D3),
354 PINMUX_SINGLE(D4),
355 PINMUX_SINGLE(D5),
356 PINMUX_SINGLE(D6),
357 PINMUX_SINGLE(D7),
358 PINMUX_SINGLE(D8),
359 PINMUX_SINGLE(D9),
360 PINMUX_SINGLE(D10),
361 PINMUX_SINGLE(D11),
362 PINMUX_SINGLE(D12),
363 PINMUX_SINGLE(D13),
364 PINMUX_SINGLE(D14),
365 PINMUX_SINGLE(D15),
366 PINMUX_SINGLE(A0),
367 PINMUX_SINGLE(A1),
368 PINMUX_SINGLE(A2),
369 PINMUX_SINGLE(A3),
370 PINMUX_SINGLE(A4),
371 PINMUX_SINGLE(A5),
372 PINMUX_SINGLE(A6),
373 PINMUX_SINGLE(A7),
374 PINMUX_SINGLE(A8),
375 PINMUX_SINGLE(A9),
376 PINMUX_SINGLE(A10),
377 PINMUX_SINGLE(A11),
378 PINMUX_SINGLE(A12),
379 PINMUX_SINGLE(A13),
380 PINMUX_SINGLE(A14),
381 PINMUX_SINGLE(A15),
382 PINMUX_SINGLE(A16),
383 PINMUX_SINGLE(A17),
384 PINMUX_SINGLE(A18),
385 PINMUX_SINGLE(A19),
386 PINMUX_SINGLE(CS1_N_A26),
387 PINMUX_SINGLE(EX_CS0_N),
388 PINMUX_SINGLE(EX_CS1_N),
389 PINMUX_SINGLE(EX_CS2_N),
390 PINMUX_SINGLE(EX_CS3_N),
391 PINMUX_SINGLE(EX_CS4_N),
392 PINMUX_SINGLE(EX_CS5_N),
393 PINMUX_SINGLE(BS_N),
394 PINMUX_SINGLE(RD_N),
395 PINMUX_SINGLE(RD_WR_N),
396 PINMUX_SINGLE(WE0_N),
397 PINMUX_SINGLE(WE1_N),
398 PINMUX_SINGLE(EX_WAIT0),
399 PINMUX_SINGLE(IRQ0),
400 PINMUX_SINGLE(IRQ1),
401 PINMUX_SINGLE(IRQ2),
402 PINMUX_SINGLE(IRQ3),
403 PINMUX_SINGLE(CS0_N),
404 PINMUX_SINGLE(VI0_CLK),
405 PINMUX_SINGLE(VI0_CLKENB),
406 PINMUX_SINGLE(VI0_HSYNC_N),
407 PINMUX_SINGLE(VI0_VSYNC_N),
408 PINMUX_SINGLE(VI0_D0_B0_C0),
409 PINMUX_SINGLE(VI0_D1_B1_C1),
410 PINMUX_SINGLE(VI0_D2_B2_C2),
411 PINMUX_SINGLE(VI0_D3_B3_C3),
412 PINMUX_SINGLE(VI0_D4_B4_C4),
413 PINMUX_SINGLE(VI0_D5_B5_C5),
414 PINMUX_SINGLE(VI0_D6_B6_C6),
415 PINMUX_SINGLE(VI0_D7_B7_C7),
416 PINMUX_SINGLE(VI0_D8_G0_Y0),
417 PINMUX_SINGLE(VI0_D9_G1_Y1),
418 PINMUX_SINGLE(VI0_D10_G2_Y2),
419 PINMUX_SINGLE(VI0_D11_G3_Y3),
420 PINMUX_SINGLE(VI0_FIELD),
421 PINMUX_SINGLE(VI1_CLK),
422 PINMUX_SINGLE(VI1_CLKENB),
423 PINMUX_SINGLE(VI1_HSYNC_N),
424 PINMUX_SINGLE(VI1_VSYNC_N),
425 PINMUX_SINGLE(VI1_D0_B0_C0),
426 PINMUX_SINGLE(VI1_D1_B1_C1),
427 PINMUX_SINGLE(VI1_D2_B2_C2),
428 PINMUX_SINGLE(VI1_D3_B3_C3),
429 PINMUX_SINGLE(VI1_D4_B4_C4),
430 PINMUX_SINGLE(VI1_D5_B5_C5),
431 PINMUX_SINGLE(VI1_D6_B6_C6),
432 PINMUX_SINGLE(VI1_D7_B7_C7),
433 PINMUX_SINGLE(VI1_D8_G0_Y0),
434 PINMUX_SINGLE(VI1_D9_G1_Y1),
435 PINMUX_SINGLE(VI1_D10_G2_Y2),
436 PINMUX_SINGLE(VI1_D11_G3_Y3),
437 PINMUX_SINGLE(VI1_FIELD),
438 PINMUX_SINGLE(VI3_D10_Y2),
439 PINMUX_SINGLE(VI3_FIELD),
440 PINMUX_SINGLE(VI4_CLK),
441 PINMUX_SINGLE(VI5_CLK),
442 PINMUX_SINGLE(VI5_D9_Y1),
443 PINMUX_SINGLE(VI5_D10_Y2),
444 PINMUX_SINGLE(VI5_D11_Y3),
445 PINMUX_SINGLE(VI5_FIELD),
446 PINMUX_SINGLE(HRTS0_N),
447 PINMUX_SINGLE(HCTS1_N),
448 PINMUX_SINGLE(SCK0),
449 PINMUX_SINGLE(CTS0_N),
450 PINMUX_SINGLE(RTS0_N),
451 PINMUX_SINGLE(TX0),
452 PINMUX_SINGLE(RX0),
453 PINMUX_SINGLE(SCK1),
454 PINMUX_SINGLE(CTS1_N),
455 PINMUX_SINGLE(RTS1_N),
456 PINMUX_SINGLE(TX1),
457 PINMUX_SINGLE(RX1),
458 PINMUX_SINGLE(SCIF_CLK),
459 PINMUX_SINGLE(CAN0_TX),
460 PINMUX_SINGLE(CAN0_RX),
461 PINMUX_SINGLE(CAN_CLK),
462 PINMUX_SINGLE(CAN1_TX),
463 PINMUX_SINGLE(CAN1_RX),
464 PINMUX_SINGLE(SD0_CLK),
465 PINMUX_SINGLE(SD0_CMD),
466 PINMUX_SINGLE(SD0_DAT0),
467 PINMUX_SINGLE(SD0_DAT1),
468 PINMUX_SINGLE(SD0_DAT2),
469 PINMUX_SINGLE(SD0_DAT3),
470 PINMUX_SINGLE(SD0_CD),
471 PINMUX_SINGLE(SD0_WP),
472 PINMUX_SINGLE(ADICLK),
473 PINMUX_SINGLE(ADICS_SAMP),
474 PINMUX_SINGLE(ADIDATA),
475 PINMUX_SINGLE(ADICHS0),
476 PINMUX_SINGLE(ADICHS1),
477 PINMUX_SINGLE(ADICHS2),
478 PINMUX_SINGLE(AVS1),
479 PINMUX_SINGLE(AVS2),
480
481 /* IPSR0 */
482 PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
483 PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
484 PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
485 PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
486 PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
487 PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
488 PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
489 PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
490 PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
491 PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
492 PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
493 PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
494 PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
495 PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
496 PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
497 PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
498 PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
499 PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
500 PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
501 PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
502 PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
503 PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
504 PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
505 PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
506
507 /* IPSR1 */
508 PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
509 PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
510 PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
511 PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
512 PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
513 PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
514 PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
515 PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
516 PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
517 PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
518 PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
519 PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
520 PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
521 PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
522 PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
523 PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
524 PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
525 PINMUX_IPSR_GPSR(IP1_17, A20),
526 PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
527 PINMUX_IPSR_GPSR(IP1_18, A21),
528 PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
529 PINMUX_IPSR_GPSR(IP1_19, A22),
530 PINMUX_IPSR_GPSR(IP1_19, IO2),
531 PINMUX_IPSR_GPSR(IP1_20, A23),
532 PINMUX_IPSR_GPSR(IP1_20, IO3),
533 PINMUX_IPSR_GPSR(IP1_21, A24),
534 PINMUX_IPSR_GPSR(IP1_21, SPCLK),
535 PINMUX_IPSR_GPSR(IP1_22, A25),
536 PINMUX_IPSR_GPSR(IP1_22, SSL),
537
538 /* IPSR2 */
539 PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
540 PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
541 PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
542 PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
543 PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
544 PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
545 PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
546 PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
547 PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
548 PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
549 PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
550 PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
551 PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
552 PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
553 PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
554 PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
555 PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
556 PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
557 PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
558 PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
559 PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
560 PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
561 PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
562 PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
563 PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
564 PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
565 PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
566 PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
567 PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
568 PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
569 PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
570 PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
571 PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
572 PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
573
574 /* IPSR3 */
575 PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
576 PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
577 PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
578 PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
579 PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
580 PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
581 PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
582 PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
583 PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
584 PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
585 PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
586 PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
587 PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
588 PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
589 PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
590 PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
591 PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
592 PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
593 PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
594 PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
595 PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
596 PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
597 PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
598 PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
599 PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
600 PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
601 PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
602 PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
603 PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
604 PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
605
606 /* IPSR4 */
607 PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
608 PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
609 PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
610 PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
611 PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
612 PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
613 PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
614 PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
615 PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
616 PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
617 PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
618 PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
619 PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
620 PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
621 PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
622 PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
623 PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
624 PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
625 PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
626 PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
627 PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
628 PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
629 PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
630 PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
631 PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
632 PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
633 PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
634 PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
635 PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
636 PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
637 PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
638 PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
639 PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
640 PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
641 PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
642 PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
643 PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
644 PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
645 PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
646 PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
647
648 /* IPSR5 */
649 PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
650 PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
651 PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
652 PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
653 PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
654 PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
655 PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
656 PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
657 PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
658 PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
659 PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
660 PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
661 PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
662 PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
663 PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
664 PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
665 PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
666 PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
667 PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
668 PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
669 PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
670 PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
671 PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
672 PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
673
674 /* IPSR6 */
675 PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
676 PINMUX_IPSR_GPSR(IP6_0, HSCK0),
677 PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
678 PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
679 PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
680 PINMUX_IPSR_GPSR(IP6_2, HTX0),
681 PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
682 PINMUX_IPSR_GPSR(IP6_3, HRX0),
683 PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
684 PINMUX_IPSR_GPSR(IP6_4, HSCK1),
685 PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
686 PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
687 PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
688 PINMUX_IPSR_GPSR(IP6_6, HTX1),
689 PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
690 PINMUX_IPSR_GPSR(IP6_7, HRX1),
691 PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
692 PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
693 PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
694 PINMUX_IPSR_GPSR(IP6_11_10, TX2),
695 PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
696 PINMUX_IPSR_GPSR(IP6_13_12, RX2),
697 PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
698 PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
699 PINMUX_IPSR_GPSR(IP6_16, TX3),
700 PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
701 PINMUX_IPSR_GPSR(IP6_18_17, RX3),
702
703 /* IPSR7 */
704 PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
705 PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
706 PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
707 PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
708 PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
709 PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
710 PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
711 PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
712 PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
713 PINMUX_IPSR_GPSR(IP7_6, PWM3),
714 PINMUX_IPSR_GPSR(IP7_7, PWM4),
715 PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
716 PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
717 PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
718 PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
719 PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
720 PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
721 PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
722 PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
723 PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
724 PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
725 PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
726 PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
727 PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
728 };
729
730 static const struct sh_pfc_pin pinmux_pins[] = {
731 PINMUX_GPIO_GP_ALL(),
732 };
733
734 /* - AVB -------------------------------------------------------------------- */
735 static const unsigned int avb_link_pins[] = {
736 RCAR_GP_PIN(7, 9),
737 };
738 static const unsigned int avb_link_mux[] = {
739 AVB_LINK_MARK,
740 };
741 static const unsigned int avb_magic_pins[] = {
742 RCAR_GP_PIN(7, 10),
743 };
744 static const unsigned int avb_magic_mux[] = {
745 AVB_MAGIC_MARK,
746 };
747 static const unsigned int avb_phy_int_pins[] = {
748 RCAR_GP_PIN(7, 11),
749 };
750 static const unsigned int avb_phy_int_mux[] = {
751 AVB_PHY_INT_MARK,
752 };
753 static const unsigned int avb_mdio_pins[] = {
754 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
755 };
756 static const unsigned int avb_mdio_mux[] = {
757 AVB_MDC_MARK, AVB_MDIO_MARK,
758 };
759 static const unsigned int avb_mii_pins[] = {
760 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
761 RCAR_GP_PIN(6, 12),
762
763 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
764 RCAR_GP_PIN(6, 5),
765
766 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
767 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
768 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(6, 11),
769 };
770 static const unsigned int avb_mii_mux[] = {
771 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
772 AVB_TXD3_MARK,
773
774 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
775 AVB_RXD3_MARK,
776
777 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
778 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
779 AVB_TX_CLK_MARK, AVB_COL_MARK,
780 };
781 static const unsigned int avb_gmii_pins[] = {
782 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
783 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 2),
784 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
785
786 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
787 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
788 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
789
790 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
791 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
792 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
793 RCAR_GP_PIN(6, 11),
794 };
795 static const unsigned int avb_gmii_mux[] = {
796 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
797 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
798 AVB_TXD6_MARK, AVB_TXD7_MARK,
799
800 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
801 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
802 AVB_RXD6_MARK, AVB_RXD7_MARK,
803
804 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
805 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
806 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
807 AVB_COL_MARK,
808 };
809 static const unsigned int avb_avtp_match_pins[] = {
810 RCAR_GP_PIN(7, 15),
811 };
812 static const unsigned int avb_avtp_match_mux[] = {
813 AVB_AVTP_MATCH_MARK,
814 };
815 /* - INTC ------------------------------------------------------------------- */
816 static const unsigned int intc_irq0_pins[] = {
817 /* IRQ0 */
818 RCAR_GP_PIN(3, 19),
819 };
820 static const unsigned int intc_irq0_mux[] = {
821 IRQ0_MARK,
822 };
823 static const unsigned int intc_irq1_pins[] = {
824 /* IRQ1 */
825 RCAR_GP_PIN(3, 20),
826 };
827 static const unsigned int intc_irq1_mux[] = {
828 IRQ1_MARK,
829 };
830 static const unsigned int intc_irq2_pins[] = {
831 /* IRQ2 */
832 RCAR_GP_PIN(3, 21),
833 };
834 static const unsigned int intc_irq2_mux[] = {
835 IRQ2_MARK,
836 };
837 static const unsigned int intc_irq3_pins[] = {
838 /* IRQ3 */
839 RCAR_GP_PIN(3, 22),
840 };
841 static const unsigned int intc_irq3_mux[] = {
842 IRQ3_MARK,
843 };
844 /* - LBSC ------------------------------------------------------------------- */
845 static const unsigned int lbsc_cs0_pins[] = {
846 /* CS0# */
847 RCAR_GP_PIN(3, 27),
848 };
849 static const unsigned int lbsc_cs0_mux[] = {
850 CS0_N_MARK,
851 };
852 static const unsigned int lbsc_cs1_pins[] = {
853 /* CS1#_A26 */
854 RCAR_GP_PIN(3, 6),
855 };
856 static const unsigned int lbsc_cs1_mux[] = {
857 CS1_N_A26_MARK,
858 };
859 static const unsigned int lbsc_ex_cs0_pins[] = {
860 /* EX_CS0# */
861 RCAR_GP_PIN(3, 7),
862 };
863 static const unsigned int lbsc_ex_cs0_mux[] = {
864 EX_CS0_N_MARK,
865 };
866 static const unsigned int lbsc_ex_cs1_pins[] = {
867 /* EX_CS1# */
868 RCAR_GP_PIN(3, 8),
869 };
870 static const unsigned int lbsc_ex_cs1_mux[] = {
871 EX_CS1_N_MARK,
872 };
873 static const unsigned int lbsc_ex_cs2_pins[] = {
874 /* EX_CS2# */
875 RCAR_GP_PIN(3, 9),
876 };
877 static const unsigned int lbsc_ex_cs2_mux[] = {
878 EX_CS2_N_MARK,
879 };
880 static const unsigned int lbsc_ex_cs3_pins[] = {
881 /* EX_CS3# */
882 RCAR_GP_PIN(3, 10),
883 };
884 static const unsigned int lbsc_ex_cs3_mux[] = {
885 EX_CS3_N_MARK,
886 };
887 static const unsigned int lbsc_ex_cs4_pins[] = {
888 /* EX_CS4# */
889 RCAR_GP_PIN(3, 11),
890 };
891 static const unsigned int lbsc_ex_cs4_mux[] = {
892 EX_CS4_N_MARK,
893 };
894 static const unsigned int lbsc_ex_cs5_pins[] = {
895 /* EX_CS5# */
896 RCAR_GP_PIN(3, 12),
897 };
898 static const unsigned int lbsc_ex_cs5_mux[] = {
899 EX_CS5_N_MARK,
900 };
901 /* - SCIF0 ------------------------------------------------------------------ */
902 static const unsigned int scif0_data_pins[] = {
903 /* RX, TX */
904 RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
905 };
906 static const unsigned int scif0_data_mux[] = {
907 RX0_MARK, TX0_MARK,
908 };
909 static const unsigned int scif0_clk_pins[] = {
910 /* SCK */
911 RCAR_GP_PIN(10, 10),
912 };
913 static const unsigned int scif0_clk_mux[] = {
914 SCK0_MARK,
915 };
916 static const unsigned int scif0_ctrl_pins[] = {
917 /* RTS, CTS */
918 RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
919 };
920 static const unsigned int scif0_ctrl_mux[] = {
921 RTS0_N_MARK, CTS0_N_MARK,
922 };
923 /* - SCIF3 ------------------------------------------------------------------ */
924 static const unsigned int scif3_data_pins[] = {
925 /* RX, TX */
926 RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
927 };
928 static const unsigned int scif3_data_mux[] = {
929 RX3_MARK, TX3_MARK,
930 };
931 static const unsigned int scif3_clk_pins[] = {
932 /* SCK */
933 RCAR_GP_PIN(10, 23),
934 };
935 static const unsigned int scif3_clk_mux[] = {
936 SCK3_MARK,
937 };
938
939 static const struct sh_pfc_pin_group pinmux_groups[] = {
940 SH_PFC_PIN_GROUP(avb_link),
941 SH_PFC_PIN_GROUP(avb_magic),
942 SH_PFC_PIN_GROUP(avb_phy_int),
943 SH_PFC_PIN_GROUP(avb_mdio),
944 SH_PFC_PIN_GROUP(avb_mii),
945 SH_PFC_PIN_GROUP(avb_gmii),
946 SH_PFC_PIN_GROUP(avb_avtp_match),
947 SH_PFC_PIN_GROUP(intc_irq0),
948 SH_PFC_PIN_GROUP(intc_irq1),
949 SH_PFC_PIN_GROUP(intc_irq2),
950 SH_PFC_PIN_GROUP(intc_irq3),
951 SH_PFC_PIN_GROUP(lbsc_cs0),
952 SH_PFC_PIN_GROUP(lbsc_cs1),
953 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
954 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
955 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
956 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
957 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
958 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
959 SH_PFC_PIN_GROUP(scif0_data),
960 SH_PFC_PIN_GROUP(scif0_clk),
961 SH_PFC_PIN_GROUP(scif0_ctrl),
962 SH_PFC_PIN_GROUP(scif3_data),
963 SH_PFC_PIN_GROUP(scif3_clk),
964 };
965
966 static const char * const avb_groups[] = {
967 "avb_link",
968 "avb_magic",
969 "avb_phy_int",
970 "avb_mdio",
971 "avb_mii",
972 "avb_gmii",
973 "avb_avtp_match",
974 };
975
976 static const char * const intc_groups[] = {
977 "intc_irq0",
978 "intc_irq1",
979 "intc_irq2",
980 "intc_irq3",
981 };
982
983 static const char * const lbsc_groups[] = {
984 "lbsc_cs0",
985 "lbsc_cs1",
986 "lbsc_ex_cs0",
987 "lbsc_ex_cs1",
988 "lbsc_ex_cs2",
989 "lbsc_ex_cs3",
990 "lbsc_ex_cs4",
991 "lbsc_ex_cs5",
992 };
993
994 static const char * const scif0_groups[] = {
995 "scif0_data",
996 "scif0_clk",
997 "scif0_ctrl",
998 };
999
1000 static const char * const scif3_groups[] = {
1001 "scif3_data",
1002 "scif3_clk",
1003 };
1004
1005 static const struct sh_pfc_function pinmux_functions[] = {
1006 SH_PFC_FUNCTION(avb),
1007 SH_PFC_FUNCTION(intc),
1008 SH_PFC_FUNCTION(lbsc),
1009 SH_PFC_FUNCTION(scif0),
1010 SH_PFC_FUNCTION(scif3),
1011 };
1012
1013 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1014 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1015 0, 0,
1016 0, 0,
1017 0, 0,
1018 GP_0_28_FN, FN_IP1_4,
1019 GP_0_27_FN, FN_IP1_3,
1020 GP_0_26_FN, FN_IP1_2,
1021 GP_0_25_FN, FN_IP1_1,
1022 GP_0_24_FN, FN_IP1_0,
1023 GP_0_23_FN, FN_IP0_23,
1024 GP_0_22_FN, FN_IP0_22,
1025 GP_0_21_FN, FN_IP0_21,
1026 GP_0_20_FN, FN_IP0_20,
1027 GP_0_19_FN, FN_IP0_19,
1028 GP_0_18_FN, FN_IP0_18,
1029 GP_0_17_FN, FN_IP0_17,
1030 GP_0_16_FN, FN_IP0_16,
1031 GP_0_15_FN, FN_IP0_15,
1032 GP_0_14_FN, FN_IP0_14,
1033 GP_0_13_FN, FN_IP0_13,
1034 GP_0_12_FN, FN_IP0_12,
1035 GP_0_11_FN, FN_IP0_11,
1036 GP_0_10_FN, FN_IP0_10,
1037 GP_0_9_FN, FN_IP0_9,
1038 GP_0_8_FN, FN_IP0_8,
1039 GP_0_7_FN, FN_IP0_7,
1040 GP_0_6_FN, FN_IP0_6,
1041 GP_0_5_FN, FN_IP0_5,
1042 GP_0_4_FN, FN_IP0_4,
1043 GP_0_3_FN, FN_IP0_3,
1044 GP_0_2_FN, FN_IP0_2,
1045 GP_0_1_FN, FN_IP0_1,
1046 GP_0_0_FN, FN_IP0_0 }
1047 },
1048 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1049 0, 0,
1050 0, 0,
1051 0, 0,
1052 0, 0,
1053 0, 0,
1054 0, 0,
1055 0, 0,
1056 0, 0,
1057 0, 0,
1058 GP_1_22_FN, FN_DU1_CDE,
1059 GP_1_21_FN, FN_DU1_DISP,
1060 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
1061 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
1062 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
1063 GP_1_17_FN, FN_DU1_DB7_C5,
1064 GP_1_16_FN, FN_DU1_DB6_C4,
1065 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
1066 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
1067 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
1068 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
1069 GP_1_11_FN, FN_IP1_16,
1070 GP_1_10_FN, FN_IP1_15,
1071 GP_1_9_FN, FN_IP1_14,
1072 GP_1_8_FN, FN_IP1_13,
1073 GP_1_7_FN, FN_IP1_12,
1074 GP_1_6_FN, FN_IP1_11,
1075 GP_1_5_FN, FN_IP1_10,
1076 GP_1_4_FN, FN_IP1_9,
1077 GP_1_3_FN, FN_IP1_8,
1078 GP_1_2_FN, FN_IP1_7,
1079 GP_1_1_FN, FN_IP1_6,
1080 GP_1_0_FN, FN_IP1_5, }
1081 },
1082 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1083 GP_2_31_FN, FN_A15,
1084 GP_2_30_FN, FN_A14,
1085 GP_2_29_FN, FN_A13,
1086 GP_2_28_FN, FN_A12,
1087 GP_2_27_FN, FN_A11,
1088 GP_2_26_FN, FN_A10,
1089 GP_2_25_FN, FN_A9,
1090 GP_2_24_FN, FN_A8,
1091 GP_2_23_FN, FN_A7,
1092 GP_2_22_FN, FN_A6,
1093 GP_2_21_FN, FN_A5,
1094 GP_2_20_FN, FN_A4,
1095 GP_2_19_FN, FN_A3,
1096 GP_2_18_FN, FN_A2,
1097 GP_2_17_FN, FN_A1,
1098 GP_2_16_FN, FN_A0,
1099 GP_2_15_FN, FN_D15,
1100 GP_2_14_FN, FN_D14,
1101 GP_2_13_FN, FN_D13,
1102 GP_2_12_FN, FN_D12,
1103 GP_2_11_FN, FN_D11,
1104 GP_2_10_FN, FN_D10,
1105 GP_2_9_FN, FN_D9,
1106 GP_2_8_FN, FN_D8,
1107 GP_2_7_FN, FN_D7,
1108 GP_2_6_FN, FN_D6,
1109 GP_2_5_FN, FN_D5,
1110 GP_2_4_FN, FN_D4,
1111 GP_2_3_FN, FN_D3,
1112 GP_2_2_FN, FN_D2,
1113 GP_2_1_FN, FN_D1,
1114 GP_2_0_FN, FN_D0 }
1115 },
1116 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1117 0, 0,
1118 0, 0,
1119 0, 0,
1120 0, 0,
1121 GP_3_27_FN, FN_CS0_N,
1122 GP_3_26_FN, FN_IP1_22,
1123 GP_3_25_FN, FN_IP1_21,
1124 GP_3_24_FN, FN_IP1_20,
1125 GP_3_23_FN, FN_IP1_19,
1126 GP_3_22_FN, FN_IRQ3,
1127 GP_3_21_FN, FN_IRQ2,
1128 GP_3_20_FN, FN_IRQ1,
1129 GP_3_19_FN, FN_IRQ0,
1130 GP_3_18_FN, FN_EX_WAIT0,
1131 GP_3_17_FN, FN_WE1_N,
1132 GP_3_16_FN, FN_WE0_N,
1133 GP_3_15_FN, FN_RD_WR_N,
1134 GP_3_14_FN, FN_RD_N,
1135 GP_3_13_FN, FN_BS_N,
1136 GP_3_12_FN, FN_EX_CS5_N,
1137 GP_3_11_FN, FN_EX_CS4_N,
1138 GP_3_10_FN, FN_EX_CS3_N,
1139 GP_3_9_FN, FN_EX_CS2_N,
1140 GP_3_8_FN, FN_EX_CS1_N,
1141 GP_3_7_FN, FN_EX_CS0_N,
1142 GP_3_6_FN, FN_CS1_N_A26,
1143 GP_3_5_FN, FN_IP1_18,
1144 GP_3_4_FN, FN_IP1_17,
1145 GP_3_3_FN, FN_A19,
1146 GP_3_2_FN, FN_A18,
1147 GP_3_1_FN, FN_A17,
1148 GP_3_0_FN, FN_A16 }
1149 },
1150 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1151 0, 0,
1152 0, 0,
1153 0, 0,
1154 0, 0,
1155 0, 0,
1156 0, 0,
1157 0, 0,
1158 0, 0,
1159 0, 0,
1160 0, 0,
1161 0, 0,
1162 0, 0,
1163 0, 0,
1164 0, 0,
1165 0, 0,
1166 GP_4_16_FN, FN_VI0_FIELD,
1167 GP_4_15_FN, FN_VI0_D11_G3_Y3,
1168 GP_4_14_FN, FN_VI0_D10_G2_Y2,
1169 GP_4_13_FN, FN_VI0_D9_G1_Y1,
1170 GP_4_12_FN, FN_VI0_D8_G0_Y0,
1171 GP_4_11_FN, FN_VI0_D7_B7_C7,
1172 GP_4_10_FN, FN_VI0_D6_B6_C6,
1173 GP_4_9_FN, FN_VI0_D5_B5_C5,
1174 GP_4_8_FN, FN_VI0_D4_B4_C4,
1175 GP_4_7_FN, FN_VI0_D3_B3_C3,
1176 GP_4_6_FN, FN_VI0_D2_B2_C2,
1177 GP_4_5_FN, FN_VI0_D1_B1_C1,
1178 GP_4_4_FN, FN_VI0_D0_B0_C0,
1179 GP_4_3_FN, FN_VI0_VSYNC_N,
1180 GP_4_2_FN, FN_VI0_HSYNC_N,
1181 GP_4_1_FN, FN_VI0_CLKENB,
1182 GP_4_0_FN, FN_VI0_CLK }
1183 },
1184 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1185 0, 0,
1186 0, 0,
1187 0, 0,
1188 0, 0,
1189 0, 0,
1190 0, 0,
1191 0, 0,
1192 0, 0,
1193 0, 0,
1194 0, 0,
1195 0, 0,
1196 0, 0,
1197 0, 0,
1198 0, 0,
1199 0, 0,
1200 GP_5_16_FN, FN_VI1_FIELD,
1201 GP_5_15_FN, FN_VI1_D11_G3_Y3,
1202 GP_5_14_FN, FN_VI1_D10_G2_Y2,
1203 GP_5_13_FN, FN_VI1_D9_G1_Y1,
1204 GP_5_12_FN, FN_VI1_D8_G0_Y0,
1205 GP_5_11_FN, FN_VI1_D7_B7_C7,
1206 GP_5_10_FN, FN_VI1_D6_B6_C6,
1207 GP_5_9_FN, FN_VI1_D5_B5_C5,
1208 GP_5_8_FN, FN_VI1_D4_B4_C4,
1209 GP_5_7_FN, FN_VI1_D3_B3_C3,
1210 GP_5_6_FN, FN_VI1_D2_B2_C2,
1211 GP_5_5_FN, FN_VI1_D1_B1_C1,
1212 GP_5_4_FN, FN_VI1_D0_B0_C0,
1213 GP_5_3_FN, FN_VI1_VSYNC_N,
1214 GP_5_2_FN, FN_VI1_HSYNC_N,
1215 GP_5_1_FN, FN_VI1_CLKENB,
1216 GP_5_0_FN, FN_VI1_CLK }
1217 },
1218 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1219 0, 0,
1220 0, 0,
1221 0, 0,
1222 0, 0,
1223 0, 0,
1224 0, 0,
1225 0, 0,
1226 0, 0,
1227 0, 0,
1228 0, 0,
1229 0, 0,
1230 0, 0,
1231 0, 0,
1232 0, 0,
1233 0, 0,
1234 GP_6_16_FN, FN_IP2_16,
1235 GP_6_15_FN, FN_IP2_15,
1236 GP_6_14_FN, FN_IP2_14,
1237 GP_6_13_FN, FN_IP2_13,
1238 GP_6_12_FN, FN_IP2_12,
1239 GP_6_11_FN, FN_IP2_11,
1240 GP_6_10_FN, FN_IP2_10,
1241 GP_6_9_FN, FN_IP2_9,
1242 GP_6_8_FN, FN_IP2_8,
1243 GP_6_7_FN, FN_IP2_7,
1244 GP_6_6_FN, FN_IP2_6,
1245 GP_6_5_FN, FN_IP2_5,
1246 GP_6_4_FN, FN_IP2_4,
1247 GP_6_3_FN, FN_IP2_3,
1248 GP_6_2_FN, FN_IP2_2,
1249 GP_6_1_FN, FN_IP2_1,
1250 GP_6_0_FN, FN_IP2_0 }
1251 },
1252 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
1253 0, 0,
1254 0, 0,
1255 0, 0,
1256 0, 0,
1257 0, 0,
1258 0, 0,
1259 0, 0,
1260 0, 0,
1261 0, 0,
1262 0, 0,
1263 0, 0,
1264 0, 0,
1265 0, 0,
1266 0, 0,
1267 0, 0,
1268 GP_7_16_FN, FN_VI3_FIELD,
1269 GP_7_15_FN, FN_IP3_14,
1270 GP_7_14_FN, FN_VI3_D10_Y2,
1271 GP_7_13_FN, FN_IP3_13,
1272 GP_7_12_FN, FN_IP3_12,
1273 GP_7_11_FN, FN_IP3_11,
1274 GP_7_10_FN, FN_IP3_10,
1275 GP_7_9_FN, FN_IP3_9,
1276 GP_7_8_FN, FN_IP3_8,
1277 GP_7_7_FN, FN_IP3_7,
1278 GP_7_6_FN, FN_IP3_6,
1279 GP_7_5_FN, FN_IP3_5,
1280 GP_7_4_FN, FN_IP3_4,
1281 GP_7_3_FN, FN_IP3_3,
1282 GP_7_2_FN, FN_IP3_2,
1283 GP_7_1_FN, FN_IP3_1,
1284 GP_7_0_FN, FN_IP3_0 }
1285 },
1286 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
1287 0, 0,
1288 0, 0,
1289 0, 0,
1290 0, 0,
1291 0, 0,
1292 0, 0,
1293 0, 0,
1294 0, 0,
1295 0, 0,
1296 0, 0,
1297 0, 0,
1298 0, 0,
1299 0, 0,
1300 0, 0,
1301 0, 0,
1302 GP_8_16_FN, FN_IP4_24,
1303 GP_8_15_FN, FN_IP4_23,
1304 GP_8_14_FN, FN_IP4_22,
1305 GP_8_13_FN, FN_IP4_21,
1306 GP_8_12_FN, FN_IP4_20_19,
1307 GP_8_11_FN, FN_IP4_18_17,
1308 GP_8_10_FN, FN_IP4_16_15,
1309 GP_8_9_FN, FN_IP4_14_13,
1310 GP_8_8_FN, FN_IP4_12_11,
1311 GP_8_7_FN, FN_IP4_10_9,
1312 GP_8_6_FN, FN_IP4_8_7,
1313 GP_8_5_FN, FN_IP4_6_5,
1314 GP_8_4_FN, FN_IP4_4,
1315 GP_8_3_FN, FN_IP4_3_2,
1316 GP_8_2_FN, FN_IP4_1,
1317 GP_8_1_FN, FN_IP4_0,
1318 GP_8_0_FN, FN_VI4_CLK }
1319 },
1320 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
1321 0, 0,
1322 0, 0,
1323 0, 0,
1324 0, 0,
1325 0, 0,
1326 0, 0,
1327 0, 0,
1328 0, 0,
1329 0, 0,
1330 0, 0,
1331 0, 0,
1332 0, 0,
1333 0, 0,
1334 0, 0,
1335 0, 0,
1336 GP_9_16_FN, FN_VI5_FIELD,
1337 GP_9_15_FN, FN_VI5_D11_Y3,
1338 GP_9_14_FN, FN_VI5_D10_Y2,
1339 GP_9_13_FN, FN_VI5_D9_Y1,
1340 GP_9_12_FN, FN_IP5_11,
1341 GP_9_11_FN, FN_IP5_10,
1342 GP_9_10_FN, FN_IP5_9,
1343 GP_9_9_FN, FN_IP5_8,
1344 GP_9_8_FN, FN_IP5_7,
1345 GP_9_7_FN, FN_IP5_6,
1346 GP_9_6_FN, FN_IP5_5,
1347 GP_9_5_FN, FN_IP5_4,
1348 GP_9_4_FN, FN_IP5_3,
1349 GP_9_3_FN, FN_IP5_2,
1350 GP_9_2_FN, FN_IP5_1,
1351 GP_9_1_FN, FN_IP5_0,
1352 GP_9_0_FN, FN_VI5_CLK }
1353 },
1354 { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
1355 GP_10_31_FN, FN_CAN1_RX,
1356 GP_10_30_FN, FN_CAN1_TX,
1357 GP_10_29_FN, FN_CAN_CLK,
1358 GP_10_28_FN, FN_CAN0_RX,
1359 GP_10_27_FN, FN_CAN0_TX,
1360 GP_10_26_FN, FN_SCIF_CLK,
1361 GP_10_25_FN, FN_IP6_18_17,
1362 GP_10_24_FN, FN_IP6_16,
1363 GP_10_23_FN, FN_IP6_15_14,
1364 GP_10_22_FN, FN_IP6_13_12,
1365 GP_10_21_FN, FN_IP6_11_10,
1366 GP_10_20_FN, FN_IP6_9_8,
1367 GP_10_19_FN, FN_RX1,
1368 GP_10_18_FN, FN_TX1,
1369 GP_10_17_FN, FN_RTS1_N,
1370 GP_10_16_FN, FN_CTS1_N,
1371 GP_10_15_FN, FN_SCK1,
1372 GP_10_14_FN, FN_RX0,
1373 GP_10_13_FN, FN_TX0,
1374 GP_10_12_FN, FN_RTS0_N,
1375 GP_10_11_FN, FN_CTS0_N,
1376 GP_10_10_FN, FN_SCK0,
1377 GP_10_9_FN, FN_IP6_7,
1378 GP_10_8_FN, FN_IP6_6,
1379 GP_10_7_FN, FN_HCTS1_N,
1380 GP_10_6_FN, FN_IP6_5,
1381 GP_10_5_FN, FN_IP6_4,
1382 GP_10_4_FN, FN_IP6_3,
1383 GP_10_3_FN, FN_IP6_2,
1384 GP_10_2_FN, FN_HRTS0_N,
1385 GP_10_1_FN, FN_IP6_1,
1386 GP_10_0_FN, FN_IP6_0 }
1387 },
1388 { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
1389 0, 0,
1390 0, 0,
1391 GP_11_29_FN, FN_AVS2,
1392 GP_11_28_FN, FN_AVS1,
1393 GP_11_27_FN, FN_ADICHS2,
1394 GP_11_26_FN, FN_ADICHS1,
1395 GP_11_25_FN, FN_ADICHS0,
1396 GP_11_24_FN, FN_ADIDATA,
1397 GP_11_23_FN, FN_ADICS_SAMP,
1398 GP_11_22_FN, FN_ADICLK,
1399 GP_11_21_FN, FN_IP7_20,
1400 GP_11_20_FN, FN_IP7_19,
1401 GP_11_19_FN, FN_IP7_18,
1402 GP_11_18_FN, FN_IP7_17,
1403 GP_11_17_FN, FN_IP7_16,
1404 GP_11_16_FN, FN_IP7_15_14,
1405 GP_11_15_FN, FN_IP7_13_12,
1406 GP_11_14_FN, FN_IP7_11_10,
1407 GP_11_13_FN, FN_IP7_9_8,
1408 GP_11_12_FN, FN_SD0_WP,
1409 GP_11_11_FN, FN_SD0_CD,
1410 GP_11_10_FN, FN_SD0_DAT3,
1411 GP_11_9_FN, FN_SD0_DAT2,
1412 GP_11_8_FN, FN_SD0_DAT1,
1413 GP_11_7_FN, FN_SD0_DAT0,
1414 GP_11_6_FN, FN_SD0_CMD,
1415 GP_11_5_FN, FN_SD0_CLK,
1416 GP_11_4_FN, FN_IP7_7,
1417 GP_11_3_FN, FN_IP7_6,
1418 GP_11_2_FN, FN_IP7_5_4,
1419 GP_11_1_FN, FN_IP7_3_2,
1420 GP_11_0_FN, FN_IP7_1_0 }
1421 },
1422 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
1423 4, 4,
1424 1, 1, 1, 1, 1, 1, 1, 1,
1425 1, 1, 1, 1, 1, 1, 1, 1,
1426 1, 1, 1, 1, 1, 1, 1, 1) {
1427 /* IP0_31_28 [4] */
1428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1429 /* IP0_27_24 [4] */
1430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1431 /* IP0_23 [1] */
1432 FN_DU0_DB7_C5, 0,
1433 /* IP0_22 [1] */
1434 FN_DU0_DB6_C4, 0,
1435 /* IP0_21 [1] */
1436 FN_DU0_DB5_C3, 0,
1437 /* IP0_20 [1] */
1438 FN_DU0_DB4_C2, 0,
1439 /* IP0_19 [1] */
1440 FN_DU0_DB3_C1, 0,
1441 /* IP0_18 [1] */
1442 FN_DU0_DB2_C0, 0,
1443 /* IP0_17 [1] */
1444 FN_DU0_DB1, 0,
1445 /* IP0_16 [1] */
1446 FN_DU0_DB0, 0,
1447 /* IP0_15 [1] */
1448 FN_DU0_DG7_Y3_DATA15, 0,
1449 /* IP0_14 [1] */
1450 FN_DU0_DG6_Y2_DATA14, 0,
1451 /* IP0_13 [1] */
1452 FN_DU0_DG5_Y1_DATA13, 0,
1453 /* IP0_12 [1] */
1454 FN_DU0_DG4_Y0_DATA12, 0,
1455 /* IP0_11 [1] */
1456 FN_DU0_DG3_C7_DATA11, 0,
1457 /* IP0_10 [1] */
1458 FN_DU0_DG2_C6_DATA10, 0,
1459 /* IP0_9 [1] */
1460 FN_DU0_DG1_DATA9, 0,
1461 /* IP0_8 [1] */
1462 FN_DU0_DG0_DATA8, 0,
1463 /* IP0_7 [1] */
1464 FN_DU0_DR7_Y9_DATA7, 0,
1465 /* IP0_6 [1] */
1466 FN_DU0_DR6_Y8_DATA6, 0,
1467 /* IP0_5 [1] */
1468 FN_DU0_DR5_Y7_DATA5, 0,
1469 /* IP0_4 [1] */
1470 FN_DU0_DR4_Y6_DATA4, 0,
1471 /* IP0_3 [1] */
1472 FN_DU0_DR3_Y5_DATA3, 0,
1473 /* IP0_2 [1] */
1474 FN_DU0_DR2_Y4_DATA2, 0,
1475 /* IP0_1 [1] */
1476 FN_DU0_DR1_DATA1, 0,
1477 /* IP0_0 [1] */
1478 FN_DU0_DR0_DATA0, 0 }
1479 },
1480 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
1481 4, 4,
1482 1, 1, 1, 1, 1, 1, 1, 1,
1483 1, 1, 1, 1, 1, 1, 1, 1,
1484 1, 1, 1, 1, 1, 1, 1, 1) {
1485 /* IP1_31_28 [4] */
1486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1487 /* IP1_27_24 [4] */
1488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1489 /* IP1_23 [1] */
1490 0, 0,
1491 /* IP1_22 [1] */
1492 FN_A25, FN_SSL,
1493 /* IP1_21 [1] */
1494 FN_A24, FN_SPCLK,
1495 /* IP1_20 [1] */
1496 FN_A23, FN_IO3,
1497 /* IP1_19 [1] */
1498 FN_A22, FN_IO2,
1499 /* IP1_18 [1] */
1500 FN_A21, FN_MISO_IO1,
1501 /* IP1_17 [1] */
1502 FN_A20, FN_MOSI_IO0,
1503 /* IP1_16 [1] */
1504 FN_DU1_DG7_Y3_DATA11, 0,
1505 /* IP1_15 [1] */
1506 FN_DU1_DG6_Y2_DATA10, 0,
1507 /* IP1_14 [1] */
1508 FN_DU1_DG5_Y1_DATA9, 0,
1509 /* IP1_13 [1] */
1510 FN_DU1_DG4_Y0_DATA8, 0,
1511 /* IP1_12 [1] */
1512 FN_DU1_DG3_C7_DATA7, 0,
1513 /* IP1_11 [1] */
1514 FN_DU1_DG2_C6_DATA6, 0,
1515 /* IP1_10 [1] */
1516 FN_DU1_DR7_DATA5, 0,
1517 /* IP1_9 [1] */
1518 FN_DU1_DR6_DATA4, 0,
1519 /* IP1_8 [1] */
1520 FN_DU1_DR5_Y7_DATA3, 0,
1521 /* IP1_7 [1] */
1522 FN_DU1_DR4_Y6_DATA2, 0,
1523 /* IP1_6 [1] */
1524 FN_DU1_DR3_Y5_DATA1, 0,
1525 /* IP1_5 [1] */
1526 FN_DU1_DR2_Y4_DATA0, 0,
1527 /* IP1_4 [1] */
1528 FN_DU0_CDE, 0,
1529 /* IP1_3 [1] */
1530 FN_DU0_DISP, 0,
1531 /* IP1_2 [1] */
1532 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
1533 /* IP1_1 [1] */
1534 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
1535 /* IP1_0 [1] */
1536 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
1537 },
1538 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
1539 4, 4,
1540 4, 3, 1,
1541 1, 1, 1, 1, 1, 1, 1, 1,
1542 1, 1, 1, 1, 1, 1, 1, 1) {
1543 /* IP2_31_28 [4] */
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1545 /* IP2_27_24 [4] */
1546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1547 /* IP2_23_20 [4] */
1548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1549 /* IP2_19_17 [3] */
1550 0, 0, 0, 0, 0, 0, 0, 0,
1551 /* IP2_16 [1] */
1552 FN_VI2_FIELD, FN_AVB_TXD2,
1553 /* IP2_15 [1] */
1554 FN_VI2_D11_Y3, FN_AVB_TXD1,
1555 /* IP2_14 [1] */
1556 FN_VI2_D10_Y2, FN_AVB_TXD0,
1557 /* IP2_13 [1] */
1558 FN_VI2_D9_Y1, FN_AVB_TX_EN,
1559 /* IP2_12 [1] */
1560 FN_VI2_D8_Y0, FN_AVB_TXD3,
1561 /* IP2_11 [1] */
1562 FN_VI2_D7_C7, FN_AVB_COL,
1563 /* IP2_10 [1] */
1564 FN_VI2_D6_C6, FN_AVB_RX_ER,
1565 /* IP2_9 [1] */
1566 FN_VI2_D5_C5, FN_AVB_RXD7,
1567 /* IP2_8 [1] */
1568 FN_VI2_D4_C4, FN_AVB_RXD6,
1569 /* IP2_7 [1] */
1570 FN_VI2_D3_C3, FN_AVB_RXD5,
1571 /* IP2_6 [1] */
1572 FN_VI2_D2_C2, FN_AVB_RXD4,
1573 /* IP2_5 [1] */
1574 FN_VI2_D1_C1, FN_AVB_RXD3,
1575 /* IP2_4 [1] */
1576 FN_VI2_D0_C0, FN_AVB_RXD2,
1577 /* IP2_3 [1] */
1578 FN_VI2_VSYNC_N, FN_AVB_RXD1,
1579 /* IP2_2 [1] */
1580 FN_VI2_HSYNC_N, FN_AVB_RXD0,
1581 /* IP2_1 [1] */
1582 FN_VI2_CLKENB, FN_AVB_RX_DV,
1583 /* IP2_0 [1] */
1584 FN_VI2_CLK, FN_AVB_RX_CLK }
1585 },
1586 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
1587 4, 4,
1588 4, 4,
1589 1, 1, 1, 1, 1, 1, 1, 1,
1590 1, 1, 1, 1, 1, 1, 1, 1) {
1591 /* IP3_31_28 [4] */
1592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1593 /* IP3_27_24 [4] */
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1595 /* IP3_23_20 [4] */
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1597 /* IP3_19_16 [4] */
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1599 /* IP3_15 [1] */
1600 0, 0,
1601 /* IP3_14 [1] */
1602 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
1603 /* IP3_13 [1] */
1604 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
1605 /* IP3_12 [1] */
1606 FN_VI3_D8_Y0, FN_AVB_CRS,
1607 /* IP3_11 [1] */
1608 FN_VI3_D7_C7, FN_AVB_PHY_INT,
1609 /* IP3_10 [1] */
1610 FN_VI3_D6_C6, FN_AVB_MAGIC,
1611 /* IP3_9 [1] */
1612 FN_VI3_D5_C5, FN_AVB_LINK,
1613 /* IP3_8 [1] */
1614 FN_VI3_D4_C4, FN_AVB_MDIO,
1615 /* IP3_7 [1] */
1616 FN_VI3_D3_C3, FN_AVB_MDC,
1617 /* IP3_6 [1] */
1618 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
1619 /* IP3_5 [1] */
1620 FN_VI3_D1_C1, FN_AVB_TX_ER,
1621 /* IP3_4 [1] */
1622 FN_VI3_D0_C0, FN_AVB_TXD7,
1623 /* IP3_3 [1] */
1624 FN_VI3_VSYNC_N, FN_AVB_TXD6,
1625 /* IP3_2 [1] */
1626 FN_VI3_HSYNC_N, FN_AVB_TXD5,
1627 /* IP3_1 [1] */
1628 FN_VI3_CLKENB, FN_AVB_TXD4,
1629 /* IP3_0 [1] */
1630 FN_VI3_CLK, FN_AVB_TX_CLK }
1631 },
1632 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
1633 4, 3, 1,
1634 1, 1, 1, 2, 2, 2,
1635 2, 2, 2, 2, 2, 1, 2, 1, 1) {
1636 /* IP4_31_28 [4] */
1637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1638 /* IP4_27_25 [3] */
1639 0, 0, 0, 0, 0, 0, 0, 0,
1640 /* IP4_24 [1] */
1641 FN_VI4_FIELD, FN_VI3_D15_Y7,
1642 /* IP4_23 [1] */
1643 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
1644 /* IP4_22 [1] */
1645 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
1646 /* IP4_21 [1] */
1647 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
1648 /* IP4_20_19 [2] */
1649 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
1650 /* IP4_18_17 [2] */
1651 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
1652 /* IP4_16_15 [2] */
1653 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
1654 /* IP4_14_13 [2] */
1655 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
1656 /* IP4_12_11 [2] */
1657 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
1658 /* IP4_10_9 [2] */
1659 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
1660 /* IP4_8_7 [2] */
1661 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
1662 /* IP4_6_5 [2] */
1663 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
1664 /* IP4_4 [1] */
1665 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
1666 /* IP4_3_2 [2] */
1667 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
1668 /* IP4_1 [1] */
1669 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
1670 /* IP4_0 [1] */
1671 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
1672 },
1673 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
1674 4, 4,
1675 4, 4,
1676 4, 1, 1, 1, 1,
1677 1, 1, 1, 1, 1, 1, 1, 1) {
1678 /* IP5_31_28 [4] */
1679 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1680 /* IP5_27_24 [4] */
1681 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1682 /* IP5_23_20 [4] */
1683 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1684 /* IP5_19_16 [4] */
1685 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1686 /* IP5_15_12 [4] */
1687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1688 /* IP5_11 [1] */
1689 FN_VI5_D8_Y0, FN_VI1_D23_R7,
1690 /* IP5_10 [1] */
1691 FN_VI5_D7_C7, FN_VI1_D22_R6,
1692 /* IP5_9 [1] */
1693 FN_VI5_D6_C6, FN_VI1_D21_R5,
1694 /* IP5_8 [1] */
1695 FN_VI5_D5_C5, FN_VI1_D20_R4,
1696 /* IP5_7 [1] */
1697 FN_VI5_D4_C4, FN_VI1_D19_R3,
1698 /* IP5_6 [1] */
1699 FN_VI5_D3_C3, FN_VI1_D18_R2,
1700 /* IP5_5 [1] */
1701 FN_VI5_D2_C2, FN_VI1_D17_R1,
1702 /* IP5_4 [1] */
1703 FN_VI5_D1_C1, FN_VI1_D16_R0,
1704 /* IP5_3 [1] */
1705 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
1706 /* IP5_2 [1] */
1707 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
1708 /* IP5_1 [1] */
1709 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
1710 /* IP5_0 [1] */
1711 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
1712 },
1713 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
1714 4, 4,
1715 4, 1, 2, 1,
1716 2, 2, 2, 2,
1717 1, 1, 1, 1, 1, 1, 1, 1) {
1718 /* IP6_31_28 [4] */
1719 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1720 /* IP6_27_24 [4] */
1721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1722 /* IP6_23_20 [4] */
1723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1724 /* IP6_19 [1] */
1725 0, 0,
1726 /* IP6_18_17 [2] */
1727 FN_DREQ1_N, FN_RX3, 0, 0,
1728 /* IP6_16 [1] */
1729 FN_TX3, 0,
1730 /* IP6_15_14 [2] */
1731 FN_DACK1, FN_SCK3, 0, 0,
1732 /* IP6_13_12 [2] */
1733 FN_DREQ0_N, FN_RX2, 0, 0,
1734 /* IP6_11_10 [2] */
1735 FN_DACK0, FN_TX2, 0, 0,
1736 /* IP6_9_8 [2] */
1737 FN_DRACK0, FN_SCK2, 0, 0,
1738 /* IP6_7 [1] */
1739 FN_MSIOF1_RXD, FN_HRX1,
1740 /* IP6_6 [1] */
1741 FN_MSIOF1_TXD, FN_HTX1,
1742 /* IP6_5 [1] */
1743 FN_MSIOF1_SYNC, FN_HRTS1_N,
1744 /* IP6_4 [1] */
1745 FN_MSIOF1_SCK, FN_HSCK1,
1746 /* IP6_3 [1] */
1747 FN_MSIOF0_RXD, FN_HRX0,
1748 /* IP6_2 [1] */
1749 FN_MSIOF0_TXD, FN_HTX0,
1750 /* IP6_1 [1] */
1751 FN_MSIOF0_SYNC, FN_HCTS0_N,
1752 /* IP6_0 [1] */
1753 FN_MSIOF0_SCK, FN_HSCK0 }
1754 },
1755 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
1756 4, 4,
1757 3, 1, 1, 1, 1, 1,
1758 2, 2, 2, 2,
1759 1, 1, 2, 2, 2) {
1760 /* IP7_31_28 [4] */
1761 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1762 /* IP7_27_24 [4] */
1763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1764 /* IP7_23_21 [3] */
1765 0, 0, 0, 0, 0, 0, 0, 0,
1766 /* IP7_20 [1] */
1767 FN_AUDIO_CLKB, 0,
1768 /* IP7_19 [1] */
1769 FN_AUDIO_CLKA, 0,
1770 /* IP7_18 [1] */
1771 FN_AUDIO_CLKOUT, 0,
1772 /* IP7_17 [1] */
1773 FN_SSI_SDATA4, 0,
1774 /* IP7_16 [1] */
1775 FN_SSI_WS4, 0,
1776 /* IP7_15_14 [2] */
1777 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
1778 /* IP7_13_12 [2] */
1779 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
1780 /* IP7_11_10 [2] */
1781 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
1782 /* IP7_9_8 [2] */
1783 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
1784 /* IP7_7 [1] */
1785 FN_PWM4, 0,
1786 /* IP7_6 [1] */
1787 FN_PWM3, 0,
1788 /* IP7_5_4 [2] */
1789 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
1790 /* IP7_3_2 [2] */
1791 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
1792 /* IP7_1_0 [2] */
1793 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
1794 },
1795 { },
1796 };
1797
1798 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
1799 .name = "r8a77920_pfc",
1800 .unlock_reg = 0xe6060000, /* PMMR */
1801
1802 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1803
1804 .pins = pinmux_pins,
1805 .nr_pins = ARRAY_SIZE(pinmux_pins),
1806 .groups = pinmux_groups,
1807 .nr_groups = ARRAY_SIZE(pinmux_groups),
1808 .functions = pinmux_functions,
1809 .nr_functions = ARRAY_SIZE(pinmux_functions),
1810
1811 .cfg_regs = pinmux_config_regs,
1812
1813 .pinmux_data = pinmux_data,
1814 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1815 };
(deprecated) Btrfs devel tree