2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
36 #include "intel_drv.h"
40 struct intel_hdmi
*enc_to_intel_hdmi(struct drm_encoder
*encoder
)
42 return container_of(encoder
, struct intel_hdmi
, base
.base
);
45 static struct intel_hdmi
*intel_attached_hdmi(struct drm_connector
*connector
)
47 return container_of(intel_attached_encoder(connector
),
48 struct intel_hdmi
, base
);
51 void intel_dip_infoframe_csum(struct dip_infoframe
*frame
)
53 uint8_t *data
= (uint8_t *)frame
;
60 for (i
= 0; i
< frame
->len
+ DIP_HEADER_SIZE
; i
++)
63 frame
->checksum
= 0x100 - sum
;
66 static u32
g4x_infoframe_index(struct dip_infoframe
*frame
)
68 switch (frame
->type
) {
70 return VIDEO_DIP_SELECT_AVI
;
72 return VIDEO_DIP_SELECT_SPD
;
74 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
79 static u32
g4x_infoframe_enable(struct dip_infoframe
*frame
)
81 switch (frame
->type
) {
83 return VIDEO_DIP_ENABLE_AVI
;
85 return VIDEO_DIP_ENABLE_SPD
;
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
92 static u32
hsw_infoframe_enable(struct dip_infoframe
*frame
)
94 switch (frame
->type
) {
96 return VIDEO_DIP_ENABLE_AVI_HSW
;
98 return VIDEO_DIP_ENABLE_SPD_HSW
;
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
105 static u32
hsw_infoframe_data_reg(struct dip_infoframe
*frame
, enum pipe pipe
)
107 switch (frame
->type
) {
109 return HSW_TVIDEO_DIP_AVI_DATA(pipe
);
111 return HSW_TVIDEO_DIP_SPD_DATA(pipe
);
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame
->type
);
118 static void g4x_write_infoframe(struct drm_encoder
*encoder
,
119 struct dip_infoframe
*frame
)
121 uint32_t *data
= (uint32_t *)frame
;
122 struct drm_device
*dev
= encoder
->dev
;
123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
124 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
125 u32 val
= I915_READ(VIDEO_DIP_CTL
);
126 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
128 val
&= ~VIDEO_DIP_PORT_MASK
;
129 if (intel_hdmi
->sdvox_reg
== SDVOB
)
130 val
|= VIDEO_DIP_PORT_B
;
131 else if (intel_hdmi
->sdvox_reg
== SDVOC
)
132 val
|= VIDEO_DIP_PORT_C
;
136 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
137 val
|= g4x_infoframe_index(frame
);
139 val
&= ~g4x_infoframe_enable(frame
);
140 val
|= VIDEO_DIP_ENABLE
;
142 I915_WRITE(VIDEO_DIP_CTL
, val
);
144 for (i
= 0; i
< len
; i
+= 4) {
145 I915_WRITE(VIDEO_DIP_DATA
, *data
);
149 val
|= g4x_infoframe_enable(frame
);
150 val
&= ~VIDEO_DIP_FREQ_MASK
;
151 val
|= VIDEO_DIP_FREQ_VSYNC
;
153 I915_WRITE(VIDEO_DIP_CTL
, val
);
156 static void ibx_write_infoframe(struct drm_encoder
*encoder
,
157 struct dip_infoframe
*frame
)
159 uint32_t *data
= (uint32_t *)frame
;
160 struct drm_device
*dev
= encoder
->dev
;
161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
162 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
163 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
164 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
165 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
166 u32 val
= I915_READ(reg
);
168 val
&= ~VIDEO_DIP_PORT_MASK
;
169 switch (intel_hdmi
->sdvox_reg
) {
171 val
|= VIDEO_DIP_PORT_B
;
174 val
|= VIDEO_DIP_PORT_C
;
177 val
|= VIDEO_DIP_PORT_D
;
183 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
185 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
186 val
|= g4x_infoframe_index(frame
);
188 val
&= ~g4x_infoframe_enable(frame
);
189 val
|= VIDEO_DIP_ENABLE
;
191 I915_WRITE(reg
, val
);
193 for (i
= 0; i
< len
; i
+= 4) {
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
198 val
|= g4x_infoframe_enable(frame
);
199 val
&= ~VIDEO_DIP_FREQ_MASK
;
200 val
|= VIDEO_DIP_FREQ_VSYNC
;
202 I915_WRITE(reg
, val
);
205 static void cpt_write_infoframe(struct drm_encoder
*encoder
,
206 struct dip_infoframe
*frame
)
208 uint32_t *data
= (uint32_t *)frame
;
209 struct drm_device
*dev
= encoder
->dev
;
210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
211 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
212 int reg
= TVIDEO_DIP_CTL(intel_crtc
->pipe
);
213 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
214 u32 val
= I915_READ(reg
);
216 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
218 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
219 val
|= g4x_infoframe_index(frame
);
221 /* The DIP control register spec says that we need to update the AVI
222 * infoframe without clearing its enable bit */
223 if (frame
->type
== DIP_TYPE_AVI
)
224 val
|= VIDEO_DIP_ENABLE_AVI
;
226 val
&= ~g4x_infoframe_enable(frame
);
228 val
|= VIDEO_DIP_ENABLE
;
230 I915_WRITE(reg
, val
);
232 for (i
= 0; i
< len
; i
+= 4) {
233 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
237 val
|= g4x_infoframe_enable(frame
);
238 val
&= ~VIDEO_DIP_FREQ_MASK
;
239 val
|= VIDEO_DIP_FREQ_VSYNC
;
241 I915_WRITE(reg
, val
);
244 static void vlv_write_infoframe(struct drm_encoder
*encoder
,
245 struct dip_infoframe
*frame
)
247 uint32_t *data
= (uint32_t *)frame
;
248 struct drm_device
*dev
= encoder
->dev
;
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
250 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
251 int reg
= VLV_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
252 unsigned i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
253 u32 val
= I915_READ(reg
);
255 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
257 val
&= ~(VIDEO_DIP_SELECT_MASK
| 0xf); /* clear DIP data offset */
258 val
|= g4x_infoframe_index(frame
);
260 val
&= ~g4x_infoframe_enable(frame
);
261 val
|= VIDEO_DIP_ENABLE
;
263 I915_WRITE(reg
, val
);
265 for (i
= 0; i
< len
; i
+= 4) {
266 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc
->pipe
), *data
);
270 val
|= g4x_infoframe_enable(frame
);
271 val
&= ~VIDEO_DIP_FREQ_MASK
;
272 val
|= VIDEO_DIP_FREQ_VSYNC
;
274 I915_WRITE(reg
, val
);
277 static void hsw_write_infoframe(struct drm_encoder
*encoder
,
278 struct dip_infoframe
*frame
)
280 uint32_t *data
= (uint32_t *)frame
;
281 struct drm_device
*dev
= encoder
->dev
;
282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
283 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
284 u32 ctl_reg
= HSW_TVIDEO_DIP_CTL(intel_crtc
->pipe
);
285 u32 data_reg
= hsw_infoframe_data_reg(frame
, intel_crtc
->pipe
);
286 unsigned int i
, len
= DIP_HEADER_SIZE
+ frame
->len
;
287 u32 val
= I915_READ(ctl_reg
);
292 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
294 val
&= ~hsw_infoframe_enable(frame
);
295 I915_WRITE(ctl_reg
, val
);
297 for (i
= 0; i
< len
; i
+= 4) {
298 I915_WRITE(data_reg
+ i
, *data
);
302 val
|= hsw_infoframe_enable(frame
);
303 I915_WRITE(ctl_reg
, val
);
306 static void intel_set_infoframe(struct drm_encoder
*encoder
,
307 struct dip_infoframe
*frame
)
309 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
311 if (!intel_hdmi
->has_hdmi_sink
)
314 intel_dip_infoframe_csum(frame
);
315 intel_hdmi
->write_infoframe(encoder
, frame
);
318 void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
,
319 struct drm_display_mode
*adjusted_mode
)
321 struct dip_infoframe avi_if
= {
322 .type
= DIP_TYPE_AVI
,
323 .ver
= DIP_VERSION_AVI
,
327 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
328 avi_if
.body
.avi
.YQ_CN_PR
|= DIP_AVI_PR_2
;
330 intel_set_infoframe(encoder
, &avi_if
);
333 void intel_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
335 struct dip_infoframe spd_if
;
337 memset(&spd_if
, 0, sizeof(spd_if
));
338 spd_if
.type
= DIP_TYPE_SPD
;
339 spd_if
.ver
= DIP_VERSION_SPD
;
340 spd_if
.len
= DIP_LEN_SPD
;
341 strcpy(spd_if
.body
.spd
.vn
, "Intel");
342 strcpy(spd_if
.body
.spd
.pd
, "Integrated gfx");
343 spd_if
.body
.spd
.sdi
= DIP_SPD_PC
;
345 intel_set_infoframe(encoder
, &spd_if
);
348 static void intel_hdmi_mode_set(struct drm_encoder
*encoder
,
349 struct drm_display_mode
*mode
,
350 struct drm_display_mode
*adjusted_mode
)
352 struct drm_device
*dev
= encoder
->dev
;
353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
354 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
355 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
358 sdvox
= SDVO_ENCODING_HDMI
| SDVO_BORDER_ENABLE
;
359 if (!HAS_PCH_SPLIT(dev
))
360 sdvox
|= intel_hdmi
->color_range
;
361 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
362 sdvox
|= SDVO_VSYNC_ACTIVE_HIGH
;
363 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
364 sdvox
|= SDVO_HSYNC_ACTIVE_HIGH
;
366 if (intel_crtc
->bpp
> 24)
367 sdvox
|= COLOR_FORMAT_12bpc
;
369 sdvox
|= COLOR_FORMAT_8bpc
;
371 /* Required on CPT */
372 if (intel_hdmi
->has_hdmi_sink
&& HAS_PCH_CPT(dev
))
373 sdvox
|= HDMI_MODE_SELECT
;
375 if (intel_hdmi
->has_audio
) {
376 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
377 pipe_name(intel_crtc
->pipe
));
378 sdvox
|= SDVO_AUDIO_ENABLE
;
379 sdvox
|= SDVO_NULL_PACKETS_DURING_VSYNC
;
380 intel_write_eld(encoder
, adjusted_mode
);
383 if (HAS_PCH_CPT(dev
))
384 sdvox
|= PORT_TRANS_SEL_CPT(intel_crtc
->pipe
);
385 else if (intel_crtc
->pipe
== 1)
386 sdvox
|= SDVO_PIPE_B_SELECT
;
388 I915_WRITE(intel_hdmi
->sdvox_reg
, sdvox
);
389 POSTING_READ(intel_hdmi
->sdvox_reg
);
391 intel_hdmi_set_avi_infoframe(encoder
, adjusted_mode
);
392 intel_hdmi_set_spd_infoframe(encoder
);
395 static void intel_hdmi_dpms(struct drm_encoder
*encoder
, int mode
)
397 struct drm_device
*dev
= encoder
->dev
;
398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
399 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
401 u32 enable_bits
= SDVO_ENABLE
;
403 if (intel_hdmi
->has_audio
)
404 enable_bits
|= SDVO_AUDIO_ENABLE
;
406 temp
= I915_READ(intel_hdmi
->sdvox_reg
);
408 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
409 * we do this anyway which shows more stable in testing.
411 if (HAS_PCH_SPLIT(dev
)) {
412 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
& ~SDVO_ENABLE
);
413 POSTING_READ(intel_hdmi
->sdvox_reg
);
416 if (mode
!= DRM_MODE_DPMS_ON
) {
417 temp
&= ~enable_bits
;
422 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
423 POSTING_READ(intel_hdmi
->sdvox_reg
);
425 /* HW workaround, need to write this twice for issue that may result
426 * in first write getting masked.
428 if (HAS_PCH_SPLIT(dev
)) {
429 I915_WRITE(intel_hdmi
->sdvox_reg
, temp
);
430 POSTING_READ(intel_hdmi
->sdvox_reg
);
434 static int intel_hdmi_mode_valid(struct drm_connector
*connector
,
435 struct drm_display_mode
*mode
)
437 if (mode
->clock
> 165000)
438 return MODE_CLOCK_HIGH
;
439 if (mode
->clock
< 20000)
440 return MODE_CLOCK_LOW
;
442 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
443 return MODE_NO_DBLESCAN
;
448 static bool intel_hdmi_mode_fixup(struct drm_encoder
*encoder
,
449 struct drm_display_mode
*mode
,
450 struct drm_display_mode
*adjusted_mode
)
455 static enum drm_connector_status
456 intel_hdmi_detect(struct drm_connector
*connector
, bool force
)
458 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
459 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
461 enum drm_connector_status status
= connector_status_disconnected
;
463 intel_hdmi
->has_hdmi_sink
= false;
464 intel_hdmi
->has_audio
= false;
465 edid
= drm_get_edid(connector
,
466 intel_gmbus_get_adapter(dev_priv
,
467 intel_hdmi
->ddc_bus
));
470 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
471 status
= connector_status_connected
;
472 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_OFF_DVI
)
473 intel_hdmi
->has_hdmi_sink
=
474 drm_detect_hdmi_monitor(edid
);
475 intel_hdmi
->has_audio
= drm_detect_monitor_audio(edid
);
477 connector
->display_info
.raw_edid
= NULL
;
481 if (status
== connector_status_connected
) {
482 if (intel_hdmi
->force_audio
!= HDMI_AUDIO_AUTO
)
483 intel_hdmi
->has_audio
=
484 (intel_hdmi
->force_audio
== HDMI_AUDIO_ON
);
490 static int intel_hdmi_get_modes(struct drm_connector
*connector
)
492 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
493 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
495 /* We should parse the EDID data and find out if it's an HDMI sink so
496 * we can send audio to it.
499 return intel_ddc_get_modes(connector
,
500 intel_gmbus_get_adapter(dev_priv
,
501 intel_hdmi
->ddc_bus
));
505 intel_hdmi_detect_audio(struct drm_connector
*connector
)
507 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
508 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
510 bool has_audio
= false;
512 edid
= drm_get_edid(connector
,
513 intel_gmbus_get_adapter(dev_priv
,
514 intel_hdmi
->ddc_bus
));
516 if (edid
->input
& DRM_EDID_INPUT_DIGITAL
)
517 has_audio
= drm_detect_monitor_audio(edid
);
519 connector
->display_info
.raw_edid
= NULL
;
527 intel_hdmi_set_property(struct drm_connector
*connector
,
528 struct drm_property
*property
,
531 struct intel_hdmi
*intel_hdmi
= intel_attached_hdmi(connector
);
532 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
535 ret
= drm_connector_property_set_value(connector
, property
, val
);
539 if (property
== dev_priv
->force_audio_property
) {
540 enum hdmi_force_audio i
= val
;
543 if (i
== intel_hdmi
->force_audio
)
546 intel_hdmi
->force_audio
= i
;
548 if (i
== HDMI_AUDIO_AUTO
)
549 has_audio
= intel_hdmi_detect_audio(connector
);
551 has_audio
= (i
== HDMI_AUDIO_ON
);
553 if (i
== HDMI_AUDIO_OFF_DVI
)
554 intel_hdmi
->has_hdmi_sink
= 0;
556 intel_hdmi
->has_audio
= has_audio
;
560 if (property
== dev_priv
->broadcast_rgb_property
) {
561 if (val
== !!intel_hdmi
->color_range
)
564 intel_hdmi
->color_range
= val
? SDVO_COLOR_RANGE_16_235
: 0;
571 if (intel_hdmi
->base
.base
.crtc
) {
572 struct drm_crtc
*crtc
= intel_hdmi
->base
.base
.crtc
;
573 drm_crtc_helper_set_mode(crtc
, &crtc
->mode
,
581 static void intel_hdmi_destroy(struct drm_connector
*connector
)
583 drm_sysfs_connector_remove(connector
);
584 drm_connector_cleanup(connector
);
588 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw
= {
589 .dpms
= intel_ddi_dpms
,
590 .mode_fixup
= intel_hdmi_mode_fixup
,
591 .prepare
= intel_encoder_prepare
,
592 .mode_set
= intel_ddi_mode_set
,
593 .commit
= intel_encoder_commit
,
596 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs
= {
597 .dpms
= intel_hdmi_dpms
,
598 .mode_fixup
= intel_hdmi_mode_fixup
,
599 .prepare
= intel_encoder_prepare
,
600 .mode_set
= intel_hdmi_mode_set
,
601 .commit
= intel_encoder_commit
,
604 static const struct drm_connector_funcs intel_hdmi_connector_funcs
= {
605 .dpms
= drm_helper_connector_dpms
,
606 .detect
= intel_hdmi_detect
,
607 .fill_modes
= drm_helper_probe_single_connector_modes
,
608 .set_property
= intel_hdmi_set_property
,
609 .destroy
= intel_hdmi_destroy
,
612 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
= {
613 .get_modes
= intel_hdmi_get_modes
,
614 .mode_valid
= intel_hdmi_mode_valid
,
615 .best_encoder
= intel_best_encoder
,
618 static const struct drm_encoder_funcs intel_hdmi_enc_funcs
= {
619 .destroy
= intel_encoder_destroy
,
623 intel_hdmi_add_properties(struct intel_hdmi
*intel_hdmi
, struct drm_connector
*connector
)
625 intel_attach_force_audio_property(connector
);
626 intel_attach_broadcast_rgb_property(connector
);
629 void intel_hdmi_init(struct drm_device
*dev
, int sdvox_reg
)
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
632 struct drm_connector
*connector
;
633 struct intel_encoder
*intel_encoder
;
634 struct intel_connector
*intel_connector
;
635 struct intel_hdmi
*intel_hdmi
;
638 intel_hdmi
= kzalloc(sizeof(struct intel_hdmi
), GFP_KERNEL
);
642 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
643 if (!intel_connector
) {
648 intel_encoder
= &intel_hdmi
->base
;
649 drm_encoder_init(dev
, &intel_encoder
->base
, &intel_hdmi_enc_funcs
,
650 DRM_MODE_ENCODER_TMDS
);
652 connector
= &intel_connector
->base
;
653 drm_connector_init(dev
, connector
, &intel_hdmi_connector_funcs
,
654 DRM_MODE_CONNECTOR_HDMIA
);
655 drm_connector_helper_add(connector
, &intel_hdmi_connector_helper_funcs
);
657 intel_encoder
->type
= INTEL_OUTPUT_HDMI
;
659 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
660 connector
->interlace_allowed
= 1;
661 connector
->doublescan_allowed
= 0;
662 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
664 /* Set up the DDC bus. */
665 if (sdvox_reg
== SDVOB
) {
666 intel_encoder
->clone_mask
= (1 << INTEL_HDMIB_CLONE_BIT
);
667 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
668 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
669 } else if (sdvox_reg
== SDVOC
) {
670 intel_encoder
->clone_mask
= (1 << INTEL_HDMIC_CLONE_BIT
);
671 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
672 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
673 } else if (sdvox_reg
== HDMIB
) {
674 intel_encoder
->clone_mask
= (1 << INTEL_HDMID_CLONE_BIT
);
675 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
676 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
677 } else if (sdvox_reg
== HDMIC
) {
678 intel_encoder
->clone_mask
= (1 << INTEL_HDMIE_CLONE_BIT
);
679 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
680 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
681 } else if (sdvox_reg
== HDMID
) {
682 intel_encoder
->clone_mask
= (1 << INTEL_HDMIF_CLONE_BIT
);
683 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
684 dev_priv
->hotplug_supported_mask
|= HDMID_HOTPLUG_INT_STATUS
;
685 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_B
)) {
686 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
687 intel_encoder
->clone_mask
= (1 << INTEL_HDMIB_CLONE_BIT
);
688 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPB
;
689 intel_hdmi
->ddi_port
= PORT_B
;
690 dev_priv
->hotplug_supported_mask
|= HDMIB_HOTPLUG_INT_STATUS
;
691 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_C
)) {
692 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
693 intel_encoder
->clone_mask
= (1 << INTEL_HDMIC_CLONE_BIT
);
694 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPC
;
695 intel_hdmi
->ddi_port
= PORT_C
;
696 dev_priv
->hotplug_supported_mask
|= HDMIC_HOTPLUG_INT_STATUS
;
697 } else if (sdvox_reg
== DDI_BUF_CTL(PORT_D
)) {
698 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
699 intel_encoder
->clone_mask
= (1 << INTEL_HDMID_CLONE_BIT
);
700 intel_hdmi
->ddc_bus
= GMBUS_PORT_DPD
;
701 intel_hdmi
->ddi_port
= PORT_D
;
702 dev_priv
->hotplug_supported_mask
|= HDMID_HOTPLUG_INT_STATUS
;
704 /* If we got an unknown sdvox_reg, things are pretty much broken
705 * in a way that we should let the kernel know about it */
709 intel_hdmi
->sdvox_reg
= sdvox_reg
;
711 if (!HAS_PCH_SPLIT(dev
)) {
712 intel_hdmi
->write_infoframe
= g4x_write_infoframe
;
713 I915_WRITE(VIDEO_DIP_CTL
, 0);
714 } else if (IS_VALLEYVIEW(dev
)) {
715 intel_hdmi
->write_infoframe
= vlv_write_infoframe
;
717 I915_WRITE(VLV_TVIDEO_DIP_CTL(i
), 0);
718 } else if (IS_HASWELL(dev
)) {
719 /* FIXME: Haswell has a new set of DIP frame registers, but we are
720 * just doing the minimal required for HDMI to work at this stage.
722 intel_hdmi
->write_infoframe
= hsw_write_infoframe
;
724 I915_WRITE(HSW_TVIDEO_DIP_CTL(i
), 0);
725 } else if (HAS_PCH_IBX(dev
)) {
726 intel_hdmi
->write_infoframe
= ibx_write_infoframe
;
728 I915_WRITE(TVIDEO_DIP_CTL(i
), 0);
730 intel_hdmi
->write_infoframe
= cpt_write_infoframe
;
732 I915_WRITE(TVIDEO_DIP_CTL(i
), 0);
736 drm_encoder_helper_add(&intel_encoder
->base
, &intel_hdmi_helper_funcs_hsw
);
738 drm_encoder_helper_add(&intel_encoder
->base
, &intel_hdmi_helper_funcs
);
740 intel_hdmi_add_properties(intel_hdmi
, connector
);
742 intel_connector_attach_encoder(intel_connector
, intel_encoder
);
743 drm_sysfs_connector_add(connector
);
745 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
746 * 0xd. Failure to do so will result in spurious interrupts being
747 * generated on the port when a cable is not attached.
749 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
750 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
751 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);