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drm/i915: Silence sparse over duplicate members in static initializer
[linux-2.6/btrfs-unstable.git] / drivers / serial / 8250_pci.c
blob746a44621d9157e3a50448ce60e577d66dfc1246
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71 }
72
73 static int
74 setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76 {
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap_nocache(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106 }
107
108 /*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_port *port, int idx)
114 {
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132 }
133
134 /*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138 static int
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_port *port, int idx)
141 {
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153 }
154
155 /*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162 static int pci_hp_diva_init(struct pci_dev *dev)
163 {
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186 }
187
188 /*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192 static int
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
196 {
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
217 return setup_port(priv, port, bar, offset, board->reg_shift);
218 }
219
220 /*
221 * Added for EKF Intel i960 serial boards
222 */
223 static int pci_inteli960ni_init(struct pci_dev *dev)
224 {
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237 }
238
239 /*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
245 static int pci_plx9050_init(struct pci_dev *dev)
246 {
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258 irq_config = 0x43;
259
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 /*
272 * enable/disable interrupts
273 */
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286 }
287
288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289 {
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308 }
309
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
312
313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314 {
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334 }
335
336
337 /* MITE registers */
338 #define MITE_IOWBSR1 0xc4
339 #define MITE_IOWCR1 0xf4
340 #define MITE_LCIMR1 0x08
341 #define MITE_LCIMR2 0x10
342
343 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346 {
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365 }
366
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368 static int
369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_port *port, int idx)
371 {
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386 }
387
388 /*
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
393 */
394
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
397
398 static int sbs_init(struct pci_dev *dev)
399 {
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416 }
417
418 /*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422 static void __devexit sbs_exit(struct pci_dev *dev)
423 {
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
429 writeb(0, p + OCT_REG_CR_OFF);
430 iounmap(p);
431 }
432
433 /*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
445 *
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
463 static int pci_siig10x_init(struct pci_dev *dev)
464 {
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488 }
489
490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
493 static int pci_siig20x_init(struct pci_dev *dev)
494 {
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508 }
509
510 static int pci_siig_init(struct pci_dev *dev)
511 {
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521 }
522
523 static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_port *port, int idx)
526 {
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535 }
536
537 /*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
542 static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544 };
545
546 static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552 };
553
554 static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559 };
560
561 static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564 };
565
566 static const struct timedia_struct {
567 int num;
568 const unsigned short *ids;
569 } timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
574 };
575
576 static int pci_timedia_init(struct pci_dev *dev)
577 {
578 const unsigned short *ids;
579 int i, j;
580
581 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
582 ids = timedia_data[i].ids;
583 for (j = 0; ids[j]; j++)
584 if (dev->subsystem_device == ids[j])
585 return timedia_data[i].num;
586 }
587 return 0;
588 }
589
590 /*
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
593 */
594 static int
595 pci_timedia_setup(struct serial_private *priv,
596 const struct pciserial_board *board,
597 struct uart_port *port, int idx)
598 {
599 unsigned int bar = 0, offset = board->first_offset;
600
601 switch (idx) {
602 case 0:
603 bar = 0;
604 break;
605 case 1:
606 offset = board->uart_offset;
607 bar = 0;
608 break;
609 case 2:
610 bar = 1;
611 break;
612 case 3:
613 offset = board->uart_offset;
614 /* FALLTHROUGH */
615 case 4: /* BAR 2 */
616 case 5: /* BAR 3 */
617 case 6: /* BAR 4 */
618 case 7: /* BAR 5 */
619 bar = idx - 2;
620 }
621
622 return setup_port(priv, port, bar, offset, board->reg_shift);
623 }
624
625 /*
626 * Some Titan cards are also a little weird
627 */
628 static int
629 titan_400l_800l_setup(struct serial_private *priv,
630 const struct pciserial_board *board,
631 struct uart_port *port, int idx)
632 {
633 unsigned int bar, offset = board->first_offset;
634
635 switch (idx) {
636 case 0:
637 bar = 1;
638 break;
639 case 1:
640 bar = 2;
641 break;
642 default:
643 bar = 4;
644 offset = (idx - 2) * board->uart_offset;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 static int pci_xircom_init(struct pci_dev *dev)
651 {
652 msleep(100);
653 return 0;
654 }
655
656 static int pci_ni8420_init(struct pci_dev *dev)
657 {
658 void __iomem *p;
659 unsigned long base, len;
660 unsigned int bar = 0;
661
662 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
663 moan_device("no memory in bar", dev);
664 return 0;
665 }
666
667 base = pci_resource_start(dev, bar);
668 len = pci_resource_len(dev, bar);
669 p = ioremap_nocache(base, len);
670 if (p == NULL)
671 return -ENOMEM;
672
673 /* Enable CPU Interrupt */
674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
675 p + NI8420_INT_ENABLE_REG);
676
677 iounmap(p);
678 return 0;
679 }
680
681 #define MITE_IOWBSR1_WSIZE 0xa
682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
683 #define MITE_IOWBSR1_WENAB (1 << 7)
684 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
687
688 static int pci_ni8430_init(struct pci_dev *dev)
689 {
690 void __iomem *p;
691 unsigned long base, len;
692 u32 device_window;
693 unsigned int bar = 0;
694
695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
696 moan_device("no memory in bar", dev);
697 return 0;
698 }
699
700 base = pci_resource_start(dev, bar);
701 len = pci_resource_len(dev, bar);
702 p = ioremap_nocache(base, len);
703 if (p == NULL)
704 return -ENOMEM;
705
706 /* Set device window address and size in BAR0 */
707 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
709 writel(device_window, p + MITE_IOWBSR1);
710
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
713 p + MITE_IOWCR1);
714
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
717
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
720
721 iounmap(p);
722 return 0;
723 }
724
725 /* UART Port Control Register */
726 #define NI8430_PORTCON 0x0f
727 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
728
729 static int
730 pci_ni8430_setup(struct serial_private *priv,
731 const struct pciserial_board *board,
732 struct uart_port *port, int idx)
733 {
734 void __iomem *p;
735 unsigned long base, len;
736 unsigned int bar, offset = board->first_offset;
737
738 if (idx >= board->num_ports)
739 return 1;
740
741 bar = FL_GET_BASE(board->flags);
742 offset += idx * board->uart_offset;
743
744 base = pci_resource_start(priv->dev, bar);
745 len = pci_resource_len(priv->dev, bar);
746 p = ioremap_nocache(base, len);
747
748 /* enable the transciever */
749 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
750 p + offset + NI8430_PORTCON);
751
752 iounmap(p);
753
754 return setup_port(priv, port, bar, offset, board->reg_shift);
755 }
756
757
758 static int pci_netmos_init(struct pci_dev *dev)
759 {
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial = dev->subsystem_device & 0xf;
762
763 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
764 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
765 return 0;
766 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
767 dev->subsystem_device == 0x0299)
768 return 0;
769
770 if (num_serial == 0)
771 return -ENODEV;
772 return num_serial;
773 }
774
775 /*
776 * These chips are available with optionally one parallel port and up to
777 * two serial ports. Unfortunately they all have the same product id.
778 *
779 * Basic configuration is done over a region of 32 I/O ports. The base
780 * ioport is called INTA or INTC, depending on docs/other drivers.
781 *
782 * The region of the 32 I/O ports is configured in POSIO0R...
783 */
784
785 /* registers */
786 #define ITE_887x_MISCR 0x9c
787 #define ITE_887x_INTCBAR 0x78
788 #define ITE_887x_UARTBAR 0x7c
789 #define ITE_887x_PS0BAR 0x10
790 #define ITE_887x_POSIO0 0x60
791
792 /* I/O space size */
793 #define ITE_887x_IOSIZE 32
794 /* I/O space size (bits 26-24; 8 bytes = 011b) */
795 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
796 /* I/O space size (bits 26-24; 32 bytes = 101b) */
797 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
798 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
799 #define ITE_887x_POSIO_SPEED (3 << 29)
800 /* enable IO_Space bit */
801 #define ITE_887x_POSIO_ENABLE (1 << 31)
802
803 static int pci_ite887x_init(struct pci_dev *dev)
804 {
805 /* inta_addr are the configuration addresses of the ITE */
806 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
807 0x200, 0x280, 0 };
808 int ret, i, type;
809 struct resource *iobase = NULL;
810 u32 miscr, uartbar, ioport;
811
812 /* search for the base-ioport */
813 i = 0;
814 while (inta_addr[i] && iobase == NULL) {
815 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
816 "ite887x");
817 if (iobase != NULL) {
818 /* write POSIO0R - speed | size | ioport */
819 pci_write_config_dword(dev, ITE_887x_POSIO0,
820 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
821 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
822 /* write INTCBAR - ioport */
823 pci_write_config_dword(dev, ITE_887x_INTCBAR,
824 inta_addr[i]);
825 ret = inb(inta_addr[i]);
826 if (ret != 0xff) {
827 /* ioport connected */
828 break;
829 }
830 release_region(iobase->start, ITE_887x_IOSIZE);
831 iobase = NULL;
832 }
833 i++;
834 }
835
836 if (!inta_addr[i]) {
837 printk(KERN_ERR "ite887x: could not find iobase\n");
838 return -ENODEV;
839 }
840
841 /* start of undocumented type checking (see parport_pc.c) */
842 type = inb(iobase->start + 0x18) & 0x0f;
843
844 switch (type) {
845 case 0x2: /* ITE8871 (1P) */
846 case 0xa: /* ITE8875 (1P) */
847 ret = 0;
848 break;
849 case 0xe: /* ITE8872 (2S1P) */
850 ret = 2;
851 break;
852 case 0x6: /* ITE8873 (1S) */
853 ret = 1;
854 break;
855 case 0x8: /* ITE8874 (2S) */
856 ret = 2;
857 break;
858 default:
859 moan_device("Unknown ITE887x", dev);
860 ret = -ENODEV;
861 }
862
863 /* configure all serial ports */
864 for (i = 0; i < ret; i++) {
865 /* read the I/O port from the device */
866 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
867 &ioport);
868 ioport &= 0x0000FF00; /* the actual base address */
869 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
870 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
871 ITE_887x_POSIO_IOSIZE_8 | ioport);
872
873 /* write the ioport to the UARTBAR */
874 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
875 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
876 uartbar |= (ioport << (16 * i)); /* set the ioport */
877 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
878
879 /* get current config */
880 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
881 /* disable interrupts (UARTx_Routing[3:0]) */
882 miscr &= ~(0xf << (12 - 4 * i));
883 /* activate the UART (UARTx_En) */
884 miscr |= 1 << (23 - i);
885 /* write new config with activated UART */
886 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
887 }
888
889 if (ret <= 0) {
890 /* the device has no UARTs if we get here */
891 release_region(iobase->start, ITE_887x_IOSIZE);
892 }
893
894 return ret;
895 }
896
897 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
898 {
899 u32 ioport;
900 /* the ioport is bit 0-15 in POSIO0R */
901 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
902 ioport &= 0xffff;
903 release_region(ioport, ITE_887x_IOSIZE);
904 }
905
906 /*
907 * Oxford Semiconductor Inc.
908 * Check that device is part of the Tornado range of devices, then determine
909 * the number of ports available on the device.
910 */
911 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
912 {
913 u8 __iomem *p;
914 unsigned long deviceID;
915 unsigned int number_uarts = 0;
916
917 /* OxSemi Tornado devices are all 0xCxxx */
918 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
919 (dev->device & 0xF000) != 0xC000)
920 return 0;
921
922 p = pci_iomap(dev, 0, 5);
923 if (p == NULL)
924 return -ENOMEM;
925
926 deviceID = ioread32(p);
927 /* Tornado device */
928 if (deviceID == 0x07000200) {
929 number_uarts = ioread8(p + 4);
930 printk(KERN_DEBUG
931 "%d ports detected on Oxford PCI Express device\n",
932 number_uarts);
933 }
934 pci_iounmap(dev, p);
935 return number_uarts;
936 }
937
938 static int
939 pci_default_setup(struct serial_private *priv,
940 const struct pciserial_board *board,
941 struct uart_port *port, int idx)
942 {
943 unsigned int bar, offset = board->first_offset, maxnr;
944
945 bar = FL_GET_BASE(board->flags);
946 if (board->flags & FL_BASE_BARS)
947 bar += idx;
948 else
949 offset += idx * board->uart_offset;
950
951 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
952 (board->reg_shift + 3);
953
954 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
955 return 1;
956
957 return setup_port(priv, port, bar, offset, board->reg_shift);
958 }
959
960 static int skip_tx_en_setup(struct serial_private *priv,
961 const struct pciserial_board *board,
962 struct uart_port *port, int idx)
963 {
964 port->flags |= UPF_NO_TXEN_TEST;
965 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
966 "[%04x:%04x] subsystem [%04x:%04x]\n",
967 priv->dev->vendor,
968 priv->dev->device,
969 priv->dev->subsystem_vendor,
970 priv->dev->subsystem_device);
971
972 return pci_default_setup(priv, board, port, idx);
973 }
974
975 /* This should be in linux/pci_ids.h */
976 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
977 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
978 #define PCI_DEVICE_ID_OCTPRO 0x0001
979 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
980 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
981 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
982 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
983 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
984 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
985 #define PCI_DEVICE_ID_TITAN_200I 0x8028
986 #define PCI_DEVICE_ID_TITAN_400I 0x8048
987 #define PCI_DEVICE_ID_TITAN_800I 0x8088
988 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
989 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
990 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
991 #define PCI_DEVICE_ID_TITAN_100E 0xA010
992 #define PCI_DEVICE_ID_TITAN_200E 0xA012
993 #define PCI_DEVICE_ID_TITAN_400E 0xA013
994 #define PCI_DEVICE_ID_TITAN_800E 0xA014
995 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
996 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
997
998 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
999 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1000
1001 /*
1002 * Master list of serial port init/setup/exit quirks.
1003 * This does not describe the general nature of the port.
1004 * (ie, baud base, number and location of ports, etc)
1005 *
1006 * This list is ordered alphabetically by vendor then device.
1007 * Specific entries must come before more generic entries.
1008 */
1009 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1010 /*
1011 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1012 */
1013 {
1014 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1015 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1016 .subvendor = PCI_ANY_ID,
1017 .subdevice = PCI_ANY_ID,
1018 .setup = addidata_apci7800_setup,
1019 },
1020 /*
1021 * AFAVLAB cards - these may be called via parport_serial
1022 * It is not clear whether this applies to all products.
1023 */
1024 {
1025 .vendor = PCI_VENDOR_ID_AFAVLAB,
1026 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .setup = afavlab_setup,
1030 },
1031 /*
1032 * HP Diva
1033 */
1034 {
1035 .vendor = PCI_VENDOR_ID_HP,
1036 .device = PCI_DEVICE_ID_HP_DIVA,
1037 .subvendor = PCI_ANY_ID,
1038 .subdevice = PCI_ANY_ID,
1039 .init = pci_hp_diva_init,
1040 .setup = pci_hp_diva_setup,
1041 },
1042 /*
1043 * Intel
1044 */
1045 {
1046 .vendor = PCI_VENDOR_ID_INTEL,
1047 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1048 .subvendor = 0xe4bf,
1049 .subdevice = PCI_ANY_ID,
1050 .init = pci_inteli960ni_init,
1051 .setup = pci_default_setup,
1052 },
1053 {
1054 .vendor = PCI_VENDOR_ID_INTEL,
1055 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1056 .subvendor = PCI_ANY_ID,
1057 .subdevice = PCI_ANY_ID,
1058 .setup = skip_tx_en_setup,
1059 },
1060 {
1061 .vendor = PCI_VENDOR_ID_INTEL,
1062 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1063 .subvendor = PCI_ANY_ID,
1064 .subdevice = PCI_ANY_ID,
1065 .setup = skip_tx_en_setup,
1066 },
1067 {
1068 .vendor = PCI_VENDOR_ID_INTEL,
1069 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1070 .subvendor = PCI_ANY_ID,
1071 .subdevice = PCI_ANY_ID,
1072 .setup = skip_tx_en_setup,
1073 },
1074 /*
1075 * ITE
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_ITE,
1079 .device = PCI_DEVICE_ID_ITE_8872,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ite887x_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ite887x_exit),
1085 },
1086 /*
1087 * National Instruments
1088 */
1089 {
1090 .vendor = PCI_VENDOR_ID_NI,
1091 .device = PCI_DEVICE_ID_NI_PCI23216,
1092 .subvendor = PCI_ANY_ID,
1093 .subdevice = PCI_ANY_ID,
1094 .init = pci_ni8420_init,
1095 .setup = pci_default_setup,
1096 .exit = __devexit_p(pci_ni8420_exit),
1097 },
1098 {
1099 .vendor = PCI_VENDOR_ID_NI,
1100 .device = PCI_DEVICE_ID_NI_PCI2328,
1101 .subvendor = PCI_ANY_ID,
1102 .subdevice = PCI_ANY_ID,
1103 .init = pci_ni8420_init,
1104 .setup = pci_default_setup,
1105 .exit = __devexit_p(pci_ni8420_exit),
1106 },
1107 {
1108 .vendor = PCI_VENDOR_ID_NI,
1109 .device = PCI_DEVICE_ID_NI_PCI2324,
1110 .subvendor = PCI_ANY_ID,
1111 .subdevice = PCI_ANY_ID,
1112 .init = pci_ni8420_init,
1113 .setup = pci_default_setup,
1114 .exit = __devexit_p(pci_ni8420_exit),
1115 },
1116 {
1117 .vendor = PCI_VENDOR_ID_NI,
1118 .device = PCI_DEVICE_ID_NI_PCI2322,
1119 .subvendor = PCI_ANY_ID,
1120 .subdevice = PCI_ANY_ID,
1121 .init = pci_ni8420_init,
1122 .setup = pci_default_setup,
1123 .exit = __devexit_p(pci_ni8420_exit),
1124 },
1125 {
1126 .vendor = PCI_VENDOR_ID_NI,
1127 .device = PCI_DEVICE_ID_NI_PCI2324I,
1128 .subvendor = PCI_ANY_ID,
1129 .subdevice = PCI_ANY_ID,
1130 .init = pci_ni8420_init,
1131 .setup = pci_default_setup,
1132 .exit = __devexit_p(pci_ni8420_exit),
1133 },
1134 {
1135 .vendor = PCI_VENDOR_ID_NI,
1136 .device = PCI_DEVICE_ID_NI_PCI2322I,
1137 .subvendor = PCI_ANY_ID,
1138 .subdevice = PCI_ANY_ID,
1139 .init = pci_ni8420_init,
1140 .setup = pci_default_setup,
1141 .exit = __devexit_p(pci_ni8420_exit),
1142 },
1143 {
1144 .vendor = PCI_VENDOR_ID_NI,
1145 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1146 .subvendor = PCI_ANY_ID,
1147 .subdevice = PCI_ANY_ID,
1148 .init = pci_ni8420_init,
1149 .setup = pci_default_setup,
1150 .exit = __devexit_p(pci_ni8420_exit),
1151 },
1152 {
1153 .vendor = PCI_VENDOR_ID_NI,
1154 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1155 .subvendor = PCI_ANY_ID,
1156 .subdevice = PCI_ANY_ID,
1157 .init = pci_ni8420_init,
1158 .setup = pci_default_setup,
1159 .exit = __devexit_p(pci_ni8420_exit),
1160 },
1161 {
1162 .vendor = PCI_VENDOR_ID_NI,
1163 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1164 .subvendor = PCI_ANY_ID,
1165 .subdevice = PCI_ANY_ID,
1166 .init = pci_ni8420_init,
1167 .setup = pci_default_setup,
1168 .exit = __devexit_p(pci_ni8420_exit),
1169 },
1170 {
1171 .vendor = PCI_VENDOR_ID_NI,
1172 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1173 .subvendor = PCI_ANY_ID,
1174 .subdevice = PCI_ANY_ID,
1175 .init = pci_ni8420_init,
1176 .setup = pci_default_setup,
1177 .exit = __devexit_p(pci_ni8420_exit),
1178 },
1179 {
1180 .vendor = PCI_VENDOR_ID_NI,
1181 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1182 .subvendor = PCI_ANY_ID,
1183 .subdevice = PCI_ANY_ID,
1184 .init = pci_ni8420_init,
1185 .setup = pci_default_setup,
1186 .exit = __devexit_p(pci_ni8420_exit),
1187 },
1188 {
1189 .vendor = PCI_VENDOR_ID_NI,
1190 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1191 .subvendor = PCI_ANY_ID,
1192 .subdevice = PCI_ANY_ID,
1193 .init = pci_ni8420_init,
1194 .setup = pci_default_setup,
1195 .exit = __devexit_p(pci_ni8420_exit),
1196 },
1197 {
1198 .vendor = PCI_VENDOR_ID_NI,
1199 .device = PCI_ANY_ID,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_ni8430_init,
1203 .setup = pci_ni8430_setup,
1204 .exit = __devexit_p(pci_ni8430_exit),
1205 },
1206 /*
1207 * Panacom
1208 */
1209 {
1210 .vendor = PCI_VENDOR_ID_PANACOM,
1211 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1212 .subvendor = PCI_ANY_ID,
1213 .subdevice = PCI_ANY_ID,
1214 .init = pci_plx9050_init,
1215 .setup = pci_default_setup,
1216 .exit = __devexit_p(pci_plx9050_exit),
1217 },
1218 {
1219 .vendor = PCI_VENDOR_ID_PANACOM,
1220 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1221 .subvendor = PCI_ANY_ID,
1222 .subdevice = PCI_ANY_ID,
1223 .init = pci_plx9050_init,
1224 .setup = pci_default_setup,
1225 .exit = __devexit_p(pci_plx9050_exit),
1226 },
1227 /*
1228 * PLX
1229 */
1230 {
1231 .vendor = PCI_VENDOR_ID_PLX,
1232 .device = PCI_DEVICE_ID_PLX_9030,
1233 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1234 .subdevice = PCI_ANY_ID,
1235 .setup = pci_default_setup,
1236 },
1237 {
1238 .vendor = PCI_VENDOR_ID_PLX,
1239 .device = PCI_DEVICE_ID_PLX_9050,
1240 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1241 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1242 .init = pci_plx9050_init,
1243 .setup = pci_default_setup,
1244 .exit = __devexit_p(pci_plx9050_exit),
1245 },
1246 {
1247 .vendor = PCI_VENDOR_ID_PLX,
1248 .device = PCI_DEVICE_ID_PLX_9050,
1249 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1250 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1251 .init = pci_plx9050_init,
1252 .setup = pci_default_setup,
1253 .exit = __devexit_p(pci_plx9050_exit),
1254 },
1255 {
1256 .vendor = PCI_VENDOR_ID_PLX,
1257 .device = PCI_DEVICE_ID_PLX_9050,
1258 .subvendor = PCI_VENDOR_ID_PLX,
1259 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1260 .init = pci_plx9050_init,
1261 .setup = pci_default_setup,
1262 .exit = __devexit_p(pci_plx9050_exit),
1263 },
1264 {
1265 .vendor = PCI_VENDOR_ID_PLX,
1266 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1267 .subvendor = PCI_VENDOR_ID_PLX,
1268 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1269 .init = pci_plx9050_init,
1270 .setup = pci_default_setup,
1271 .exit = __devexit_p(pci_plx9050_exit),
1272 },
1273 /*
1274 * SBS Technologies, Inc., PMC-OCTALPRO 232
1275 */
1276 {
1277 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1278 .device = PCI_DEVICE_ID_OCTPRO,
1279 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1280 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1281 .init = sbs_init,
1282 .setup = sbs_setup,
1283 .exit = __devexit_p(sbs_exit),
1284 },
1285 /*
1286 * SBS Technologies, Inc., PMC-OCTALPRO 422
1287 */
1288 {
1289 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1290 .device = PCI_DEVICE_ID_OCTPRO,
1291 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1292 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1293 .init = sbs_init,
1294 .setup = sbs_setup,
1295 .exit = __devexit_p(sbs_exit),
1296 },
1297 /*
1298 * SBS Technologies, Inc., P-Octal 232
1299 */
1300 {
1301 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1302 .device = PCI_DEVICE_ID_OCTPRO,
1303 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1304 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1305 .init = sbs_init,
1306 .setup = sbs_setup,
1307 .exit = __devexit_p(sbs_exit),
1308 },
1309 /*
1310 * SBS Technologies, Inc., P-Octal 422
1311 */
1312 {
1313 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1314 .device = PCI_DEVICE_ID_OCTPRO,
1315 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1316 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1317 .init = sbs_init,
1318 .setup = sbs_setup,
1319 .exit = __devexit_p(sbs_exit),
1320 },
1321 /*
1322 * SIIG cards - these may be called via parport_serial
1323 */
1324 {
1325 .vendor = PCI_VENDOR_ID_SIIG,
1326 .device = PCI_ANY_ID,
1327 .subvendor = PCI_ANY_ID,
1328 .subdevice = PCI_ANY_ID,
1329 .init = pci_siig_init,
1330 .setup = pci_siig_setup,
1331 },
1332 /*
1333 * Titan cards
1334 */
1335 {
1336 .vendor = PCI_VENDOR_ID_TITAN,
1337 .device = PCI_DEVICE_ID_TITAN_400L,
1338 .subvendor = PCI_ANY_ID,
1339 .subdevice = PCI_ANY_ID,
1340 .setup = titan_400l_800l_setup,
1341 },
1342 {
1343 .vendor = PCI_VENDOR_ID_TITAN,
1344 .device = PCI_DEVICE_ID_TITAN_800L,
1345 .subvendor = PCI_ANY_ID,
1346 .subdevice = PCI_ANY_ID,
1347 .setup = titan_400l_800l_setup,
1348 },
1349 /*
1350 * Timedia cards
1351 */
1352 {
1353 .vendor = PCI_VENDOR_ID_TIMEDIA,
1354 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1355 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1356 .subdevice = PCI_ANY_ID,
1357 .init = pci_timedia_init,
1358 .setup = pci_timedia_setup,
1359 },
1360 {
1361 .vendor = PCI_VENDOR_ID_TIMEDIA,
1362 .device = PCI_ANY_ID,
1363 .subvendor = PCI_ANY_ID,
1364 .subdevice = PCI_ANY_ID,
1365 .setup = pci_timedia_setup,
1366 },
1367 /*
1368 * Xircom cards
1369 */
1370 {
1371 .vendor = PCI_VENDOR_ID_XIRCOM,
1372 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1373 .subvendor = PCI_ANY_ID,
1374 .subdevice = PCI_ANY_ID,
1375 .init = pci_xircom_init,
1376 .setup = pci_default_setup,
1377 },
1378 /*
1379 * Netmos cards - these may be called via parport_serial
1380 */
1381 {
1382 .vendor = PCI_VENDOR_ID_NETMOS,
1383 .device = PCI_ANY_ID,
1384 .subvendor = PCI_ANY_ID,
1385 .subdevice = PCI_ANY_ID,
1386 .init = pci_netmos_init,
1387 .setup = pci_default_setup,
1388 },
1389 /*
1390 * For Oxford Semiconductor and Mainpine
1391 */
1392 {
1393 .vendor = PCI_VENDOR_ID_OXSEMI,
1394 .device = PCI_ANY_ID,
1395 .subvendor = PCI_ANY_ID,
1396 .subdevice = PCI_ANY_ID,
1397 .init = pci_oxsemi_tornado_init,
1398 .setup = pci_default_setup,
1399 },
1400 {
1401 .vendor = PCI_VENDOR_ID_MAINPINE,
1402 .device = PCI_ANY_ID,
1403 .subvendor = PCI_ANY_ID,
1404 .subdevice = PCI_ANY_ID,
1405 .init = pci_oxsemi_tornado_init,
1406 .setup = pci_default_setup,
1407 },
1408 /*
1409 * Default "match everything" terminator entry
1410 */
1411 {
1412 .vendor = PCI_ANY_ID,
1413 .device = PCI_ANY_ID,
1414 .subvendor = PCI_ANY_ID,
1415 .subdevice = PCI_ANY_ID,
1416 .setup = pci_default_setup,
1417 }
1418 };
1419
1420 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1421 {
1422 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1423 }
1424
1425 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1426 {
1427 struct pci_serial_quirk *quirk;
1428
1429 for (quirk = pci_serial_quirks; ; quirk++)
1430 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1431 quirk_id_matches(quirk->device, dev->device) &&
1432 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1433 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1434 break;
1435 return quirk;
1436 }
1437
1438 static inline int get_pci_irq(struct pci_dev *dev,
1439 const struct pciserial_board *board)
1440 {
1441 if (board->flags & FL_NOIRQ)
1442 return 0;
1443 else
1444 return dev->irq;
1445 }
1446
1447 /*
1448 * This is the configuration table for all of the PCI serial boards
1449 * which we support. It is directly indexed by the pci_board_num_t enum
1450 * value, which is encoded in the pci_device_id PCI probe table's
1451 * driver_data member.
1452 *
1453 * The makeup of these names are:
1454 * pbn_bn{_bt}_n_baud{_offsetinhex}
1455 *
1456 * bn = PCI BAR number
1457 * bt = Index using PCI BARs
1458 * n = number of serial ports
1459 * baud = baud rate
1460 * offsetinhex = offset for each sequential port (in hex)
1461 *
1462 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1463 *
1464 * Please note: in theory if n = 1, _bt infix should make no difference.
1465 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1466 */
1467 enum pci_board_num_t {
1468 pbn_default = 0,
1469
1470 pbn_b0_1_115200,
1471 pbn_b0_2_115200,
1472 pbn_b0_4_115200,
1473 pbn_b0_5_115200,
1474 pbn_b0_8_115200,
1475
1476 pbn_b0_1_921600,
1477 pbn_b0_2_921600,
1478 pbn_b0_4_921600,
1479
1480 pbn_b0_2_1130000,
1481
1482 pbn_b0_4_1152000,
1483
1484 pbn_b0_2_1843200,
1485 pbn_b0_4_1843200,
1486
1487 pbn_b0_2_1843200_200,
1488 pbn_b0_4_1843200_200,
1489 pbn_b0_8_1843200_200,
1490
1491 pbn_b0_1_4000000,
1492
1493 pbn_b0_bt_1_115200,
1494 pbn_b0_bt_2_115200,
1495 pbn_b0_bt_4_115200,
1496 pbn_b0_bt_8_115200,
1497
1498 pbn_b0_bt_1_460800,
1499 pbn_b0_bt_2_460800,
1500 pbn_b0_bt_4_460800,
1501
1502 pbn_b0_bt_1_921600,
1503 pbn_b0_bt_2_921600,
1504 pbn_b0_bt_4_921600,
1505 pbn_b0_bt_8_921600,
1506
1507 pbn_b1_1_115200,
1508 pbn_b1_2_115200,
1509 pbn_b1_4_115200,
1510 pbn_b1_8_115200,
1511 pbn_b1_16_115200,
1512
1513 pbn_b1_1_921600,
1514 pbn_b1_2_921600,
1515 pbn_b1_4_921600,
1516 pbn_b1_8_921600,
1517
1518 pbn_b1_2_1250000,
1519
1520 pbn_b1_bt_1_115200,
1521 pbn_b1_bt_2_115200,
1522 pbn_b1_bt_4_115200,
1523
1524 pbn_b1_bt_2_921600,
1525
1526 pbn_b1_1_1382400,
1527 pbn_b1_2_1382400,
1528 pbn_b1_4_1382400,
1529 pbn_b1_8_1382400,
1530
1531 pbn_b2_1_115200,
1532 pbn_b2_2_115200,
1533 pbn_b2_4_115200,
1534 pbn_b2_8_115200,
1535
1536 pbn_b2_1_460800,
1537 pbn_b2_4_460800,
1538 pbn_b2_8_460800,
1539 pbn_b2_16_460800,
1540
1541 pbn_b2_1_921600,
1542 pbn_b2_4_921600,
1543 pbn_b2_8_921600,
1544
1545 pbn_b2_bt_1_115200,
1546 pbn_b2_bt_2_115200,
1547 pbn_b2_bt_4_115200,
1548
1549 pbn_b2_bt_2_921600,
1550 pbn_b2_bt_4_921600,
1551
1552 pbn_b3_2_115200,
1553 pbn_b3_4_115200,
1554 pbn_b3_8_115200,
1555
1556 pbn_b4_bt_2_921600,
1557 pbn_b4_bt_4_921600,
1558 pbn_b4_bt_8_921600,
1559
1560 /*
1561 * Board-specific versions.
1562 */
1563 pbn_panacom,
1564 pbn_panacom2,
1565 pbn_panacom4,
1566 pbn_exsys_4055,
1567 pbn_plx_romulus,
1568 pbn_oxsemi,
1569 pbn_oxsemi_1_4000000,
1570 pbn_oxsemi_2_4000000,
1571 pbn_oxsemi_4_4000000,
1572 pbn_oxsemi_8_4000000,
1573 pbn_intel_i960,
1574 pbn_sgi_ioc3,
1575 pbn_computone_4,
1576 pbn_computone_6,
1577 pbn_computone_8,
1578 pbn_sbsxrsio,
1579 pbn_exar_XR17C152,
1580 pbn_exar_XR17C154,
1581 pbn_exar_XR17C158,
1582 pbn_exar_ibm_saturn,
1583 pbn_pasemi_1682M,
1584 pbn_ni8430_2,
1585 pbn_ni8430_4,
1586 pbn_ni8430_8,
1587 pbn_ni8430_16,
1588 pbn_ADDIDATA_PCIe_1_3906250,
1589 pbn_ADDIDATA_PCIe_2_3906250,
1590 pbn_ADDIDATA_PCIe_4_3906250,
1591 pbn_ADDIDATA_PCIe_8_3906250,
1592 };
1593
1594 /*
1595 * uart_offset - the space between channels
1596 * reg_shift - describes how the UART registers are mapped
1597 * to PCI memory by the card.
1598 * For example IER register on SBS, Inc. PMC-OctPro is located at
1599 * offset 0x10 from the UART base, while UART_IER is defined as 1
1600 * in include/linux/serial_reg.h,
1601 * see first lines of serial_in() and serial_out() in 8250.c
1602 */
1603
1604 static struct pciserial_board pci_boards[] __devinitdata = {
1605 [pbn_default] = {
1606 .flags = FL_BASE0,
1607 .num_ports = 1,
1608 .base_baud = 115200,
1609 .uart_offset = 8,
1610 },
1611 [pbn_b0_1_115200] = {
1612 .flags = FL_BASE0,
1613 .num_ports = 1,
1614 .base_baud = 115200,
1615 .uart_offset = 8,
1616 },
1617 [pbn_b0_2_115200] = {
1618 .flags = FL_BASE0,
1619 .num_ports = 2,
1620 .base_baud = 115200,
1621 .uart_offset = 8,
1622 },
1623 [pbn_b0_4_115200] = {
1624 .flags = FL_BASE0,
1625 .num_ports = 4,
1626 .base_baud = 115200,
1627 .uart_offset = 8,
1628 },
1629 [pbn_b0_5_115200] = {
1630 .flags = FL_BASE0,
1631 .num_ports = 5,
1632 .base_baud = 115200,
1633 .uart_offset = 8,
1634 },
1635 [pbn_b0_8_115200] = {
1636 .flags = FL_BASE0,
1637 .num_ports = 8,
1638 .base_baud = 115200,
1639 .uart_offset = 8,
1640 },
1641 [pbn_b0_1_921600] = {
1642 .flags = FL_BASE0,
1643 .num_ports = 1,
1644 .base_baud = 921600,
1645 .uart_offset = 8,
1646 },
1647 [pbn_b0_2_921600] = {
1648 .flags = FL_BASE0,
1649 .num_ports = 2,
1650 .base_baud = 921600,
1651 .uart_offset = 8,
1652 },
1653 [pbn_b0_4_921600] = {
1654 .flags = FL_BASE0,
1655 .num_ports = 4,
1656 .base_baud = 921600,
1657 .uart_offset = 8,
1658 },
1659
1660 [pbn_b0_2_1130000] = {
1661 .flags = FL_BASE0,
1662 .num_ports = 2,
1663 .base_baud = 1130000,
1664 .uart_offset = 8,
1665 },
1666
1667 [pbn_b0_4_1152000] = {
1668 .flags = FL_BASE0,
1669 .num_ports = 4,
1670 .base_baud = 1152000,
1671 .uart_offset = 8,
1672 },
1673
1674 [pbn_b0_2_1843200] = {
1675 .flags = FL_BASE0,
1676 .num_ports = 2,
1677 .base_baud = 1843200,
1678 .uart_offset = 8,
1679 },
1680 [pbn_b0_4_1843200] = {
1681 .flags = FL_BASE0,
1682 .num_ports = 4,
1683 .base_baud = 1843200,
1684 .uart_offset = 8,
1685 },
1686
1687 [pbn_b0_2_1843200_200] = {
1688 .flags = FL_BASE0,
1689 .num_ports = 2,
1690 .base_baud = 1843200,
1691 .uart_offset = 0x200,
1692 },
1693 [pbn_b0_4_1843200_200] = {
1694 .flags = FL_BASE0,
1695 .num_ports = 4,
1696 .base_baud = 1843200,
1697 .uart_offset = 0x200,
1698 },
1699 [pbn_b0_8_1843200_200] = {
1700 .flags = FL_BASE0,
1701 .num_ports = 8,
1702 .base_baud = 1843200,
1703 .uart_offset = 0x200,
1704 },
1705 [pbn_b0_1_4000000] = {
1706 .flags = FL_BASE0,
1707 .num_ports = 1,
1708 .base_baud = 4000000,
1709 .uart_offset = 8,
1710 },
1711
1712 [pbn_b0_bt_1_115200] = {
1713 .flags = FL_BASE0|FL_BASE_BARS,
1714 .num_ports = 1,
1715 .base_baud = 115200,
1716 .uart_offset = 8,
1717 },
1718 [pbn_b0_bt_2_115200] = {
1719 .flags = FL_BASE0|FL_BASE_BARS,
1720 .num_ports = 2,
1721 .base_baud = 115200,
1722 .uart_offset = 8,
1723 },
1724 [pbn_b0_bt_4_115200] = {
1725 .flags = FL_BASE0|FL_BASE_BARS,
1726 .num_ports = 4,
1727 .base_baud = 115200,
1728 .uart_offset = 8,
1729 },
1730 [pbn_b0_bt_8_115200] = {
1731 .flags = FL_BASE0|FL_BASE_BARS,
1732 .num_ports = 8,
1733 .base_baud = 115200,
1734 .uart_offset = 8,
1735 },
1736
1737 [pbn_b0_bt_1_460800] = {
1738 .flags = FL_BASE0|FL_BASE_BARS,
1739 .num_ports = 1,
1740 .base_baud = 460800,
1741 .uart_offset = 8,
1742 },
1743 [pbn_b0_bt_2_460800] = {
1744 .flags = FL_BASE0|FL_BASE_BARS,
1745 .num_ports = 2,
1746 .base_baud = 460800,
1747 .uart_offset = 8,
1748 },
1749 [pbn_b0_bt_4_460800] = {
1750 .flags = FL_BASE0|FL_BASE_BARS,
1751 .num_ports = 4,
1752 .base_baud = 460800,
1753 .uart_offset = 8,
1754 },
1755
1756 [pbn_b0_bt_1_921600] = {
1757 .flags = FL_BASE0|FL_BASE_BARS,
1758 .num_ports = 1,
1759 .base_baud = 921600,
1760 .uart_offset = 8,
1761 },
1762 [pbn_b0_bt_2_921600] = {
1763 .flags = FL_BASE0|FL_BASE_BARS,
1764 .num_ports = 2,
1765 .base_baud = 921600,
1766 .uart_offset = 8,
1767 },
1768 [pbn_b0_bt_4_921600] = {
1769 .flags = FL_BASE0|FL_BASE_BARS,
1770 .num_ports = 4,
1771 .base_baud = 921600,
1772 .uart_offset = 8,
1773 },
1774 [pbn_b0_bt_8_921600] = {
1775 .flags = FL_BASE0|FL_BASE_BARS,
1776 .num_ports = 8,
1777 .base_baud = 921600,
1778 .uart_offset = 8,
1779 },
1780
1781 [pbn_b1_1_115200] = {
1782 .flags = FL_BASE1,
1783 .num_ports = 1,
1784 .base_baud = 115200,
1785 .uart_offset = 8,
1786 },
1787 [pbn_b1_2_115200] = {
1788 .flags = FL_BASE1,
1789 .num_ports = 2,
1790 .base_baud = 115200,
1791 .uart_offset = 8,
1792 },
1793 [pbn_b1_4_115200] = {
1794 .flags = FL_BASE1,
1795 .num_ports = 4,
1796 .base_baud = 115200,
1797 .uart_offset = 8,
1798 },
1799 [pbn_b1_8_115200] = {
1800 .flags = FL_BASE1,
1801 .num_ports = 8,
1802 .base_baud = 115200,
1803 .uart_offset = 8,
1804 },
1805 [pbn_b1_16_115200] = {
1806 .flags = FL_BASE1,
1807 .num_ports = 16,
1808 .base_baud = 115200,
1809 .uart_offset = 8,
1810 },
1811
1812 [pbn_b1_1_921600] = {
1813 .flags = FL_BASE1,
1814 .num_ports = 1,
1815 .base_baud = 921600,
1816 .uart_offset = 8,
1817 },
1818 [pbn_b1_2_921600] = {
1819 .flags = FL_BASE1,
1820 .num_ports = 2,
1821 .base_baud = 921600,
1822 .uart_offset = 8,
1823 },
1824 [pbn_b1_4_921600] = {
1825 .flags = FL_BASE1,
1826 .num_ports = 4,
1827 .base_baud = 921600,
1828 .uart_offset = 8,
1829 },
1830 [pbn_b1_8_921600] = {
1831 .flags = FL_BASE1,
1832 .num_ports = 8,
1833 .base_baud = 921600,
1834 .uart_offset = 8,
1835 },
1836 [pbn_b1_2_1250000] = {
1837 .flags = FL_BASE1,
1838 .num_ports = 2,
1839 .base_baud = 1250000,
1840 .uart_offset = 8,
1841 },
1842
1843 [pbn_b1_bt_1_115200] = {
1844 .flags = FL_BASE1|FL_BASE_BARS,
1845 .num_ports = 1,
1846 .base_baud = 115200,
1847 .uart_offset = 8,
1848 },
1849 [pbn_b1_bt_2_115200] = {
1850 .flags = FL_BASE1|FL_BASE_BARS,
1851 .num_ports = 2,
1852 .base_baud = 115200,
1853 .uart_offset = 8,
1854 },
1855 [pbn_b1_bt_4_115200] = {
1856 .flags = FL_BASE1|FL_BASE_BARS,
1857 .num_ports = 4,
1858 .base_baud = 115200,
1859 .uart_offset = 8,
1860 },
1861
1862 [pbn_b1_bt_2_921600] = {
1863 .flags = FL_BASE1|FL_BASE_BARS,
1864 .num_ports = 2,
1865 .base_baud = 921600,
1866 .uart_offset = 8,
1867 },
1868
1869 [pbn_b1_1_1382400] = {
1870 .flags = FL_BASE1,
1871 .num_ports = 1,
1872 .base_baud = 1382400,
1873 .uart_offset = 8,
1874 },
1875 [pbn_b1_2_1382400] = {
1876 .flags = FL_BASE1,
1877 .num_ports = 2,
1878 .base_baud = 1382400,
1879 .uart_offset = 8,
1880 },
1881 [pbn_b1_4_1382400] = {
1882 .flags = FL_BASE1,
1883 .num_ports = 4,
1884 .base_baud = 1382400,
1885 .uart_offset = 8,
1886 },
1887 [pbn_b1_8_1382400] = {
1888 .flags = FL_BASE1,
1889 .num_ports = 8,
1890 .base_baud = 1382400,
1891 .uart_offset = 8,
1892 },
1893
1894 [pbn_b2_1_115200] = {
1895 .flags = FL_BASE2,
1896 .num_ports = 1,
1897 .base_baud = 115200,
1898 .uart_offset = 8,
1899 },
1900 [pbn_b2_2_115200] = {
1901 .flags = FL_BASE2,
1902 .num_ports = 2,
1903 .base_baud = 115200,
1904 .uart_offset = 8,
1905 },
1906 [pbn_b2_4_115200] = {
1907 .flags = FL_BASE2,
1908 .num_ports = 4,
1909 .base_baud = 115200,
1910 .uart_offset = 8,
1911 },
1912 [pbn_b2_8_115200] = {
1913 .flags = FL_BASE2,
1914 .num_ports = 8,
1915 .base_baud = 115200,
1916 .uart_offset = 8,
1917 },
1918
1919 [pbn_b2_1_460800] = {
1920 .flags = FL_BASE2,
1921 .num_ports = 1,
1922 .base_baud = 460800,
1923 .uart_offset = 8,
1924 },
1925 [pbn_b2_4_460800] = {
1926 .flags = FL_BASE2,
1927 .num_ports = 4,
1928 .base_baud = 460800,
1929 .uart_offset = 8,
1930 },
1931 [pbn_b2_8_460800] = {
1932 .flags = FL_BASE2,
1933 .num_ports = 8,
1934 .base_baud = 460800,
1935 .uart_offset = 8,
1936 },
1937 [pbn_b2_16_460800] = {
1938 .flags = FL_BASE2,
1939 .num_ports = 16,
1940 .base_baud = 460800,
1941 .uart_offset = 8,
1942 },
1943
1944 [pbn_b2_1_921600] = {
1945 .flags = FL_BASE2,
1946 .num_ports = 1,
1947 .base_baud = 921600,
1948 .uart_offset = 8,
1949 },
1950 [pbn_b2_4_921600] = {
1951 .flags = FL_BASE2,
1952 .num_ports = 4,
1953 .base_baud = 921600,
1954 .uart_offset = 8,
1955 },
1956 [pbn_b2_8_921600] = {
1957 .flags = FL_BASE2,
1958 .num_ports = 8,
1959 .base_baud = 921600,
1960 .uart_offset = 8,
1961 },
1962
1963 [pbn_b2_bt_1_115200] = {
1964 .flags = FL_BASE2|FL_BASE_BARS,
1965 .num_ports = 1,
1966 .base_baud = 115200,
1967 .uart_offset = 8,
1968 },
1969 [pbn_b2_bt_2_115200] = {
1970 .flags = FL_BASE2|FL_BASE_BARS,
1971 .num_ports = 2,
1972 .base_baud = 115200,
1973 .uart_offset = 8,
1974 },
1975 [pbn_b2_bt_4_115200] = {
1976 .flags = FL_BASE2|FL_BASE_BARS,
1977 .num_ports = 4,
1978 .base_baud = 115200,
1979 .uart_offset = 8,
1980 },
1981
1982 [pbn_b2_bt_2_921600] = {
1983 .flags = FL_BASE2|FL_BASE_BARS,
1984 .num_ports = 2,
1985 .base_baud = 921600,
1986 .uart_offset = 8,
1987 },
1988 [pbn_b2_bt_4_921600] = {
1989 .flags = FL_BASE2|FL_BASE_BARS,
1990 .num_ports = 4,
1991 .base_baud = 921600,
1992 .uart_offset = 8,
1993 },
1994
1995 [pbn_b3_2_115200] = {
1996 .flags = FL_BASE3,
1997 .num_ports = 2,
1998 .base_baud = 115200,
1999 .uart_offset = 8,
2000 },
2001 [pbn_b3_4_115200] = {
2002 .flags = FL_BASE3,
2003 .num_ports = 4,
2004 .base_baud = 115200,
2005 .uart_offset = 8,
2006 },
2007 [pbn_b3_8_115200] = {
2008 .flags = FL_BASE3,
2009 .num_ports = 8,
2010 .base_baud = 115200,
2011 .uart_offset = 8,
2012 },
2013
2014 [pbn_b4_bt_2_921600] = {
2015 .flags = FL_BASE4,
2016 .num_ports = 2,
2017 .base_baud = 921600,
2018 .uart_offset = 8,
2019 },
2020 [pbn_b4_bt_4_921600] = {
2021 .flags = FL_BASE4,
2022 .num_ports = 4,
2023 .base_baud = 921600,
2024 .uart_offset = 8,
2025 },
2026 [pbn_b4_bt_8_921600] = {
2027 .flags = FL_BASE4,
2028 .num_ports = 8,
2029 .base_baud = 921600,
2030 .uart_offset = 8,
2031 },
2032
2033 /*
2034 * Entries following this are board-specific.
2035 */
2036
2037 /*
2038 * Panacom - IOMEM
2039 */
2040 [pbn_panacom] = {
2041 .flags = FL_BASE2,
2042 .num_ports = 2,
2043 .base_baud = 921600,
2044 .uart_offset = 0x400,
2045 .reg_shift = 7,
2046 },
2047 [pbn_panacom2] = {
2048 .flags = FL_BASE2|FL_BASE_BARS,
2049 .num_ports = 2,
2050 .base_baud = 921600,
2051 .uart_offset = 0x400,
2052 .reg_shift = 7,
2053 },
2054 [pbn_panacom4] = {
2055 .flags = FL_BASE2|FL_BASE_BARS,
2056 .num_ports = 4,
2057 .base_baud = 921600,
2058 .uart_offset = 0x400,
2059 .reg_shift = 7,
2060 },
2061
2062 [pbn_exsys_4055] = {
2063 .flags = FL_BASE2,
2064 .num_ports = 4,
2065 .base_baud = 115200,
2066 .uart_offset = 8,
2067 },
2068
2069 /* I think this entry is broken - the first_offset looks wrong --rmk */
2070 [pbn_plx_romulus] = {
2071 .flags = FL_BASE2,
2072 .num_ports = 4,
2073 .base_baud = 921600,
2074 .uart_offset = 8 << 2,
2075 .reg_shift = 2,
2076 .first_offset = 0x03,
2077 },
2078
2079 /*
2080 * This board uses the size of PCI Base region 0 to
2081 * signal now many ports are available
2082 */
2083 [pbn_oxsemi] = {
2084 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2085 .num_ports = 32,
2086 .base_baud = 115200,
2087 .uart_offset = 8,
2088 },
2089 [pbn_oxsemi_1_4000000] = {
2090 .flags = FL_BASE0,
2091 .num_ports = 1,
2092 .base_baud = 4000000,
2093 .uart_offset = 0x200,
2094 .first_offset = 0x1000,
2095 },
2096 [pbn_oxsemi_2_4000000] = {
2097 .flags = FL_BASE0,
2098 .num_ports = 2,
2099 .base_baud = 4000000,
2100 .uart_offset = 0x200,
2101 .first_offset = 0x1000,
2102 },
2103 [pbn_oxsemi_4_4000000] = {
2104 .flags = FL_BASE0,
2105 .num_ports = 4,
2106 .base_baud = 4000000,
2107 .uart_offset = 0x200,
2108 .first_offset = 0x1000,
2109 },
2110 [pbn_oxsemi_8_4000000] = {
2111 .flags = FL_BASE0,
2112 .num_ports = 8,
2113 .base_baud = 4000000,
2114 .uart_offset = 0x200,
2115 .first_offset = 0x1000,
2116 },
2117
2118
2119 /*
2120 * EKF addition for i960 Boards form EKF with serial port.
2121 * Max 256 ports.
2122 */
2123 [pbn_intel_i960] = {
2124 .flags = FL_BASE0,
2125 .num_ports = 32,
2126 .base_baud = 921600,
2127 .uart_offset = 8 << 2,
2128 .reg_shift = 2,
2129 .first_offset = 0x10000,
2130 },
2131 [pbn_sgi_ioc3] = {
2132 .flags = FL_BASE0|FL_NOIRQ,
2133 .num_ports = 1,
2134 .base_baud = 458333,
2135 .uart_offset = 8,
2136 .reg_shift = 0,
2137 .first_offset = 0x20178,
2138 },
2139
2140 /*
2141 * Computone - uses IOMEM.
2142 */
2143 [pbn_computone_4] = {
2144 .flags = FL_BASE0,
2145 .num_ports = 4,
2146 .base_baud = 921600,
2147 .uart_offset = 0x40,
2148 .reg_shift = 2,
2149 .first_offset = 0x200,
2150 },
2151 [pbn_computone_6] = {
2152 .flags = FL_BASE0,
2153 .num_ports = 6,
2154 .base_baud = 921600,
2155 .uart_offset = 0x40,
2156 .reg_shift = 2,
2157 .first_offset = 0x200,
2158 },
2159 [pbn_computone_8] = {
2160 .flags = FL_BASE0,
2161 .num_ports = 8,
2162 .base_baud = 921600,
2163 .uart_offset = 0x40,
2164 .reg_shift = 2,
2165 .first_offset = 0x200,
2166 },
2167 [pbn_sbsxrsio] = {
2168 .flags = FL_BASE0,
2169 .num_ports = 8,
2170 .base_baud = 460800,
2171 .uart_offset = 256,
2172 .reg_shift = 4,
2173 },
2174 /*
2175 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2176 * Only basic 16550A support.
2177 * XR17C15[24] are not tested, but they should work.
2178 */
2179 [pbn_exar_XR17C152] = {
2180 .flags = FL_BASE0,
2181 .num_ports = 2,
2182 .base_baud = 921600,
2183 .uart_offset = 0x200,
2184 },
2185 [pbn_exar_XR17C154] = {
2186 .flags = FL_BASE0,
2187 .num_ports = 4,
2188 .base_baud = 921600,
2189 .uart_offset = 0x200,
2190 },
2191 [pbn_exar_XR17C158] = {
2192 .flags = FL_BASE0,
2193 .num_ports = 8,
2194 .base_baud = 921600,
2195 .uart_offset = 0x200,
2196 },
2197 [pbn_exar_ibm_saturn] = {
2198 .flags = FL_BASE0,
2199 .num_ports = 1,
2200 .base_baud = 921600,
2201 .uart_offset = 0x200,
2202 },
2203
2204 /*
2205 * PA Semi PWRficient PA6T-1682M on-chip UART
2206 */
2207 [pbn_pasemi_1682M] = {
2208 .flags = FL_BASE0,
2209 .num_ports = 1,
2210 .base_baud = 8333333,
2211 },
2212 /*
2213 * National Instruments 843x
2214 */
2215 [pbn_ni8430_16] = {
2216 .flags = FL_BASE0,
2217 .num_ports = 16,
2218 .base_baud = 3686400,
2219 .uart_offset = 0x10,
2220 .first_offset = 0x800,
2221 },
2222 [pbn_ni8430_8] = {
2223 .flags = FL_BASE0,
2224 .num_ports = 8,
2225 .base_baud = 3686400,
2226 .uart_offset = 0x10,
2227 .first_offset = 0x800,
2228 },
2229 [pbn_ni8430_4] = {
2230 .flags = FL_BASE0,
2231 .num_ports = 4,
2232 .base_baud = 3686400,
2233 .uart_offset = 0x10,
2234 .first_offset = 0x800,
2235 },
2236 [pbn_ni8430_2] = {
2237 .flags = FL_BASE0,
2238 .num_ports = 2,
2239 .base_baud = 3686400,
2240 .uart_offset = 0x10,
2241 .first_offset = 0x800,
2242 },
2243 /*
2244 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2245 */
2246 [pbn_ADDIDATA_PCIe_1_3906250] = {
2247 .flags = FL_BASE0,
2248 .num_ports = 1,
2249 .base_baud = 3906250,
2250 .uart_offset = 0x200,
2251 .first_offset = 0x1000,
2252 },
2253 [pbn_ADDIDATA_PCIe_2_3906250] = {
2254 .flags = FL_BASE0,
2255 .num_ports = 2,
2256 .base_baud = 3906250,
2257 .uart_offset = 0x200,
2258 .first_offset = 0x1000,
2259 },
2260 [pbn_ADDIDATA_PCIe_4_3906250] = {
2261 .flags = FL_BASE0,
2262 .num_ports = 4,
2263 .base_baud = 3906250,
2264 .uart_offset = 0x200,
2265 .first_offset = 0x1000,
2266 },
2267 [pbn_ADDIDATA_PCIe_8_3906250] = {
2268 .flags = FL_BASE0,
2269 .num_ports = 8,
2270 .base_baud = 3906250,
2271 .uart_offset = 0x200,
2272 .first_offset = 0x1000,
2273 },
2274 };
2275
2276 static const struct pci_device_id softmodem_blacklist[] = {
2277 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2278 };
2279
2280 /*
2281 * Given a complete unknown PCI device, try to use some heuristics to
2282 * guess what the configuration might be, based on the pitiful PCI
2283 * serial specs. Returns 0 on success, 1 on failure.
2284 */
2285 static int __devinit
2286 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2287 {
2288 const struct pci_device_id *blacklist;
2289 int num_iomem, num_port, first_port = -1, i;
2290
2291 /*
2292 * If it is not a communications device or the programming
2293 * interface is greater than 6, give up.
2294 *
2295 * (Should we try to make guesses for multiport serial devices
2296 * later?)
2297 */
2298 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2299 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2300 (dev->class & 0xff) > 6)
2301 return -ENODEV;
2302
2303 /*
2304 * Do not access blacklisted devices that are known not to
2305 * feature serial ports.
2306 */
2307 for (blacklist = softmodem_blacklist;
2308 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2309 blacklist++) {
2310 if (dev->vendor == blacklist->vendor &&
2311 dev->device == blacklist->device)
2312 return -ENODEV;
2313 }
2314
2315 num_iomem = num_port = 0;
2316 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2317 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2318 num_port++;
2319 if (first_port == -1)
2320 first_port = i;
2321 }
2322 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2323 num_iomem++;
2324 }
2325
2326 /*
2327 * If there is 1 or 0 iomem regions, and exactly one port,
2328 * use it. We guess the number of ports based on the IO
2329 * region size.
2330 */
2331 if (num_iomem <= 1 && num_port == 1) {
2332 board->flags = first_port;
2333 board->num_ports = pci_resource_len(dev, first_port) / 8;
2334 return 0;
2335 }
2336
2337 /*
2338 * Now guess if we've got a board which indexes by BARs.
2339 * Each IO BAR should be 8 bytes, and they should follow
2340 * consecutively.
2341 */
2342 first_port = -1;
2343 num_port = 0;
2344 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2345 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2346 pci_resource_len(dev, i) == 8 &&
2347 (first_port == -1 || (first_port + num_port) == i)) {
2348 num_port++;
2349 if (first_port == -1)
2350 first_port = i;
2351 }
2352 }
2353
2354 if (num_port > 1) {
2355 board->flags = first_port | FL_BASE_BARS;
2356 board->num_ports = num_port;
2357 return 0;
2358 }
2359
2360 return -ENODEV;
2361 }
2362
2363 static inline int
2364 serial_pci_matches(const struct pciserial_board *board,
2365 const struct pciserial_board *guessed)
2366 {
2367 return
2368 board->num_ports == guessed->num_ports &&
2369 board->base_baud == guessed->base_baud &&
2370 board->uart_offset == guessed->uart_offset &&
2371 board->reg_shift == guessed->reg_shift &&
2372 board->first_offset == guessed->first_offset;
2373 }
2374
2375 struct serial_private *
2376 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2377 {
2378 struct uart_port serial_port;
2379 struct serial_private *priv;
2380 struct pci_serial_quirk *quirk;
2381 int rc, nr_ports, i;
2382
2383 nr_ports = board->num_ports;
2384
2385 /*
2386 * Find an init and setup quirks.
2387 */
2388 quirk = find_quirk(dev);
2389
2390 /*
2391 * Run the new-style initialization function.
2392 * The initialization function returns:
2393 * <0 - error
2394 * 0 - use board->num_ports
2395 * >0 - number of ports
2396 */
2397 if (quirk->init) {
2398 rc = quirk->init(dev);
2399 if (rc < 0) {
2400 priv = ERR_PTR(rc);
2401 goto err_out;
2402 }
2403 if (rc)
2404 nr_ports = rc;
2405 }
2406
2407 priv = kzalloc(sizeof(struct serial_private) +
2408 sizeof(unsigned int) * nr_ports,
2409 GFP_KERNEL);
2410 if (!priv) {
2411 priv = ERR_PTR(-ENOMEM);
2412 goto err_deinit;
2413 }
2414
2415 priv->dev = dev;
2416 priv->quirk = quirk;
2417
2418 memset(&serial_port, 0, sizeof(struct uart_port));
2419 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2420 serial_port.uartclk = board->base_baud * 16;
2421 serial_port.irq = get_pci_irq(dev, board);
2422 serial_port.dev = &dev->dev;
2423
2424 for (i = 0; i < nr_ports; i++) {
2425 if (quirk->setup(priv, board, &serial_port, i))
2426 break;
2427
2428 #ifdef SERIAL_DEBUG_PCI
2429 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2430 serial_port.iobase, serial_port.irq, serial_port.iotype);
2431 #endif
2432
2433 priv->line[i] = serial8250_register_port(&serial_port);
2434 if (priv->line[i] < 0) {
2435 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2436 break;
2437 }
2438 }
2439 priv->nr = i;
2440 return priv;
2441
2442 err_deinit:
2443 if (quirk->exit)
2444 quirk->exit(dev);
2445 err_out:
2446 return priv;
2447 }
2448 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2449
2450 void pciserial_remove_ports(struct serial_private *priv)
2451 {
2452 struct pci_serial_quirk *quirk;
2453 int i;
2454
2455 for (i = 0; i < priv->nr; i++)
2456 serial8250_unregister_port(priv->line[i]);
2457
2458 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2459 if (priv->remapped_bar[i])
2460 iounmap(priv->remapped_bar[i]);
2461 priv->remapped_bar[i] = NULL;
2462 }
2463
2464 /*
2465 * Find the exit quirks.
2466 */
2467 quirk = find_quirk(priv->dev);
2468 if (quirk->exit)
2469 quirk->exit(priv->dev);
2470
2471 kfree(priv);
2472 }
2473 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2474
2475 void pciserial_suspend_ports(struct serial_private *priv)
2476 {
2477 int i;
2478
2479 for (i = 0; i < priv->nr; i++)
2480 if (priv->line[i] >= 0)
2481 serial8250_suspend_port(priv->line[i]);
2482 }
2483 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2484
2485 void pciserial_resume_ports(struct serial_private *priv)
2486 {
2487 int i;
2488
2489 /*
2490 * Ensure that the board is correctly configured.
2491 */
2492 if (priv->quirk->init)
2493 priv->quirk->init(priv->dev);
2494
2495 for (i = 0; i < priv->nr; i++)
2496 if (priv->line[i] >= 0)
2497 serial8250_resume_port(priv->line[i]);
2498 }
2499 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2500
2501 /*
2502 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2503 * to the arrangement of serial ports on a PCI card.
2504 */
2505 static int __devinit
2506 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2507 {
2508 struct serial_private *priv;
2509 const struct pciserial_board *board;
2510 struct pciserial_board tmp;
2511 int rc;
2512
2513 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2514 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2515 ent->driver_data);
2516 return -EINVAL;
2517 }
2518
2519 board = &pci_boards[ent->driver_data];
2520
2521 rc = pci_enable_device(dev);
2522 if (rc)
2523 return rc;
2524
2525 if (ent->driver_data == pbn_default) {
2526 /*
2527 * Use a copy of the pci_board entry for this;
2528 * avoid changing entries in the table.
2529 */
2530 memcpy(&tmp, board, sizeof(struct pciserial_board));
2531 board = &tmp;
2532
2533 /*
2534 * We matched one of our class entries. Try to
2535 * determine the parameters of this board.
2536 */
2537 rc = serial_pci_guess_board(dev, &tmp);
2538 if (rc)
2539 goto disable;
2540 } else {
2541 /*
2542 * We matched an explicit entry. If we are able to
2543 * detect this boards settings with our heuristic,
2544 * then we no longer need this entry.
2545 */
2546 memcpy(&tmp, &pci_boards[pbn_default],
2547 sizeof(struct pciserial_board));
2548 rc = serial_pci_guess_board(dev, &tmp);
2549 if (rc == 0 && serial_pci_matches(board, &tmp))
2550 moan_device("Redundant entry in serial pci_table.",
2551 dev);
2552 }
2553
2554 priv = pciserial_init_ports(dev, board);
2555 if (!IS_ERR(priv)) {
2556 pci_set_drvdata(dev, priv);
2557 return 0;
2558 }
2559
2560 rc = PTR_ERR(priv);
2561
2562 disable:
2563 pci_disable_device(dev);
2564 return rc;
2565 }
2566
2567 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2568 {
2569 struct serial_private *priv = pci_get_drvdata(dev);
2570
2571 pci_set_drvdata(dev, NULL);
2572
2573 pciserial_remove_ports(priv);
2574
2575 pci_disable_device(dev);
2576 }
2577
2578 #ifdef CONFIG_PM
2579 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2580 {
2581 struct serial_private *priv = pci_get_drvdata(dev);
2582
2583 if (priv)
2584 pciserial_suspend_ports(priv);
2585
2586 pci_save_state(dev);
2587 pci_set_power_state(dev, pci_choose_state(dev, state));
2588 return 0;
2589 }
2590
2591 static int pciserial_resume_one(struct pci_dev *dev)
2592 {
2593 int err;
2594 struct serial_private *priv = pci_get_drvdata(dev);
2595
2596 pci_set_power_state(dev, PCI_D0);
2597 pci_restore_state(dev);
2598
2599 if (priv) {
2600 /*
2601 * The device may have been disabled. Re-enable it.
2602 */
2603 err = pci_enable_device(dev);
2604 /* FIXME: We cannot simply error out here */
2605 if (err)
2606 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2607 pciserial_resume_ports(priv);
2608 }
2609 return 0;
2610 }
2611 #endif
2612
2613 static struct pci_device_id serial_pci_tbl[] = {
2614 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2615 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2616 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2617 pbn_b2_8_921600 },
2618 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2619 PCI_SUBVENDOR_ID_CONNECT_TECH,
2620 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2621 pbn_b1_8_1382400 },
2622 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2623 PCI_SUBVENDOR_ID_CONNECT_TECH,
2624 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2625 pbn_b1_4_1382400 },
2626 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2627 PCI_SUBVENDOR_ID_CONNECT_TECH,
2628 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2629 pbn_b1_2_1382400 },
2630 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2631 PCI_SUBVENDOR_ID_CONNECT_TECH,
2632 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2633 pbn_b1_8_1382400 },
2634 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2635 PCI_SUBVENDOR_ID_CONNECT_TECH,
2636 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2637 pbn_b1_4_1382400 },
2638 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2639 PCI_SUBVENDOR_ID_CONNECT_TECH,
2640 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2641 pbn_b1_2_1382400 },
2642 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2643 PCI_SUBVENDOR_ID_CONNECT_TECH,
2644 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2645 pbn_b1_8_921600 },
2646 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2647 PCI_SUBVENDOR_ID_CONNECT_TECH,
2648 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2649 pbn_b1_8_921600 },
2650 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2651 PCI_SUBVENDOR_ID_CONNECT_TECH,
2652 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2653 pbn_b1_4_921600 },
2654 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2655 PCI_SUBVENDOR_ID_CONNECT_TECH,
2656 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2657 pbn_b1_4_921600 },
2658 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2659 PCI_SUBVENDOR_ID_CONNECT_TECH,
2660 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2661 pbn_b1_2_921600 },
2662 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2663 PCI_SUBVENDOR_ID_CONNECT_TECH,
2664 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2665 pbn_b1_8_921600 },
2666 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2667 PCI_SUBVENDOR_ID_CONNECT_TECH,
2668 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2669 pbn_b1_8_921600 },
2670 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2671 PCI_SUBVENDOR_ID_CONNECT_TECH,
2672 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2673 pbn_b1_4_921600 },
2674 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2675 PCI_SUBVENDOR_ID_CONNECT_TECH,
2676 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2677 pbn_b1_2_1250000 },
2678 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2679 PCI_SUBVENDOR_ID_CONNECT_TECH,
2680 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2681 pbn_b0_2_1843200 },
2682 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2683 PCI_SUBVENDOR_ID_CONNECT_TECH,
2684 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2685 pbn_b0_4_1843200 },
2686 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2687 PCI_VENDOR_ID_AFAVLAB,
2688 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2689 pbn_b0_4_1152000 },
2690 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2691 PCI_SUBVENDOR_ID_CONNECT_TECH,
2692 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2693 pbn_b0_2_1843200_200 },
2694 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2695 PCI_SUBVENDOR_ID_CONNECT_TECH,
2696 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2697 pbn_b0_4_1843200_200 },
2698 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2699 PCI_SUBVENDOR_ID_CONNECT_TECH,
2700 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2701 pbn_b0_8_1843200_200 },
2702 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2703 PCI_SUBVENDOR_ID_CONNECT_TECH,
2704 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2705 pbn_b0_2_1843200_200 },
2706 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2707 PCI_SUBVENDOR_ID_CONNECT_TECH,
2708 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2709 pbn_b0_4_1843200_200 },
2710 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2711 PCI_SUBVENDOR_ID_CONNECT_TECH,
2712 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2713 pbn_b0_8_1843200_200 },
2714 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2715 PCI_SUBVENDOR_ID_CONNECT_TECH,
2716 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2717 pbn_b0_2_1843200_200 },
2718 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2719 PCI_SUBVENDOR_ID_CONNECT_TECH,
2720 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2721 pbn_b0_4_1843200_200 },
2722 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2723 PCI_SUBVENDOR_ID_CONNECT_TECH,
2724 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2725 pbn_b0_8_1843200_200 },
2726 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2727 PCI_SUBVENDOR_ID_CONNECT_TECH,
2728 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2729 pbn_b0_2_1843200_200 },
2730 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2731 PCI_SUBVENDOR_ID_CONNECT_TECH,
2732 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2733 pbn_b0_4_1843200_200 },
2734 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2735 PCI_SUBVENDOR_ID_CONNECT_TECH,
2736 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2737 pbn_b0_8_1843200_200 },
2738 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2739 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2740 0, 0, pbn_exar_ibm_saturn },
2741
2742 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2744 pbn_b2_bt_1_115200 },
2745 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2747 pbn_b2_bt_2_115200 },
2748 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2750 pbn_b2_bt_4_115200 },
2751 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2753 pbn_b2_bt_2_115200 },
2754 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2756 pbn_b2_bt_4_115200 },
2757 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2759 pbn_b2_8_115200 },
2760 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2762 pbn_b2_8_460800 },
2763 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2765 pbn_b2_8_115200 },
2766
2767 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2769 pbn_b2_bt_2_115200 },
2770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2772 pbn_b2_bt_2_921600 },
2773 /*
2774 * VScom SPCOM800, from sl@s.pl
2775 */
2776 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2778 pbn_b2_8_921600 },
2779 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2781 pbn_b2_4_921600 },
2782 /* Unknown card - subdevice 0x1584 */
2783 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2784 PCI_VENDOR_ID_PLX,
2785 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2786 pbn_b0_4_115200 },
2787 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2788 PCI_SUBVENDOR_ID_KEYSPAN,
2789 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2790 pbn_panacom },
2791 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2793 pbn_panacom4 },
2794 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2796 pbn_panacom2 },
2797 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2798 PCI_VENDOR_ID_ESDGMBH,
2799 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2800 pbn_b2_4_115200 },
2801 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2802 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2803 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2804 pbn_b2_4_460800 },
2805 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2806 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2807 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2808 pbn_b2_8_460800 },
2809 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2810 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2811 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2812 pbn_b2_16_460800 },
2813 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2814 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2815 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2816 pbn_b2_16_460800 },
2817 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2818 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2819 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2820 pbn_b2_4_460800 },
2821 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2822 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2823 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2824 pbn_b2_8_460800 },
2825 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2826 PCI_SUBVENDOR_ID_EXSYS,
2827 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2828 pbn_exsys_4055 },
2829 /*
2830 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2831 * (Exoray@isys.ca)
2832 */
2833 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2834 0x10b5, 0x106a, 0, 0,
2835 pbn_plx_romulus },
2836 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2838 pbn_b1_4_115200 },
2839 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2841 pbn_b1_2_115200 },
2842 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2844 pbn_b1_8_115200 },
2845 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2847 pbn_b1_8_115200 },
2848 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2849 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2850 0, 0,
2851 pbn_b0_4_921600 },
2852 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2853 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2854 0, 0,
2855 pbn_b0_4_1152000 },
2856
2857 /*
2858 * The below card is a little controversial since it is the
2859 * subject of a PCI vendor/device ID clash. (See
2860 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2861 * For now just used the hex ID 0x950a.
2862 */
2863 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2864 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2865 pbn_b0_2_115200 },
2866 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2868 pbn_b0_2_1130000 },
2869 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2870 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2871 pbn_b0_1_921600 },
2872 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2874 pbn_b0_4_115200 },
2875 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2877 pbn_b0_bt_2_921600 },
2878
2879 /*
2880 * Oxford Semiconductor Inc. Tornado PCI express device range.
2881 */
2882 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2884 pbn_b0_1_4000000 },
2885 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2887 pbn_b0_1_4000000 },
2888 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2890 pbn_oxsemi_1_4000000 },
2891 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2893 pbn_oxsemi_1_4000000 },
2894 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2896 pbn_b0_1_4000000 },
2897 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2899 pbn_b0_1_4000000 },
2900 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2902 pbn_oxsemi_1_4000000 },
2903 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2905 pbn_oxsemi_1_4000000 },
2906 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2908 pbn_b0_1_4000000 },
2909 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2911 pbn_b0_1_4000000 },
2912 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2914 pbn_b0_1_4000000 },
2915 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2917 pbn_b0_1_4000000 },
2918 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2920 pbn_oxsemi_2_4000000 },
2921 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2923 pbn_oxsemi_2_4000000 },
2924 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2926 pbn_oxsemi_4_4000000 },
2927 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2929 pbn_oxsemi_4_4000000 },
2930 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2932 pbn_oxsemi_8_4000000 },
2933 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2935 pbn_oxsemi_8_4000000 },
2936 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2938 pbn_oxsemi_1_4000000 },
2939 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2941 pbn_oxsemi_1_4000000 },
2942 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2944 pbn_oxsemi_1_4000000 },
2945 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2947 pbn_oxsemi_1_4000000 },
2948 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2950 pbn_oxsemi_1_4000000 },
2951 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2953 pbn_oxsemi_1_4000000 },
2954 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2956 pbn_oxsemi_1_4000000 },
2957 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2959 pbn_oxsemi_1_4000000 },
2960 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2962 pbn_oxsemi_1_4000000 },
2963 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2965 pbn_oxsemi_1_4000000 },
2966 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2968 pbn_oxsemi_1_4000000 },
2969 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2971 pbn_oxsemi_1_4000000 },
2972 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2974 pbn_oxsemi_1_4000000 },
2975 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2977 pbn_oxsemi_1_4000000 },
2978 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2980 pbn_oxsemi_1_4000000 },
2981 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2983 pbn_oxsemi_1_4000000 },
2984 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2986 pbn_oxsemi_1_4000000 },
2987 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2989 pbn_oxsemi_1_4000000 },
2990 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
2991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2992 pbn_oxsemi_1_4000000 },
2993 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
2994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2995 pbn_oxsemi_1_4000000 },
2996 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
2997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2998 pbn_oxsemi_1_4000000 },
2999 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3001 pbn_oxsemi_1_4000000 },
3002 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3004 pbn_oxsemi_1_4000000 },
3005 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3007 pbn_oxsemi_1_4000000 },
3008 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3010 pbn_oxsemi_1_4000000 },
3011 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3013 pbn_oxsemi_1_4000000 },
3014 /*
3015 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3016 */
3017 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3018 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3019 pbn_oxsemi_1_4000000 },
3020 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3021 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3022 pbn_oxsemi_2_4000000 },
3023 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3024 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3025 pbn_oxsemi_4_4000000 },
3026 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3027 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3028 pbn_oxsemi_8_4000000 },
3029 /*
3030 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3031 * from skokodyn@yahoo.com
3032 */
3033 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3034 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3035 pbn_sbsxrsio },
3036 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3037 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3038 pbn_sbsxrsio },
3039 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3040 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3041 pbn_sbsxrsio },
3042 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3043 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3044 pbn_sbsxrsio },
3045
3046 /*
3047 * Digitan DS560-558, from jimd@esoft.com
3048 */
3049 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051 pbn_b1_1_115200 },
3052
3053 /*
3054 * Titan Electronic cards
3055 * The 400L and 800L have a custom setup quirk.
3056 */
3057 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059 pbn_b0_1_921600 },
3060 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062 pbn_b0_2_921600 },
3063 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3065 pbn_b0_4_921600 },
3066 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3068 pbn_b0_4_921600 },
3069 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3071 pbn_b1_1_921600 },
3072 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3074 pbn_b1_bt_2_921600 },
3075 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3077 pbn_b0_bt_4_921600 },
3078 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3080 pbn_b0_bt_8_921600 },
3081 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083 pbn_b4_bt_2_921600 },
3084 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086 pbn_b4_bt_4_921600 },
3087 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089 pbn_b4_bt_8_921600 },
3090 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092 pbn_b0_4_921600 },
3093 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095 pbn_b0_4_921600 },
3096 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098 pbn_b0_4_921600 },
3099 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101 pbn_oxsemi_1_4000000 },
3102 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3104 pbn_oxsemi_2_4000000 },
3105 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107 pbn_oxsemi_4_4000000 },
3108 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110 pbn_oxsemi_8_4000000 },
3111 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3113 pbn_oxsemi_2_4000000 },
3114 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3116 pbn_oxsemi_2_4000000 },
3117
3118 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120 pbn_b2_1_460800 },
3121 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123 pbn_b2_1_460800 },
3124 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_b2_1_460800 },
3127 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_b2_bt_2_921600 },
3130 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3132 pbn_b2_bt_2_921600 },
3133 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135 pbn_b2_bt_2_921600 },
3136 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3138 pbn_b2_bt_4_921600 },
3139 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3141 pbn_b2_bt_4_921600 },
3142 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3144 pbn_b2_bt_4_921600 },
3145 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147 pbn_b0_1_921600 },
3148 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3150 pbn_b0_1_921600 },
3151 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b0_1_921600 },
3154 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_b0_bt_2_921600 },
3157 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b0_bt_2_921600 },
3160 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_b0_bt_2_921600 },
3163 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3165 pbn_b0_bt_4_921600 },
3166 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3168 pbn_b0_bt_4_921600 },
3169 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3171 pbn_b0_bt_4_921600 },
3172 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3174 pbn_b0_bt_8_921600 },
3175 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177 pbn_b0_bt_8_921600 },
3178 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180 pbn_b0_bt_8_921600 },
3181
3182 /*
3183 * Computone devices submitted by Doug McNash dmcnash@computone.com
3184 */
3185 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3186 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3187 0, 0, pbn_computone_4 },
3188 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3189 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3190 0, 0, pbn_computone_8 },
3191 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3192 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3193 0, 0, pbn_computone_6 },
3194
3195 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197 pbn_oxsemi },
3198 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3199 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3200 pbn_b0_bt_1_921600 },
3201
3202 /*
3203 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3204 */
3205 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 pbn_b0_bt_8_115200 },
3208 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210 pbn_b0_bt_8_115200 },
3211
3212 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b0_bt_2_115200 },
3215 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b0_bt_2_115200 },
3218 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b0_bt_2_115200 },
3221 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b0_bt_2_115200 },
3224 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_b0_bt_2_115200 },
3227 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_b0_bt_4_460800 },
3230 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232 pbn_b0_bt_4_460800 },
3233 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235 pbn_b0_bt_2_460800 },
3236 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_b0_bt_2_460800 },
3239 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_b0_bt_2_460800 },
3242 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_b0_bt_1_115200 },
3245 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247 pbn_b0_bt_1_460800 },
3248
3249 /*
3250 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3251 * Cards are identified by their subsystem vendor IDs, which
3252 * (in hex) match the model number.
3253 *
3254 * Note that JC140x are RS422/485 cards which require ox950
3255 * ACR = 0x10, and as such are not currently fully supported.
3256 */
3257 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3258 0x1204, 0x0004, 0, 0,
3259 pbn_b0_4_921600 },
3260 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3261 0x1208, 0x0004, 0, 0,
3262 pbn_b0_4_921600 },
3263 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3264 0x1402, 0x0002, 0, 0,
3265 pbn_b0_2_921600 }, */
3266 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3267 0x1404, 0x0004, 0, 0,
3268 pbn_b0_4_921600 }, */
3269 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3270 0x1208, 0x0004, 0, 0,
3271 pbn_b0_4_921600 },
3272
3273 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3274 0x1204, 0x0004, 0, 0,
3275 pbn_b0_4_921600 },
3276 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3277 0x1208, 0x0004, 0, 0,
3278 pbn_b0_4_921600 },
3279 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3280 0x1208, 0x0004, 0, 0,
3281 pbn_b0_4_921600 },
3282 /*
3283 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3284 */
3285 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_b1_1_1382400 },
3288
3289 /*
3290 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3291 */
3292 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_b1_1_1382400 },
3295
3296 /*
3297 * RAStel 2 port modem, gerg@moreton.com.au
3298 */
3299 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 pbn_b2_bt_2_115200 },
3302
3303 /*
3304 * EKF addition for i960 Boards form EKF with serial port
3305 */
3306 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3307 0xE4BF, PCI_ANY_ID, 0, 0,
3308 pbn_intel_i960 },
3309
3310 /*
3311 * Xircom Cardbus/Ethernet combos
3312 */
3313 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315 pbn_b0_1_115200 },
3316 /*
3317 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3318 */
3319 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321 pbn_b0_1_115200 },
3322
3323 /*
3324 * Untested PCI modems, sent in from various folks...
3325 */
3326
3327 /*
3328 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3329 */
3330 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3331 0x1048, 0x1500, 0, 0,
3332 pbn_b1_1_115200 },
3333
3334 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3335 0xFF00, 0, 0, 0,
3336 pbn_sgi_ioc3 },
3337
3338 /*
3339 * HP Diva card
3340 */
3341 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3342 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3343 pbn_b1_1_115200 },
3344 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346 pbn_b0_5_115200 },
3347 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349 pbn_b2_1_115200 },
3350
3351 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353 pbn_b3_2_115200 },
3354 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356 pbn_b3_4_115200 },
3357 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359 pbn_b3_8_115200 },
3360
3361 /*
3362 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3363 */
3364 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3365 PCI_ANY_ID, PCI_ANY_ID,
3366 0,
3367 0, pbn_exar_XR17C152 },
3368 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3369 PCI_ANY_ID, PCI_ANY_ID,
3370 0,
3371 0, pbn_exar_XR17C154 },
3372 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3373 PCI_ANY_ID, PCI_ANY_ID,
3374 0,
3375 0, pbn_exar_XR17C158 },
3376
3377 /*
3378 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3379 */
3380 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3382 pbn_b0_1_115200 },
3383 /*
3384 * ITE
3385 */
3386 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3387 PCI_ANY_ID, PCI_ANY_ID,
3388 0, 0,
3389 pbn_b1_bt_1_115200 },
3390
3391 /*
3392 * IntaShield IS-200
3393 */
3394 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3396 pbn_b2_2_115200 },
3397 /*
3398 * IntaShield IS-400
3399 */
3400 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3402 pbn_b2_4_115200 },
3403 /*
3404 * Perle PCI-RAS cards
3405 */
3406 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3407 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3408 0, 0, pbn_b2_4_921600 },
3409 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3410 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3411 0, 0, pbn_b2_8_921600 },
3412
3413 /*
3414 * Mainpine series cards: Fairly standard layout but fools
3415 * parts of the autodetect in some cases and uses otherwise
3416 * unmatched communications subclasses in the PCI Express case
3417 */
3418
3419 { /* RockForceDUO */
3420 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3421 PCI_VENDOR_ID_MAINPINE, 0x0200,
3422 0, 0, pbn_b0_2_115200 },
3423 { /* RockForceQUATRO */
3424 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3425 PCI_VENDOR_ID_MAINPINE, 0x0300,
3426 0, 0, pbn_b0_4_115200 },
3427 { /* RockForceDUO+ */
3428 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3429 PCI_VENDOR_ID_MAINPINE, 0x0400,
3430 0, 0, pbn_b0_2_115200 },
3431 { /* RockForceQUATRO+ */
3432 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3433 PCI_VENDOR_ID_MAINPINE, 0x0500,
3434 0, 0, pbn_b0_4_115200 },
3435 { /* RockForce+ */
3436 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3437 PCI_VENDOR_ID_MAINPINE, 0x0600,
3438 0, 0, pbn_b0_2_115200 },
3439 { /* RockForce+ */
3440 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3441 PCI_VENDOR_ID_MAINPINE, 0x0700,
3442 0, 0, pbn_b0_4_115200 },
3443 { /* RockForceOCTO+ */
3444 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3445 PCI_VENDOR_ID_MAINPINE, 0x0800,
3446 0, 0, pbn_b0_8_115200 },
3447 { /* RockForceDUO+ */
3448 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3449 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3450 0, 0, pbn_b0_2_115200 },
3451 { /* RockForceQUARTRO+ */
3452 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3453 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3454 0, 0, pbn_b0_4_115200 },
3455 { /* RockForceOCTO+ */
3456 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3457 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3458 0, 0, pbn_b0_8_115200 },
3459 { /* RockForceD1 */
3460 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3461 PCI_VENDOR_ID_MAINPINE, 0x2000,
3462 0, 0, pbn_b0_1_115200 },
3463 { /* RockForceF1 */
3464 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3465 PCI_VENDOR_ID_MAINPINE, 0x2100,
3466 0, 0, pbn_b0_1_115200 },
3467 { /* RockForceD2 */
3468 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3469 PCI_VENDOR_ID_MAINPINE, 0x2200,
3470 0, 0, pbn_b0_2_115200 },
3471 { /* RockForceF2 */
3472 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3473 PCI_VENDOR_ID_MAINPINE, 0x2300,
3474 0, 0, pbn_b0_2_115200 },
3475 { /* RockForceD4 */
3476 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3477 PCI_VENDOR_ID_MAINPINE, 0x2400,
3478 0, 0, pbn_b0_4_115200 },
3479 { /* RockForceF4 */
3480 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3481 PCI_VENDOR_ID_MAINPINE, 0x2500,
3482 0, 0, pbn_b0_4_115200 },
3483 { /* RockForceD8 */
3484 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3485 PCI_VENDOR_ID_MAINPINE, 0x2600,
3486 0, 0, pbn_b0_8_115200 },
3487 { /* RockForceF8 */
3488 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3489 PCI_VENDOR_ID_MAINPINE, 0x2700,
3490 0, 0, pbn_b0_8_115200 },
3491 { /* IQ Express D1 */
3492 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3493 PCI_VENDOR_ID_MAINPINE, 0x3000,
3494 0, 0, pbn_b0_1_115200 },
3495 { /* IQ Express F1 */
3496 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3497 PCI_VENDOR_ID_MAINPINE, 0x3100,
3498 0, 0, pbn_b0_1_115200 },
3499 { /* IQ Express D2 */
3500 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3501 PCI_VENDOR_ID_MAINPINE, 0x3200,
3502 0, 0, pbn_b0_2_115200 },
3503 { /* IQ Express F2 */
3504 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3505 PCI_VENDOR_ID_MAINPINE, 0x3300,
3506 0, 0, pbn_b0_2_115200 },
3507 { /* IQ Express D4 */
3508 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3509 PCI_VENDOR_ID_MAINPINE, 0x3400,
3510 0, 0, pbn_b0_4_115200 },
3511 { /* IQ Express F4 */
3512 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3513 PCI_VENDOR_ID_MAINPINE, 0x3500,
3514 0, 0, pbn_b0_4_115200 },
3515 { /* IQ Express D8 */
3516 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3517 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3518 0, 0, pbn_b0_8_115200 },
3519 { /* IQ Express F8 */
3520 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3521 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3522 0, 0, pbn_b0_8_115200 },
3523
3524
3525 /*
3526 * PA Semi PA6T-1682M on-chip UART
3527 */
3528 { PCI_VENDOR_ID_PASEMI, 0xa004,
3529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530 pbn_pasemi_1682M },
3531
3532 /*
3533 * National Instruments
3534 */
3535 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3537 pbn_b1_16_115200 },
3538 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3540 pbn_b1_8_115200 },
3541 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543 pbn_b1_bt_4_115200 },
3544 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3545 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3546 pbn_b1_bt_2_115200 },
3547 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3548 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3549 pbn_b1_bt_4_115200 },
3550 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3551 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552 pbn_b1_bt_2_115200 },
3553 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555 pbn_b1_16_115200 },
3556 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3558 pbn_b1_8_115200 },
3559 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561 pbn_b1_bt_4_115200 },
3562 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564 pbn_b1_bt_2_115200 },
3565 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3567 pbn_b1_bt_4_115200 },
3568 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3570 pbn_b1_bt_2_115200 },
3571 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3573 pbn_ni8430_2 },
3574 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3576 pbn_ni8430_2 },
3577 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3579 pbn_ni8430_4 },
3580 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3582 pbn_ni8430_4 },
3583 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3585 pbn_ni8430_8 },
3586 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3588 pbn_ni8430_8 },
3589 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3591 pbn_ni8430_16 },
3592 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3594 pbn_ni8430_16 },
3595 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3597 pbn_ni8430_2 },
3598 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600 pbn_ni8430_2 },
3601 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603 pbn_ni8430_4 },
3604 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606 pbn_ni8430_4 },
3607
3608 /*
3609 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3610 */
3611 { PCI_VENDOR_ID_ADDIDATA,
3612 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3613 PCI_ANY_ID,
3614 PCI_ANY_ID,
3615 0,
3616 0,
3617 pbn_b0_4_115200 },
3618
3619 { PCI_VENDOR_ID_ADDIDATA,
3620 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3621 PCI_ANY_ID,
3622 PCI_ANY_ID,
3623 0,
3624 0,
3625 pbn_b0_2_115200 },
3626
3627 { PCI_VENDOR_ID_ADDIDATA,
3628 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3629 PCI_ANY_ID,
3630 PCI_ANY_ID,
3631 0,
3632 0,
3633 pbn_b0_1_115200 },
3634
3635 { PCI_VENDOR_ID_ADDIDATA_OLD,
3636 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3637 PCI_ANY_ID,
3638 PCI_ANY_ID,
3639 0,
3640 0,
3641 pbn_b1_8_115200 },
3642
3643 { PCI_VENDOR_ID_ADDIDATA,
3644 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3645 PCI_ANY_ID,
3646 PCI_ANY_ID,
3647 0,
3648 0,
3649 pbn_b0_4_115200 },
3650
3651 { PCI_VENDOR_ID_ADDIDATA,
3652 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3653 PCI_ANY_ID,
3654 PCI_ANY_ID,
3655 0,
3656 0,
3657 pbn_b0_2_115200 },
3658
3659 { PCI_VENDOR_ID_ADDIDATA,
3660 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3661 PCI_ANY_ID,
3662 PCI_ANY_ID,
3663 0,
3664 0,
3665 pbn_b0_1_115200 },
3666
3667 { PCI_VENDOR_ID_ADDIDATA,
3668 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3669 PCI_ANY_ID,
3670 PCI_ANY_ID,
3671 0,
3672 0,
3673 pbn_b0_4_115200 },
3674
3675 { PCI_VENDOR_ID_ADDIDATA,
3676 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3677 PCI_ANY_ID,
3678 PCI_ANY_ID,
3679 0,
3680 0,
3681 pbn_b0_2_115200 },
3682
3683 { PCI_VENDOR_ID_ADDIDATA,
3684 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3685 PCI_ANY_ID,
3686 PCI_ANY_ID,
3687 0,
3688 0,
3689 pbn_b0_1_115200 },
3690
3691 { PCI_VENDOR_ID_ADDIDATA,
3692 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3693 PCI_ANY_ID,
3694 PCI_ANY_ID,
3695 0,
3696 0,
3697 pbn_b0_8_115200 },
3698
3699 { PCI_VENDOR_ID_ADDIDATA,
3700 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3701 PCI_ANY_ID,
3702 PCI_ANY_ID,
3703 0,
3704 0,
3705 pbn_ADDIDATA_PCIe_4_3906250 },
3706
3707 { PCI_VENDOR_ID_ADDIDATA,
3708 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3709 PCI_ANY_ID,
3710 PCI_ANY_ID,
3711 0,
3712 0,
3713 pbn_ADDIDATA_PCIe_2_3906250 },
3714
3715 { PCI_VENDOR_ID_ADDIDATA,
3716 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3717 PCI_ANY_ID,
3718 PCI_ANY_ID,
3719 0,
3720 0,
3721 pbn_ADDIDATA_PCIe_1_3906250 },
3722
3723 { PCI_VENDOR_ID_ADDIDATA,
3724 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3725 PCI_ANY_ID,
3726 PCI_ANY_ID,
3727 0,
3728 0,
3729 pbn_ADDIDATA_PCIe_8_3906250 },
3730
3731 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3732 PCI_VENDOR_ID_IBM, 0x0299,
3733 0, 0, pbn_b0_bt_2_115200 },
3734
3735 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3736 0xA000, 0x1000,
3737 0, 0, pbn_b0_1_115200 },
3738
3739 /*
3740 * Best Connectivity PCI Multi I/O cards
3741 */
3742
3743 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3744 0xA000, 0x1000,
3745 0, 0, pbn_b0_1_115200 },
3746
3747 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3748 0xA000, 0x3004,
3749 0, 0, pbn_b0_bt_4_115200 },
3750
3751 /*
3752 * These entries match devices with class COMMUNICATION_SERIAL,
3753 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3754 */
3755 { PCI_ANY_ID, PCI_ANY_ID,
3756 PCI_ANY_ID, PCI_ANY_ID,
3757 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3758 0xffff00, pbn_default },
3759 { PCI_ANY_ID, PCI_ANY_ID,
3760 PCI_ANY_ID, PCI_ANY_ID,
3761 PCI_CLASS_COMMUNICATION_MODEM << 8,
3762 0xffff00, pbn_default },
3763 { PCI_ANY_ID, PCI_ANY_ID,
3764 PCI_ANY_ID, PCI_ANY_ID,
3765 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3766 0xffff00, pbn_default },
3767 { 0, }
3768 };
3769
3770 static struct pci_driver serial_pci_driver = {
3771 .name = "serial",
3772 .probe = pciserial_init_one,
3773 .remove = __devexit_p(pciserial_remove_one),
3774 #ifdef CONFIG_PM
3775 .suspend = pciserial_suspend_one,
3776 .resume = pciserial_resume_one,
3777 #endif
3778 .id_table = serial_pci_tbl,
3779 };
3780
3781 static int __init serial8250_pci_init(void)
3782 {
3783 return pci_register_driver(&serial_pci_driver);
3784 }
3785
3786 static void __exit serial8250_pci_exit(void)
3787 {
3788 pci_unregister_driver(&serial_pci_driver);
3789 }
3790
3791 module_init(serial8250_pci_init);
3792 module_exit(serial8250_pci_exit);
3793
3794 MODULE_LICENSE("GPL");
3795 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3796 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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