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igb: Add media switching feature for i354 PHY's
[linux-2.6/btrfs-unstable.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
blobfe9db48f9084e0b1374de3d3d966c8317cce0ca2
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/types.h>
35 #include <linux/if_ether.h>
36 #include <linux/i2c.h>
37
38 #include "e1000_mac.h"
39 #include "e1000_82575.h"
40 #include "e1000_i210.h"
41
42 static s32 igb_get_invariants_82575(struct e1000_hw *);
43 static s32 igb_acquire_phy_82575(struct e1000_hw *);
44 static void igb_release_phy_82575(struct e1000_hw *);
45 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46 static void igb_release_nvm_82575(struct e1000_hw *);
47 static s32 igb_check_for_link_82575(struct e1000_hw *);
48 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49 static s32 igb_init_hw_82575(struct e1000_hw *);
50 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
52 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
54 static s32 igb_reset_hw_82575(struct e1000_hw *);
55 static s32 igb_reset_hw_82580(struct e1000_hw *);
56 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
57 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
59 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
60 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
61 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
64 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66 static s32 igb_get_phy_id_82575(struct e1000_hw *);
67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68 static bool igb_sgmii_active_82575(struct e1000_hw *);
69 static s32 igb_reset_init_script_82575(struct e1000_hw *);
70 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
71 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
72 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
73 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
77 static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80 #define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
83 /**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91 {
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
103 case e1000_i354:
104 case e1000_i210:
105 case e1000_i211:
106 reg = rd32(E1000_MDICNFG);
107 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
108 break;
109 default:
110 break;
111 }
112 return ext_mdio;
113 }
114
115 /**
116 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
117 * @hw: pointer to the HW structure
118 *
119 * Poll the M88E1112 interfaces to see which interface achieved link.
120 */
121 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
122 {
123 struct e1000_phy_info *phy = &hw->phy;
124 s32 ret_val;
125 u16 data;
126 u8 port = 0;
127
128 /* Check the copper medium. */
129 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
130 if (ret_val)
131 return ret_val;
132
133 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
134 if (ret_val)
135 return ret_val;
136
137 if (data & E1000_M88E1112_STATUS_LINK)
138 port = E1000_MEDIA_PORT_COPPER;
139
140 /* Check the other medium. */
141 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
142 if (ret_val)
143 return ret_val;
144
145 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
146 if (ret_val)
147 return ret_val;
148
149 /* reset page to 0 */
150 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
151 if (ret_val)
152 return ret_val;
153
154 if (data & E1000_M88E1112_STATUS_LINK)
155 port = E1000_MEDIA_PORT_OTHER;
156
157 /* Determine if a swap needs to happen. */
158 if (port && (hw->dev_spec._82575.media_port != port)) {
159 hw->dev_spec._82575.media_port = port;
160 hw->dev_spec._82575.media_changed = true;
161 } else {
162 ret_val = igb_check_for_link_82575(hw);
163 }
164
165 return E1000_SUCCESS;
166 }
167
168 /**
169 * igb_init_phy_params_82575 - Init PHY func ptrs.
170 * @hw: pointer to the HW structure
171 **/
172 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
173 {
174 struct e1000_phy_info *phy = &hw->phy;
175 s32 ret_val = 0;
176 u32 ctrl_ext;
177
178 if (hw->phy.media_type != e1000_media_type_copper) {
179 phy->type = e1000_phy_none;
180 goto out;
181 }
182
183 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
184 phy->reset_delay_us = 100;
185
186 ctrl_ext = rd32(E1000_CTRL_EXT);
187
188 if (igb_sgmii_active_82575(hw)) {
189 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
190 ctrl_ext |= E1000_CTRL_I2C_ENA;
191 } else {
192 phy->ops.reset = igb_phy_hw_reset;
193 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
194 }
195
196 wr32(E1000_CTRL_EXT, ctrl_ext);
197 igb_reset_mdicnfg_82580(hw);
198
199 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
200 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
201 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
202 } else {
203 switch (hw->mac.type) {
204 case e1000_82580:
205 case e1000_i350:
206 case e1000_i354:
207 phy->ops.read_reg = igb_read_phy_reg_82580;
208 phy->ops.write_reg = igb_write_phy_reg_82580;
209 break;
210 case e1000_i210:
211 case e1000_i211:
212 phy->ops.read_reg = igb_read_phy_reg_gs40g;
213 phy->ops.write_reg = igb_write_phy_reg_gs40g;
214 break;
215 default:
216 phy->ops.read_reg = igb_read_phy_reg_igp;
217 phy->ops.write_reg = igb_write_phy_reg_igp;
218 }
219 }
220
221 /* set lan id */
222 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
223 E1000_STATUS_FUNC_SHIFT;
224
225 /* Set phy->phy_addr and phy->id. */
226 ret_val = igb_get_phy_id_82575(hw);
227 if (ret_val)
228 return ret_val;
229
230 /* Verify phy id and set remaining function pointers */
231 switch (phy->id) {
232 case M88E1543_E_PHY_ID:
233 case I347AT4_E_PHY_ID:
234 case M88E1112_E_PHY_ID:
235 case M88E1111_I_PHY_ID:
236 phy->type = e1000_phy_m88;
237 phy->ops.check_polarity = igb_check_polarity_m88;
238 phy->ops.get_phy_info = igb_get_phy_info_m88;
239 if (phy->id != M88E1111_I_PHY_ID)
240 phy->ops.get_cable_length =
241 igb_get_cable_length_m88_gen2;
242 else
243 phy->ops.get_cable_length = igb_get_cable_length_m88;
244 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
245 /* Check if this PHY is confgured for media swap. */
246 if (phy->id == M88E1112_E_PHY_ID) {
247 u16 data;
248
249 ret_val = phy->ops.write_reg(hw,
250 E1000_M88E1112_PAGE_ADDR,
251 2);
252 if (ret_val)
253 goto out;
254
255 ret_val = phy->ops.read_reg(hw,
256 E1000_M88E1112_MAC_CTRL_1,
257 &data);
258 if (ret_val)
259 goto out;
260
261 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
262 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
263 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
264 data == E1000_M88E1112_AUTO_COPPER_BASEX)
265 hw->mac.ops.check_for_link =
266 igb_check_for_link_media_swap;
267 }
268 break;
269 case IGP03E1000_E_PHY_ID:
270 phy->type = e1000_phy_igp_3;
271 phy->ops.get_phy_info = igb_get_phy_info_igp;
272 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
273 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
274 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
275 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
276 break;
277 case I82580_I_PHY_ID:
278 case I350_I_PHY_ID:
279 phy->type = e1000_phy_82580;
280 phy->ops.force_speed_duplex =
281 igb_phy_force_speed_duplex_82580;
282 phy->ops.get_cable_length = igb_get_cable_length_82580;
283 phy->ops.get_phy_info = igb_get_phy_info_82580;
284 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
285 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
286 break;
287 case I210_I_PHY_ID:
288 phy->type = e1000_phy_i210;
289 phy->ops.check_polarity = igb_check_polarity_m88;
290 phy->ops.get_phy_info = igb_get_phy_info_m88;
291 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
292 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
293 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
294 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
295 break;
296 default:
297 ret_val = -E1000_ERR_PHY;
298 goto out;
299 }
300
301 out:
302 return ret_val;
303 }
304
305 /**
306 * igb_init_nvm_params_82575 - Init NVM func ptrs.
307 * @hw: pointer to the HW structure
308 **/
309 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
310 {
311 struct e1000_nvm_info *nvm = &hw->nvm;
312 u32 eecd = rd32(E1000_EECD);
313 u16 size;
314
315 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
316 E1000_EECD_SIZE_EX_SHIFT);
317
318 /* Added to a constant, "size" becomes the left-shift value
319 * for setting word_size.
320 */
321 size += NVM_WORD_SIZE_BASE_SHIFT;
322
323 /* Just in case size is out of range, cap it to the largest
324 * EEPROM size supported
325 */
326 if (size > 15)
327 size = 15;
328
329 nvm->word_size = 1 << size;
330 nvm->opcode_bits = 8;
331 nvm->delay_usec = 1;
332
333 switch (nvm->override) {
334 case e1000_nvm_override_spi_large:
335 nvm->page_size = 32;
336 nvm->address_bits = 16;
337 break;
338 case e1000_nvm_override_spi_small:
339 nvm->page_size = 8;
340 nvm->address_bits = 8;
341 break;
342 default:
343 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
344 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
345 16 : 8;
346 break;
347 }
348 if (nvm->word_size == (1 << 15))
349 nvm->page_size = 128;
350
351 nvm->type = e1000_nvm_eeprom_spi;
352
353 /* NVM Function Pointers */
354 nvm->ops.acquire = igb_acquire_nvm_82575;
355 nvm->ops.release = igb_release_nvm_82575;
356 nvm->ops.write = igb_write_nvm_spi;
357 nvm->ops.validate = igb_validate_nvm_checksum;
358 nvm->ops.update = igb_update_nvm_checksum;
359 if (nvm->word_size < (1 << 15))
360 nvm->ops.read = igb_read_nvm_eerd;
361 else
362 nvm->ops.read = igb_read_nvm_spi;
363
364 /* override generic family function pointers for specific descendants */
365 switch (hw->mac.type) {
366 case e1000_82580:
367 nvm->ops.validate = igb_validate_nvm_checksum_82580;
368 nvm->ops.update = igb_update_nvm_checksum_82580;
369 break;
370 case e1000_i354:
371 case e1000_i350:
372 nvm->ops.validate = igb_validate_nvm_checksum_i350;
373 nvm->ops.update = igb_update_nvm_checksum_i350;
374 break;
375 default:
376 break;
377 }
378
379 return 0;
380 }
381
382 /**
383 * igb_init_mac_params_82575 - Init MAC func ptrs.
384 * @hw: pointer to the HW structure
385 **/
386 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
387 {
388 struct e1000_mac_info *mac = &hw->mac;
389 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
390
391 /* Set mta register count */
392 mac->mta_reg_count = 128;
393 /* Set rar entry count */
394 switch (mac->type) {
395 case e1000_82576:
396 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
397 break;
398 case e1000_82580:
399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
400 break;
401 case e1000_i350:
402 case e1000_i354:
403 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
404 break;
405 default:
406 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
407 break;
408 }
409 /* reset */
410 if (mac->type >= e1000_82580)
411 mac->ops.reset_hw = igb_reset_hw_82580;
412 else
413 mac->ops.reset_hw = igb_reset_hw_82575;
414
415 if (mac->type >= e1000_i210) {
416 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
417 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
418
419 } else {
420 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
421 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
422 }
423
424 /* Set if part includes ASF firmware */
425 mac->asf_firmware_present = true;
426 /* Set if manageability features are enabled. */
427 mac->arc_subsystem_valid =
428 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
429 ? true : false;
430 /* enable EEE on i350 parts and later parts */
431 if (mac->type >= e1000_i350)
432 dev_spec->eee_disable = false;
433 else
434 dev_spec->eee_disable = true;
435 /* Allow a single clear of the SW semaphore on I210 and newer */
436 if (mac->type >= e1000_i210)
437 dev_spec->clear_semaphore_once = true;
438 /* physical interface link setup */
439 mac->ops.setup_physical_interface =
440 (hw->phy.media_type == e1000_media_type_copper)
441 ? igb_setup_copper_link_82575
442 : igb_setup_serdes_link_82575;
443
444 return 0;
445 }
446
447 /**
448 * igb_set_sfp_media_type_82575 - derives SFP module media type.
449 * @hw: pointer to the HW structure
450 *
451 * The media type is chosen based on SFP module.
452 * compatibility flags retrieved from SFP ID EEPROM.
453 **/
454 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
455 {
456 s32 ret_val = E1000_ERR_CONFIG;
457 u32 ctrl_ext = 0;
458 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
459 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
460 u8 tranceiver_type = 0;
461 s32 timeout = 3;
462
463 /* Turn I2C interface ON and power on sfp cage */
464 ctrl_ext = rd32(E1000_CTRL_EXT);
465 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
466 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
467
468 wrfl();
469
470 /* Read SFP module data */
471 while (timeout) {
472 ret_val = igb_read_sfp_data_byte(hw,
473 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
474 &tranceiver_type);
475 if (ret_val == 0)
476 break;
477 msleep(100);
478 timeout--;
479 }
480 if (ret_val != 0)
481 goto out;
482
483 ret_val = igb_read_sfp_data_byte(hw,
484 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
485 (u8 *)eth_flags);
486 if (ret_val != 0)
487 goto out;
488
489 /* Check if there is some SFP module plugged and powered */
490 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
491 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
492 dev_spec->module_plugged = true;
493 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
494 hw->phy.media_type = e1000_media_type_internal_serdes;
495 } else if (eth_flags->e100_base_fx) {
496 dev_spec->sgmii_active = true;
497 hw->phy.media_type = e1000_media_type_internal_serdes;
498 } else if (eth_flags->e1000_base_t) {
499 dev_spec->sgmii_active = true;
500 hw->phy.media_type = e1000_media_type_copper;
501 } else {
502 hw->phy.media_type = e1000_media_type_unknown;
503 hw_dbg("PHY module has not been recognized\n");
504 goto out;
505 }
506 } else {
507 hw->phy.media_type = e1000_media_type_unknown;
508 }
509 ret_val = 0;
510 out:
511 /* Restore I2C interface setting */
512 wr32(E1000_CTRL_EXT, ctrl_ext);
513 return ret_val;
514 }
515
516 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
517 {
518 struct e1000_mac_info *mac = &hw->mac;
519 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
520 s32 ret_val;
521 u32 ctrl_ext = 0;
522 u32 link_mode = 0;
523
524 switch (hw->device_id) {
525 case E1000_DEV_ID_82575EB_COPPER:
526 case E1000_DEV_ID_82575EB_FIBER_SERDES:
527 case E1000_DEV_ID_82575GB_QUAD_COPPER:
528 mac->type = e1000_82575;
529 break;
530 case E1000_DEV_ID_82576:
531 case E1000_DEV_ID_82576_NS:
532 case E1000_DEV_ID_82576_NS_SERDES:
533 case E1000_DEV_ID_82576_FIBER:
534 case E1000_DEV_ID_82576_SERDES:
535 case E1000_DEV_ID_82576_QUAD_COPPER:
536 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
537 case E1000_DEV_ID_82576_SERDES_QUAD:
538 mac->type = e1000_82576;
539 break;
540 case E1000_DEV_ID_82580_COPPER:
541 case E1000_DEV_ID_82580_FIBER:
542 case E1000_DEV_ID_82580_QUAD_FIBER:
543 case E1000_DEV_ID_82580_SERDES:
544 case E1000_DEV_ID_82580_SGMII:
545 case E1000_DEV_ID_82580_COPPER_DUAL:
546 case E1000_DEV_ID_DH89XXCC_SGMII:
547 case E1000_DEV_ID_DH89XXCC_SERDES:
548 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
549 case E1000_DEV_ID_DH89XXCC_SFP:
550 mac->type = e1000_82580;
551 break;
552 case E1000_DEV_ID_I350_COPPER:
553 case E1000_DEV_ID_I350_FIBER:
554 case E1000_DEV_ID_I350_SERDES:
555 case E1000_DEV_ID_I350_SGMII:
556 mac->type = e1000_i350;
557 break;
558 case E1000_DEV_ID_I210_COPPER:
559 case E1000_DEV_ID_I210_FIBER:
560 case E1000_DEV_ID_I210_SERDES:
561 case E1000_DEV_ID_I210_SGMII:
562 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
563 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
564 mac->type = e1000_i210;
565 break;
566 case E1000_DEV_ID_I211_COPPER:
567 mac->type = e1000_i211;
568 break;
569 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
570 case E1000_DEV_ID_I354_SGMII:
571 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
572 mac->type = e1000_i354;
573 break;
574 default:
575 return -E1000_ERR_MAC_INIT;
576 break;
577 }
578
579 /* Set media type */
580 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
581 * based on the EEPROM. We cannot rely upon device ID. There
582 * is no distinguishable difference between fiber and internal
583 * SerDes mode on the 82575. There can be an external PHY attached
584 * on the SGMII interface. For this, we'll set sgmii_active to true.
585 */
586 hw->phy.media_type = e1000_media_type_copper;
587 dev_spec->sgmii_active = false;
588 dev_spec->module_plugged = false;
589
590 ctrl_ext = rd32(E1000_CTRL_EXT);
591
592 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
593 switch (link_mode) {
594 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
595 hw->phy.media_type = e1000_media_type_internal_serdes;
596 break;
597 case E1000_CTRL_EXT_LINK_MODE_SGMII:
598 /* Get phy control interface type set (MDIO vs. I2C)*/
599 if (igb_sgmii_uses_mdio_82575(hw)) {
600 hw->phy.media_type = e1000_media_type_copper;
601 dev_spec->sgmii_active = true;
602 break;
603 }
604 /* fall through for I2C based SGMII */
605 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
606 /* read media type from SFP EEPROM */
607 ret_val = igb_set_sfp_media_type_82575(hw);
608 if ((ret_val != 0) ||
609 (hw->phy.media_type == e1000_media_type_unknown)) {
610 /* If media type was not identified then return media
611 * type defined by the CTRL_EXT settings.
612 */
613 hw->phy.media_type = e1000_media_type_internal_serdes;
614
615 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
616 hw->phy.media_type = e1000_media_type_copper;
617 dev_spec->sgmii_active = true;
618 }
619
620 break;
621 }
622
623 /* do not change link mode for 100BaseFX */
624 if (dev_spec->eth_flags.e100_base_fx)
625 break;
626
627 /* change current link mode setting */
628 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
629
630 if (hw->phy.media_type == e1000_media_type_copper)
631 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
632 else
633 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
634
635 wr32(E1000_CTRL_EXT, ctrl_ext);
636
637 break;
638 default:
639 break;
640 }
641
642 /* mac initialization and operations */
643 ret_val = igb_init_mac_params_82575(hw);
644 if (ret_val)
645 goto out;
646
647 /* NVM initialization */
648 ret_val = igb_init_nvm_params_82575(hw);
649 switch (hw->mac.type) {
650 case e1000_i210:
651 case e1000_i211:
652 ret_val = igb_init_nvm_params_i210(hw);
653 break;
654 default:
655 break;
656 }
657
658 if (ret_val)
659 goto out;
660
661 /* if part supports SR-IOV then initialize mailbox parameters */
662 switch (mac->type) {
663 case e1000_82576:
664 case e1000_i350:
665 igb_init_mbx_params_pf(hw);
666 break;
667 default:
668 break;
669 }
670
671 /* setup PHY parameters */
672 ret_val = igb_init_phy_params_82575(hw);
673
674 out:
675 return ret_val;
676 }
677
678 /**
679 * igb_acquire_phy_82575 - Acquire rights to access PHY
680 * @hw: pointer to the HW structure
681 *
682 * Acquire access rights to the correct PHY. This is a
683 * function pointer entry point called by the api module.
684 **/
685 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
686 {
687 u16 mask = E1000_SWFW_PHY0_SM;
688
689 if (hw->bus.func == E1000_FUNC_1)
690 mask = E1000_SWFW_PHY1_SM;
691 else if (hw->bus.func == E1000_FUNC_2)
692 mask = E1000_SWFW_PHY2_SM;
693 else if (hw->bus.func == E1000_FUNC_3)
694 mask = E1000_SWFW_PHY3_SM;
695
696 return hw->mac.ops.acquire_swfw_sync(hw, mask);
697 }
698
699 /**
700 * igb_release_phy_82575 - Release rights to access PHY
701 * @hw: pointer to the HW structure
702 *
703 * A wrapper to release access rights to the correct PHY. This is a
704 * function pointer entry point called by the api module.
705 **/
706 static void igb_release_phy_82575(struct e1000_hw *hw)
707 {
708 u16 mask = E1000_SWFW_PHY0_SM;
709
710 if (hw->bus.func == E1000_FUNC_1)
711 mask = E1000_SWFW_PHY1_SM;
712 else if (hw->bus.func == E1000_FUNC_2)
713 mask = E1000_SWFW_PHY2_SM;
714 else if (hw->bus.func == E1000_FUNC_3)
715 mask = E1000_SWFW_PHY3_SM;
716
717 hw->mac.ops.release_swfw_sync(hw, mask);
718 }
719
720 /**
721 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
722 * @hw: pointer to the HW structure
723 * @offset: register offset to be read
724 * @data: pointer to the read data
725 *
726 * Reads the PHY register at offset using the serial gigabit media independent
727 * interface and stores the retrieved information in data.
728 **/
729 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
730 u16 *data)
731 {
732 s32 ret_val = -E1000_ERR_PARAM;
733
734 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
735 hw_dbg("PHY Address %u is out of range\n", offset);
736 goto out;
737 }
738
739 ret_val = hw->phy.ops.acquire(hw);
740 if (ret_val)
741 goto out;
742
743 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
744
745 hw->phy.ops.release(hw);
746
747 out:
748 return ret_val;
749 }
750
751 /**
752 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
753 * @hw: pointer to the HW structure
754 * @offset: register offset to write to
755 * @data: data to write at register offset
756 *
757 * Writes the data to PHY register at the offset using the serial gigabit
758 * media independent interface.
759 **/
760 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
761 u16 data)
762 {
763 s32 ret_val = -E1000_ERR_PARAM;
764
765
766 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
767 hw_dbg("PHY Address %d is out of range\n", offset);
768 goto out;
769 }
770
771 ret_val = hw->phy.ops.acquire(hw);
772 if (ret_val)
773 goto out;
774
775 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
776
777 hw->phy.ops.release(hw);
778
779 out:
780 return ret_val;
781 }
782
783 /**
784 * igb_get_phy_id_82575 - Retrieve PHY addr and id
785 * @hw: pointer to the HW structure
786 *
787 * Retrieves the PHY address and ID for both PHY's which do and do not use
788 * sgmi interface.
789 **/
790 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
791 {
792 struct e1000_phy_info *phy = &hw->phy;
793 s32 ret_val = 0;
794 u16 phy_id;
795 u32 ctrl_ext;
796 u32 mdic;
797
798 /* Extra read required for some PHY's on i354 */
799 if (hw->mac.type == e1000_i354)
800 igb_get_phy_id(hw);
801
802 /* For SGMII PHYs, we try the list of possible addresses until
803 * we find one that works. For non-SGMII PHYs
804 * (e.g. integrated copper PHYs), an address of 1 should
805 * work. The result of this function should mean phy->phy_addr
806 * and phy->id are set correctly.
807 */
808 if (!(igb_sgmii_active_82575(hw))) {
809 phy->addr = 1;
810 ret_val = igb_get_phy_id(hw);
811 goto out;
812 }
813
814 if (igb_sgmii_uses_mdio_82575(hw)) {
815 switch (hw->mac.type) {
816 case e1000_82575:
817 case e1000_82576:
818 mdic = rd32(E1000_MDIC);
819 mdic &= E1000_MDIC_PHY_MASK;
820 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
821 break;
822 case e1000_82580:
823 case e1000_i350:
824 case e1000_i354:
825 case e1000_i210:
826 case e1000_i211:
827 mdic = rd32(E1000_MDICNFG);
828 mdic &= E1000_MDICNFG_PHY_MASK;
829 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
830 break;
831 default:
832 ret_val = -E1000_ERR_PHY;
833 goto out;
834 break;
835 }
836 ret_val = igb_get_phy_id(hw);
837 goto out;
838 }
839
840 /* Power on sgmii phy if it is disabled */
841 ctrl_ext = rd32(E1000_CTRL_EXT);
842 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
843 wrfl();
844 msleep(300);
845
846 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
847 * Therefore, we need to test 1-7
848 */
849 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
850 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
851 if (ret_val == 0) {
852 hw_dbg("Vendor ID 0x%08X read at address %u\n",
853 phy_id, phy->addr);
854 /* At the time of this writing, The M88 part is
855 * the only supported SGMII PHY product.
856 */
857 if (phy_id == M88_VENDOR)
858 break;
859 } else {
860 hw_dbg("PHY address %u was unreadable\n", phy->addr);
861 }
862 }
863
864 /* A valid PHY type couldn't be found. */
865 if (phy->addr == 8) {
866 phy->addr = 0;
867 ret_val = -E1000_ERR_PHY;
868 goto out;
869 } else {
870 ret_val = igb_get_phy_id(hw);
871 }
872
873 /* restore previous sfp cage power state */
874 wr32(E1000_CTRL_EXT, ctrl_ext);
875
876 out:
877 return ret_val;
878 }
879
880 /**
881 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
882 * @hw: pointer to the HW structure
883 *
884 * Resets the PHY using the serial gigabit media independent interface.
885 **/
886 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
887 {
888 s32 ret_val;
889
890 /* This isn't a true "hard" reset, but is the only reset
891 * available to us at this time.
892 */
893
894 hw_dbg("Soft resetting SGMII attached PHY...\n");
895
896 /* SFP documentation requires the following to configure the SPF module
897 * to work on SGMII. No further documentation is given.
898 */
899 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
900 if (ret_val)
901 goto out;
902
903 ret_val = igb_phy_sw_reset(hw);
904
905 out:
906 return ret_val;
907 }
908
909 /**
910 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
911 * @hw: pointer to the HW structure
912 * @active: true to enable LPLU, false to disable
913 *
914 * Sets the LPLU D0 state according to the active flag. When
915 * activating LPLU this function also disables smart speed
916 * and vice versa. LPLU will not be activated unless the
917 * device autonegotiation advertisement meets standards of
918 * either 10 or 10/100 or 10/100/1000 at all duplexes.
919 * This is a function pointer entry point only called by
920 * PHY setup routines.
921 **/
922 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
923 {
924 struct e1000_phy_info *phy = &hw->phy;
925 s32 ret_val;
926 u16 data;
927
928 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
929 if (ret_val)
930 goto out;
931
932 if (active) {
933 data |= IGP02E1000_PM_D0_LPLU;
934 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
935 data);
936 if (ret_val)
937 goto out;
938
939 /* When LPLU is enabled, we should disable SmartSpeed */
940 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
941 &data);
942 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
943 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
944 data);
945 if (ret_val)
946 goto out;
947 } else {
948 data &= ~IGP02E1000_PM_D0_LPLU;
949 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
950 data);
951 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
952 * during Dx states where the power conservation is most
953 * important. During driver activity we should enable
954 * SmartSpeed, so performance is maintained.
955 */
956 if (phy->smart_speed == e1000_smart_speed_on) {
957 ret_val = phy->ops.read_reg(hw,
958 IGP01E1000_PHY_PORT_CONFIG, &data);
959 if (ret_val)
960 goto out;
961
962 data |= IGP01E1000_PSCFR_SMART_SPEED;
963 ret_val = phy->ops.write_reg(hw,
964 IGP01E1000_PHY_PORT_CONFIG, data);
965 if (ret_val)
966 goto out;
967 } else if (phy->smart_speed == e1000_smart_speed_off) {
968 ret_val = phy->ops.read_reg(hw,
969 IGP01E1000_PHY_PORT_CONFIG, &data);
970 if (ret_val)
971 goto out;
972
973 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
974 ret_val = phy->ops.write_reg(hw,
975 IGP01E1000_PHY_PORT_CONFIG, data);
976 if (ret_val)
977 goto out;
978 }
979 }
980
981 out:
982 return ret_val;
983 }
984
985 /**
986 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
987 * @hw: pointer to the HW structure
988 * @active: true to enable LPLU, false to disable
989 *
990 * Sets the LPLU D0 state according to the active flag. When
991 * activating LPLU this function also disables smart speed
992 * and vice versa. LPLU will not be activated unless the
993 * device autonegotiation advertisement meets standards of
994 * either 10 or 10/100 or 10/100/1000 at all duplexes.
995 * This is a function pointer entry point only called by
996 * PHY setup routines.
997 **/
998 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
999 {
1000 struct e1000_phy_info *phy = &hw->phy;
1001 s32 ret_val = 0;
1002 u16 data;
1003
1004 data = rd32(E1000_82580_PHY_POWER_MGMT);
1005
1006 if (active) {
1007 data |= E1000_82580_PM_D0_LPLU;
1008
1009 /* When LPLU is enabled, we should disable SmartSpeed */
1010 data &= ~E1000_82580_PM_SPD;
1011 } else {
1012 data &= ~E1000_82580_PM_D0_LPLU;
1013
1014 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1015 * during Dx states where the power conservation is most
1016 * important. During driver activity we should enable
1017 * SmartSpeed, so performance is maintained.
1018 */
1019 if (phy->smart_speed == e1000_smart_speed_on)
1020 data |= E1000_82580_PM_SPD;
1021 else if (phy->smart_speed == e1000_smart_speed_off)
1022 data &= ~E1000_82580_PM_SPD; }
1023
1024 wr32(E1000_82580_PHY_POWER_MGMT, data);
1025 return ret_val;
1026 }
1027
1028 /**
1029 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1030 * @hw: pointer to the HW structure
1031 * @active: boolean used to enable/disable lplu
1032 *
1033 * Success returns 0, Failure returns 1
1034 *
1035 * The low power link up (lplu) state is set to the power management level D3
1036 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1037 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1038 * is used during Dx states where the power conservation is most important.
1039 * During driver activity, SmartSpeed should be enabled so performance is
1040 * maintained.
1041 **/
1042 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1043 {
1044 struct e1000_phy_info *phy = &hw->phy;
1045 s32 ret_val = 0;
1046 u16 data;
1047
1048 data = rd32(E1000_82580_PHY_POWER_MGMT);
1049
1050 if (!active) {
1051 data &= ~E1000_82580_PM_D3_LPLU;
1052 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1053 * during Dx states where the power conservation is most
1054 * important. During driver activity we should enable
1055 * SmartSpeed, so performance is maintained.
1056 */
1057 if (phy->smart_speed == e1000_smart_speed_on)
1058 data |= E1000_82580_PM_SPD;
1059 else if (phy->smart_speed == e1000_smart_speed_off)
1060 data &= ~E1000_82580_PM_SPD;
1061 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1062 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1063 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1064 data |= E1000_82580_PM_D3_LPLU;
1065 /* When LPLU is enabled, we should disable SmartSpeed */
1066 data &= ~E1000_82580_PM_SPD;
1067 }
1068
1069 wr32(E1000_82580_PHY_POWER_MGMT, data);
1070 return ret_val;
1071 }
1072
1073 /**
1074 * igb_acquire_nvm_82575 - Request for access to EEPROM
1075 * @hw: pointer to the HW structure
1076 *
1077 * Acquire the necessary semaphores for exclusive access to the EEPROM.
1078 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1079 * Return successful if access grant bit set, else clear the request for
1080 * EEPROM access and return -E1000_ERR_NVM (-1).
1081 **/
1082 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1083 {
1084 s32 ret_val;
1085
1086 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1087 if (ret_val)
1088 goto out;
1089
1090 ret_val = igb_acquire_nvm(hw);
1091
1092 if (ret_val)
1093 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1094
1095 out:
1096 return ret_val;
1097 }
1098
1099 /**
1100 * igb_release_nvm_82575 - Release exclusive access to EEPROM
1101 * @hw: pointer to the HW structure
1102 *
1103 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1104 * then release the semaphores acquired.
1105 **/
1106 static void igb_release_nvm_82575(struct e1000_hw *hw)
1107 {
1108 igb_release_nvm(hw);
1109 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1110 }
1111
1112 /**
1113 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1114 * @hw: pointer to the HW structure
1115 * @mask: specifies which semaphore to acquire
1116 *
1117 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1118 * will also specify which port we're acquiring the lock for.
1119 **/
1120 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1121 {
1122 u32 swfw_sync;
1123 u32 swmask = mask;
1124 u32 fwmask = mask << 16;
1125 s32 ret_val = 0;
1126 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1127
1128 while (i < timeout) {
1129 if (igb_get_hw_semaphore(hw)) {
1130 ret_val = -E1000_ERR_SWFW_SYNC;
1131 goto out;
1132 }
1133
1134 swfw_sync = rd32(E1000_SW_FW_SYNC);
1135 if (!(swfw_sync & (fwmask | swmask)))
1136 break;
1137
1138 /* Firmware currently using resource (fwmask)
1139 * or other software thread using resource (swmask)
1140 */
1141 igb_put_hw_semaphore(hw);
1142 mdelay(5);
1143 i++;
1144 }
1145
1146 if (i == timeout) {
1147 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1148 ret_val = -E1000_ERR_SWFW_SYNC;
1149 goto out;
1150 }
1151
1152 swfw_sync |= swmask;
1153 wr32(E1000_SW_FW_SYNC, swfw_sync);
1154
1155 igb_put_hw_semaphore(hw);
1156
1157 out:
1158 return ret_val;
1159 }
1160
1161 /**
1162 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
1163 * @hw: pointer to the HW structure
1164 * @mask: specifies which semaphore to acquire
1165 *
1166 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1167 * will also specify which port we're releasing the lock for.
1168 **/
1169 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1170 {
1171 u32 swfw_sync;
1172
1173 while (igb_get_hw_semaphore(hw) != 0);
1174 /* Empty */
1175
1176 swfw_sync = rd32(E1000_SW_FW_SYNC);
1177 swfw_sync &= ~mask;
1178 wr32(E1000_SW_FW_SYNC, swfw_sync);
1179
1180 igb_put_hw_semaphore(hw);
1181 }
1182
1183 /**
1184 * igb_get_cfg_done_82575 - Read config done bit
1185 * @hw: pointer to the HW structure
1186 *
1187 * Read the management control register for the config done bit for
1188 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1189 * to read the config done bit, so an error is *ONLY* logged and returns
1190 * 0. If we were to return with error, EEPROM-less silicon
1191 * would not be able to be reset or change link.
1192 **/
1193 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1194 {
1195 s32 timeout = PHY_CFG_TIMEOUT;
1196 s32 ret_val = 0;
1197 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1198
1199 if (hw->bus.func == 1)
1200 mask = E1000_NVM_CFG_DONE_PORT_1;
1201 else if (hw->bus.func == E1000_FUNC_2)
1202 mask = E1000_NVM_CFG_DONE_PORT_2;
1203 else if (hw->bus.func == E1000_FUNC_3)
1204 mask = E1000_NVM_CFG_DONE_PORT_3;
1205
1206 while (timeout) {
1207 if (rd32(E1000_EEMNGCTL) & mask)
1208 break;
1209 msleep(1);
1210 timeout--;
1211 }
1212 if (!timeout)
1213 hw_dbg("MNG configuration cycle has not completed.\n");
1214
1215 /* If EEPROM is not marked present, init the PHY manually */
1216 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1217 (hw->phy.type == e1000_phy_igp_3))
1218 igb_phy_init_script_igp3(hw);
1219
1220 return ret_val;
1221 }
1222
1223 /**
1224 * igb_get_link_up_info_82575 - Get link speed/duplex info
1225 * @hw: pointer to the HW structure
1226 * @speed: stores the current speed
1227 * @duplex: stores the current duplex
1228 *
1229 * This is a wrapper function, if using the serial gigabit media independent
1230 * interface, use PCS to retrieve the link speed and duplex information.
1231 * Otherwise, use the generic function to get the link speed and duplex info.
1232 **/
1233 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1234 u16 *duplex)
1235 {
1236 s32 ret_val;
1237
1238 if (hw->phy.media_type != e1000_media_type_copper)
1239 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1240 duplex);
1241 else
1242 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1243 duplex);
1244
1245 return ret_val;
1246 }
1247
1248 /**
1249 * igb_check_for_link_82575 - Check for link
1250 * @hw: pointer to the HW structure
1251 *
1252 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1253 * use the generic interface for determining link.
1254 **/
1255 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1256 {
1257 s32 ret_val;
1258 u16 speed, duplex;
1259
1260 if (hw->phy.media_type != e1000_media_type_copper) {
1261 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1262 &duplex);
1263 /* Use this flag to determine if link needs to be checked or
1264 * not. If we have link clear the flag so that we do not
1265 * continue to check for link.
1266 */
1267 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1268
1269 /* Configure Flow Control now that Auto-Neg has completed.
1270 * First, we need to restore the desired flow control
1271 * settings because we may have had to re-autoneg with a
1272 * different link partner.
1273 */
1274 ret_val = igb_config_fc_after_link_up(hw);
1275 if (ret_val)
1276 hw_dbg("Error configuring flow control\n");
1277 } else {
1278 ret_val = igb_check_for_copper_link(hw);
1279 }
1280
1281 return ret_val;
1282 }
1283
1284 /**
1285 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1286 * @hw: pointer to the HW structure
1287 **/
1288 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1289 {
1290 u32 reg;
1291
1292
1293 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1294 !igb_sgmii_active_82575(hw))
1295 return;
1296
1297 /* Enable PCS to turn on link */
1298 reg = rd32(E1000_PCS_CFG0);
1299 reg |= E1000_PCS_CFG_PCS_EN;
1300 wr32(E1000_PCS_CFG0, reg);
1301
1302 /* Power up the laser */
1303 reg = rd32(E1000_CTRL_EXT);
1304 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1305 wr32(E1000_CTRL_EXT, reg);
1306
1307 /* flush the write to verify completion */
1308 wrfl();
1309 msleep(1);
1310 }
1311
1312 /**
1313 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1314 * @hw: pointer to the HW structure
1315 * @speed: stores the current speed
1316 * @duplex: stores the current duplex
1317 *
1318 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1319 * duplex, then store the values in the pointers provided.
1320 **/
1321 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1322 u16 *duplex)
1323 {
1324 struct e1000_mac_info *mac = &hw->mac;
1325 u32 pcs, status;
1326
1327 /* Set up defaults for the return values of this function */
1328 mac->serdes_has_link = false;
1329 *speed = 0;
1330 *duplex = 0;
1331
1332 /* Read the PCS Status register for link state. For non-copper mode,
1333 * the status register is not accurate. The PCS status register is
1334 * used instead.
1335 */
1336 pcs = rd32(E1000_PCS_LSTAT);
1337
1338 /* The link up bit determines when link is up on autoneg. The sync ok
1339 * gets set once both sides sync up and agree upon link. Stable link
1340 * can be determined by checking for both link up and link sync ok
1341 */
1342 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1343 mac->serdes_has_link = true;
1344
1345 /* Detect and store PCS speed */
1346 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1347 *speed = SPEED_1000;
1348 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1349 *speed = SPEED_100;
1350 else
1351 *speed = SPEED_10;
1352
1353 /* Detect and store PCS duplex */
1354 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1355 *duplex = FULL_DUPLEX;
1356 else
1357 *duplex = HALF_DUPLEX;
1358
1359 /* Check if it is an I354 2.5Gb backplane connection. */
1360 if (mac->type == e1000_i354) {
1361 status = rd32(E1000_STATUS);
1362 if ((status & E1000_STATUS_2P5_SKU) &&
1363 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1364 *speed = SPEED_2500;
1365 *duplex = FULL_DUPLEX;
1366 hw_dbg("2500 Mbs, ");
1367 hw_dbg("Full Duplex\n");
1368 }
1369 }
1370
1371 }
1372
1373 return 0;
1374 }
1375
1376 /**
1377 * igb_shutdown_serdes_link_82575 - Remove link during power down
1378 * @hw: pointer to the HW structure
1379 *
1380 * In the case of fiber serdes, shut down optics and PCS on driver unload
1381 * when management pass thru is not enabled.
1382 **/
1383 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1384 {
1385 u32 reg;
1386
1387 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1388 igb_sgmii_active_82575(hw))
1389 return;
1390
1391 if (!igb_enable_mng_pass_thru(hw)) {
1392 /* Disable PCS to turn off link */
1393 reg = rd32(E1000_PCS_CFG0);
1394 reg &= ~E1000_PCS_CFG_PCS_EN;
1395 wr32(E1000_PCS_CFG0, reg);
1396
1397 /* shutdown the laser */
1398 reg = rd32(E1000_CTRL_EXT);
1399 reg |= E1000_CTRL_EXT_SDP3_DATA;
1400 wr32(E1000_CTRL_EXT, reg);
1401
1402 /* flush the write to verify completion */
1403 wrfl();
1404 msleep(1);
1405 }
1406 }
1407
1408 /**
1409 * igb_reset_hw_82575 - Reset hardware
1410 * @hw: pointer to the HW structure
1411 *
1412 * This resets the hardware into a known state. This is a
1413 * function pointer entry point called by the api module.
1414 **/
1415 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1416 {
1417 u32 ctrl;
1418 s32 ret_val;
1419
1420 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1421 * on the last TLP read/write transaction when MAC is reset.
1422 */
1423 ret_val = igb_disable_pcie_master(hw);
1424 if (ret_val)
1425 hw_dbg("PCI-E Master disable polling has failed.\n");
1426
1427 /* set the completion timeout for interface */
1428 ret_val = igb_set_pcie_completion_timeout(hw);
1429 if (ret_val) {
1430 hw_dbg("PCI-E Set completion timeout has failed.\n");
1431 }
1432
1433 hw_dbg("Masking off all interrupts\n");
1434 wr32(E1000_IMC, 0xffffffff);
1435
1436 wr32(E1000_RCTL, 0);
1437 wr32(E1000_TCTL, E1000_TCTL_PSP);
1438 wrfl();
1439
1440 msleep(10);
1441
1442 ctrl = rd32(E1000_CTRL);
1443
1444 hw_dbg("Issuing a global reset to MAC\n");
1445 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1446
1447 ret_val = igb_get_auto_rd_done(hw);
1448 if (ret_val) {
1449 /* When auto config read does not complete, do not
1450 * return with an error. This can happen in situations
1451 * where there is no eeprom and prevents getting link.
1452 */
1453 hw_dbg("Auto Read Done did not complete\n");
1454 }
1455
1456 /* If EEPROM is not present, run manual init scripts */
1457 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1458 igb_reset_init_script_82575(hw);
1459
1460 /* Clear any pending interrupt events. */
1461 wr32(E1000_IMC, 0xffffffff);
1462 rd32(E1000_ICR);
1463
1464 /* Install any alternate MAC address into RAR0 */
1465 ret_val = igb_check_alt_mac_addr(hw);
1466
1467 return ret_val;
1468 }
1469
1470 /**
1471 * igb_init_hw_82575 - Initialize hardware
1472 * @hw: pointer to the HW structure
1473 *
1474 * This inits the hardware readying it for operation.
1475 **/
1476 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1477 {
1478 struct e1000_mac_info *mac = &hw->mac;
1479 s32 ret_val;
1480 u16 i, rar_count = mac->rar_entry_count;
1481
1482 /* Initialize identification LED */
1483 ret_val = igb_id_led_init(hw);
1484 if (ret_val) {
1485 hw_dbg("Error initializing identification LED\n");
1486 /* This is not fatal and we should not stop init due to this */
1487 }
1488
1489 /* Disabling VLAN filtering */
1490 hw_dbg("Initializing the IEEE VLAN\n");
1491 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1492 igb_clear_vfta_i350(hw);
1493 else
1494 igb_clear_vfta(hw);
1495
1496 /* Setup the receive address */
1497 igb_init_rx_addrs(hw, rar_count);
1498
1499 /* Zero out the Multicast HASH table */
1500 hw_dbg("Zeroing the MTA\n");
1501 for (i = 0; i < mac->mta_reg_count; i++)
1502 array_wr32(E1000_MTA, i, 0);
1503
1504 /* Zero out the Unicast HASH table */
1505 hw_dbg("Zeroing the UTA\n");
1506 for (i = 0; i < mac->uta_reg_count; i++)
1507 array_wr32(E1000_UTA, i, 0);
1508
1509 /* Setup link and flow control */
1510 ret_val = igb_setup_link(hw);
1511
1512 /* Clear all of the statistics registers (clear on read). It is
1513 * important that we do this after we have tried to establish link
1514 * because the symbol error count will increment wildly if there
1515 * is no link.
1516 */
1517 igb_clear_hw_cntrs_82575(hw);
1518 return ret_val;
1519 }
1520
1521 /**
1522 * igb_setup_copper_link_82575 - Configure copper link settings
1523 * @hw: pointer to the HW structure
1524 *
1525 * Configures the link for auto-neg or forced speed and duplex. Then we check
1526 * for link, once link is established calls to configure collision distance
1527 * and flow control are called.
1528 **/
1529 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1530 {
1531 u32 ctrl;
1532 s32 ret_val;
1533 u32 phpm_reg;
1534
1535 ctrl = rd32(E1000_CTRL);
1536 ctrl |= E1000_CTRL_SLU;
1537 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1538 wr32(E1000_CTRL, ctrl);
1539
1540 /* Clear Go Link Disconnect bit on supported devices */
1541 switch (hw->mac.type) {
1542 case e1000_82580:
1543 case e1000_i350:
1544 case e1000_i210:
1545 case e1000_i211:
1546 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1547 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1548 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1549 break;
1550 default:
1551 break;
1552 }
1553
1554 ret_val = igb_setup_serdes_link_82575(hw);
1555 if (ret_val)
1556 goto out;
1557
1558 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1559 /* allow time for SFP cage time to power up phy */
1560 msleep(300);
1561
1562 ret_val = hw->phy.ops.reset(hw);
1563 if (ret_val) {
1564 hw_dbg("Error resetting the PHY.\n");
1565 goto out;
1566 }
1567 }
1568 switch (hw->phy.type) {
1569 case e1000_phy_i210:
1570 case e1000_phy_m88:
1571 switch (hw->phy.id) {
1572 case I347AT4_E_PHY_ID:
1573 case M88E1112_E_PHY_ID:
1574 case M88E1543_E_PHY_ID:
1575 case I210_I_PHY_ID:
1576 ret_val = igb_copper_link_setup_m88_gen2(hw);
1577 break;
1578 default:
1579 ret_val = igb_copper_link_setup_m88(hw);
1580 break;
1581 }
1582 break;
1583 case e1000_phy_igp_3:
1584 ret_val = igb_copper_link_setup_igp(hw);
1585 break;
1586 case e1000_phy_82580:
1587 ret_val = igb_copper_link_setup_82580(hw);
1588 break;
1589 default:
1590 ret_val = -E1000_ERR_PHY;
1591 break;
1592 }
1593
1594 if (ret_val)
1595 goto out;
1596
1597 ret_val = igb_setup_copper_link(hw);
1598 out:
1599 return ret_val;
1600 }
1601
1602 /**
1603 * igb_setup_serdes_link_82575 - Setup link for serdes
1604 * @hw: pointer to the HW structure
1605 *
1606 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1607 * used on copper connections where the serialized gigabit media independent
1608 * interface (sgmii), or serdes fiber is being used. Configures the link
1609 * for auto-negotiation or forces speed/duplex.
1610 **/
1611 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1612 {
1613 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1614 bool pcs_autoneg;
1615 s32 ret_val = E1000_SUCCESS;
1616 u16 data;
1617
1618 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1619 !igb_sgmii_active_82575(hw))
1620 return ret_val;
1621
1622
1623 /* On the 82575, SerDes loopback mode persists until it is
1624 * explicitly turned off or a power cycle is performed. A read to
1625 * the register does not indicate its status. Therefore, we ensure
1626 * loopback mode is disabled during initialization.
1627 */
1628 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1629
1630 /* power on the sfp cage if present and turn on I2C */
1631 ctrl_ext = rd32(E1000_CTRL_EXT);
1632 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1633 ctrl_ext |= E1000_CTRL_I2C_ENA;
1634 wr32(E1000_CTRL_EXT, ctrl_ext);
1635
1636 ctrl_reg = rd32(E1000_CTRL);
1637 ctrl_reg |= E1000_CTRL_SLU;
1638
1639 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1640 /* set both sw defined pins */
1641 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1642
1643 /* Set switch control to serdes energy detect */
1644 reg = rd32(E1000_CONNSW);
1645 reg |= E1000_CONNSW_ENRGSRC;
1646 wr32(E1000_CONNSW, reg);
1647 }
1648
1649 reg = rd32(E1000_PCS_LCTL);
1650
1651 /* default pcs_autoneg to the same setting as mac autoneg */
1652 pcs_autoneg = hw->mac.autoneg;
1653
1654 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1655 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1656 /* sgmii mode lets the phy handle forcing speed/duplex */
1657 pcs_autoneg = true;
1658 /* autoneg time out should be disabled for SGMII mode */
1659 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1660 break;
1661 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1662 /* disable PCS autoneg and support parallel detect only */
1663 pcs_autoneg = false;
1664 default:
1665 if (hw->mac.type == e1000_82575 ||
1666 hw->mac.type == e1000_82576) {
1667 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1668 if (ret_val) {
1669 printk(KERN_DEBUG "NVM Read Error\n\n");
1670 return ret_val;
1671 }
1672
1673 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1674 pcs_autoneg = false;
1675 }
1676
1677 /* non-SGMII modes only supports a speed of 1000/Full for the
1678 * link so it is best to just force the MAC and let the pcs
1679 * link either autoneg or be forced to 1000/Full
1680 */
1681 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1682 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1683
1684 /* set speed of 1000/Full if speed/duplex is forced */
1685 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1686 break;
1687 }
1688
1689 wr32(E1000_CTRL, ctrl_reg);
1690
1691 /* New SerDes mode allows for forcing speed or autonegotiating speed
1692 * at 1gb. Autoneg should be default set by most drivers. This is the
1693 * mode that will be compatible with older link partners and switches.
1694 * However, both are supported by the hardware and some drivers/tools.
1695 */
1696 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1697 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1698
1699 if (pcs_autoneg) {
1700 /* Set PCS register for autoneg */
1701 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1702 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1703
1704 /* Disable force flow control for autoneg */
1705 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1706
1707 /* Configure flow control advertisement for autoneg */
1708 anadv_reg = rd32(E1000_PCS_ANADV);
1709 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1710 switch (hw->fc.requested_mode) {
1711 case e1000_fc_full:
1712 case e1000_fc_rx_pause:
1713 anadv_reg |= E1000_TXCW_ASM_DIR;
1714 anadv_reg |= E1000_TXCW_PAUSE;
1715 break;
1716 case e1000_fc_tx_pause:
1717 anadv_reg |= E1000_TXCW_ASM_DIR;
1718 break;
1719 default:
1720 break;
1721 }
1722 wr32(E1000_PCS_ANADV, anadv_reg);
1723
1724 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1725 } else {
1726 /* Set PCS register for forced link */
1727 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1728
1729 /* Force flow control for forced link */
1730 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1731
1732 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1733 }
1734
1735 wr32(E1000_PCS_LCTL, reg);
1736
1737 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1738 igb_force_mac_fc(hw);
1739
1740 return ret_val;
1741 }
1742
1743 /**
1744 * igb_sgmii_active_82575 - Return sgmii state
1745 * @hw: pointer to the HW structure
1746 *
1747 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1748 * which can be enabled for use in the embedded applications. Simply
1749 * return the current state of the sgmii interface.
1750 **/
1751 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1752 {
1753 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1754 return dev_spec->sgmii_active;
1755 }
1756
1757 /**
1758 * igb_reset_init_script_82575 - Inits HW defaults after reset
1759 * @hw: pointer to the HW structure
1760 *
1761 * Inits recommended HW defaults after a reset when there is no EEPROM
1762 * detected. This is only for the 82575.
1763 **/
1764 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1765 {
1766 if (hw->mac.type == e1000_82575) {
1767 hw_dbg("Running reset init script for 82575\n");
1768 /* SerDes configuration via SERDESCTRL */
1769 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1770 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1771 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1772 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1773
1774 /* CCM configuration via CCMCTL register */
1775 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1776 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1777
1778 /* PCIe lanes configuration */
1779 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1780 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1781 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1782 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1783
1784 /* PCIe PLL Configuration */
1785 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1786 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1787 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1788 }
1789
1790 return 0;
1791 }
1792
1793 /**
1794 * igb_read_mac_addr_82575 - Read device MAC address
1795 * @hw: pointer to the HW structure
1796 **/
1797 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1798 {
1799 s32 ret_val = 0;
1800
1801 /* If there's an alternate MAC address place it in RAR0
1802 * so that it will override the Si installed default perm
1803 * address.
1804 */
1805 ret_val = igb_check_alt_mac_addr(hw);
1806 if (ret_val)
1807 goto out;
1808
1809 ret_val = igb_read_mac_addr(hw);
1810
1811 out:
1812 return ret_val;
1813 }
1814
1815 /**
1816 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1817 * @hw: pointer to the HW structure
1818 *
1819 * In the case of a PHY power down to save power, or to turn off link during a
1820 * driver unload, or wake on lan is not enabled, remove the link.
1821 **/
1822 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1823 {
1824 /* If the management interface is not enabled, then power down */
1825 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1826 igb_power_down_phy_copper(hw);
1827 }
1828
1829 /**
1830 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1831 * @hw: pointer to the HW structure
1832 *
1833 * Clears the hardware counters by reading the counter registers.
1834 **/
1835 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1836 {
1837 igb_clear_hw_cntrs_base(hw);
1838
1839 rd32(E1000_PRC64);
1840 rd32(E1000_PRC127);
1841 rd32(E1000_PRC255);
1842 rd32(E1000_PRC511);
1843 rd32(E1000_PRC1023);
1844 rd32(E1000_PRC1522);
1845 rd32(E1000_PTC64);
1846 rd32(E1000_PTC127);
1847 rd32(E1000_PTC255);
1848 rd32(E1000_PTC511);
1849 rd32(E1000_PTC1023);
1850 rd32(E1000_PTC1522);
1851
1852 rd32(E1000_ALGNERRC);
1853 rd32(E1000_RXERRC);
1854 rd32(E1000_TNCRS);
1855 rd32(E1000_CEXTERR);
1856 rd32(E1000_TSCTC);
1857 rd32(E1000_TSCTFC);
1858
1859 rd32(E1000_MGTPRC);
1860 rd32(E1000_MGTPDC);
1861 rd32(E1000_MGTPTC);
1862
1863 rd32(E1000_IAC);
1864 rd32(E1000_ICRXOC);
1865
1866 rd32(E1000_ICRXPTC);
1867 rd32(E1000_ICRXATC);
1868 rd32(E1000_ICTXPTC);
1869 rd32(E1000_ICTXATC);
1870 rd32(E1000_ICTXQEC);
1871 rd32(E1000_ICTXQMTC);
1872 rd32(E1000_ICRXDMTC);
1873
1874 rd32(E1000_CBTMPC);
1875 rd32(E1000_HTDPMC);
1876 rd32(E1000_CBRMPC);
1877 rd32(E1000_RPTHC);
1878 rd32(E1000_HGPTC);
1879 rd32(E1000_HTCBDPC);
1880 rd32(E1000_HGORCL);
1881 rd32(E1000_HGORCH);
1882 rd32(E1000_HGOTCL);
1883 rd32(E1000_HGOTCH);
1884 rd32(E1000_LENERRS);
1885
1886 /* This register should not be read in copper configurations */
1887 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1888 igb_sgmii_active_82575(hw))
1889 rd32(E1000_SCVPC);
1890 }
1891
1892 /**
1893 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1894 * @hw: pointer to the HW structure
1895 *
1896 * After rx enable if managability is enabled then there is likely some
1897 * bad data at the start of the fifo and possibly in the DMA fifo. This
1898 * function clears the fifos and flushes any packets that came in as rx was
1899 * being enabled.
1900 **/
1901 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1902 {
1903 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1904 int i, ms_wait;
1905
1906 if (hw->mac.type != e1000_82575 ||
1907 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1908 return;
1909
1910 /* Disable all RX queues */
1911 for (i = 0; i < 4; i++) {
1912 rxdctl[i] = rd32(E1000_RXDCTL(i));
1913 wr32(E1000_RXDCTL(i),
1914 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1915 }
1916 /* Poll all queues to verify they have shut down */
1917 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1918 msleep(1);
1919 rx_enabled = 0;
1920 for (i = 0; i < 4; i++)
1921 rx_enabled |= rd32(E1000_RXDCTL(i));
1922 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1923 break;
1924 }
1925
1926 if (ms_wait == 10)
1927 hw_dbg("Queue disable timed out after 10ms\n");
1928
1929 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1930 * incoming packets are rejected. Set enable and wait 2ms so that
1931 * any packet that was coming in as RCTL.EN was set is flushed
1932 */
1933 rfctl = rd32(E1000_RFCTL);
1934 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1935
1936 rlpml = rd32(E1000_RLPML);
1937 wr32(E1000_RLPML, 0);
1938
1939 rctl = rd32(E1000_RCTL);
1940 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1941 temp_rctl |= E1000_RCTL_LPE;
1942
1943 wr32(E1000_RCTL, temp_rctl);
1944 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1945 wrfl();
1946 msleep(2);
1947
1948 /* Enable RX queues that were previously enabled and restore our
1949 * previous state
1950 */
1951 for (i = 0; i < 4; i++)
1952 wr32(E1000_RXDCTL(i), rxdctl[i]);
1953 wr32(E1000_RCTL, rctl);
1954 wrfl();
1955
1956 wr32(E1000_RLPML, rlpml);
1957 wr32(E1000_RFCTL, rfctl);
1958
1959 /* Flush receive errors generated by workaround */
1960 rd32(E1000_ROC);
1961 rd32(E1000_RNBC);
1962 rd32(E1000_MPC);
1963 }
1964
1965 /**
1966 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1967 * @hw: pointer to the HW structure
1968 *
1969 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1970 * however the hardware default for these parts is 500us to 1ms which is less
1971 * than the 10ms recommended by the pci-e spec. To address this we need to
1972 * increase the value to either 10ms to 200ms for capability version 1 config,
1973 * or 16ms to 55ms for version 2.
1974 **/
1975 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1976 {
1977 u32 gcr = rd32(E1000_GCR);
1978 s32 ret_val = 0;
1979 u16 pcie_devctl2;
1980
1981 /* only take action if timeout value is defaulted to 0 */
1982 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1983 goto out;
1984
1985 /* if capabilities version is type 1 we can write the
1986 * timeout of 10ms to 200ms through the GCR register
1987 */
1988 if (!(gcr & E1000_GCR_CAP_VER2)) {
1989 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1990 goto out;
1991 }
1992
1993 /* for version 2 capabilities we need to write the config space
1994 * directly in order to set the completion timeout value for
1995 * 16ms to 55ms
1996 */
1997 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1998 &pcie_devctl2);
1999 if (ret_val)
2000 goto out;
2001
2002 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2003
2004 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2005 &pcie_devctl2);
2006 out:
2007 /* disable completion timeout resend */
2008 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2009
2010 wr32(E1000_GCR, gcr);
2011 return ret_val;
2012 }
2013
2014 /**
2015 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2016 * @hw: pointer to the hardware struct
2017 * @enable: state to enter, either enabled or disabled
2018 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2019 *
2020 * enables/disables L2 switch anti-spoofing functionality.
2021 **/
2022 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2023 {
2024 u32 reg_val, reg_offset;
2025
2026 switch (hw->mac.type) {
2027 case e1000_82576:
2028 reg_offset = E1000_DTXSWC;
2029 break;
2030 case e1000_i350:
2031 case e1000_i354:
2032 reg_offset = E1000_TXSWC;
2033 break;
2034 default:
2035 return;
2036 }
2037
2038 reg_val = rd32(reg_offset);
2039 if (enable) {
2040 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2041 E1000_DTXSWC_VLAN_SPOOF_MASK);
2042 /* The PF can spoof - it has to in order to
2043 * support emulation mode NICs
2044 */
2045 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2046 } else {
2047 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2048 E1000_DTXSWC_VLAN_SPOOF_MASK);
2049 }
2050 wr32(reg_offset, reg_val);
2051 }
2052
2053 /**
2054 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2055 * @hw: pointer to the hardware struct
2056 * @enable: state to enter, either enabled or disabled
2057 *
2058 * enables/disables L2 switch loopback functionality.
2059 **/
2060 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2061 {
2062 u32 dtxswc;
2063
2064 switch (hw->mac.type) {
2065 case e1000_82576:
2066 dtxswc = rd32(E1000_DTXSWC);
2067 if (enable)
2068 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2069 else
2070 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2071 wr32(E1000_DTXSWC, dtxswc);
2072 break;
2073 case e1000_i354:
2074 case e1000_i350:
2075 dtxswc = rd32(E1000_TXSWC);
2076 if (enable)
2077 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2078 else
2079 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2080 wr32(E1000_TXSWC, dtxswc);
2081 break;
2082 default:
2083 /* Currently no other hardware supports loopback */
2084 break;
2085 }
2086
2087 }
2088
2089 /**
2090 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2091 * @hw: pointer to the hardware struct
2092 * @enable: state to enter, either enabled or disabled
2093 *
2094 * enables/disables replication of packets across multiple pools.
2095 **/
2096 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2097 {
2098 u32 vt_ctl = rd32(E1000_VT_CTL);
2099
2100 if (enable)
2101 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2102 else
2103 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2104
2105 wr32(E1000_VT_CTL, vt_ctl);
2106 }
2107
2108 /**
2109 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2110 * @hw: pointer to the HW structure
2111 * @offset: register offset to be read
2112 * @data: pointer to the read data
2113 *
2114 * Reads the MDI control register in the PHY at offset and stores the
2115 * information read to data.
2116 **/
2117 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2118 {
2119 s32 ret_val;
2120
2121 ret_val = hw->phy.ops.acquire(hw);
2122 if (ret_val)
2123 goto out;
2124
2125 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2126
2127 hw->phy.ops.release(hw);
2128
2129 out:
2130 return ret_val;
2131 }
2132
2133 /**
2134 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2135 * @hw: pointer to the HW structure
2136 * @offset: register offset to write to
2137 * @data: data to write to register at offset
2138 *
2139 * Writes data to MDI control register in the PHY at offset.
2140 **/
2141 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2142 {
2143 s32 ret_val;
2144
2145
2146 ret_val = hw->phy.ops.acquire(hw);
2147 if (ret_val)
2148 goto out;
2149
2150 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2151
2152 hw->phy.ops.release(hw);
2153
2154 out:
2155 return ret_val;
2156 }
2157
2158 /**
2159 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2160 * @hw: pointer to the HW structure
2161 *
2162 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2163 * the values found in the EEPROM. This addresses an issue in which these
2164 * bits are not restored from EEPROM after reset.
2165 **/
2166 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2167 {
2168 s32 ret_val = 0;
2169 u32 mdicnfg;
2170 u16 nvm_data = 0;
2171
2172 if (hw->mac.type != e1000_82580)
2173 goto out;
2174 if (!igb_sgmii_active_82575(hw))
2175 goto out;
2176
2177 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2178 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2179 &nvm_data);
2180 if (ret_val) {
2181 hw_dbg("NVM Read Error\n");
2182 goto out;
2183 }
2184
2185 mdicnfg = rd32(E1000_MDICNFG);
2186 if (nvm_data & NVM_WORD24_EXT_MDIO)
2187 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2188 if (nvm_data & NVM_WORD24_COM_MDIO)
2189 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2190 wr32(E1000_MDICNFG, mdicnfg);
2191 out:
2192 return ret_val;
2193 }
2194
2195 /**
2196 * igb_reset_hw_82580 - Reset hardware
2197 * @hw: pointer to the HW structure
2198 *
2199 * This resets function or entire device (all ports, etc.)
2200 * to a known state.
2201 **/
2202 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2203 {
2204 s32 ret_val = 0;
2205 /* BH SW mailbox bit in SW_FW_SYNC */
2206 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2207 u32 ctrl;
2208 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2209
2210 hw->dev_spec._82575.global_device_reset = false;
2211
2212 /* due to hw errata, global device reset doesn't always
2213 * work on 82580
2214 */
2215 if (hw->mac.type == e1000_82580)
2216 global_device_reset = false;
2217
2218 /* Get current control state. */
2219 ctrl = rd32(E1000_CTRL);
2220
2221 /* Prevent the PCI-E bus from sticking if there is no TLP connection
2222 * on the last TLP read/write transaction when MAC is reset.
2223 */
2224 ret_val = igb_disable_pcie_master(hw);
2225 if (ret_val)
2226 hw_dbg("PCI-E Master disable polling has failed.\n");
2227
2228 hw_dbg("Masking off all interrupts\n");
2229 wr32(E1000_IMC, 0xffffffff);
2230 wr32(E1000_RCTL, 0);
2231 wr32(E1000_TCTL, E1000_TCTL_PSP);
2232 wrfl();
2233
2234 msleep(10);
2235
2236 /* Determine whether or not a global dev reset is requested */
2237 if (global_device_reset &&
2238 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2239 global_device_reset = false;
2240
2241 if (global_device_reset &&
2242 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2243 ctrl |= E1000_CTRL_DEV_RST;
2244 else
2245 ctrl |= E1000_CTRL_RST;
2246
2247 wr32(E1000_CTRL, ctrl);
2248 wrfl();
2249
2250 /* Add delay to insure DEV_RST has time to complete */
2251 if (global_device_reset)
2252 msleep(5);
2253
2254 ret_val = igb_get_auto_rd_done(hw);
2255 if (ret_val) {
2256 /* When auto config read does not complete, do not
2257 * return with an error. This can happen in situations
2258 * where there is no eeprom and prevents getting link.
2259 */
2260 hw_dbg("Auto Read Done did not complete\n");
2261 }
2262
2263 /* clear global device reset status bit */
2264 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2265
2266 /* Clear any pending interrupt events. */
2267 wr32(E1000_IMC, 0xffffffff);
2268 rd32(E1000_ICR);
2269
2270 ret_val = igb_reset_mdicnfg_82580(hw);
2271 if (ret_val)
2272 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2273
2274 /* Install any alternate MAC address into RAR0 */
2275 ret_val = igb_check_alt_mac_addr(hw);
2276
2277 /* Release semaphore */
2278 if (global_device_reset)
2279 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2280
2281 return ret_val;
2282 }
2283
2284 /**
2285 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2286 * @data: data received by reading RXPBS register
2287 *
2288 * The 82580 uses a table based approach for packet buffer allocation sizes.
2289 * This function converts the retrieved value into the correct table value
2290 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2291 * 0x0 36 72 144 1 2 4 8 16
2292 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2293 */
2294 u16 igb_rxpbs_adjust_82580(u32 data)
2295 {
2296 u16 ret_val = 0;
2297
2298 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2299 ret_val = e1000_82580_rxpbs_table[data];
2300
2301 return ret_val;
2302 }
2303
2304 /**
2305 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2306 * checksum
2307 * @hw: pointer to the HW structure
2308 * @offset: offset in words of the checksum protected region
2309 *
2310 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2311 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2312 **/
2313 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2314 u16 offset)
2315 {
2316 s32 ret_val = 0;
2317 u16 checksum = 0;
2318 u16 i, nvm_data;
2319
2320 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2321 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2322 if (ret_val) {
2323 hw_dbg("NVM Read Error\n");
2324 goto out;
2325 }
2326 checksum += nvm_data;
2327 }
2328
2329 if (checksum != (u16) NVM_SUM) {
2330 hw_dbg("NVM Checksum Invalid\n");
2331 ret_val = -E1000_ERR_NVM;
2332 goto out;
2333 }
2334
2335 out:
2336 return ret_val;
2337 }
2338
2339 /**
2340 * igb_update_nvm_checksum_with_offset - Update EEPROM
2341 * checksum
2342 * @hw: pointer to the HW structure
2343 * @offset: offset in words of the checksum protected region
2344 *
2345 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2346 * up to the checksum. Then calculates the EEPROM checksum and writes the
2347 * value to the EEPROM.
2348 **/
2349 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2350 {
2351 s32 ret_val;
2352 u16 checksum = 0;
2353 u16 i, nvm_data;
2354
2355 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2356 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2357 if (ret_val) {
2358 hw_dbg("NVM Read Error while updating checksum.\n");
2359 goto out;
2360 }
2361 checksum += nvm_data;
2362 }
2363 checksum = (u16) NVM_SUM - checksum;
2364 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2365 &checksum);
2366 if (ret_val)
2367 hw_dbg("NVM Write Error while updating checksum.\n");
2368
2369 out:
2370 return ret_val;
2371 }
2372
2373 /**
2374 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2375 * @hw: pointer to the HW structure
2376 *
2377 * Calculates the EEPROM section checksum by reading/adding each word of
2378 * the EEPROM and then verifies that the sum of the EEPROM is
2379 * equal to 0xBABA.
2380 **/
2381 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2382 {
2383 s32 ret_val = 0;
2384 u16 eeprom_regions_count = 1;
2385 u16 j, nvm_data;
2386 u16 nvm_offset;
2387
2388 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2389 if (ret_val) {
2390 hw_dbg("NVM Read Error\n");
2391 goto out;
2392 }
2393
2394 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2395 /* if checksums compatibility bit is set validate checksums
2396 * for all 4 ports.
2397 */
2398 eeprom_regions_count = 4;
2399 }
2400
2401 for (j = 0; j < eeprom_regions_count; j++) {
2402 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2403 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2404 nvm_offset);
2405 if (ret_val != 0)
2406 goto out;
2407 }
2408
2409 out:
2410 return ret_val;
2411 }
2412
2413 /**
2414 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2415 * @hw: pointer to the HW structure
2416 *
2417 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2418 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2419 * checksum and writes the value to the EEPROM.
2420 **/
2421 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2422 {
2423 s32 ret_val;
2424 u16 j, nvm_data;
2425 u16 nvm_offset;
2426
2427 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2428 if (ret_val) {
2429 hw_dbg("NVM Read Error while updating checksum"
2430 " compatibility bit.\n");
2431 goto out;
2432 }
2433
2434 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2435 /* set compatibility bit to validate checksums appropriately */
2436 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2437 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2438 &nvm_data);
2439 if (ret_val) {
2440 hw_dbg("NVM Write Error while updating checksum"
2441 " compatibility bit.\n");
2442 goto out;
2443 }
2444 }
2445
2446 for (j = 0; j < 4; j++) {
2447 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2448 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2449 if (ret_val)
2450 goto out;
2451 }
2452
2453 out:
2454 return ret_val;
2455 }
2456
2457 /**
2458 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2459 * @hw: pointer to the HW structure
2460 *
2461 * Calculates the EEPROM section checksum by reading/adding each word of
2462 * the EEPROM and then verifies that the sum of the EEPROM is
2463 * equal to 0xBABA.
2464 **/
2465 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2466 {
2467 s32 ret_val = 0;
2468 u16 j;
2469 u16 nvm_offset;
2470
2471 for (j = 0; j < 4; j++) {
2472 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2473 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2474 nvm_offset);
2475 if (ret_val != 0)
2476 goto out;
2477 }
2478
2479 out:
2480 return ret_val;
2481 }
2482
2483 /**
2484 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2485 * @hw: pointer to the HW structure
2486 *
2487 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2488 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2489 * checksum and writes the value to the EEPROM.
2490 **/
2491 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2492 {
2493 s32 ret_val = 0;
2494 u16 j;
2495 u16 nvm_offset;
2496
2497 for (j = 0; j < 4; j++) {
2498 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2499 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2500 if (ret_val != 0)
2501 goto out;
2502 }
2503
2504 out:
2505 return ret_val;
2506 }
2507
2508 /**
2509 * __igb_access_emi_reg - Read/write EMI register
2510 * @hw: pointer to the HW structure
2511 * @addr: EMI address to program
2512 * @data: pointer to value to read/write from/to the EMI address
2513 * @read: boolean flag to indicate read or write
2514 **/
2515 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2516 u16 *data, bool read)
2517 {
2518 s32 ret_val = E1000_SUCCESS;
2519
2520 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2521 if (ret_val)
2522 return ret_val;
2523
2524 if (read)
2525 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2526 else
2527 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2528
2529 return ret_val;
2530 }
2531
2532 /**
2533 * igb_read_emi_reg - Read Extended Management Interface register
2534 * @hw: pointer to the HW structure
2535 * @addr: EMI address to program
2536 * @data: value to be read from the EMI address
2537 **/
2538 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2539 {
2540 return __igb_access_emi_reg(hw, addr, data, true);
2541 }
2542
2543 /**
2544 * igb_set_eee_i350 - Enable/disable EEE support
2545 * @hw: pointer to the HW structure
2546 *
2547 * Enable/disable EEE based on setting in dev_spec structure.
2548 *
2549 **/
2550 s32 igb_set_eee_i350(struct e1000_hw *hw)
2551 {
2552 s32 ret_val = 0;
2553 u32 ipcnfg, eeer;
2554
2555 if ((hw->mac.type < e1000_i350) ||
2556 (hw->phy.media_type != e1000_media_type_copper))
2557 goto out;
2558 ipcnfg = rd32(E1000_IPCNFG);
2559 eeer = rd32(E1000_EEER);
2560
2561 /* enable or disable per user setting */
2562 if (!(hw->dev_spec._82575.eee_disable)) {
2563 u32 eee_su = rd32(E1000_EEE_SU);
2564
2565 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2566 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2567 E1000_EEER_LPI_FC);
2568
2569 /* This bit should not be set in normal operation. */
2570 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2571 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2572
2573 } else {
2574 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2575 E1000_IPCNFG_EEE_100M_AN);
2576 eeer &= ~(E1000_EEER_TX_LPI_EN |
2577 E1000_EEER_RX_LPI_EN |
2578 E1000_EEER_LPI_FC);
2579 }
2580 wr32(E1000_IPCNFG, ipcnfg);
2581 wr32(E1000_EEER, eeer);
2582 rd32(E1000_IPCNFG);
2583 rd32(E1000_EEER);
2584 out:
2585
2586 return ret_val;
2587 }
2588
2589 /**
2590 * igb_set_eee_i354 - Enable/disable EEE support
2591 * @hw: pointer to the HW structure
2592 *
2593 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2594 *
2595 **/
2596 s32 igb_set_eee_i354(struct e1000_hw *hw)
2597 {
2598 struct e1000_phy_info *phy = &hw->phy;
2599 s32 ret_val = 0;
2600 u16 phy_data;
2601
2602 if ((hw->phy.media_type != e1000_media_type_copper) ||
2603 (phy->id != M88E1543_E_PHY_ID))
2604 goto out;
2605
2606 if (!hw->dev_spec._82575.eee_disable) {
2607 /* Switch to PHY page 18. */
2608 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2609 if (ret_val)
2610 goto out;
2611
2612 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2613 &phy_data);
2614 if (ret_val)
2615 goto out;
2616
2617 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2619 phy_data);
2620 if (ret_val)
2621 goto out;
2622
2623 /* Return the PHY to page 0. */
2624 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2625 if (ret_val)
2626 goto out;
2627
2628 /* Turn on EEE advertisement. */
2629 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2630 E1000_EEE_ADV_DEV_I354,
2631 &phy_data);
2632 if (ret_val)
2633 goto out;
2634
2635 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2636 E1000_EEE_ADV_1000_SUPPORTED;
2637 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2638 E1000_EEE_ADV_DEV_I354,
2639 phy_data);
2640 } else {
2641 /* Turn off EEE advertisement. */
2642 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2643 E1000_EEE_ADV_DEV_I354,
2644 &phy_data);
2645 if (ret_val)
2646 goto out;
2647
2648 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2649 E1000_EEE_ADV_1000_SUPPORTED);
2650 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2651 E1000_EEE_ADV_DEV_I354,
2652 phy_data);
2653 }
2654
2655 out:
2656 return ret_val;
2657 }
2658
2659 /**
2660 * igb_get_eee_status_i354 - Get EEE status
2661 * @hw: pointer to the HW structure
2662 * @status: EEE status
2663 *
2664 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2665 * been received.
2666 **/
2667 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2668 {
2669 struct e1000_phy_info *phy = &hw->phy;
2670 s32 ret_val = 0;
2671 u16 phy_data;
2672
2673 /* Check if EEE is supported on this device. */
2674 if ((hw->phy.media_type != e1000_media_type_copper) ||
2675 (phy->id != M88E1543_E_PHY_ID))
2676 goto out;
2677
2678 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2679 E1000_PCS_STATUS_DEV_I354,
2680 &phy_data);
2681 if (ret_val)
2682 goto out;
2683
2684 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2685 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2686
2687 out:
2688 return ret_val;
2689 }
2690
2691 static const u8 e1000_emc_temp_data[4] = {
2692 E1000_EMC_INTERNAL_DATA,
2693 E1000_EMC_DIODE1_DATA,
2694 E1000_EMC_DIODE2_DATA,
2695 E1000_EMC_DIODE3_DATA
2696 };
2697 static const u8 e1000_emc_therm_limit[4] = {
2698 E1000_EMC_INTERNAL_THERM_LIMIT,
2699 E1000_EMC_DIODE1_THERM_LIMIT,
2700 E1000_EMC_DIODE2_THERM_LIMIT,
2701 E1000_EMC_DIODE3_THERM_LIMIT
2702 };
2703
2704 /**
2705 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2706 * @hw: pointer to hardware structure
2707 *
2708 * Updates the temperatures in mac.thermal_sensor_data
2709 **/
2710 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2711 {
2712 s32 status = E1000_SUCCESS;
2713 u16 ets_offset;
2714 u16 ets_cfg;
2715 u16 ets_sensor;
2716 u8 num_sensors;
2717 u8 sensor_index;
2718 u8 sensor_location;
2719 u8 i;
2720 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2721
2722 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2723 return E1000_NOT_IMPLEMENTED;
2724
2725 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2726
2727 /* Return the internal sensor only if ETS is unsupported */
2728 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2729 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2730 return status;
2731
2732 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2733 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2734 != NVM_ETS_TYPE_EMC)
2735 return E1000_NOT_IMPLEMENTED;
2736
2737 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2738 if (num_sensors > E1000_MAX_SENSORS)
2739 num_sensors = E1000_MAX_SENSORS;
2740
2741 for (i = 1; i < num_sensors; i++) {
2742 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2743 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2744 NVM_ETS_DATA_INDEX_SHIFT);
2745 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2746 NVM_ETS_DATA_LOC_SHIFT);
2747
2748 if (sensor_location != 0)
2749 hw->phy.ops.read_i2c_byte(hw,
2750 e1000_emc_temp_data[sensor_index],
2751 E1000_I2C_THERMAL_SENSOR_ADDR,
2752 &data->sensor[i].temp);
2753 }
2754 return status;
2755 }
2756
2757 /**
2758 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2759 * @hw: pointer to hardware structure
2760 *
2761 * Sets the thermal sensor thresholds according to the NVM map
2762 * and save off the threshold and location values into mac.thermal_sensor_data
2763 **/
2764 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2765 {
2766 s32 status = E1000_SUCCESS;
2767 u16 ets_offset;
2768 u16 ets_cfg;
2769 u16 ets_sensor;
2770 u8 low_thresh_delta;
2771 u8 num_sensors;
2772 u8 sensor_index;
2773 u8 sensor_location;
2774 u8 therm_limit;
2775 u8 i;
2776 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2777
2778 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2779 return E1000_NOT_IMPLEMENTED;
2780
2781 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2782
2783 data->sensor[0].location = 0x1;
2784 data->sensor[0].caution_thresh =
2785 (rd32(E1000_THHIGHTC) & 0xFF);
2786 data->sensor[0].max_op_thresh =
2787 (rd32(E1000_THLOWTC) & 0xFF);
2788
2789 /* Return the internal sensor only if ETS is unsupported */
2790 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2791 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2792 return status;
2793
2794 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2795 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2796 != NVM_ETS_TYPE_EMC)
2797 return E1000_NOT_IMPLEMENTED;
2798
2799 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2800 NVM_ETS_LTHRES_DELTA_SHIFT);
2801 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2802
2803 for (i = 1; i <= num_sensors; i++) {
2804 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2805 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2806 NVM_ETS_DATA_INDEX_SHIFT);
2807 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2808 NVM_ETS_DATA_LOC_SHIFT);
2809 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2810
2811 hw->phy.ops.write_i2c_byte(hw,
2812 e1000_emc_therm_limit[sensor_index],
2813 E1000_I2C_THERMAL_SENSOR_ADDR,
2814 therm_limit);
2815
2816 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2817 data->sensor[i].location = sensor_location;
2818 data->sensor[i].caution_thresh = therm_limit;
2819 data->sensor[i].max_op_thresh = therm_limit -
2820 low_thresh_delta;
2821 }
2822 }
2823 return status;
2824 }
2825
2826 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2827 .init_hw = igb_init_hw_82575,
2828 .check_for_link = igb_check_for_link_82575,
2829 .rar_set = igb_rar_set,
2830 .read_mac_addr = igb_read_mac_addr_82575,
2831 .get_speed_and_duplex = igb_get_link_up_info_82575,
2832 #ifdef CONFIG_IGB_HWMON
2833 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2834 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2835 #endif
2836 };
2837
2838 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2839 .acquire = igb_acquire_phy_82575,
2840 .get_cfg_done = igb_get_cfg_done_82575,
2841 .release = igb_release_phy_82575,
2842 .write_i2c_byte = igb_write_i2c_byte,
2843 .read_i2c_byte = igb_read_i2c_byte,
2844 };
2845
2846 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2847 .acquire = igb_acquire_nvm_82575,
2848 .read = igb_read_nvm_eerd,
2849 .release = igb_release_nvm_82575,
2850 .write = igb_write_nvm_spi,
2851 };
2852
2853 const struct e1000_info e1000_82575_info = {
2854 .get_invariants = igb_get_invariants_82575,
2855 .mac_ops = &e1000_mac_ops_82575,
2856 .phy_ops = &e1000_phy_ops_82575,
2857 .nvm_ops = &e1000_nvm_ops_82575,
2858 };
2859
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