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ALSA: hda - Move the dsp loader to hda_controller
[linux-2.6/btrfs-unstable.git] / sound / pci / hda / hda_intel.c
blob80250b3a6fc3375de42cf40f2c206e5311ed679f
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_controller.h"
67 #include "hda_priv.h"
68
69
70 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
72 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
73 static char *model[SNDRV_CARDS];
74 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
77 static int probe_only[SNDRV_CARDS];
78 static int jackpoll_ms[SNDRV_CARDS];
79 static bool single_cmd;
80 static int enable_msi = -1;
81 #ifdef CONFIG_SND_HDA_PATCH_LOADER
82 static char *patch[SNDRV_CARDS];
83 #endif
84 #ifdef CONFIG_SND_HDA_INPUT_BEEP
85 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87 #endif
88
89 module_param_array(index, int, NULL, 0444);
90 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
91 module_param_array(id, charp, NULL, 0444);
92 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
93 module_param_array(enable, bool, NULL, 0444);
94 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95 module_param_array(model, charp, NULL, 0444);
96 MODULE_PARM_DESC(model, "Use the given board model.");
97 module_param_array(position_fix, int, NULL, 0444);
98 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
100 module_param_array(bdl_pos_adj, int, NULL, 0644);
101 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
102 module_param_array(probe_mask, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
104 module_param_array(probe_only, int, NULL, 0444);
105 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
106 module_param_array(jackpoll_ms, int, NULL, 0444);
107 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
108 module_param(single_cmd, bool, 0444);
109 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
111 module_param(enable_msi, bint, 0444);
112 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
113 #ifdef CONFIG_SND_HDA_PATCH_LOADER
114 module_param_array(patch, charp, NULL, 0444);
115 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116 #endif
117 #ifdef CONFIG_SND_HDA_INPUT_BEEP
118 module_param_array(beep_mode, bool, NULL, 0444);
119 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
120 "(0=off, 1=on) (default=1).");
121 #endif
122
123 #ifdef CONFIG_PM
124 static int param_set_xint(const char *val, const struct kernel_param *kp);
125 static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128 };
129 #define param_check_xint param_check_int
130
131 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
132 static int *power_save_addr = &power_save;
133 module_param(power_save, xint, 0644);
134 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
136
137 /* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
141 static bool power_save_controller = 1;
142 module_param(power_save_controller, bool, 0644);
143 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
144 #else
145 static int *power_save_addr;
146 #endif /* CONFIG_PM */
147
148 static int align_buffer_size = -1;
149 module_param(align_buffer_size, bint, 0644);
150 MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
153 #ifdef CONFIG_X86
154 static bool hda_snoop = true;
155 module_param_named(snoop, hda_snoop, bool, 0444);
156 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
157 #else
158 #define hda_snoop true
159 #endif
160
161
162 MODULE_LICENSE("GPL");
163 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
165 "{Intel, ICH7},"
166 "{Intel, ESB2},"
167 "{Intel, ICH8},"
168 "{Intel, ICH9},"
169 "{Intel, ICH10},"
170 "{Intel, PCH},"
171 "{Intel, CPT},"
172 "{Intel, PPT},"
173 "{Intel, LPT},"
174 "{Intel, LPT_LP},"
175 "{Intel, WPT_LP},"
176 "{Intel, HPT},"
177 "{Intel, PBG},"
178 "{Intel, SCH},"
179 "{ATI, SB450},"
180 "{ATI, SB600},"
181 "{ATI, RS600},"
182 "{ATI, RS690},"
183 "{ATI, RS780},"
184 "{ATI, R600},"
185 "{ATI, RV630},"
186 "{ATI, RV610},"
187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
191 "{VIA, VT8251},"
192 "{VIA, VT8237A},"
193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
195 MODULE_DESCRIPTION("Intel HDA driver");
196
197 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
198 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
199 #define SUPPORT_VGA_SWITCHEROO
200 #endif
201 #endif
202
203
204 /*
205 */
206
207 /* driver types */
208 enum {
209 AZX_DRIVER_ICH,
210 AZX_DRIVER_PCH,
211 AZX_DRIVER_SCH,
212 AZX_DRIVER_HDMI,
213 AZX_DRIVER_ATI,
214 AZX_DRIVER_ATIHDMI,
215 AZX_DRIVER_ATIHDMI_NS,
216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
219 AZX_DRIVER_NVIDIA,
220 AZX_DRIVER_TERA,
221 AZX_DRIVER_CTX,
222 AZX_DRIVER_CTHDA,
223 AZX_DRIVER_GENERIC,
224 AZX_NUM_DRIVERS, /* keep this as last entry */
225 };
226
227 /* quirks for Intel PCH */
228 #define AZX_DCAPS_INTEL_PCH_NOPM \
229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232 #define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
234
235 #define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
240 /* quirks for ATI SB / AMD Hudson */
241 #define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245 /* quirks for ATI/AMD HDMI */
246 #define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249 /* quirks for Nvidia */
250 #define AZX_DCAPS_PRESET_NVIDIA \
251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
253
254 #define AZX_DCAPS_PRESET_CTHDA \
255 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
256
257 /*
258 * VGA-switcher support
259 */
260 #ifdef SUPPORT_VGA_SWITCHEROO
261 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
262 #else
263 #define use_vga_switcheroo(chip) 0
264 #endif
265
266 static char *driver_short_names[] = {
267 [AZX_DRIVER_ICH] = "HDA Intel",
268 [AZX_DRIVER_PCH] = "HDA Intel PCH",
269 [AZX_DRIVER_SCH] = "HDA Intel MID",
270 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
271 [AZX_DRIVER_ATI] = "HDA ATI SB",
272 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
273 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
274 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
275 [AZX_DRIVER_SIS] = "HDA SIS966",
276 [AZX_DRIVER_ULI] = "HDA ULI M5461",
277 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
278 [AZX_DRIVER_TERA] = "HDA Teradici",
279 [AZX_DRIVER_CTX] = "HDA Creative",
280 [AZX_DRIVER_CTHDA] = "HDA Creative",
281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
282 };
283
284 #ifdef CONFIG_X86
285 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
286 {
287 int pages;
288
289 if (azx_snoop(chip))
290 return;
291 if (!dmab || !dmab->area || !dmab->bytes)
292 return;
293
294 #ifdef CONFIG_SND_DMA_SGBUF
295 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
296 struct snd_sg_buf *sgbuf = dmab->private_data;
297 if (on)
298 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
299 else
300 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
301 return;
302 }
303 #endif
304
305 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
306 if (on)
307 set_memory_wc((unsigned long)dmab->area, pages);
308 else
309 set_memory_wb((unsigned long)dmab->area, pages);
310 }
311
312 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
313 bool on)
314 {
315 __mark_pages_wc(chip, buf, on);
316 }
317 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
318 struct snd_pcm_substream *substream, bool on)
319 {
320 if (azx_dev->wc_marked != on) {
321 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
322 azx_dev->wc_marked = on;
323 }
324 }
325 #else
326 /* NOP for other archs */
327 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329 {
330 }
331 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
332 struct snd_pcm_substream *substream, bool on)
333 {
334 }
335 #endif
336
337 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
338 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
339 /*
340 * Interface for HD codec
341 */
342
343 /*
344 * CORB / RIRB interface
345 */
346 static int azx_alloc_cmd_io(struct azx *chip)
347 {
348 int err;
349
350 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
351 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
352 PAGE_SIZE, &chip->rb);
353 if (err < 0)
354 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
355 return err;
356 }
357
358 static void azx_init_cmd_io(struct azx *chip)
359 {
360 int timeout;
361
362 spin_lock_irq(&chip->reg_lock);
363 /* CORB set up */
364 chip->corb.addr = chip->rb.addr;
365 chip->corb.buf = (u32 *)chip->rb.area;
366 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
367 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
368
369 /* set the corb size to 256 entries (ULI requires explicitly) */
370 azx_writeb(chip, CORBSIZE, 0x02);
371 /* set the corb write pointer to 0 */
372 azx_writew(chip, CORBWP, 0);
373
374 /* reset the corb hw read pointer */
375 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
376 for (timeout = 1000; timeout > 0; timeout--) {
377 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
378 break;
379 udelay(1);
380 }
381 if (timeout <= 0)
382 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
383 azx_readw(chip, CORBRP));
384
385 azx_writew(chip, CORBRP, 0);
386 for (timeout = 1000; timeout > 0; timeout--) {
387 if (azx_readw(chip, CORBRP) == 0)
388 break;
389 udelay(1);
390 }
391 if (timeout <= 0)
392 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
393 azx_readw(chip, CORBRP));
394
395 /* enable corb dma */
396 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
397
398 /* RIRB set up */
399 chip->rirb.addr = chip->rb.addr + 2048;
400 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
401 chip->rirb.wp = chip->rirb.rp = 0;
402 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
403 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
404 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
405
406 /* set the rirb size to 256 entries (ULI requires explicitly) */
407 azx_writeb(chip, RIRBSIZE, 0x02);
408 /* reset the rirb hw write pointer */
409 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
410 /* set N=1, get RIRB response interrupt for new entry */
411 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
412 azx_writew(chip, RINTCNT, 0xc0);
413 else
414 azx_writew(chip, RINTCNT, 1);
415 /* enable rirb dma and response irq */
416 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
417 spin_unlock_irq(&chip->reg_lock);
418 }
419
420 static void azx_free_cmd_io(struct azx *chip)
421 {
422 spin_lock_irq(&chip->reg_lock);
423 /* disable ringbuffer DMAs */
424 azx_writeb(chip, RIRBCTL, 0);
425 azx_writeb(chip, CORBCTL, 0);
426 spin_unlock_irq(&chip->reg_lock);
427 }
428
429 static unsigned int azx_command_addr(u32 cmd)
430 {
431 unsigned int addr = cmd >> 28;
432
433 if (addr >= AZX_MAX_CODECS) {
434 snd_BUG();
435 addr = 0;
436 }
437
438 return addr;
439 }
440
441 /* send a command */
442 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
443 {
444 struct azx *chip = bus->private_data;
445 unsigned int addr = azx_command_addr(val);
446 unsigned int wp, rp;
447
448 spin_lock_irq(&chip->reg_lock);
449
450 /* add command to corb */
451 wp = azx_readw(chip, CORBWP);
452 if (wp == 0xffff) {
453 /* something wrong, controller likely turned to D3 */
454 spin_unlock_irq(&chip->reg_lock);
455 return -EIO;
456 }
457 wp++;
458 wp %= ICH6_MAX_CORB_ENTRIES;
459
460 rp = azx_readw(chip, CORBRP);
461 if (wp == rp) {
462 /* oops, it's full */
463 spin_unlock_irq(&chip->reg_lock);
464 return -EAGAIN;
465 }
466
467 chip->rirb.cmds[addr]++;
468 chip->corb.buf[wp] = cpu_to_le32(val);
469 azx_writew(chip, CORBWP, wp);
470
471 spin_unlock_irq(&chip->reg_lock);
472
473 return 0;
474 }
475
476 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
477
478 /* retrieve RIRB entry - called from interrupt handler */
479 static void azx_update_rirb(struct azx *chip)
480 {
481 unsigned int rp, wp;
482 unsigned int addr;
483 u32 res, res_ex;
484
485 wp = azx_readw(chip, RIRBWP);
486 if (wp == 0xffff) {
487 /* something wrong, controller likely turned to D3 */
488 return;
489 }
490
491 if (wp == chip->rirb.wp)
492 return;
493 chip->rirb.wp = wp;
494
495 while (chip->rirb.rp != wp) {
496 chip->rirb.rp++;
497 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
498
499 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
500 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
501 res = le32_to_cpu(chip->rirb.buf[rp]);
502 addr = res_ex & 0xf;
503 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
504 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
505 res, res_ex,
506 chip->rirb.rp, wp);
507 snd_BUG();
508 }
509 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
510 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
511 else if (chip->rirb.cmds[addr]) {
512 chip->rirb.res[addr] = res;
513 smp_wmb();
514 chip->rirb.cmds[addr]--;
515 } else if (printk_ratelimit()) {
516 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
517 res, res_ex,
518 chip->last_cmd[addr]);
519 }
520 }
521 }
522
523 /* receive a response */
524 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
525 unsigned int addr)
526 {
527 struct azx *chip = bus->private_data;
528 unsigned long timeout;
529 unsigned long loopcounter;
530 int do_poll = 0;
531
532 again:
533 timeout = jiffies + msecs_to_jiffies(1000);
534
535 for (loopcounter = 0;; loopcounter++) {
536 if (chip->polling_mode || do_poll) {
537 spin_lock_irq(&chip->reg_lock);
538 azx_update_rirb(chip);
539 spin_unlock_irq(&chip->reg_lock);
540 }
541 if (!chip->rirb.cmds[addr]) {
542 smp_rmb();
543 bus->rirb_error = 0;
544
545 if (!do_poll)
546 chip->poll_count = 0;
547 return chip->rirb.res[addr]; /* the last value */
548 }
549 if (time_after(jiffies, timeout))
550 break;
551 if (bus->needs_damn_long_delay || loopcounter > 3000)
552 msleep(2); /* temporary workaround */
553 else {
554 udelay(10);
555 cond_resched();
556 }
557 }
558
559 if (!bus->no_response_fallback)
560 return -1;
561
562 if (!chip->polling_mode && chip->poll_count < 2) {
563 dev_dbg(chip->card->dev,
564 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
565 chip->last_cmd[addr]);
566 do_poll = 1;
567 chip->poll_count++;
568 goto again;
569 }
570
571
572 if (!chip->polling_mode) {
573 dev_warn(chip->card->dev,
574 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
575 chip->last_cmd[addr]);
576 chip->polling_mode = 1;
577 goto again;
578 }
579
580 if (chip->msi) {
581 dev_warn(chip->card->dev,
582 "No response from codec, disabling MSI: last cmd=0x%08x\n",
583 chip->last_cmd[addr]);
584 if (chip->ops->disable_msi_reset_irq &&
585 chip->ops->disable_msi_reset_irq(chip) < 0) {
586 bus->rirb_error = 1;
587 return -1;
588 }
589 goto again;
590 }
591
592 if (chip->probing) {
593 /* If this critical timeout happens during the codec probing
594 * phase, this is likely an access to a non-existing codec
595 * slot. Better to return an error and reset the system.
596 */
597 return -1;
598 }
599
600 /* a fatal communication error; need either to reset or to fallback
601 * to the single_cmd mode
602 */
603 bus->rirb_error = 1;
604 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
605 bus->response_reset = 1;
606 return -1; /* give a chance to retry */
607 }
608
609 dev_err(chip->card->dev,
610 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
611 chip->last_cmd[addr]);
612 chip->single_cmd = 1;
613 bus->response_reset = 0;
614 /* release CORB/RIRB */
615 azx_free_cmd_io(chip);
616 /* disable unsolicited responses */
617 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
618 return -1;
619 }
620
621 /*
622 * Use the single immediate command instead of CORB/RIRB for simplicity
623 *
624 * Note: according to Intel, this is not preferred use. The command was
625 * intended for the BIOS only, and may get confused with unsolicited
626 * responses. So, we shouldn't use it for normal operation from the
627 * driver.
628 * I left the codes, however, for debugging/testing purposes.
629 */
630
631 /* receive a response */
632 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
633 {
634 int timeout = 50;
635
636 while (timeout--) {
637 /* check IRV busy bit */
638 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
639 /* reuse rirb.res as the response return value */
640 chip->rirb.res[addr] = azx_readl(chip, IR);
641 return 0;
642 }
643 udelay(1);
644 }
645 if (printk_ratelimit())
646 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
647 azx_readw(chip, IRS));
648 chip->rirb.res[addr] = -1;
649 return -EIO;
650 }
651
652 /* send a command */
653 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
654 {
655 struct azx *chip = bus->private_data;
656 unsigned int addr = azx_command_addr(val);
657 int timeout = 50;
658
659 bus->rirb_error = 0;
660 while (timeout--) {
661 /* check ICB busy bit */
662 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
663 /* Clear IRV valid bit */
664 azx_writew(chip, IRS, azx_readw(chip, IRS) |
665 ICH6_IRS_VALID);
666 azx_writel(chip, IC, val);
667 azx_writew(chip, IRS, azx_readw(chip, IRS) |
668 ICH6_IRS_BUSY);
669 return azx_single_wait_for_response(chip, addr);
670 }
671 udelay(1);
672 }
673 if (printk_ratelimit())
674 dev_dbg(chip->card->dev,
675 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
676 azx_readw(chip, IRS), val);
677 return -EIO;
678 }
679
680 /* receive a response */
681 static unsigned int azx_single_get_response(struct hda_bus *bus,
682 unsigned int addr)
683 {
684 struct azx *chip = bus->private_data;
685 return chip->rirb.res[addr];
686 }
687
688 /*
689 * The below are the main callbacks from hda_codec.
690 *
691 * They are just the skeleton to call sub-callbacks according to the
692 * current setting of chip->single_cmd.
693 */
694
695 /* send a command */
696 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
697 {
698 struct azx *chip = bus->private_data;
699
700 if (chip->disabled)
701 return 0;
702 chip->last_cmd[azx_command_addr(val)] = val;
703 if (chip->single_cmd)
704 return azx_single_send_cmd(bus, val);
705 else
706 return azx_corb_send_cmd(bus, val);
707 }
708
709 /* get a response */
710 static unsigned int azx_get_response(struct hda_bus *bus,
711 unsigned int addr)
712 {
713 struct azx *chip = bus->private_data;
714 if (chip->disabled)
715 return 0;
716 if (chip->single_cmd)
717 return azx_single_get_response(bus, addr);
718 else
719 return azx_rirb_get_response(bus, addr);
720 }
721
722 #ifdef CONFIG_PM
723 static void azx_power_notify(struct hda_bus *bus, bool power_up);
724 #endif
725
726 /* enter link reset */
727 static void azx_enter_link_reset(struct azx *chip)
728 {
729 unsigned long timeout;
730
731 /* reset controller */
732 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
733
734 timeout = jiffies + msecs_to_jiffies(100);
735 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
736 time_before(jiffies, timeout))
737 usleep_range(500, 1000);
738 }
739
740 /* exit link reset */
741 static void azx_exit_link_reset(struct azx *chip)
742 {
743 unsigned long timeout;
744
745 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
746
747 timeout = jiffies + msecs_to_jiffies(100);
748 while (!azx_readb(chip, GCTL) &&
749 time_before(jiffies, timeout))
750 usleep_range(500, 1000);
751 }
752
753 /* reset codec link */
754 static int azx_reset(struct azx *chip, int full_reset)
755 {
756 if (!full_reset)
757 goto __skip;
758
759 /* clear STATESTS */
760 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
761
762 /* reset controller */
763 azx_enter_link_reset(chip);
764
765 /* delay for >= 100us for codec PLL to settle per spec
766 * Rev 0.9 section 5.5.1
767 */
768 usleep_range(500, 1000);
769
770 /* Bring controller out of reset */
771 azx_exit_link_reset(chip);
772
773 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
774 usleep_range(1000, 1200);
775
776 __skip:
777 /* check to see if controller is ready */
778 if (!azx_readb(chip, GCTL)) {
779 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
780 return -EBUSY;
781 }
782
783 /* Accept unsolicited responses */
784 if (!chip->single_cmd)
785 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
786 ICH6_GCTL_UNSOL);
787
788 /* detect codecs */
789 if (!chip->codec_mask) {
790 chip->codec_mask = azx_readw(chip, STATESTS);
791 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
792 chip->codec_mask);
793 }
794
795 return 0;
796 }
797
798
799 /*
800 * Lowlevel interface
801 */
802
803 /* enable interrupts */
804 static void azx_int_enable(struct azx *chip)
805 {
806 /* enable controller CIE and GIE */
807 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
808 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
809 }
810
811 /* disable interrupts */
812 static void azx_int_disable(struct azx *chip)
813 {
814 int i;
815
816 /* disable interrupts in stream descriptor */
817 for (i = 0; i < chip->num_streams; i++) {
818 struct azx_dev *azx_dev = &chip->azx_dev[i];
819 azx_sd_writeb(chip, azx_dev, SD_CTL,
820 azx_sd_readb(chip, azx_dev, SD_CTL) &
821 ~SD_INT_MASK);
822 }
823
824 /* disable SIE for all streams */
825 azx_writeb(chip, INTCTL, 0);
826
827 /* disable controller CIE and GIE */
828 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
829 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
830 }
831
832 /* clear interrupts */
833 static void azx_int_clear(struct azx *chip)
834 {
835 int i;
836
837 /* clear stream status */
838 for (i = 0; i < chip->num_streams; i++) {
839 struct azx_dev *azx_dev = &chip->azx_dev[i];
840 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
841 }
842
843 /* clear STATESTS */
844 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
845
846 /* clear rirb status */
847 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
848
849 /* clear int status */
850 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
851 }
852
853 /*
854 * reset and start the controller registers
855 */
856 static void azx_init_chip(struct azx *chip, int full_reset)
857 {
858 if (chip->initialized)
859 return;
860
861 /* reset controller */
862 azx_reset(chip, full_reset);
863
864 /* initialize interrupts */
865 azx_int_clear(chip);
866 azx_int_enable(chip);
867
868 /* initialize the codec command I/O */
869 if (!chip->single_cmd)
870 azx_init_cmd_io(chip);
871
872 /* program the position buffer */
873 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
874 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
875
876 chip->initialized = 1;
877 }
878
879 /*
880 * initialize the PCI registers
881 */
882 /* update bits in a PCI register byte */
883 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
884 unsigned char mask, unsigned char val)
885 {
886 unsigned char data;
887
888 pci_read_config_byte(pci, reg, &data);
889 data &= ~mask;
890 data |= (val & mask);
891 pci_write_config_byte(pci, reg, data);
892 }
893
894 static void azx_init_pci(struct azx *chip)
895 {
896 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
897 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
898 * Ensuring these bits are 0 clears playback static on some HD Audio
899 * codecs.
900 * The PCI register TCSEL is defined in the Intel manuals.
901 */
902 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
903 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
904 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
905 }
906
907 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
908 * we need to enable snoop.
909 */
910 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
911 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
912 azx_snoop(chip));
913 update_pci_byte(chip->pci,
914 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
915 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
916 }
917
918 /* For NVIDIA HDA, enable snoop */
919 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
920 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
921 azx_snoop(chip));
922 update_pci_byte(chip->pci,
923 NVIDIA_HDA_TRANSREG_ADDR,
924 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
925 update_pci_byte(chip->pci,
926 NVIDIA_HDA_ISTRM_COH,
927 0x01, NVIDIA_HDA_ENABLE_COHBIT);
928 update_pci_byte(chip->pci,
929 NVIDIA_HDA_OSTRM_COH,
930 0x01, NVIDIA_HDA_ENABLE_COHBIT);
931 }
932
933 /* Enable SCH/PCH snoop if needed */
934 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
935 unsigned short snoop;
936 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
937 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
938 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
939 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
940 if (!azx_snoop(chip))
941 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
942 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
943 pci_read_config_word(chip->pci,
944 INTEL_SCH_HDA_DEVC, &snoop);
945 }
946 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
947 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
948 "Disabled" : "Enabled");
949 }
950 }
951
952
953 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
954
955 /*
956 * interrupt handler
957 */
958 static irqreturn_t azx_interrupt(int irq, void *dev_id)
959 {
960 struct azx *chip = dev_id;
961 struct azx_dev *azx_dev;
962 u32 status;
963 u8 sd_status;
964 int i, ok;
965
966 #ifdef CONFIG_PM_RUNTIME
967 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
968 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
969 return IRQ_NONE;
970 #endif
971
972 spin_lock(&chip->reg_lock);
973
974 if (chip->disabled) {
975 spin_unlock(&chip->reg_lock);
976 return IRQ_NONE;
977 }
978
979 status = azx_readl(chip, INTSTS);
980 if (status == 0 || status == 0xffffffff) {
981 spin_unlock(&chip->reg_lock);
982 return IRQ_NONE;
983 }
984
985 for (i = 0; i < chip->num_streams; i++) {
986 azx_dev = &chip->azx_dev[i];
987 if (status & azx_dev->sd_int_sta_mask) {
988 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
989 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
990 if (!azx_dev->substream || !azx_dev->running ||
991 !(sd_status & SD_INT_COMPLETE))
992 continue;
993 /* check whether this IRQ is really acceptable */
994 ok = azx_position_ok(chip, azx_dev);
995 if (ok == 1) {
996 azx_dev->irq_pending = 0;
997 spin_unlock(&chip->reg_lock);
998 snd_pcm_period_elapsed(azx_dev->substream);
999 spin_lock(&chip->reg_lock);
1000 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1001 /* bogus IRQ, process it later */
1002 azx_dev->irq_pending = 1;
1003 queue_work(chip->bus->workq,
1004 &chip->irq_pending_work);
1005 }
1006 }
1007 }
1008
1009 /* clear rirb int */
1010 status = azx_readb(chip, RIRBSTS);
1011 if (status & RIRB_INT_MASK) {
1012 if (status & RIRB_INT_RESPONSE) {
1013 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1014 udelay(80);
1015 azx_update_rirb(chip);
1016 }
1017 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1018 }
1019
1020 spin_unlock(&chip->reg_lock);
1021
1022 return IRQ_HANDLED;
1023 }
1024
1025 /*
1026 * Probe the given codec address
1027 */
1028 static int probe_codec(struct azx *chip, int addr)
1029 {
1030 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1031 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1032 unsigned int res;
1033
1034 mutex_lock(&chip->bus->cmd_mutex);
1035 chip->probing = 1;
1036 azx_send_cmd(chip->bus, cmd);
1037 res = azx_get_response(chip->bus, addr);
1038 chip->probing = 0;
1039 mutex_unlock(&chip->bus->cmd_mutex);
1040 if (res == -1)
1041 return -EIO;
1042 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1043 return 0;
1044 }
1045
1046 static void azx_stop_chip(struct azx *chip);
1047
1048 static void azx_bus_reset(struct hda_bus *bus)
1049 {
1050 struct azx *chip = bus->private_data;
1051
1052 bus->in_reset = 1;
1053 azx_stop_chip(chip);
1054 azx_init_chip(chip, 1);
1055 #ifdef CONFIG_PM
1056 if (chip->initialized) {
1057 struct azx_pcm *p;
1058 list_for_each_entry(p, &chip->pcm_list, list)
1059 snd_pcm_suspend_all(p->pcm);
1060 snd_hda_suspend(chip->bus);
1061 snd_hda_resume(chip->bus);
1062 }
1063 #endif
1064 bus->in_reset = 0;
1065 }
1066
1067 static int get_jackpoll_interval(struct azx *chip)
1068 {
1069 int i;
1070 unsigned int j;
1071
1072 if (!chip->jackpoll_ms)
1073 return 0;
1074
1075 i = chip->jackpoll_ms[chip->dev_index];
1076 if (i == 0)
1077 return 0;
1078 if (i < 50 || i > 60000)
1079 j = 0;
1080 else
1081 j = msecs_to_jiffies(i);
1082 if (j == 0)
1083 dev_warn(chip->card->dev,
1084 "jackpoll_ms value out of range: %d\n", i);
1085 return j;
1086 }
1087
1088 /*
1089 * Codec initialization
1090 */
1091
1092 static int azx_codec_create(struct azx *chip, const char *model,
1093 unsigned int max_slots,
1094 int *power_save_to)
1095 {
1096 struct hda_bus_template bus_temp;
1097 int c, codecs, err;
1098
1099 memset(&bus_temp, 0, sizeof(bus_temp));
1100 bus_temp.private_data = chip;
1101 bus_temp.modelname = model;
1102 bus_temp.pci = chip->pci;
1103 bus_temp.ops.command = azx_send_cmd;
1104 bus_temp.ops.get_response = azx_get_response;
1105 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1106 bus_temp.ops.bus_reset = azx_bus_reset;
1107 #ifdef CONFIG_PM
1108 bus_temp.power_save = power_save_to;
1109 bus_temp.ops.pm_notify = azx_power_notify;
1110 #endif
1111 #ifdef CONFIG_SND_HDA_DSP_LOADER
1112 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1113 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1114 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1115 #endif
1116
1117 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1118 if (err < 0)
1119 return err;
1120
1121 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1122 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1123 chip->bus->needs_damn_long_delay = 1;
1124 }
1125
1126 codecs = 0;
1127 if (!max_slots)
1128 max_slots = AZX_DEFAULT_CODECS;
1129
1130 /* First try to probe all given codec slots */
1131 for (c = 0; c < max_slots; c++) {
1132 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1133 if (probe_codec(chip, c) < 0) {
1134 /* Some BIOSen give you wrong codec addresses
1135 * that don't exist
1136 */
1137 dev_warn(chip->card->dev,
1138 "Codec #%d probe error; disabling it...\n", c);
1139 chip->codec_mask &= ~(1 << c);
1140 /* More badly, accessing to a non-existing
1141 * codec often screws up the controller chip,
1142 * and disturbs the further communications.
1143 * Thus if an error occurs during probing,
1144 * better to reset the controller chip to
1145 * get back to the sanity state.
1146 */
1147 azx_stop_chip(chip);
1148 azx_init_chip(chip, 1);
1149 }
1150 }
1151 }
1152
1153 /* AMD chipsets often cause the communication stalls upon certain
1154 * sequence like the pin-detection. It seems that forcing the synced
1155 * access works around the stall. Grrr...
1156 */
1157 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1158 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1159 chip->bus->sync_write = 1;
1160 chip->bus->allow_bus_reset = 1;
1161 }
1162
1163 /* Then create codec instances */
1164 for (c = 0; c < max_slots; c++) {
1165 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1166 struct hda_codec *codec;
1167 err = snd_hda_codec_new(chip->bus, c, &codec);
1168 if (err < 0)
1169 continue;
1170 codec->jackpoll_interval = get_jackpoll_interval(chip);
1171 codec->beep_mode = chip->beep_mode;
1172 codecs++;
1173 }
1174 }
1175 if (!codecs) {
1176 dev_err(chip->card->dev, "no codecs initialized\n");
1177 return -ENXIO;
1178 }
1179 return 0;
1180 }
1181
1182 /* configure each codec instance */
1183 static int azx_codec_configure(struct azx *chip)
1184 {
1185 struct hda_codec *codec;
1186 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1187 snd_hda_codec_configure(codec);
1188 }
1189 return 0;
1190 }
1191
1192 /*
1193 * Check whether the current DMA position is acceptable for updating
1194 * periods. Returns non-zero if it's OK.
1195 *
1196 * Many HD-audio controllers appear pretty inaccurate about
1197 * the update-IRQ timing. The IRQ is issued before actually the
1198 * data is processed. So, we need to process it afterwords in a
1199 * workqueue.
1200 */
1201 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1202 {
1203 u32 wallclk;
1204 unsigned int pos;
1205
1206 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1207 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1208 return -1; /* bogus (too early) interrupt */
1209
1210 pos = azx_get_position(chip, azx_dev, true);
1211
1212 if (WARN_ONCE(!azx_dev->period_bytes,
1213 "hda-intel: zero azx_dev->period_bytes"))
1214 return -1; /* this shouldn't happen! */
1215 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1216 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1217 /* NG - it's below the first next period boundary */
1218 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
1219 azx_dev->start_wallclk += wallclk;
1220 return 1; /* OK, it's fine */
1221 }
1222
1223 /*
1224 * The work for pending PCM period updates.
1225 */
1226 static void azx_irq_pending_work(struct work_struct *work)
1227 {
1228 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1229 int i, pending, ok;
1230
1231 if (!chip->irq_pending_warned) {
1232 dev_info(chip->card->dev,
1233 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
1234 chip->card->number);
1235 chip->irq_pending_warned = 1;
1236 }
1237
1238 for (;;) {
1239 pending = 0;
1240 spin_lock_irq(&chip->reg_lock);
1241 for (i = 0; i < chip->num_streams; i++) {
1242 struct azx_dev *azx_dev = &chip->azx_dev[i];
1243 if (!azx_dev->irq_pending ||
1244 !azx_dev->substream ||
1245 !azx_dev->running)
1246 continue;
1247 ok = azx_position_ok(chip, azx_dev);
1248 if (ok > 0) {
1249 azx_dev->irq_pending = 0;
1250 spin_unlock(&chip->reg_lock);
1251 snd_pcm_period_elapsed(azx_dev->substream);
1252 spin_lock(&chip->reg_lock);
1253 } else if (ok < 0) {
1254 pending = 0; /* too early */
1255 } else
1256 pending++;
1257 }
1258 spin_unlock_irq(&chip->reg_lock);
1259 if (!pending)
1260 return;
1261 msleep(1);
1262 }
1263 }
1264
1265 /* clear irq_pending flags and assure no on-going workq */
1266 static void azx_clear_irq_pending(struct azx *chip)
1267 {
1268 int i;
1269
1270 spin_lock_irq(&chip->reg_lock);
1271 for (i = 0; i < chip->num_streams; i++)
1272 chip->azx_dev[i].irq_pending = 0;
1273 spin_unlock_irq(&chip->reg_lock);
1274 }
1275
1276 /*
1277 * mixer creation - all stuff is implemented in hda module
1278 */
1279 static int azx_mixer_create(struct azx *chip)
1280 {
1281 return snd_hda_build_controls(chip->bus);
1282 }
1283
1284
1285 /*
1286 * initialize SD streams
1287 */
1288 static int azx_init_stream(struct azx *chip)
1289 {
1290 int i;
1291
1292 /* initialize each stream (aka device)
1293 * assign the starting bdl address to each stream (device)
1294 * and initialize
1295 */
1296 for (i = 0; i < chip->num_streams; i++) {
1297 struct azx_dev *azx_dev = &chip->azx_dev[i];
1298 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1299 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1300 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1301 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1302 azx_dev->sd_int_sta_mask = 1 << i;
1303 /* stream tag: must be non-zero and unique */
1304 azx_dev->index = i;
1305 azx_dev->stream_tag = i + 1;
1306 }
1307
1308 return 0;
1309 }
1310
1311 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1312 {
1313 if (request_irq(chip->pci->irq, azx_interrupt,
1314 chip->msi ? 0 : IRQF_SHARED,
1315 KBUILD_MODNAME, chip)) {
1316 dev_err(chip->card->dev,
1317 "unable to grab IRQ %d, disabling device\n",
1318 chip->pci->irq);
1319 if (do_disconnect)
1320 snd_card_disconnect(chip->card);
1321 return -1;
1322 }
1323 chip->irq = chip->pci->irq;
1324 pci_intx(chip->pci, !chip->msi);
1325 return 0;
1326 }
1327
1328
1329 static void azx_stop_chip(struct azx *chip)
1330 {
1331 if (!chip->initialized)
1332 return;
1333
1334 /* disable interrupts */
1335 azx_int_disable(chip);
1336 azx_int_clear(chip);
1337
1338 /* disable CORB/RIRB */
1339 azx_free_cmd_io(chip);
1340
1341 /* disable position buffer */
1342 azx_writel(chip, DPLBASE, 0);
1343 azx_writel(chip, DPUBASE, 0);
1344
1345 chip->initialized = 0;
1346 }
1347
1348 #ifdef CONFIG_PM
1349 /* power-up/down the controller */
1350 static void azx_power_notify(struct hda_bus *bus, bool power_up)
1351 {
1352 struct azx *chip = bus->private_data;
1353
1354 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1355 return;
1356
1357 if (power_up)
1358 pm_runtime_get_sync(chip->card->dev);
1359 else
1360 pm_runtime_put_sync(chip->card->dev);
1361 }
1362
1363 static DEFINE_MUTEX(card_list_lock);
1364 static LIST_HEAD(card_list);
1365
1366 static void azx_add_card_list(struct azx *chip)
1367 {
1368 mutex_lock(&card_list_lock);
1369 list_add(&chip->list, &card_list);
1370 mutex_unlock(&card_list_lock);
1371 }
1372
1373 static void azx_del_card_list(struct azx *chip)
1374 {
1375 mutex_lock(&card_list_lock);
1376 list_del_init(&chip->list);
1377 mutex_unlock(&card_list_lock);
1378 }
1379
1380 /* trigger power-save check at writing parameter */
1381 static int param_set_xint(const char *val, const struct kernel_param *kp)
1382 {
1383 struct azx *chip;
1384 struct hda_codec *c;
1385 int prev = power_save;
1386 int ret = param_set_int(val, kp);
1387
1388 if (ret || prev == power_save)
1389 return ret;
1390
1391 mutex_lock(&card_list_lock);
1392 list_for_each_entry(chip, &card_list, list) {
1393 if (!chip->bus || chip->disabled)
1394 continue;
1395 list_for_each_entry(c, &chip->bus->codec_list, list)
1396 snd_hda_power_sync(c);
1397 }
1398 mutex_unlock(&card_list_lock);
1399 return 0;
1400 }
1401 #else
1402 #define azx_add_card_list(chip) /* NOP */
1403 #define azx_del_card_list(chip) /* NOP */
1404 #endif /* CONFIG_PM */
1405
1406 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
1407 /*
1408 * power management
1409 */
1410 static int azx_suspend(struct device *dev)
1411 {
1412 struct pci_dev *pci = to_pci_dev(dev);
1413 struct snd_card *card = dev_get_drvdata(dev);
1414 struct azx *chip = card->private_data;
1415 struct azx_pcm *p;
1416
1417 if (chip->disabled)
1418 return 0;
1419
1420 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1421 azx_clear_irq_pending(chip);
1422 list_for_each_entry(p, &chip->pcm_list, list)
1423 snd_pcm_suspend_all(p->pcm);
1424 if (chip->initialized)
1425 snd_hda_suspend(chip->bus);
1426 azx_stop_chip(chip);
1427 azx_enter_link_reset(chip);
1428 if (chip->irq >= 0) {
1429 free_irq(chip->irq, chip);
1430 chip->irq = -1;
1431 }
1432 if (chip->msi)
1433 pci_disable_msi(chip->pci);
1434 pci_disable_device(pci);
1435 pci_save_state(pci);
1436 pci_set_power_state(pci, PCI_D3hot);
1437 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1438 hda_display_power(false);
1439 return 0;
1440 }
1441
1442 static int azx_resume(struct device *dev)
1443 {
1444 struct pci_dev *pci = to_pci_dev(dev);
1445 struct snd_card *card = dev_get_drvdata(dev);
1446 struct azx *chip = card->private_data;
1447
1448 if (chip->disabled)
1449 return 0;
1450
1451 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1452 hda_display_power(true);
1453 pci_set_power_state(pci, PCI_D0);
1454 pci_restore_state(pci);
1455 if (pci_enable_device(pci) < 0) {
1456 dev_err(chip->card->dev,
1457 "pci_enable_device failed, disabling device\n");
1458 snd_card_disconnect(card);
1459 return -EIO;
1460 }
1461 pci_set_master(pci);
1462 if (chip->msi)
1463 if (pci_enable_msi(pci) < 0)
1464 chip->msi = 0;
1465 if (azx_acquire_irq(chip, 1) < 0)
1466 return -EIO;
1467 azx_init_pci(chip);
1468
1469 azx_init_chip(chip, 1);
1470
1471 snd_hda_resume(chip->bus);
1472 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1473 return 0;
1474 }
1475 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1476
1477 #ifdef CONFIG_PM_RUNTIME
1478 static int azx_runtime_suspend(struct device *dev)
1479 {
1480 struct snd_card *card = dev_get_drvdata(dev);
1481 struct azx *chip = card->private_data;
1482
1483 if (chip->disabled)
1484 return 0;
1485
1486 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1487 return 0;
1488
1489 /* enable controller wake up event */
1490 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1491 STATESTS_INT_MASK);
1492
1493 azx_stop_chip(chip);
1494 azx_enter_link_reset(chip);
1495 azx_clear_irq_pending(chip);
1496 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1497 hda_display_power(false);
1498 return 0;
1499 }
1500
1501 static int azx_runtime_resume(struct device *dev)
1502 {
1503 struct snd_card *card = dev_get_drvdata(dev);
1504 struct azx *chip = card->private_data;
1505 struct hda_bus *bus;
1506 struct hda_codec *codec;
1507 int status;
1508
1509 if (chip->disabled)
1510 return 0;
1511
1512 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1513 return 0;
1514
1515 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1516 hda_display_power(true);
1517
1518 /* Read STATESTS before controller reset */
1519 status = azx_readw(chip, STATESTS);
1520
1521 azx_init_pci(chip);
1522 azx_init_chip(chip, 1);
1523
1524 bus = chip->bus;
1525 if (status && bus) {
1526 list_for_each_entry(codec, &bus->codec_list, list)
1527 if (status & (1 << codec->addr))
1528 queue_delayed_work(codec->bus->workq,
1529 &codec->jackpoll_work, codec->jackpoll_interval);
1530 }
1531
1532 /* disable controller Wake Up event*/
1533 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1534 ~STATESTS_INT_MASK);
1535
1536 return 0;
1537 }
1538
1539 static int azx_runtime_idle(struct device *dev)
1540 {
1541 struct snd_card *card = dev_get_drvdata(dev);
1542 struct azx *chip = card->private_data;
1543
1544 if (chip->disabled)
1545 return 0;
1546
1547 if (!power_save_controller ||
1548 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1549 return -EBUSY;
1550
1551 return 0;
1552 }
1553
1554 #endif /* CONFIG_PM_RUNTIME */
1555
1556 #ifdef CONFIG_PM
1557 static const struct dev_pm_ops azx_pm = {
1558 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1559 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1560 };
1561
1562 #define AZX_PM_OPS &azx_pm
1563 #else
1564 #define AZX_PM_OPS NULL
1565 #endif /* CONFIG_PM */
1566
1567
1568 /*
1569 * reboot notifier for hang-up problem at power-down
1570 */
1571 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1572 {
1573 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1574 snd_hda_bus_reboot_notify(chip->bus);
1575 azx_stop_chip(chip);
1576 return NOTIFY_OK;
1577 }
1578
1579 static void azx_notifier_register(struct azx *chip)
1580 {
1581 chip->reboot_notifier.notifier_call = azx_halt;
1582 register_reboot_notifier(&chip->reboot_notifier);
1583 }
1584
1585 static void azx_notifier_unregister(struct azx *chip)
1586 {
1587 if (chip->reboot_notifier.notifier_call)
1588 unregister_reboot_notifier(&chip->reboot_notifier);
1589 }
1590
1591 static int azx_probe_continue(struct azx *chip);
1592
1593 #ifdef SUPPORT_VGA_SWITCHEROO
1594 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1595
1596 static void azx_vs_set_state(struct pci_dev *pci,
1597 enum vga_switcheroo_state state)
1598 {
1599 struct snd_card *card = pci_get_drvdata(pci);
1600 struct azx *chip = card->private_data;
1601 bool disabled;
1602
1603 wait_for_completion(&chip->probe_wait);
1604 if (chip->init_failed)
1605 return;
1606
1607 disabled = (state == VGA_SWITCHEROO_OFF);
1608 if (chip->disabled == disabled)
1609 return;
1610
1611 if (!chip->bus) {
1612 chip->disabled = disabled;
1613 if (!disabled) {
1614 dev_info(chip->card->dev,
1615 "Start delayed initialization\n");
1616 if (azx_probe_continue(chip) < 0) {
1617 dev_err(chip->card->dev, "initialization error\n");
1618 chip->init_failed = true;
1619 }
1620 }
1621 } else {
1622 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1623 disabled ? "Disabling" : "Enabling");
1624 if (disabled) {
1625 pm_runtime_put_sync_suspend(card->dev);
1626 azx_suspend(card->dev);
1627 /* when we get suspended by vga switcheroo we end up in D3cold,
1628 * however we have no ACPI handle, so pci/acpi can't put us there,
1629 * put ourselves there */
1630 pci->current_state = PCI_D3cold;
1631 chip->disabled = true;
1632 if (snd_hda_lock_devices(chip->bus))
1633 dev_warn(chip->card->dev,
1634 "Cannot lock devices!\n");
1635 } else {
1636 snd_hda_unlock_devices(chip->bus);
1637 pm_runtime_get_noresume(card->dev);
1638 chip->disabled = false;
1639 azx_resume(card->dev);
1640 }
1641 }
1642 }
1643
1644 static bool azx_vs_can_switch(struct pci_dev *pci)
1645 {
1646 struct snd_card *card = pci_get_drvdata(pci);
1647 struct azx *chip = card->private_data;
1648
1649 wait_for_completion(&chip->probe_wait);
1650 if (chip->init_failed)
1651 return false;
1652 if (chip->disabled || !chip->bus)
1653 return true;
1654 if (snd_hda_lock_devices(chip->bus))
1655 return false;
1656 snd_hda_unlock_devices(chip->bus);
1657 return true;
1658 }
1659
1660 static void init_vga_switcheroo(struct azx *chip)
1661 {
1662 struct pci_dev *p = get_bound_vga(chip->pci);
1663 if (p) {
1664 dev_info(chip->card->dev,
1665 "Handle VGA-switcheroo audio client\n");
1666 chip->use_vga_switcheroo = 1;
1667 pci_dev_put(p);
1668 }
1669 }
1670
1671 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1672 .set_gpu_state = azx_vs_set_state,
1673 .can_switch = azx_vs_can_switch,
1674 };
1675
1676 static int register_vga_switcheroo(struct azx *chip)
1677 {
1678 int err;
1679
1680 if (!chip->use_vga_switcheroo)
1681 return 0;
1682 /* FIXME: currently only handling DIS controller
1683 * is there any machine with two switchable HDMI audio controllers?
1684 */
1685 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1686 VGA_SWITCHEROO_DIS,
1687 chip->bus != NULL);
1688 if (err < 0)
1689 return err;
1690 chip->vga_switcheroo_registered = 1;
1691
1692 /* register as an optimus hdmi audio power domain */
1693 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1694 &chip->hdmi_pm_domain);
1695 return 0;
1696 }
1697 #else
1698 #define init_vga_switcheroo(chip) /* NOP */
1699 #define register_vga_switcheroo(chip) 0
1700 #define check_hdmi_disabled(pci) false
1701 #endif /* SUPPORT_VGA_SWITCHER */
1702
1703 /*
1704 * destructor
1705 */
1706 static int azx_free(struct azx *chip)
1707 {
1708 struct pci_dev *pci = chip->pci;
1709 int i;
1710
1711 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1712 && chip->running)
1713 pm_runtime_get_noresume(&pci->dev);
1714
1715 azx_del_card_list(chip);
1716
1717 azx_notifier_unregister(chip);
1718
1719 chip->init_failed = 1; /* to be sure */
1720 complete_all(&chip->probe_wait);
1721
1722 if (use_vga_switcheroo(chip)) {
1723 if (chip->disabled && chip->bus)
1724 snd_hda_unlock_devices(chip->bus);
1725 if (chip->vga_switcheroo_registered)
1726 vga_switcheroo_unregister_client(chip->pci);
1727 }
1728
1729 if (chip->initialized) {
1730 azx_clear_irq_pending(chip);
1731 for (i = 0; i < chip->num_streams; i++)
1732 azx_stream_stop(chip, &chip->azx_dev[i]);
1733 azx_stop_chip(chip);
1734 }
1735
1736 if (chip->irq >= 0)
1737 free_irq(chip->irq, (void*)chip);
1738 if (chip->msi)
1739 pci_disable_msi(chip->pci);
1740 if (chip->remap_addr)
1741 iounmap(chip->remap_addr);
1742
1743 azx_free_stream_pages(chip);
1744 if (chip->region_requested)
1745 pci_release_regions(chip->pci);
1746 pci_disable_device(chip->pci);
1747 kfree(chip->azx_dev);
1748 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1749 if (chip->fw)
1750 release_firmware(chip->fw);
1751 #endif
1752 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1753 hda_display_power(false);
1754 hda_i915_exit();
1755 }
1756 kfree(chip);
1757
1758 return 0;
1759 }
1760
1761 static int azx_dev_free(struct snd_device *device)
1762 {
1763 return azx_free(device->device_data);
1764 }
1765
1766 #ifdef SUPPORT_VGA_SWITCHEROO
1767 /*
1768 * Check of disabled HDMI controller by vga-switcheroo
1769 */
1770 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1771 {
1772 struct pci_dev *p;
1773
1774 /* check only discrete GPU */
1775 switch (pci->vendor) {
1776 case PCI_VENDOR_ID_ATI:
1777 case PCI_VENDOR_ID_AMD:
1778 case PCI_VENDOR_ID_NVIDIA:
1779 if (pci->devfn == 1) {
1780 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1781 pci->bus->number, 0);
1782 if (p) {
1783 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1784 return p;
1785 pci_dev_put(p);
1786 }
1787 }
1788 break;
1789 }
1790 return NULL;
1791 }
1792
1793 static bool check_hdmi_disabled(struct pci_dev *pci)
1794 {
1795 bool vga_inactive = false;
1796 struct pci_dev *p = get_bound_vga(pci);
1797
1798 if (p) {
1799 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1800 vga_inactive = true;
1801 pci_dev_put(p);
1802 }
1803 return vga_inactive;
1804 }
1805 #endif /* SUPPORT_VGA_SWITCHEROO */
1806
1807 /*
1808 * white/black-listing for position_fix
1809 */
1810 static struct snd_pci_quirk position_fix_list[] = {
1811 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1812 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1813 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1814 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1815 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1816 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1817 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1818 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1819 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1820 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1821 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1822 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1823 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1824 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1825 {}
1826 };
1827
1828 static int check_position_fix(struct azx *chip, int fix)
1829 {
1830 const struct snd_pci_quirk *q;
1831
1832 switch (fix) {
1833 case POS_FIX_AUTO:
1834 case POS_FIX_LPIB:
1835 case POS_FIX_POSBUF:
1836 case POS_FIX_VIACOMBO:
1837 case POS_FIX_COMBO:
1838 return fix;
1839 }
1840
1841 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1842 if (q) {
1843 dev_info(chip->card->dev,
1844 "position_fix set to %d for device %04x:%04x\n",
1845 q->value, q->subvendor, q->subdevice);
1846 return q->value;
1847 }
1848
1849 /* Check VIA/ATI HD Audio Controller exist */
1850 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1851 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1852 return POS_FIX_VIACOMBO;
1853 }
1854 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1855 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1856 return POS_FIX_LPIB;
1857 }
1858 return POS_FIX_AUTO;
1859 }
1860
1861 /*
1862 * black-lists for probe_mask
1863 */
1864 static struct snd_pci_quirk probe_mask_list[] = {
1865 /* Thinkpad often breaks the controller communication when accessing
1866 * to the non-working (or non-existing) modem codec slot.
1867 */
1868 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1869 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1870 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1871 /* broken BIOS */
1872 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1873 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1874 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1875 /* forced codec slots */
1876 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1877 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1878 /* WinFast VP200 H (Teradici) user reported broken communication */
1879 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1880 {}
1881 };
1882
1883 #define AZX_FORCE_CODEC_MASK 0x100
1884
1885 static void check_probe_mask(struct azx *chip, int dev)
1886 {
1887 const struct snd_pci_quirk *q;
1888
1889 chip->codec_probe_mask = probe_mask[dev];
1890 if (chip->codec_probe_mask == -1) {
1891 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1892 if (q) {
1893 dev_info(chip->card->dev,
1894 "probe_mask set to 0x%x for device %04x:%04x\n",
1895 q->value, q->subvendor, q->subdevice);
1896 chip->codec_probe_mask = q->value;
1897 }
1898 }
1899
1900 /* check forced option */
1901 if (chip->codec_probe_mask != -1 &&
1902 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1903 chip->codec_mask = chip->codec_probe_mask & 0xff;
1904 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1905 chip->codec_mask);
1906 }
1907 }
1908
1909 /*
1910 * white/black-list for enable_msi
1911 */
1912 static struct snd_pci_quirk msi_black_list[] = {
1913 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1914 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1915 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1916 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1917 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1918 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1919 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1920 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1921 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1922 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1923 {}
1924 };
1925
1926 static void check_msi(struct azx *chip)
1927 {
1928 const struct snd_pci_quirk *q;
1929
1930 if (enable_msi >= 0) {
1931 chip->msi = !!enable_msi;
1932 return;
1933 }
1934 chip->msi = 1; /* enable MSI as default */
1935 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1936 if (q) {
1937 dev_info(chip->card->dev,
1938 "msi for device %04x:%04x set to %d\n",
1939 q->subvendor, q->subdevice, q->value);
1940 chip->msi = q->value;
1941 return;
1942 }
1943
1944 /* NVidia chipsets seem to cause troubles with MSI */
1945 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1946 dev_info(chip->card->dev, "Disabling MSI\n");
1947 chip->msi = 0;
1948 }
1949 }
1950
1951 /* check the snoop mode availability */
1952 static void azx_check_snoop_available(struct azx *chip)
1953 {
1954 bool snoop = chip->snoop;
1955
1956 switch (chip->driver_type) {
1957 case AZX_DRIVER_VIA:
1958 /* force to non-snoop mode for a new VIA controller
1959 * when BIOS is set
1960 */
1961 if (snoop) {
1962 u8 val;
1963 pci_read_config_byte(chip->pci, 0x42, &val);
1964 if (!(val & 0x80) && chip->pci->revision == 0x30)
1965 snoop = false;
1966 }
1967 break;
1968 case AZX_DRIVER_ATIHDMI_NS:
1969 /* new ATI HDMI requires non-snoop */
1970 snoop = false;
1971 break;
1972 case AZX_DRIVER_CTHDA:
1973 snoop = false;
1974 break;
1975 }
1976
1977 if (snoop != chip->snoop) {
1978 dev_info(chip->card->dev, "Force to %s mode\n",
1979 snoop ? "snoop" : "non-snoop");
1980 chip->snoop = snoop;
1981 }
1982 }
1983
1984 static void azx_probe_work(struct work_struct *work)
1985 {
1986 azx_probe_continue(container_of(work, struct azx, probe_work));
1987 }
1988
1989 /*
1990 * constructor
1991 */
1992 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1993 int dev, unsigned int driver_caps,
1994 const struct hda_controller_ops *hda_ops,
1995 struct azx **rchip)
1996 {
1997 static struct snd_device_ops ops = {
1998 .dev_free = azx_dev_free,
1999 };
2000 struct azx *chip;
2001 int err;
2002
2003 *rchip = NULL;
2004
2005 err = pci_enable_device(pci);
2006 if (err < 0)
2007 return err;
2008
2009 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2010 if (!chip) {
2011 dev_err(card->dev, "Cannot allocate chip\n");
2012 pci_disable_device(pci);
2013 return -ENOMEM;
2014 }
2015
2016 spin_lock_init(&chip->reg_lock);
2017 mutex_init(&chip->open_mutex);
2018 chip->card = card;
2019 chip->pci = pci;
2020 chip->ops = hda_ops;
2021 chip->irq = -1;
2022 chip->driver_caps = driver_caps;
2023 chip->driver_type = driver_caps & 0xff;
2024 check_msi(chip);
2025 chip->dev_index = dev;
2026 chip->jackpoll_ms = jackpoll_ms;
2027 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2028 INIT_LIST_HEAD(&chip->pcm_list);
2029 INIT_LIST_HEAD(&chip->list);
2030 init_vga_switcheroo(chip);
2031 init_completion(&chip->probe_wait);
2032
2033 chip->position_fix[0] = chip->position_fix[1] =
2034 check_position_fix(chip, position_fix[dev]);
2035 /* combo mode uses LPIB for playback */
2036 if (chip->position_fix[0] == POS_FIX_COMBO) {
2037 chip->position_fix[0] = POS_FIX_LPIB;
2038 chip->position_fix[1] = POS_FIX_AUTO;
2039 }
2040
2041 check_probe_mask(chip, dev);
2042
2043 chip->single_cmd = single_cmd;
2044 chip->snoop = hda_snoop;
2045 azx_check_snoop_available(chip);
2046
2047 if (bdl_pos_adj[dev] < 0) {
2048 switch (chip->driver_type) {
2049 case AZX_DRIVER_ICH:
2050 case AZX_DRIVER_PCH:
2051 bdl_pos_adj[dev] = 1;
2052 break;
2053 default:
2054 bdl_pos_adj[dev] = 32;
2055 break;
2056 }
2057 }
2058 chip->bdl_pos_adj = bdl_pos_adj;
2059
2060 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2061 if (err < 0) {
2062 dev_err(card->dev, "Error creating device [card]!\n");
2063 azx_free(chip);
2064 return err;
2065 }
2066
2067 /* continue probing in work context as may trigger request module */
2068 INIT_WORK(&chip->probe_work, azx_probe_work);
2069
2070 *rchip = chip;
2071
2072 return 0;
2073 }
2074
2075 static int azx_first_init(struct azx *chip)
2076 {
2077 int dev = chip->dev_index;
2078 struct pci_dev *pci = chip->pci;
2079 struct snd_card *card = chip->card;
2080 int err;
2081 unsigned short gcap;
2082
2083 #if BITS_PER_LONG != 64
2084 /* Fix up base address on ULI M5461 */
2085 if (chip->driver_type == AZX_DRIVER_ULI) {
2086 u16 tmp3;
2087 pci_read_config_word(pci, 0x40, &tmp3);
2088 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2089 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2090 }
2091 #endif
2092
2093 err = pci_request_regions(pci, "ICH HD audio");
2094 if (err < 0)
2095 return err;
2096 chip->region_requested = 1;
2097
2098 chip->addr = pci_resource_start(pci, 0);
2099 chip->remap_addr = pci_ioremap_bar(pci, 0);
2100 if (chip->remap_addr == NULL) {
2101 dev_err(card->dev, "ioremap error\n");
2102 return -ENXIO;
2103 }
2104
2105 if (chip->msi)
2106 if (pci_enable_msi(pci) < 0)
2107 chip->msi = 0;
2108
2109 if (azx_acquire_irq(chip, 0) < 0)
2110 return -EBUSY;
2111
2112 pci_set_master(pci);
2113 synchronize_irq(chip->irq);
2114
2115 gcap = azx_readw(chip, GCAP);
2116 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
2117
2118 /* disable SB600 64bit support for safety */
2119 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2120 struct pci_dev *p_smbus;
2121 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2122 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2123 NULL);
2124 if (p_smbus) {
2125 if (p_smbus->revision < 0x30)
2126 gcap &= ~ICH6_GCAP_64OK;
2127 pci_dev_put(p_smbus);
2128 }
2129 }
2130
2131 /* disable 64bit DMA address on some devices */
2132 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2133 dev_dbg(card->dev, "Disabling 64bit DMA\n");
2134 gcap &= ~ICH6_GCAP_64OK;
2135 }
2136
2137 /* disable buffer size rounding to 128-byte multiples if supported */
2138 if (align_buffer_size >= 0)
2139 chip->align_buffer_size = !!align_buffer_size;
2140 else {
2141 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2142 chip->align_buffer_size = 0;
2143 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2144 chip->align_buffer_size = 1;
2145 else
2146 chip->align_buffer_size = 1;
2147 }
2148
2149 /* allow 64bit DMA address if supported by H/W */
2150 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2151 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2152 else {
2153 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2154 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2155 }
2156
2157 /* read number of streams from GCAP register instead of using
2158 * hardcoded value
2159 */
2160 chip->capture_streams = (gcap >> 8) & 0x0f;
2161 chip->playback_streams = (gcap >> 12) & 0x0f;
2162 if (!chip->playback_streams && !chip->capture_streams) {
2163 /* gcap didn't give any info, switching to old method */
2164
2165 switch (chip->driver_type) {
2166 case AZX_DRIVER_ULI:
2167 chip->playback_streams = ULI_NUM_PLAYBACK;
2168 chip->capture_streams = ULI_NUM_CAPTURE;
2169 break;
2170 case AZX_DRIVER_ATIHDMI:
2171 case AZX_DRIVER_ATIHDMI_NS:
2172 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2173 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2174 break;
2175 case AZX_DRIVER_GENERIC:
2176 default:
2177 chip->playback_streams = ICH6_NUM_PLAYBACK;
2178 chip->capture_streams = ICH6_NUM_CAPTURE;
2179 break;
2180 }
2181 }
2182 chip->capture_index_offset = 0;
2183 chip->playback_index_offset = chip->capture_streams;
2184 chip->num_streams = chip->playback_streams + chip->capture_streams;
2185 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2186 GFP_KERNEL);
2187 if (!chip->azx_dev) {
2188 dev_err(card->dev, "cannot malloc azx_dev\n");
2189 return -ENOMEM;
2190 }
2191
2192 err = azx_alloc_stream_pages(chip);
2193 if (err < 0)
2194 return err;
2195 /* allocate CORB/RIRB */
2196 err = azx_alloc_cmd_io(chip);
2197 if (err < 0)
2198 return err;
2199
2200 /* initialize streams */
2201 azx_init_stream(chip);
2202
2203 /* initialize chip */
2204 azx_init_pci(chip);
2205 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2206
2207 /* codec detection */
2208 if (!chip->codec_mask) {
2209 dev_err(card->dev, "no codecs found!\n");
2210 return -ENODEV;
2211 }
2212
2213 strcpy(card->driver, "HDA-Intel");
2214 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2215 sizeof(card->shortname));
2216 snprintf(card->longname, sizeof(card->longname),
2217 "%s at 0x%lx irq %i",
2218 card->shortname, chip->addr, chip->irq);
2219
2220 return 0;
2221 }
2222
2223 static void power_down_all_codecs(struct azx *chip)
2224 {
2225 #ifdef CONFIG_PM
2226 /* The codecs were powered up in snd_hda_codec_new().
2227 * Now all initialization done, so turn them down if possible
2228 */
2229 struct hda_codec *codec;
2230 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2231 snd_hda_power_down(codec);
2232 }
2233 #endif
2234 }
2235
2236 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2237 /* callback from request_firmware_nowait() */
2238 static void azx_firmware_cb(const struct firmware *fw, void *context)
2239 {
2240 struct snd_card *card = context;
2241 struct azx *chip = card->private_data;
2242 struct pci_dev *pci = chip->pci;
2243
2244 if (!fw) {
2245 dev_err(card->dev, "Cannot load firmware, aborting\n");
2246 goto error;
2247 }
2248
2249 chip->fw = fw;
2250 if (!chip->disabled) {
2251 /* continue probing */
2252 if (azx_probe_continue(chip))
2253 goto error;
2254 }
2255 return; /* OK */
2256
2257 error:
2258 snd_card_free(card);
2259 pci_set_drvdata(pci, NULL);
2260 }
2261 #endif
2262
2263 /*
2264 * HDA controller ops.
2265 */
2266
2267 /* PCI register access. */
2268 static void pci_azx_writel(u32 value, u32 *addr)
2269 {
2270 writel(value, addr);
2271 }
2272
2273 static u32 pci_azx_readl(u32 *addr)
2274 {
2275 return readl(addr);
2276 }
2277
2278 static void pci_azx_writew(u16 value, u16 *addr)
2279 {
2280 writew(value, addr);
2281 }
2282
2283 static u16 pci_azx_readw(u16 *addr)
2284 {
2285 return readw(addr);
2286 }
2287
2288 static void pci_azx_writeb(u8 value, u8 *addr)
2289 {
2290 writeb(value, addr);
2291 }
2292
2293 static u8 pci_azx_readb(u8 *addr)
2294 {
2295 return readb(addr);
2296 }
2297
2298 static int disable_msi_reset_irq(struct azx *chip)
2299 {
2300 int err;
2301
2302 free_irq(chip->irq, chip);
2303 chip->irq = -1;
2304 pci_disable_msi(chip->pci);
2305 chip->msi = 0;
2306 err = azx_acquire_irq(chip, 1);
2307 if (err < 0)
2308 return err;
2309
2310 return 0;
2311 }
2312
2313 /* DMA page allocation helpers. */
2314 static int dma_alloc_pages(struct azx *chip,
2315 int type,
2316 size_t size,
2317 struct snd_dma_buffer *buf)
2318 {
2319 int err;
2320
2321 err = snd_dma_alloc_pages(type,
2322 chip->card->dev,
2323 size, buf);
2324 if (err < 0)
2325 return err;
2326 mark_pages_wc(chip, buf, true);
2327 return 0;
2328 }
2329
2330 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
2331 {
2332 mark_pages_wc(chip, buf, false);
2333 snd_dma_free_pages(buf);
2334 }
2335
2336 static int substream_alloc_pages(struct azx *chip,
2337 struct snd_pcm_substream *substream,
2338 size_t size)
2339 {
2340 struct azx_dev *azx_dev = get_azx_dev(substream);
2341 int ret;
2342
2343 mark_runtime_wc(chip, azx_dev, substream, false);
2344 azx_dev->bufsize = 0;
2345 azx_dev->period_bytes = 0;
2346 azx_dev->format_val = 0;
2347 ret = snd_pcm_lib_malloc_pages(substream, size);
2348 if (ret < 0)
2349 return ret;
2350 mark_runtime_wc(chip, azx_dev, substream, true);
2351 return 0;
2352 }
2353
2354 static int substream_free_pages(struct azx *chip,
2355 struct snd_pcm_substream *substream)
2356 {
2357 struct azx_dev *azx_dev = get_azx_dev(substream);
2358 mark_runtime_wc(chip, azx_dev, substream, false);
2359 return snd_pcm_lib_free_pages(substream);
2360 }
2361
2362 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2363 struct vm_area_struct *area)
2364 {
2365 #ifdef CONFIG_X86
2366 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2367 struct azx *chip = apcm->chip;
2368 if (!azx_snoop(chip))
2369 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2370 #endif
2371 }
2372
2373 static const struct hda_controller_ops pci_hda_ops = {
2374 .writel = pci_azx_writel,
2375 .readl = pci_azx_readl,
2376 .writew = pci_azx_writew,
2377 .readw = pci_azx_readw,
2378 .writeb = pci_azx_writeb,
2379 .readb = pci_azx_readb,
2380 .disable_msi_reset_irq = disable_msi_reset_irq,
2381 .dma_alloc_pages = dma_alloc_pages,
2382 .dma_free_pages = dma_free_pages,
2383 .substream_alloc_pages = substream_alloc_pages,
2384 .substream_free_pages = substream_free_pages,
2385 .pcm_mmap_prepare = pcm_mmap_prepare,
2386 };
2387
2388 static int azx_probe(struct pci_dev *pci,
2389 const struct pci_device_id *pci_id)
2390 {
2391 static int dev;
2392 struct snd_card *card;
2393 struct azx *chip;
2394 bool schedule_probe;
2395 int err;
2396
2397 if (dev >= SNDRV_CARDS)
2398 return -ENODEV;
2399 if (!enable[dev]) {
2400 dev++;
2401 return -ENOENT;
2402 }
2403
2404 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2405 0, &card);
2406 if (err < 0) {
2407 dev_err(&pci->dev, "Error creating card!\n");
2408 return err;
2409 }
2410
2411 err = azx_create(card, pci, dev, pci_id->driver_data,
2412 &pci_hda_ops, &chip);
2413 if (err < 0)
2414 goto out_free;
2415 card->private_data = chip;
2416
2417 pci_set_drvdata(pci, card);
2418
2419 err = register_vga_switcheroo(chip);
2420 if (err < 0) {
2421 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
2422 goto out_free;
2423 }
2424
2425 if (check_hdmi_disabled(pci)) {
2426 dev_info(card->dev, "VGA controller is disabled\n");
2427 dev_info(card->dev, "Delaying initialization\n");
2428 chip->disabled = true;
2429 }
2430
2431 schedule_probe = !chip->disabled;
2432
2433 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2434 if (patch[dev] && *patch[dev]) {
2435 dev_info(card->dev, "Applying patch firmware '%s'\n",
2436 patch[dev]);
2437 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2438 &pci->dev, GFP_KERNEL, card,
2439 azx_firmware_cb);
2440 if (err < 0)
2441 goto out_free;
2442 schedule_probe = false; /* continued in azx_firmware_cb() */
2443 }
2444 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2445
2446 #ifndef CONFIG_SND_HDA_I915
2447 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2448 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2449 #endif
2450
2451 if (schedule_probe)
2452 schedule_work(&chip->probe_work);
2453
2454 dev++;
2455 if (chip->disabled)
2456 complete_all(&chip->probe_wait);
2457 return 0;
2458
2459 out_free:
2460 snd_card_free(card);
2461 return err;
2462 }
2463
2464 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2465 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2466 [AZX_DRIVER_NVIDIA] = 8,
2467 [AZX_DRIVER_TERA] = 1,
2468 };
2469
2470 static int azx_probe_continue(struct azx *chip)
2471 {
2472 struct pci_dev *pci = chip->pci;
2473 int dev = chip->dev_index;
2474 int err;
2475
2476 /* Request power well for Haswell HDA controller and codec */
2477 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2478 #ifdef CONFIG_SND_HDA_I915
2479 err = hda_i915_init();
2480 if (err < 0) {
2481 dev_err(chip->card->dev,
2482 "Error request power-well from i915\n");
2483 goto out_free;
2484 }
2485 #endif
2486 hda_display_power(true);
2487 }
2488
2489 err = azx_first_init(chip);
2490 if (err < 0)
2491 goto out_free;
2492
2493 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2494 chip->beep_mode = beep_mode[dev];
2495 #endif
2496
2497 /* create codec instances */
2498 err = azx_codec_create(chip, model[dev],
2499 azx_max_codecs[chip->driver_type],
2500 power_save_addr);
2501
2502 if (err < 0)
2503 goto out_free;
2504 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2505 if (chip->fw) {
2506 err = snd_hda_load_patch(chip->bus, chip->fw->size,
2507 chip->fw->data);
2508 if (err < 0)
2509 goto out_free;
2510 #ifndef CONFIG_PM
2511 release_firmware(chip->fw); /* no longer needed */
2512 chip->fw = NULL;
2513 #endif
2514 }
2515 #endif
2516 if ((probe_only[dev] & 1) == 0) {
2517 err = azx_codec_configure(chip);
2518 if (err < 0)
2519 goto out_free;
2520 }
2521
2522 /* create PCM streams */
2523 err = snd_hda_build_pcms(chip->bus);
2524 if (err < 0)
2525 goto out_free;
2526
2527 /* create mixer controls */
2528 err = azx_mixer_create(chip);
2529 if (err < 0)
2530 goto out_free;
2531
2532 err = snd_card_register(chip->card);
2533 if (err < 0)
2534 goto out_free;
2535
2536 chip->running = 1;
2537 power_down_all_codecs(chip);
2538 azx_notifier_register(chip);
2539 azx_add_card_list(chip);
2540 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
2541 pm_runtime_put_noidle(&pci->dev);
2542
2543 out_free:
2544 if (err < 0)
2545 chip->init_failed = 1;
2546 complete_all(&chip->probe_wait);
2547 return err;
2548 }
2549
2550 static void azx_remove(struct pci_dev *pci)
2551 {
2552 struct snd_card *card = pci_get_drvdata(pci);
2553
2554 if (card)
2555 snd_card_free(card);
2556 }
2557
2558 /* PCI IDs */
2559 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2560 /* CPT */
2561 { PCI_DEVICE(0x8086, 0x1c20),
2562 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2563 /* PBG */
2564 { PCI_DEVICE(0x8086, 0x1d20),
2565 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2566 /* Panther Point */
2567 { PCI_DEVICE(0x8086, 0x1e20),
2568 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2569 /* Lynx Point */
2570 { PCI_DEVICE(0x8086, 0x8c20),
2571 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2572 /* Wellsburg */
2573 { PCI_DEVICE(0x8086, 0x8d20),
2574 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2575 { PCI_DEVICE(0x8086, 0x8d21),
2576 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2577 /* Lynx Point-LP */
2578 { PCI_DEVICE(0x8086, 0x9c20),
2579 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2580 /* Lynx Point-LP */
2581 { PCI_DEVICE(0x8086, 0x9c21),
2582 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2583 /* Wildcat Point-LP */
2584 { PCI_DEVICE(0x8086, 0x9ca0),
2585 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2586 /* Haswell */
2587 { PCI_DEVICE(0x8086, 0x0a0c),
2588 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2589 { PCI_DEVICE(0x8086, 0x0c0c),
2590 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2591 { PCI_DEVICE(0x8086, 0x0d0c),
2592 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2593 /* Broadwell */
2594 { PCI_DEVICE(0x8086, 0x160c),
2595 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2596 /* 5 Series/3400 */
2597 { PCI_DEVICE(0x8086, 0x3b56),
2598 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2599 /* Poulsbo */
2600 { PCI_DEVICE(0x8086, 0x811b),
2601 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2602 /* Oaktrail */
2603 { PCI_DEVICE(0x8086, 0x080a),
2604 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2605 /* BayTrail */
2606 { PCI_DEVICE(0x8086, 0x0f04),
2607 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2608 /* ICH */
2609 { PCI_DEVICE(0x8086, 0x2668),
2610 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2611 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2612 { PCI_DEVICE(0x8086, 0x27d8),
2613 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2614 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2615 { PCI_DEVICE(0x8086, 0x269a),
2616 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2617 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2618 { PCI_DEVICE(0x8086, 0x284b),
2619 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2620 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2621 { PCI_DEVICE(0x8086, 0x293e),
2622 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2623 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2624 { PCI_DEVICE(0x8086, 0x293f),
2625 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2626 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2627 { PCI_DEVICE(0x8086, 0x3a3e),
2628 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2629 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2630 { PCI_DEVICE(0x8086, 0x3a6e),
2631 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2632 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2633 /* Generic Intel */
2634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2635 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2636 .class_mask = 0xffffff,
2637 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2638 /* ATI SB 450/600/700/800/900 */
2639 { PCI_DEVICE(0x1002, 0x437b),
2640 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2641 { PCI_DEVICE(0x1002, 0x4383),
2642 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2643 /* AMD Hudson */
2644 { PCI_DEVICE(0x1022, 0x780d),
2645 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2646 /* ATI HDMI */
2647 { PCI_DEVICE(0x1002, 0x793b),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_DEVICE(0x1002, 0x7919),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_DEVICE(0x1002, 0x960f),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_DEVICE(0x1002, 0x970f),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_DEVICE(0x1002, 0xaa00),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_DEVICE(0x1002, 0xaa08),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_DEVICE(0x1002, 0xaa10),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_DEVICE(0x1002, 0xaa18),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_DEVICE(0x1002, 0xaa20),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_DEVICE(0x1002, 0xaa28),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_DEVICE(0x1002, 0xaa30),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_DEVICE(0x1002, 0xaa38),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_DEVICE(0x1002, 0xaa40),
2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2673 { PCI_DEVICE(0x1002, 0xaa48),
2674 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2675 { PCI_DEVICE(0x1002, 0xaa50),
2676 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2677 { PCI_DEVICE(0x1002, 0xaa58),
2678 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2679 { PCI_DEVICE(0x1002, 0xaa60),
2680 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2681 { PCI_DEVICE(0x1002, 0xaa68),
2682 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2683 { PCI_DEVICE(0x1002, 0xaa80),
2684 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2685 { PCI_DEVICE(0x1002, 0xaa88),
2686 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2687 { PCI_DEVICE(0x1002, 0xaa90),
2688 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2689 { PCI_DEVICE(0x1002, 0xaa98),
2690 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2691 { PCI_DEVICE(0x1002, 0x9902),
2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2693 { PCI_DEVICE(0x1002, 0xaaa0),
2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2695 { PCI_DEVICE(0x1002, 0xaaa8),
2696 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2697 { PCI_DEVICE(0x1002, 0xaab0),
2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2699 /* VIA VT8251/VT8237A */
2700 { PCI_DEVICE(0x1106, 0x3288),
2701 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2702 /* VIA GFX VT7122/VX900 */
2703 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2704 /* VIA GFX VT6122/VX11 */
2705 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2706 /* SIS966 */
2707 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2708 /* ULI M5461 */
2709 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2710 /* NVIDIA MCP */
2711 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2712 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2713 .class_mask = 0xffffff,
2714 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2715 /* Teradici */
2716 { PCI_DEVICE(0x6549, 0x1200),
2717 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2718 { PCI_DEVICE(0x6549, 0x2200),
2719 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2720 /* Creative X-Fi (CA0110-IBG) */
2721 /* CTHDA chips */
2722 { PCI_DEVICE(0x1102, 0x0010),
2723 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2724 { PCI_DEVICE(0x1102, 0x0012),
2725 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2726 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2727 /* the following entry conflicts with snd-ctxfi driver,
2728 * as ctxfi driver mutates from HD-audio to native mode with
2729 * a special command sequence.
2730 */
2731 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2732 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2733 .class_mask = 0xffffff,
2734 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2735 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2736 #else
2737 /* this entry seems still valid -- i.e. without emu20kx chip */
2738 { PCI_DEVICE(0x1102, 0x0009),
2739 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2740 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2741 #endif
2742 /* Vortex86MX */
2743 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2744 /* VMware HDAudio */
2745 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2746 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2747 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2748 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2749 .class_mask = 0xffffff,
2750 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2751 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2752 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2753 .class_mask = 0xffffff,
2754 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2755 { 0, }
2756 };
2757 MODULE_DEVICE_TABLE(pci, azx_ids);
2758
2759 /* pci_driver definition */
2760 static struct pci_driver azx_driver = {
2761 .name = KBUILD_MODNAME,
2762 .id_table = azx_ids,
2763 .probe = azx_probe,
2764 .remove = azx_remove,
2765 .driver = {
2766 .pm = AZX_PM_OPS,
2767 },
2768 };
2769
2770 module_pci_driver(azx_driver);
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