1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
53 #include <linux/netdevice.h>
54 #include <linux/ethtool.h>
55 #include <linux/delay.h>
56 #include <linux/pci.h>
60 #define ICH_FLASH_GFPREG 0x0000
61 #define ICH_FLASH_HSFSTS 0x0004
62 #define ICH_FLASH_HSFCTL 0x0006
63 #define ICH_FLASH_FADDR 0x0008
64 #define ICH_FLASH_FDATA0 0x0010
65 #define ICH_FLASH_PR0 0x0074
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73 #define ICH_CYCLE_READ 0
74 #define ICH_CYCLE_WRITE 2
75 #define ICH_CYCLE_ERASE 3
77 #define FLASH_GFPREG_BASE_MASK 0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT 12
80 #define ICH_FLASH_SEG_SIZE_256 256
81 #define ICH_FLASH_SEG_SIZE_4K 4096
82 #define ICH_FLASH_SEG_SIZE_8K 8192
83 #define ICH_FLASH_SEG_SIZE_64K 65536
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 #define E1000_ICH_MNG_IAMT_MODE 0x2
90 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
91 (ID_LED_DEF1_OFF2 << 8) | \
92 (ID_LED_DEF1_ON2 << 4) | \
95 #define E1000_ICH_NVM_SIG_WORD 0x13
96 #define E1000_ICH_NVM_SIG_MASK 0xC000
97 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
98 #define E1000_ICH_NVM_SIG_VALUE 0x80
100 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102 #define E1000_FEXTNVM_SW_CONFIG 1
103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107 #define E1000_ICH_RAR_ENTRIES 7
109 #define PHY_PAGE_SHIFT 5
110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
111 ((reg) & MAX_PHY_REG_ADDRESS))
112 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
116 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120 /* Offset 04h HSFSTS */
121 union ich8_hws_flash_status
{
123 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
124 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
125 u16 dael
:1; /* bit 2 Direct Access error Log */
126 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
127 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
128 u16 reserved1
:2; /* bit 13:6 Reserved */
129 u16 reserved2
:6; /* bit 13:6 Reserved */
130 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
131 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137 /* Offset 06h FLCTL */
138 union ich8_hws_flash_ctrl
{
139 struct ich8_hsflctl
{
140 u16 flcgo
:1; /* 0 Flash Cycle Go */
141 u16 flcycle
:2; /* 2:1 Flash Cycle */
142 u16 reserved
:5; /* 7:3 Reserved */
143 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
144 u16 flockdn
:6; /* 15:10 Reserved */
149 /* ICH Flash Region Access Permissions */
150 union ich8_hws_flash_regacc
{
152 u32 grra
:8; /* 0:7 GbE region Read Access */
153 u32 grwa
:8; /* 8:15 GbE region Write Access */
154 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
155 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
160 /* ICH Flash Protected Region */
161 union ich8_flash_protected_range
{
163 u32 base
:13; /* 0:12 Protected Range Base */
164 u32 reserved1
:2; /* 13:14 Reserved */
165 u32 rpe
:1; /* 15 Read Protection Enable */
166 u32 limit
:13; /* 16:28 Protected Range Limit */
167 u32 reserved2
:2; /* 29:30 Reserved */
168 u32 wpe
:1; /* 31 Write Protection Enable */
173 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
174 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
175 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
176 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
177 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
178 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
179 u32 offset
, u8 byte
);
180 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
182 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
184 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
186 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
187 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
188 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
190 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
192 return readw(hw
->flash_address
+ reg
);
195 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
197 return readl(hw
->flash_address
+ reg
);
200 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
202 writew(val
, hw
->flash_address
+ reg
);
205 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
207 writel(val
, hw
->flash_address
+ reg
);
210 #define er16flash(reg) __er16flash(hw, (reg))
211 #define er32flash(reg) __er32flash(hw, (reg))
212 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
213 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
216 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217 * @hw: pointer to the HW structure
219 * Initialize family-specific PHY parameters and function pointers.
221 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
223 struct e1000_phy_info
*phy
= &hw
->phy
;
228 phy
->reset_delay_us
= 100;
231 * We may need to do this twice - once for IGP and if that fails,
232 * we'll set BM func pointers and try again
234 ret_val
= e1000e_determine_phy_address(hw
);
236 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
237 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
238 ret_val
= e1000e_determine_phy_address(hw
);
244 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
247 ret_val
= e1000e_get_phy_id(hw
);
254 case IGP03E1000_E_PHY_ID
:
255 phy
->type
= e1000_phy_igp_3
;
256 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
259 case IFE_PLUS_E_PHY_ID
:
261 phy
->type
= e1000_phy_ife
;
262 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
264 case BME1000_E_PHY_ID
:
265 phy
->type
= e1000_phy_bm
;
266 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
267 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
268 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
269 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
272 return -E1000_ERR_PHY
;
280 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
281 * @hw: pointer to the HW structure
283 * Initialize family-specific NVM parameters and function
286 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
288 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
289 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
291 u32 sector_base_addr
;
295 /* Can't read flash registers if the register set isn't mapped. */
296 if (!hw
->flash_address
) {
297 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
298 return -E1000_ERR_CONFIG
;
301 nvm
->type
= e1000_nvm_flash_sw
;
303 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
306 * sector_X_addr is a "sector"-aligned address (4096 bytes)
307 * Add 1 to sector_end_addr since this sector is included in
310 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
311 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
313 /* flash_base_addr is byte-aligned */
314 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
317 * find total size of the NVM, then cut in half since the total
318 * size represents two separate NVM banks.
320 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
321 << FLASH_SECTOR_ADDR_SHIFT
;
322 nvm
->flash_bank_size
/= 2;
323 /* Adjust to word count */
324 nvm
->flash_bank_size
/= sizeof(u16
);
326 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
328 /* Clear shadow ram */
329 for (i
= 0; i
< nvm
->word_size
; i
++) {
330 dev_spec
->shadow_ram
[i
].modified
= 0;
331 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
338 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
339 * @hw: pointer to the HW structure
341 * Initialize family-specific MAC parameters and function
344 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
346 struct e1000_hw
*hw
= &adapter
->hw
;
347 struct e1000_mac_info
*mac
= &hw
->mac
;
349 /* Set media type function pointer */
350 hw
->phy
.media_type
= e1000_media_type_copper
;
352 /* Set mta register count */
353 mac
->mta_reg_count
= 32;
354 /* Set rar entry count */
355 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
356 if (mac
->type
== e1000_ich8lan
)
357 mac
->rar_entry_count
--;
358 /* Set if manageability features are enabled. */
359 mac
->arc_subsystem_valid
= 1;
361 /* Enable PCS Lock-loss workaround for ICH8 */
362 if (mac
->type
== e1000_ich8lan
)
363 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
368 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
370 struct e1000_hw
*hw
= &adapter
->hw
;
373 rc
= e1000_init_mac_params_ich8lan(adapter
);
377 rc
= e1000_init_nvm_params_ich8lan(hw
);
381 rc
= e1000_init_phy_params_ich8lan(hw
);
385 if (adapter
->hw
.phy
.type
== e1000_phy_ife
) {
386 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
387 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
390 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
391 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
392 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
397 static DEFINE_MUTEX(nvm_mutex
);
400 * e1000_acquire_swflag_ich8lan - Acquire software control flag
401 * @hw: pointer to the HW structure
403 * Acquires the software control flag for performing NVM and PHY
404 * operations. This is a function pointer entry point only called by
405 * read/write routines for the PHY and NVM parts.
407 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
410 u32 timeout
= PHY_CFG_TIMEOUT
;
414 mutex_lock(&nvm_mutex
);
417 extcnf_ctrl
= er32(EXTCNF_CTRL
);
418 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
419 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
421 extcnf_ctrl
= er32(EXTCNF_CTRL
);
422 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
429 hw_dbg(hw
, "FW or HW has locked the resource for too long.\n");
430 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
431 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
432 mutex_unlock(&nvm_mutex
);
433 return -E1000_ERR_CONFIG
;
440 * e1000_release_swflag_ich8lan - Release software control flag
441 * @hw: pointer to the HW structure
443 * Releases the software control flag for performing NVM and PHY operations.
444 * This is a function pointer entry point only called by read/write
445 * routines for the PHY and NVM parts.
447 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
451 extcnf_ctrl
= er32(EXTCNF_CTRL
);
452 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
453 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
455 mutex_unlock(&nvm_mutex
);
459 * e1000_check_mng_mode_ich8lan - Checks management mode
460 * @hw: pointer to the HW structure
462 * This checks if the adapter has manageability enabled.
463 * This is a function pointer entry point only called by read/write
464 * routines for the PHY and NVM parts.
466 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
468 u32 fwsm
= er32(FWSM
);
470 return (fwsm
& E1000_FWSM_MODE_MASK
) ==
471 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
);
475 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
476 * @hw: pointer to the HW structure
478 * Checks if firmware is blocking the reset of the PHY.
479 * This is a function pointer entry point only called by
482 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
488 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
492 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
493 * @hw: pointer to the HW structure
495 * Forces the speed and duplex settings of the PHY.
496 * This is a function pointer entry point only called by
497 * PHY setup routines.
499 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
501 struct e1000_phy_info
*phy
= &hw
->phy
;
506 if (phy
->type
!= e1000_phy_ife
) {
507 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
511 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
515 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
517 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
521 /* Disable MDI-X support for 10/100 */
522 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
526 data
&= ~IFE_PMC_AUTO_MDIX
;
527 data
&= ~IFE_PMC_FORCE_MDIX
;
529 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
533 hw_dbg(hw
, "IFE PMC: %X\n", data
);
537 if (phy
->autoneg_wait_to_complete
) {
538 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
540 ret_val
= e1000e_phy_has_link_generic(hw
,
548 hw_dbg(hw
, "Link taking longer than expected.\n");
551 ret_val
= e1000e_phy_has_link_generic(hw
,
563 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
564 * @hw: pointer to the HW structure
567 * This is a function pointer entry point called by drivers
568 * or other shared routines.
570 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
572 struct e1000_phy_info
*phy
= &hw
->phy
;
574 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
576 u16 loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
577 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
579 ret_val
= e1000e_phy_hw_reset_generic(hw
);
584 * Initialize the PHY from the NVM on ICH platforms. This
585 * is needed due to an issue where the NVM configuration is
586 * not properly autoloaded after power transitions.
587 * Therefore, after each PHY reset, we will load the
588 * configuration data out of the NVM manually.
590 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
591 struct e1000_adapter
*adapter
= hw
->adapter
;
593 /* Check if SW needs configure the PHY */
594 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
595 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
596 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
598 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
600 data
= er32(FEXTNVM
);
601 if (!(data
& sw_cfg_mask
))
604 /* Wait for basic configuration completes before proceeding*/
607 data
&= E1000_STATUS_LAN_INIT_DONE
;
609 } while ((!data
) && --loop
);
612 * If basic configuration is incomplete before the above loop
613 * count reaches 0, loading the configuration from NVM will
614 * leave the PHY in a bad state possibly resulting in no link.
617 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
620 /* Clear the Init Done bit for the next init event */
622 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
626 * Make sure HW does not configure LCD from PHY
627 * extended configuration before SW configuration
629 data
= er32(EXTCNF_CTRL
);
630 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
633 cnf_size
= er32(EXTCNF_SIZE
);
634 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
635 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
639 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
640 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
642 /* Configure LCD from extended configuration region. */
644 /* cnf_base_addr is in DWORD */
645 word_addr
= (u16
)(cnf_base_addr
<< 1);
647 for (i
= 0; i
< cnf_size
; i
++) {
648 ret_val
= e1000_read_nvm(hw
,
655 ret_val
= e1000_read_nvm(hw
,
656 (word_addr
+ i
* 2 + 1),
662 /* Save off the PHY page for future writes. */
663 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
668 reg_addr
|= phy_page
;
670 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
680 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
681 * @hw: pointer to the HW structure
683 * Populates "phy" structure with various feature states.
684 * This function is only called by other family-specific
687 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
689 struct e1000_phy_info
*phy
= &hw
->phy
;
694 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
699 hw_dbg(hw
, "Phy info is only valid if link is up\n");
700 return -E1000_ERR_CONFIG
;
703 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
706 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
708 if (phy
->polarity_correction
) {
709 ret_val
= e1000_check_polarity_ife_ich8lan(hw
);
713 /* Polarity is forced */
714 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
715 ? e1000_rev_polarity_reversed
716 : e1000_rev_polarity_normal
;
719 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
723 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
725 /* The following parameters are undefined for 10/100 operation. */
726 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
727 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
728 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
734 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
735 * @hw: pointer to the HW structure
737 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
738 * This is a function pointer entry point called by drivers
739 * or other shared routines.
741 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
743 switch (hw
->phy
.type
) {
745 return e1000_get_phy_info_ife_ich8lan(hw
);
747 case e1000_phy_igp_3
:
749 return e1000e_get_phy_info_igp(hw
);
755 return -E1000_ERR_PHY_TYPE
;
759 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
760 * @hw: pointer to the HW structure
762 * Polarity is determined on the polarity reversal feature being enabled.
763 * This function is only called by other family-specific
766 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
768 struct e1000_phy_info
*phy
= &hw
->phy
;
770 u16 phy_data
, offset
, mask
;
773 * Polarity is determined based on the reversal feature being enabled.
775 if (phy
->polarity_correction
) {
776 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
777 mask
= IFE_PESC_POLARITY_REVERSED
;
779 offset
= IFE_PHY_SPECIAL_CONTROL
;
780 mask
= IFE_PSC_FORCE_POLARITY
;
783 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
786 phy
->cable_polarity
= (phy_data
& mask
)
787 ? e1000_rev_polarity_reversed
788 : e1000_rev_polarity_normal
;
794 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
795 * @hw: pointer to the HW structure
796 * @active: TRUE to enable LPLU, FALSE to disable
798 * Sets the LPLU D0 state according to the active flag. When
799 * activating LPLU this function also disables smart speed
800 * and vice versa. LPLU will not be activated unless the
801 * device autonegotiation advertisement meets standards of
802 * either 10 or 10/100 or 10/100/1000 at all duplexes.
803 * This is a function pointer entry point only called by
804 * PHY setup routines.
806 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
808 struct e1000_phy_info
*phy
= &hw
->phy
;
813 if (phy
->type
== e1000_phy_ife
)
816 phy_ctrl
= er32(PHY_CTRL
);
819 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
820 ew32(PHY_CTRL
, phy_ctrl
);
823 * Call gig speed drop workaround on LPLU before accessing
826 if ((hw
->mac
.type
== e1000_ich8lan
) &&
827 (hw
->phy
.type
== e1000_phy_igp_3
))
828 e1000e_gig_downshift_workaround_ich8lan(hw
);
830 /* When LPLU is enabled, we should disable SmartSpeed */
831 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
832 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
833 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
837 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
838 ew32(PHY_CTRL
, phy_ctrl
);
841 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
842 * during Dx states where the power conservation is most
843 * important. During driver activity we should enable
844 * SmartSpeed, so performance is maintained.
846 if (phy
->smart_speed
== e1000_smart_speed_on
) {
847 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
852 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
853 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
857 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
858 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
863 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
864 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
875 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
876 * @hw: pointer to the HW structure
877 * @active: TRUE to enable LPLU, FALSE to disable
879 * Sets the LPLU D3 state according to the active flag. When
880 * activating LPLU this function also disables smart speed
881 * and vice versa. LPLU will not be activated unless the
882 * device autonegotiation advertisement meets standards of
883 * either 10 or 10/100 or 10/100/1000 at all duplexes.
884 * This is a function pointer entry point only called by
885 * PHY setup routines.
887 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
889 struct e1000_phy_info
*phy
= &hw
->phy
;
894 phy_ctrl
= er32(PHY_CTRL
);
897 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
898 ew32(PHY_CTRL
, phy_ctrl
);
900 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
901 * during Dx states where the power conservation is most
902 * important. During driver activity we should enable
903 * SmartSpeed, so performance is maintained.
905 if (phy
->smart_speed
== e1000_smart_speed_on
) {
906 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
911 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
912 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
916 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
917 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
922 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
923 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
928 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
929 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
930 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
931 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
932 ew32(PHY_CTRL
, phy_ctrl
);
935 * Call gig speed drop workaround on LPLU before accessing
938 if ((hw
->mac
.type
== e1000_ich8lan
) &&
939 (hw
->phy
.type
== e1000_phy_igp_3
))
940 e1000e_gig_downshift_workaround_ich8lan(hw
);
942 /* When LPLU is enabled, we should disable SmartSpeed */
943 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
947 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
948 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
955 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
956 * @hw: pointer to the HW structure
957 * @bank: pointer to the variable that returns the active bank
959 * Reads signature byte from the NVM using the flash access registers.
960 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
962 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
965 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
966 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
967 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
971 switch (hw
->mac
.type
) {
975 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
976 E1000_EECD_SEC1VAL_VALID_MASK
) {
977 if (eecd
& E1000_EECD_SEC1VAL
)
984 hw_dbg(hw
, "Unable to determine valid NVM bank via EEC - "
985 "reading flash signature\n");
988 /* set bank to 0 in case flash read fails */
992 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
996 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
997 E1000_ICH_NVM_SIG_VALUE
) {
1003 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
1008 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
1009 E1000_ICH_NVM_SIG_VALUE
) {
1014 hw_dbg(hw
, "ERROR: No valid NVM bank present\n");
1015 return -E1000_ERR_NVM
;
1022 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1023 * @hw: pointer to the HW structure
1024 * @offset: The offset (in bytes) of the word(s) to read.
1025 * @words: Size of data to read in words
1026 * @data: Pointer to the word(s) to read at offset.
1028 * Reads a word(s) from the NVM using the flash access registers.
1030 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1033 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1034 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1040 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1042 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1043 return -E1000_ERR_NVM
;
1046 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1050 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1054 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
1055 act_offset
+= offset
;
1057 for (i
= 0; i
< words
; i
++) {
1058 if ((dev_spec
->shadow_ram
) &&
1059 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
1060 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
1062 ret_val
= e1000_read_flash_word_ich8lan(hw
,
1072 e1000_release_swflag_ich8lan(hw
);
1076 hw_dbg(hw
, "NVM read error: %d\n", ret_val
);
1082 * e1000_flash_cycle_init_ich8lan - Initialize flash
1083 * @hw: pointer to the HW structure
1085 * This function does initial flash setup so that a new read/write/erase cycle
1088 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
1090 union ich8_hws_flash_status hsfsts
;
1091 s32 ret_val
= -E1000_ERR_NVM
;
1094 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1096 /* Check if the flash descriptor is valid */
1097 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
1098 hw_dbg(hw
, "Flash descriptor invalid. "
1099 "SW Sequencing must be used.");
1100 return -E1000_ERR_NVM
;
1103 /* Clear FCERR and DAEL in hw status by writing 1 */
1104 hsfsts
.hsf_status
.flcerr
= 1;
1105 hsfsts
.hsf_status
.dael
= 1;
1107 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1110 * Either we should have a hardware SPI cycle in progress
1111 * bit to check against, in order to start a new cycle or
1112 * FDONE bit should be changed in the hardware so that it
1113 * is 1 after hardware reset, which can then be used as an
1114 * indication whether a cycle is in progress or has been
1118 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1120 * There is no cycle running at present,
1121 * so we can start a cycle
1122 * Begin by setting Flash Cycle Done.
1124 hsfsts
.hsf_status
.flcdone
= 1;
1125 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1129 * otherwise poll for sometime so the current
1130 * cycle has a chance to end before giving up.
1132 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1133 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1134 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1142 * Successful in waiting for previous cycle to timeout,
1143 * now set the Flash Cycle Done.
1145 hsfsts
.hsf_status
.flcdone
= 1;
1146 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1148 hw_dbg(hw
, "Flash controller busy, cannot get access");
1156 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1157 * @hw: pointer to the HW structure
1158 * @timeout: maximum time to wait for completion
1160 * This function starts a flash cycle and waits for its completion.
1162 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1164 union ich8_hws_flash_ctrl hsflctl
;
1165 union ich8_hws_flash_status hsfsts
;
1166 s32 ret_val
= -E1000_ERR_NVM
;
1169 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1170 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1171 hsflctl
.hsf_ctrl
.flcgo
= 1;
1172 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1174 /* wait till FDONE bit is set to 1 */
1176 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1177 if (hsfsts
.hsf_status
.flcdone
== 1)
1180 } while (i
++ < timeout
);
1182 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1189 * e1000_read_flash_word_ich8lan - Read word from flash
1190 * @hw: pointer to the HW structure
1191 * @offset: offset to data location
1192 * @data: pointer to the location for storing the data
1194 * Reads the flash word at offset into data. Offset is converted
1195 * to bytes before read.
1197 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1200 /* Must convert offset into bytes. */
1203 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1207 * e1000_read_flash_byte_ich8lan - Read byte from flash
1208 * @hw: pointer to the HW structure
1209 * @offset: The offset of the byte to read.
1210 * @data: Pointer to a byte to store the value read.
1212 * Reads a single byte from the NVM using the flash access registers.
1214 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1220 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
1230 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1231 * @hw: pointer to the HW structure
1232 * @offset: The offset (in bytes) of the byte or word to read.
1233 * @size: Size of data to read, 1=byte 2=word
1234 * @data: Pointer to the word to store the value read.
1236 * Reads a byte or word from the NVM using the flash access registers.
1238 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1241 union ich8_hws_flash_status hsfsts
;
1242 union ich8_hws_flash_ctrl hsflctl
;
1243 u32 flash_linear_addr
;
1245 s32 ret_val
= -E1000_ERR_NVM
;
1248 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1249 return -E1000_ERR_NVM
;
1251 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1252 hw
->nvm
.flash_base_addr
;
1257 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1261 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1262 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1263 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1264 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1265 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1267 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1269 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1270 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1273 * Check if FCERR is set to 1, if set to 1, clear it
1274 * and try the whole sequence a few more times, else
1275 * read in (shift in) the Flash Data0, the order is
1276 * least significant byte first msb to lsb
1279 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1281 *data
= (u8
)(flash_data
& 0x000000FF);
1282 } else if (size
== 2) {
1283 *data
= (u16
)(flash_data
& 0x0000FFFF);
1288 * If we've gotten here, then things are probably
1289 * completely hosed, but if the error condition is
1290 * detected, it won't hurt to give it another try...
1291 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1293 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1294 if (hsfsts
.hsf_status
.flcerr
== 1) {
1295 /* Repeat for some time before giving up. */
1297 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1298 hw_dbg(hw
, "Timeout error - flash cycle "
1299 "did not complete.");
1303 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1309 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1310 * @hw: pointer to the HW structure
1311 * @offset: The offset (in bytes) of the word(s) to write.
1312 * @words: Size of data to write in words
1313 * @data: Pointer to the word(s) to write at offset.
1315 * Writes a byte or word to the NVM using the flash access registers.
1317 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1320 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1321 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1325 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1327 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1328 return -E1000_ERR_NVM
;
1331 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1335 for (i
= 0; i
< words
; i
++) {
1336 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1337 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1340 e1000_release_swflag_ich8lan(hw
);
1346 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1347 * @hw: pointer to the HW structure
1349 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1350 * which writes the checksum to the shadow ram. The changes in the shadow
1351 * ram are then committed to the EEPROM by processing each bank at a time
1352 * checking for the modified bit and writing only the pending changes.
1353 * After a successful commit, the shadow ram is cleared and is ready for
1356 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1358 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1359 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1360 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
1364 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1368 if (nvm
->type
!= e1000_nvm_flash_sw
)
1371 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1376 * We're writing to the opposite bank so if we're on bank 1,
1377 * write to bank 0 etc. We also need to erase the segment that
1378 * is going to be written
1380 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
1382 e1000_release_swflag_ich8lan(hw
);
1387 new_bank_offset
= nvm
->flash_bank_size
;
1388 old_bank_offset
= 0;
1389 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
1391 e1000_release_swflag_ich8lan(hw
);
1395 old_bank_offset
= nvm
->flash_bank_size
;
1396 new_bank_offset
= 0;
1397 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
1399 e1000_release_swflag_ich8lan(hw
);
1404 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1406 * Determine whether to write the value stored
1407 * in the other NVM bank or a modified value stored
1410 if (dev_spec
->shadow_ram
[i
].modified
) {
1411 data
= dev_spec
->shadow_ram
[i
].value
;
1413 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
1421 * If the word is 0x13, then make sure the signature bits
1422 * (15:14) are 11b until the commit has completed.
1423 * This will allow us to write 10b which indicates the
1424 * signature is valid. We want to do this after the write
1425 * has completed so that we don't mark the segment valid
1426 * while the write is still in progress
1428 if (i
== E1000_ICH_NVM_SIG_WORD
)
1429 data
|= E1000_ICH_NVM_SIG_MASK
;
1431 /* Convert offset to bytes. */
1432 act_offset
= (i
+ new_bank_offset
) << 1;
1435 /* Write the bytes to the new bank. */
1436 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1443 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1451 * Don't bother writing the segment valid bits if sector
1452 * programming failed.
1455 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1456 hw_dbg(hw
, "Flash commit failed.\n");
1457 e1000_release_swflag_ich8lan(hw
);
1462 * Finally validate the new segment by setting bit 15:14
1463 * to 10b in word 0x13 , this can be done without an
1464 * erase as well since these bits are 11 to start with
1465 * and we need to change bit 14 to 0b
1467 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1468 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1470 e1000_release_swflag_ich8lan(hw
);
1474 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1478 e1000_release_swflag_ich8lan(hw
);
1483 * And invalidate the previously valid segment by setting
1484 * its signature word (0x13) high_byte to 0b. This can be
1485 * done without an erase because flash erase sets all bits
1486 * to 1's. We can write 1's to 0's without an erase
1488 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1489 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1491 e1000_release_swflag_ich8lan(hw
);
1495 /* Great! Everything worked, we can now clear the cached entries. */
1496 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1497 dev_spec
->shadow_ram
[i
].modified
= 0;
1498 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1501 e1000_release_swflag_ich8lan(hw
);
1504 * Reload the EEPROM, or else modifications will not appear
1505 * until after the next adapter reset.
1507 e1000e_reload_nvm(hw
);
1512 hw_dbg(hw
, "NVM update error: %d\n", ret_val
);
1518 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1519 * @hw: pointer to the HW structure
1521 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1522 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1523 * calculated, in which case we need to calculate the checksum and set bit 6.
1525 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1531 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1532 * needs to be fixed. This bit is an indication that the NVM
1533 * was prepared by OEM software and did not calculate the
1534 * checksum...a likely scenario.
1536 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1540 if ((data
& 0x40) == 0) {
1542 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1545 ret_val
= e1000e_update_nvm_checksum(hw
);
1550 return e1000e_validate_nvm_checksum_generic(hw
);
1554 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1555 * @hw: pointer to the HW structure
1557 * To prevent malicious write/erase of the NVM, set it to be read-only
1558 * so that the hardware ignores all write/erase cycles of the NVM via
1559 * the flash control registers. The shadow-ram copy of the NVM will
1560 * still be updated, however any updates to this copy will not stick
1561 * across driver reloads.
1563 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
1565 union ich8_flash_protected_range pr0
;
1566 union ich8_hws_flash_status hsfsts
;
1570 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1574 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
1576 /* Write-protect GbE Sector of NVM */
1577 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
1578 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
1579 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
1580 pr0
.range
.wpe
= true;
1581 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
1584 * Lock down a subset of GbE Flash Control Registers, e.g.
1585 * PR0 to prevent the write-protection from being lifted.
1586 * Once FLOCKDN is set, the registers protected by it cannot
1587 * be written until FLOCKDN is cleared by a hardware reset.
1589 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1590 hsfsts
.hsf_status
.flockdn
= true;
1591 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1593 e1000_release_swflag_ich8lan(hw
);
1597 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1598 * @hw: pointer to the HW structure
1599 * @offset: The offset (in bytes) of the byte/word to read.
1600 * @size: Size of data to read, 1=byte 2=word
1601 * @data: The byte(s) to write to the NVM.
1603 * Writes one/two bytes to the NVM using the flash access registers.
1605 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1608 union ich8_hws_flash_status hsfsts
;
1609 union ich8_hws_flash_ctrl hsflctl
;
1610 u32 flash_linear_addr
;
1615 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1616 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1617 return -E1000_ERR_NVM
;
1619 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1620 hw
->nvm
.flash_base_addr
;
1625 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1629 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1630 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1631 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1632 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1633 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1635 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1638 flash_data
= (u32
)data
& 0x00FF;
1640 flash_data
= (u32
)data
;
1642 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1645 * check if FCERR is set to 1 , if set to 1, clear it
1646 * and try the whole sequence a few more times else done
1648 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1649 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1654 * If we're here, then things are most likely
1655 * completely hosed, but if the error condition
1656 * is detected, it won't hurt to give it another
1657 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1659 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1660 if (hsfsts
.hsf_status
.flcerr
== 1)
1661 /* Repeat for some time before giving up. */
1663 if (hsfsts
.hsf_status
.flcdone
== 0) {
1664 hw_dbg(hw
, "Timeout error - flash cycle "
1665 "did not complete.");
1668 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1674 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1675 * @hw: pointer to the HW structure
1676 * @offset: The index of the byte to read.
1677 * @data: The byte to write to the NVM.
1679 * Writes a single byte to the NVM using the flash access registers.
1681 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1684 u16 word
= (u16
)data
;
1686 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1690 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1691 * @hw: pointer to the HW structure
1692 * @offset: The offset of the byte to write.
1693 * @byte: The byte to write to the NVM.
1695 * Writes a single byte to the NVM using the flash access registers.
1696 * Goes through a retry algorithm before giving up.
1698 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1699 u32 offset
, u8 byte
)
1702 u16 program_retries
;
1704 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1708 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
1709 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
1711 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1715 if (program_retries
== 100)
1716 return -E1000_ERR_NVM
;
1722 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1723 * @hw: pointer to the HW structure
1724 * @bank: 0 for first bank, 1 for second bank, etc.
1726 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1727 * bank N is 4096 * N + flash_reg_addr.
1729 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
1731 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1732 union ich8_hws_flash_status hsfsts
;
1733 union ich8_hws_flash_ctrl hsflctl
;
1734 u32 flash_linear_addr
;
1735 /* bank size is in 16bit words - adjust to bytes */
1736 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
1743 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1746 * Determine HW Sector size: Read BERASE bits of hw flash status
1748 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1749 * consecutive sectors. The start index for the nth Hw sector
1750 * can be calculated as = bank * 4096 + n * 256
1751 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1752 * The start index for the nth Hw sector can be calculated
1754 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1755 * (ich9 only, otherwise error condition)
1756 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1758 switch (hsfsts
.hsf_status
.berasesz
) {
1760 /* Hw sector size 256 */
1761 sector_size
= ICH_FLASH_SEG_SIZE_256
;
1762 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
1765 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
1766 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_4K
;
1769 if (hw
->mac
.type
== e1000_ich9lan
) {
1770 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
1771 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
1773 return -E1000_ERR_NVM
;
1777 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
1778 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_64K
;
1781 return -E1000_ERR_NVM
;
1784 /* Start with the base address, then add the sector offset. */
1785 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
1786 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
1788 for (j
= 0; j
< iteration
; j
++) {
1791 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1796 * Write a value 11 (block Erase) in Flash
1797 * Cycle field in hw flash control
1799 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1800 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
1801 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1804 * Write the last 24 bits of an index within the
1805 * block into Flash Linear address field in Flash
1808 flash_linear_addr
+= (j
* sector_size
);
1809 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1811 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1812 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
1817 * Check if FCERR is set to 1. If 1,
1818 * clear it and try the whole sequence
1819 * a few more times else Done
1821 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1822 if (hsfsts
.hsf_status
.flcerr
== 1)
1823 /* repeat for some time before giving up */
1825 else if (hsfsts
.hsf_status
.flcdone
== 0)
1827 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
1834 * e1000_valid_led_default_ich8lan - Set the default LED settings
1835 * @hw: pointer to the HW structure
1836 * @data: Pointer to the LED settings
1838 * Reads the LED default settings from the NVM to data. If the NVM LED
1839 * settings is all 0's or F's, set the LED default to a valid LED default
1842 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
1846 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1848 hw_dbg(hw
, "NVM Read Error\n");
1852 if (*data
== ID_LED_RESERVED_0000
||
1853 *data
== ID_LED_RESERVED_FFFF
)
1854 *data
= ID_LED_DEFAULT_ICH8LAN
;
1860 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1861 * @hw: pointer to the HW structure
1863 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1864 * register, so the the bus width is hard coded.
1866 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
1868 struct e1000_bus_info
*bus
= &hw
->bus
;
1871 ret_val
= e1000e_get_bus_info_pcie(hw
);
1874 * ICH devices are "PCI Express"-ish. They have
1875 * a configuration space, but do not contain
1876 * PCI Express Capability registers, so bus width
1877 * must be hardcoded.
1879 if (bus
->width
== e1000_bus_width_unknown
)
1880 bus
->width
= e1000_bus_width_pcie_x1
;
1886 * e1000_reset_hw_ich8lan - Reset the hardware
1887 * @hw: pointer to the HW structure
1889 * Does a full reset of the hardware which includes a reset of the PHY and
1892 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
1898 * Prevent the PCI-E bus from sticking if there is no TLP connection
1899 * on the last TLP read/write transaction when MAC is reset.
1901 ret_val
= e1000e_disable_pcie_master(hw
);
1903 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
1906 hw_dbg(hw
, "Masking off all interrupts\n");
1907 ew32(IMC
, 0xffffffff);
1910 * Disable the Transmit and Receive units. Then delay to allow
1911 * any pending transactions to complete before we hit the MAC
1912 * with the global reset.
1915 ew32(TCTL
, E1000_TCTL_PSP
);
1920 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1921 if (hw
->mac
.type
== e1000_ich8lan
) {
1922 /* Set Tx and Rx buffer allocation to 8k apiece. */
1923 ew32(PBA
, E1000_PBA_8K
);
1924 /* Set Packet Buffer Size to 16k. */
1925 ew32(PBS
, E1000_PBS_16K
);
1930 if (!e1000_check_reset_block(hw
)) {
1932 * PHY HW reset requires MAC CORE reset at the same
1933 * time to make sure the interface between MAC and the
1934 * external PHY is reset.
1936 ctrl
|= E1000_CTRL_PHY_RST
;
1938 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1939 /* Whether or not the swflag was acquired, we need to reset the part */
1940 hw_dbg(hw
, "Issuing a global reset to ich8lan\n");
1941 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
1945 /* release the swflag because it is not reset by
1948 e1000_release_swflag_ich8lan(hw
);
1951 ret_val
= e1000e_get_auto_rd_done(hw
);
1954 * When auto config read does not complete, do not
1955 * return with an error. This can happen in situations
1956 * where there is no eeprom and prevents getting link.
1958 hw_dbg(hw
, "Auto Read Done did not complete\n");
1961 ew32(IMC
, 0xffffffff);
1964 kab
= er32(KABGTXD
);
1965 kab
|= E1000_KABGTXD_BGSQLBIAS
;
1972 * e1000_init_hw_ich8lan - Initialize the hardware
1973 * @hw: pointer to the HW structure
1975 * Prepares the hardware for transmit and receive by doing the following:
1976 * - initialize hardware bits
1977 * - initialize LED identification
1978 * - setup receive address registers
1979 * - setup flow control
1980 * - setup transmit descriptors
1981 * - clear statistics
1983 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
1985 struct e1000_mac_info
*mac
= &hw
->mac
;
1986 u32 ctrl_ext
, txdctl
, snoop
;
1990 e1000_initialize_hw_bits_ich8lan(hw
);
1992 /* Initialize identification LED */
1993 ret_val
= e1000e_id_led_init(hw
);
1995 hw_dbg(hw
, "Error initializing identification LED\n");
1999 /* Setup the receive address. */
2000 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
2002 /* Zero out the Multicast HASH table */
2003 hw_dbg(hw
, "Zeroing the MTA\n");
2004 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
2005 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
2007 /* Setup link and flow control */
2008 ret_val
= e1000_setup_link_ich8lan(hw
);
2010 /* Set the transmit descriptor write-back policy for both queues */
2011 txdctl
= er32(TXDCTL(0));
2012 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2013 E1000_TXDCTL_FULL_TX_DESC_WB
;
2014 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2015 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2016 ew32(TXDCTL(0), txdctl
);
2017 txdctl
= er32(TXDCTL(1));
2018 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
2019 E1000_TXDCTL_FULL_TX_DESC_WB
;
2020 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
2021 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
2022 ew32(TXDCTL(1), txdctl
);
2025 * ICH8 has opposite polarity of no_snoop bits.
2026 * By default, we should use snoop behavior.
2028 if (mac
->type
== e1000_ich8lan
)
2029 snoop
= PCIE_ICH8_SNOOP_ALL
;
2031 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
2032 e1000e_set_pcie_no_snoop(hw
, snoop
);
2034 ctrl_ext
= er32(CTRL_EXT
);
2035 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
2036 ew32(CTRL_EXT
, ctrl_ext
);
2039 * Clear all of the statistics registers (clear on read). It is
2040 * important that we do this after we have tried to establish link
2041 * because the symbol error count will increment wildly if there
2044 e1000_clear_hw_cntrs_ich8lan(hw
);
2049 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2050 * @hw: pointer to the HW structure
2052 * Sets/Clears required hardware bits necessary for correctly setting up the
2053 * hardware for transmit and receive.
2055 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
2059 /* Extended Device Control */
2060 reg
= er32(CTRL_EXT
);
2062 ew32(CTRL_EXT
, reg
);
2064 /* Transmit Descriptor Control 0 */
2065 reg
= er32(TXDCTL(0));
2067 ew32(TXDCTL(0), reg
);
2069 /* Transmit Descriptor Control 1 */
2070 reg
= er32(TXDCTL(1));
2072 ew32(TXDCTL(1), reg
);
2074 /* Transmit Arbitration Control 0 */
2075 reg
= er32(TARC(0));
2076 if (hw
->mac
.type
== e1000_ich8lan
)
2077 reg
|= (1 << 28) | (1 << 29);
2078 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2081 /* Transmit Arbitration Control 1 */
2082 reg
= er32(TARC(1));
2083 if (er32(TCTL
) & E1000_TCTL_MULR
)
2087 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
2091 if (hw
->mac
.type
== e1000_ich8lan
) {
2099 * e1000_setup_link_ich8lan - Setup flow control and link settings
2100 * @hw: pointer to the HW structure
2102 * Determines which flow control settings to use, then configures flow
2103 * control. Calls the appropriate media-specific link configuration
2104 * function. Assuming the adapter has a valid link partner, a valid link
2105 * should be established. Assumes the hardware has previously been reset
2106 * and the transmitter and receiver are not enabled.
2108 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
2112 if (e1000_check_reset_block(hw
))
2116 * ICH parts do not have a word in the NVM to determine
2117 * the default flow control setting, so we explicitly
2120 if (hw
->fc
.requested_mode
== e1000_fc_default
)
2121 hw
->fc
.requested_mode
= e1000_fc_full
;
2124 * Save off the requested flow control mode for use later. Depending
2125 * on the link partner's capabilities, we may or may not use this mode.
2127 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
2129 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n",
2130 hw
->fc
.current_mode
);
2132 /* Continue to configure the copper link. */
2133 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
2137 ew32(FCTTV
, hw
->fc
.pause_time
);
2139 return e1000e_set_fc_watermarks(hw
);
2143 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2144 * @hw: pointer to the HW structure
2146 * Configures the kumeran interface to the PHY to wait the appropriate time
2147 * when polling the PHY, then call the generic setup_copper_link to finish
2148 * configuring the copper link.
2150 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
2157 ctrl
|= E1000_CTRL_SLU
;
2158 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
2162 * Set the mac to wait the maximum time between each iteration
2163 * and increase the max iterations when polling the phy;
2164 * this fixes erroneous timeouts at 10Mbps.
2166 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
2169 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
2173 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
2177 if (hw
->phy
.type
== e1000_phy_igp_3
) {
2178 ret_val
= e1000e_copper_link_setup_igp(hw
);
2181 } else if (hw
->phy
.type
== e1000_phy_bm
) {
2182 ret_val
= e1000e_copper_link_setup_m88(hw
);
2187 if (hw
->phy
.type
== e1000_phy_ife
) {
2188 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
2192 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
2194 switch (hw
->phy
.mdix
) {
2196 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
2199 reg_data
|= IFE_PMC_FORCE_MDIX
;
2203 reg_data
|= IFE_PMC_AUTO_MDIX
;
2206 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
2210 return e1000e_setup_copper_link(hw
);
2214 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2215 * @hw: pointer to the HW structure
2216 * @speed: pointer to store current link speed
2217 * @duplex: pointer to store the current link duplex
2219 * Calls the generic get_speed_and_duplex to retrieve the current link
2220 * information and then calls the Kumeran lock loss workaround for links at
2223 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
2228 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2232 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2233 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2234 (*speed
== SPEED_1000
)) {
2235 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2242 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2243 * @hw: pointer to the HW structure
2245 * Work-around for 82566 Kumeran PCS lock loss:
2246 * On link status change (i.e. PCI reset, speed change) and link is up and
2248 * 0) if workaround is optionally disabled do nothing
2249 * 1) wait 1ms for Kumeran link to come up
2250 * 2) check Kumeran Diagnostic register PCS lock loss bit
2251 * 3) if not set the link is locked (all is good), otherwise...
2253 * 5) repeat up to 10 times
2254 * Note: this is only called for IGP3 copper when speed is 1gb.
2256 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2258 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2264 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2268 * Make sure link is up before proceeding. If not just return.
2269 * Attempting this while link is negotiating fouled up link
2272 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2276 for (i
= 0; i
< 10; i
++) {
2277 /* read once to clear */
2278 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2281 /* and again to get new status */
2282 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2286 /* check for PCS lock */
2287 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2290 /* Issue PHY reset */
2291 e1000_phy_hw_reset(hw
);
2294 /* Disable GigE link negotiation */
2295 phy_ctrl
= er32(PHY_CTRL
);
2296 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2297 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2298 ew32(PHY_CTRL
, phy_ctrl
);
2301 * Call gig speed drop workaround on Gig disable before accessing
2304 e1000e_gig_downshift_workaround_ich8lan(hw
);
2306 /* unable to acquire PCS lock */
2307 return -E1000_ERR_PHY
;
2311 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2312 * @hw: pointer to the HW structure
2313 * @state: boolean value used to set the current Kumeran workaround state
2315 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2316 * /disabled - FALSE).
2318 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2321 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2323 if (hw
->mac
.type
!= e1000_ich8lan
) {
2324 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2328 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2332 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2333 * @hw: pointer to the HW structure
2335 * Workaround for 82566 power-down on D3 entry:
2336 * 1) disable gigabit link
2337 * 2) write VR power-down enable
2339 * Continue if successful, else issue LCD reset and repeat
2341 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2347 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2350 /* Try the workaround twice (if needed) */
2353 reg
= er32(PHY_CTRL
);
2354 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2355 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2356 ew32(PHY_CTRL
, reg
);
2359 * Call gig speed drop workaround on Gig disable before
2360 * accessing any PHY registers
2362 if (hw
->mac
.type
== e1000_ich8lan
)
2363 e1000e_gig_downshift_workaround_ich8lan(hw
);
2365 /* Write VR power-down enable */
2366 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2367 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2368 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2370 /* Read it back and test */
2371 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2372 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2373 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2376 /* Issue PHY reset and repeat at most one more time */
2378 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2384 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2385 * @hw: pointer to the HW structure
2387 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2388 * LPLU, Gig disable, MDIC PHY reset):
2389 * 1) Set Kumeran Near-end loopback
2390 * 2) Clear Kumeran Near-end loopback
2391 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2393 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2398 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2399 (hw
->phy
.type
!= e1000_phy_igp_3
))
2402 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2406 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2407 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2411 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2412 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2417 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2418 * @hw: pointer to the HW structure
2420 * During S0 to Sx transition, it is possible the link remains at gig
2421 * instead of negotiating to a lower speed. Before going to Sx, set
2422 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2425 * Should only be called for ICH9 and ICH10 devices.
2427 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2431 if ((hw
->mac
.type
== e1000_ich10lan
) ||
2432 (hw
->mac
.type
== e1000_ich9lan
)) {
2433 phy_ctrl
= er32(PHY_CTRL
);
2434 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2435 E1000_PHY_CTRL_GBE_DISABLE
;
2436 ew32(PHY_CTRL
, phy_ctrl
);
2443 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2444 * @hw: pointer to the HW structure
2446 * Return the LED back to the default configuration.
2448 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2450 if (hw
->phy
.type
== e1000_phy_ife
)
2451 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2453 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2458 * e1000_led_on_ich8lan - Turn LEDs on
2459 * @hw: pointer to the HW structure
2463 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2465 if (hw
->phy
.type
== e1000_phy_ife
)
2466 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2467 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2469 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2474 * e1000_led_off_ich8lan - Turn LEDs off
2475 * @hw: pointer to the HW structure
2477 * Turn off the LEDs.
2479 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2481 if (hw
->phy
.type
== e1000_phy_ife
)
2482 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2483 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2485 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2490 * e1000_get_cfg_done_ich8lan - Read config done bit
2491 * @hw: pointer to the HW structure
2493 * Read the management control register for the config done bit for
2494 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2495 * to read the config done bit, so an error is *ONLY* logged and returns
2496 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2497 * would not be able to be reset or change link.
2499 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
2503 e1000e_get_cfg_done(hw
);
2505 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2506 if (hw
->mac
.type
!= e1000_ich10lan
) {
2507 if (((er32(EECD
) & E1000_EECD_PRES
) == 0) &&
2508 (hw
->phy
.type
== e1000_phy_igp_3
)) {
2509 e1000e_phy_init_script_igp3(hw
);
2512 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
2513 /* Maybe we should do a basic PHY config */
2514 hw_dbg(hw
, "EEPROM not present\n");
2515 return -E1000_ERR_CONFIG
;
2523 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2524 * @hw: pointer to the HW structure
2526 * Clears hardware counters specific to the silicon family and calls
2527 * clear_hw_cntrs_generic to clear all general purpose counters.
2529 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
2533 e1000e_clear_hw_cntrs_base(hw
);
2535 temp
= er32(ALGNERRC
);
2536 temp
= er32(RXERRC
);
2538 temp
= er32(CEXTERR
);
2540 temp
= er32(TSCTFC
);
2542 temp
= er32(MGTPRC
);
2543 temp
= er32(MGTPDC
);
2544 temp
= er32(MGTPTC
);
2547 temp
= er32(ICRXOC
);
2551 static struct e1000_mac_operations ich8_mac_ops
= {
2552 .check_mng_mode
= e1000_check_mng_mode_ich8lan
,
2553 .check_for_link
= e1000e_check_for_copper_link
,
2554 .cleanup_led
= e1000_cleanup_led_ich8lan
,
2555 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
2556 .get_bus_info
= e1000_get_bus_info_ich8lan
,
2557 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
2558 .led_on
= e1000_led_on_ich8lan
,
2559 .led_off
= e1000_led_off_ich8lan
,
2560 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
2561 .reset_hw
= e1000_reset_hw_ich8lan
,
2562 .init_hw
= e1000_init_hw_ich8lan
,
2563 .setup_link
= e1000_setup_link_ich8lan
,
2564 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
2567 static struct e1000_phy_operations ich8_phy_ops
= {
2568 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
2569 .check_reset_block
= e1000_check_reset_block_ich8lan
,
2571 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
2572 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
2573 .get_cable_length
= e1000e_get_cable_length_igp_2
,
2574 .get_phy_info
= e1000_get_phy_info_ich8lan
,
2575 .read_phy_reg
= e1000e_read_phy_reg_igp
,
2576 .release_phy
= e1000_release_swflag_ich8lan
,
2577 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
2578 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
2579 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
2580 .write_phy_reg
= e1000e_write_phy_reg_igp
,
2583 static struct e1000_nvm_operations ich8_nvm_ops
= {
2584 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
2585 .read_nvm
= e1000_read_nvm_ich8lan
,
2586 .release_nvm
= e1000_release_swflag_ich8lan
,
2587 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
2588 .valid_led_default
= e1000_valid_led_default_ich8lan
,
2589 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
2590 .write_nvm
= e1000_write_nvm_ich8lan
,
2593 struct e1000_info e1000_ich8_info
= {
2594 .mac
= e1000_ich8lan
,
2595 .flags
= FLAG_HAS_WOL
2597 | FLAG_RX_CSUM_ENABLED
2598 | FLAG_HAS_CTRLEXT_ON_LOAD
2603 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
2604 .get_variants
= e1000_get_variants_ich8lan
,
2605 .mac_ops
= &ich8_mac_ops
,
2606 .phy_ops
= &ich8_phy_ops
,
2607 .nvm_ops
= &ich8_nvm_ops
,
2610 struct e1000_info e1000_ich9_info
= {
2611 .mac
= e1000_ich9lan
,
2612 .flags
= FLAG_HAS_JUMBO_FRAMES
2615 | FLAG_RX_CSUM_ENABLED
2616 | FLAG_HAS_CTRLEXT_ON_LOAD
2622 .max_hw_frame_size
= DEFAULT_JUMBO
,
2623 .get_variants
= e1000_get_variants_ich8lan
,
2624 .mac_ops
= &ich8_mac_ops
,
2625 .phy_ops
= &ich8_phy_ops
,
2626 .nvm_ops
= &ich8_nvm_ops
,
2629 struct e1000_info e1000_ich10_info
= {
2630 .mac
= e1000_ich10lan
,
2631 .flags
= FLAG_HAS_JUMBO_FRAMES
2634 | FLAG_RX_CSUM_ENABLED
2635 | FLAG_HAS_CTRLEXT_ON_LOAD
2641 .max_hw_frame_size
= DEFAULT_JUMBO
,
2642 .get_variants
= e1000_get_variants_ich8lan
,
2643 .mac_ops
= &ich8_mac_ops
,
2644 .phy_ops
= &ich8_phy_ops
,
2645 .nvm_ops
= &ich8_nvm_ops
,