2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <asm/processor.h>
38 #include <asm/hw_irq.h>
45 #include "mce-internal.h"
48 /* Handle unconfigured int18 (should never happen) */
49 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
51 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
55 /* Call the installed machine check handler for this CPU setup. */
56 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
57 unexpected_machine_check
;
61 #ifdef CONFIG_X86_NEW_MCE
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count
);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant
= 1;
81 static unsigned long notify_user
;
83 static int mce_bootlog
= -1;
84 static int monarch_timeout
= -1;
85 static int mce_panic_timeout
;
87 static char trigger
[128];
88 static char *trigger_argv
[2] = { trigger
, NULL
};
90 static unsigned long dont_init_banks
;
92 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
93 static DEFINE_PER_CPU(struct mce
, mces_seen
);
94 static int cpu_missing
;
97 /* MCA banks polled by the period polling timer for corrected events */
98 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
99 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
102 static inline int skip_bank_init(int i
)
104 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
107 /* Do initial initialization of a struct mce */
108 void mce_setup(struct mce
*m
)
110 memset(m
, 0, sizeof(struct mce
));
111 m
->cpu
= m
->extcpu
= smp_processor_id();
113 /* We hope get_seconds stays lockless */
114 m
->time
= get_seconds();
115 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
116 m
->cpuid
= cpuid_eax(1);
118 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
120 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
121 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
124 DEFINE_PER_CPU(struct mce
, injectm
);
125 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
128 * Lockless MCE logging infrastructure.
129 * This avoids deadlocks on printk locks without having to break locks. Also
130 * separate MCEs from kernel messages to avoid bogus bug reports.
133 static struct mce_log mcelog
= {
134 .signature
= MCE_LOG_SIGNATURE
,
136 .recordlen
= sizeof(struct mce
),
139 void mce_log(struct mce
*mce
)
141 unsigned next
, entry
;
146 entry
= rcu_dereference(mcelog
.next
);
149 * When the buffer fills up discard new entries.
150 * Assume that the earlier errors are the more
153 if (entry
>= MCE_LOG_LEN
) {
154 set_bit(MCE_OVERFLOW
,
155 (unsigned long *)&mcelog
.flags
);
158 /* Old left over entry. Skip: */
159 if (mcelog
.entry
[entry
].finished
) {
167 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
170 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
172 mcelog
.entry
[entry
].finished
= 1;
176 set_bit(0, ¬ify_user
);
179 static void print_mce(struct mce
*m
)
181 printk(KERN_EMERG
"\n"
182 KERN_EMERG
"HARDWARE ERROR\n"
184 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
185 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
187 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
188 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
190 if (m
->cs
== __KERNEL_CS
)
191 print_symbol("{%s}", m
->ip
);
194 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
196 printk("ADDR %llx ", m
->addr
);
198 printk("MISC %llx ", m
->misc
);
200 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
201 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
203 printk(KERN_EMERG
"This is not a software problem!\n");
204 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
205 "and contact your hardware vendor\n");
208 #define PANIC_TIMEOUT 5 /* 5 seconds */
210 static atomic_t mce_paniced
;
212 /* Panic in progress. Enable interrupts and wait for final IPI */
213 static void wait_for_panic(void)
215 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
218 while (timeout
-- > 0)
220 if (panic_timeout
== 0)
221 panic_timeout
= mce_panic_timeout
;
222 panic("Panicing machine check CPU died");
225 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
230 * Make sure only one CPU runs in machine check panic
232 if (atomic_add_return(1, &mce_paniced
) > 1)
238 /* First print corrected ones that are still unlogged */
239 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
240 struct mce
*m
= &mcelog
.entry
[i
];
241 if ((m
->status
& MCI_STATUS_VAL
) &&
242 !(m
->status
& MCI_STATUS_UC
))
245 /* Now print uncorrected but with the final one last */
246 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
247 struct mce
*m
= &mcelog
.entry
[i
];
248 if (!(m
->status
& MCI_STATUS_VAL
))
250 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
256 printk(KERN_EMERG
"Some CPUs didn't answer in synchronization\n");
258 printk(KERN_EMERG
"Machine check: %s\n", exp
);
259 if (panic_timeout
== 0)
260 panic_timeout
= mce_panic_timeout
;
264 /* Support code for software error injection */
266 static int msr_to_offset(u32 msr
)
268 unsigned bank
= __get_cpu_var(injectm
.bank
);
270 return offsetof(struct mce
, ip
);
271 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
272 return offsetof(struct mce
, status
);
273 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
274 return offsetof(struct mce
, addr
);
275 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
276 return offsetof(struct mce
, misc
);
277 if (msr
== MSR_IA32_MCG_STATUS
)
278 return offsetof(struct mce
, mcgstatus
);
282 /* MSR access wrappers used for error injection */
283 static u64
mce_rdmsrl(u32 msr
)
286 if (__get_cpu_var(injectm
).finished
) {
287 int offset
= msr_to_offset(msr
);
290 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
296 static void mce_wrmsrl(u32 msr
, u64 v
)
298 if (__get_cpu_var(injectm
).finished
) {
299 int offset
= msr_to_offset(msr
);
301 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
307 int mce_available(struct cpuinfo_x86
*c
)
311 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
315 * Get the address of the instruction at the time of the machine check
318 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
321 if (regs
&& (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
))) {
329 m
->ip
= mce_rdmsrl(rip_msr
);
332 #ifdef CONFIG_X86_LOCAL_APIC
334 * Called after interrupts have been reenabled again
335 * when a MCE happened during an interrupts off region
338 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
348 static void mce_report_event(struct pt_regs
*regs
)
350 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
355 #ifdef CONFIG_X86_LOCAL_APIC
357 * Without APIC do not notify. The event will be picked
364 * When interrupts are disabled we cannot use
365 * kernel services safely. Trigger an self interrupt
366 * through the APIC to instead do the notification
367 * after interrupts are reenabled again.
369 apic
->send_IPI_self(MCE_SELF_VECTOR
);
372 * Wait for idle afterwards again so that we don't leave the
373 * APIC in a non idle state because the normal APIC writes
376 apic_wait_icr_idle();
380 DEFINE_PER_CPU(unsigned, mce_poll_count
);
383 * Poll for corrected events or events that happened before reset.
384 * Those are just logged through /dev/mcelog.
386 * This is executed in standard interrupt context.
388 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
393 __get_cpu_var(mce_poll_count
)++;
397 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
398 for (i
= 0; i
< banks
; i
++) {
399 if (!bank
[i
] || !test_bit(i
, *b
))
408 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
409 if (!(m
.status
& MCI_STATUS_VAL
))
413 * Uncorrected events are handled by the exception handler
414 * when it is enabled. But when the exception is disabled log
417 * TBD do the same check for MCI_STATUS_EN here?
419 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
422 if (m
.status
& MCI_STATUS_MISCV
)
423 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
424 if (m
.status
& MCI_STATUS_ADDRV
)
425 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
427 if (!(flags
& MCP_TIMESTAMP
))
430 * Don't get the IP here because it's unlikely to
431 * have anything to do with the actual error location.
433 if (!(flags
& MCP_DONTLOG
)) {
435 add_taint(TAINT_MACHINE_CHECK
);
439 * Clear state for this bank.
441 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
445 * Don't clear MCG_STATUS here because it's only defined for
451 EXPORT_SYMBOL_GPL(machine_check_poll
);
454 * Do a quick check if any of the events requires a panic.
455 * This decides if we keep the events around or clear them.
457 static int mce_no_way_out(struct mce
*m
, char **msg
)
461 for (i
= 0; i
< banks
; i
++) {
462 m
->status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
463 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
470 * Variable to establish order between CPUs while scanning.
471 * Each CPU spins initially until executing is equal its number.
473 static atomic_t mce_executing
;
476 * Defines order of CPUs on entry. First CPU becomes Monarch.
478 static atomic_t mce_callin
;
481 * Check if a timeout waiting for other CPUs happened.
483 static int mce_timed_out(u64
*t
)
486 * The others already did panic for some reason.
487 * Bail out like in a timeout.
488 * rmb() to tell the compiler that system_state
489 * might have been modified by someone else.
492 if (atomic_read(&mce_paniced
))
494 if (!monarch_timeout
)
496 if ((s64
)*t
< SPINUNIT
) {
497 /* CHECKME: Make panic default for 1 too? */
499 mce_panic("Timeout synchronizing machine check over CPUs",
506 touch_nmi_watchdog();
511 * The Monarch's reign. The Monarch is the CPU who entered
512 * the machine check handler first. It waits for the others to
513 * raise the exception too and then grades them. When any
514 * error is fatal panic. Only then let the others continue.
516 * The other CPUs entering the MCE handler will be controlled by the
517 * Monarch. They are called Subjects.
519 * This way we prevent any potential data corruption in a unrecoverable case
520 * and also makes sure always all CPU's errors are examined.
522 * Also this detects the case of an machine check event coming from outer
523 * space (not detected by any CPUs) In this case some external agent wants
524 * us to shut down, so panic too.
526 * The other CPUs might still decide to panic if the handler happens
527 * in a unrecoverable place, but in this case the system is in a semi-stable
528 * state and won't corrupt anything by itself. It's ok to let the others
529 * continue for a bit first.
531 * All the spin loops have timeouts; when a timeout happens a CPU
532 * typically elects itself to be Monarch.
534 static void mce_reign(void)
537 struct mce
*m
= NULL
;
538 int global_worst
= 0;
543 * This CPU is the Monarch and the other CPUs have run
544 * through their handlers.
545 * Grade the severity of the errors of all the CPUs.
547 for_each_possible_cpu(cpu
) {
548 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
550 if (severity
> global_worst
) {
552 global_worst
= severity
;
553 m
= &per_cpu(mces_seen
, cpu
);
558 * Cannot recover? Panic here then.
559 * This dumps all the mces in the log buffer and stops the
562 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
563 mce_panic("Fatal Machine check", m
, msg
);
566 * For UC somewhere we let the CPU who detects it handle it.
567 * Also must let continue the others, otherwise the handling
568 * CPU could deadlock on a lock.
572 * No machine check event found. Must be some external
573 * source or one CPU is hung. Panic.
575 if (!m
&& tolerant
< 3)
576 mce_panic("Machine check from unknown source", NULL
, NULL
);
579 * Now clear all the mces_seen so that they don't reappear on
582 for_each_possible_cpu(cpu
)
583 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
586 static atomic_t global_nwo
;
589 * Start of Monarch synchronization. This waits until all CPUs have
590 * entered the exception handler and then determines if any of them
591 * saw a fatal event that requires panic. Then it executes them
592 * in the entry order.
593 * TBD double check parallel CPU hotunplug
595 static int mce_start(int no_way_out
, int *order
)
598 int cpus
= num_online_cpus();
599 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
606 atomic_add(no_way_out
, &global_nwo
);
611 while (atomic_read(&mce_callin
) != cpus
) {
612 if (mce_timed_out(&timeout
)) {
613 atomic_set(&global_nwo
, 0);
621 * Cache the global no_way_out state.
623 nwo
= atomic_read(&global_nwo
);
626 * Monarch starts executing now, the others wait.
629 atomic_set(&mce_executing
, 1);
634 * Now start the scanning loop one by one
635 * in the original callin order.
636 * This way when there are any shared banks it will
637 * be only seen by one CPU before cleared, avoiding duplicates.
639 while (atomic_read(&mce_executing
) < *order
) {
640 if (mce_timed_out(&timeout
)) {
641 atomic_set(&global_nwo
, 0);
651 * Synchronize between CPUs after main scanning loop.
652 * This invokes the bulk of the Monarch processing.
654 static int mce_end(int order
)
657 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
665 * Allow others to run.
667 atomic_inc(&mce_executing
);
670 /* CHECKME: Can this race with a parallel hotplug? */
671 int cpus
= num_online_cpus();
674 * Monarch: Wait for everyone to go through their scanning
677 while (atomic_read(&mce_executing
) <= cpus
) {
678 if (mce_timed_out(&timeout
))
688 * Subject: Wait for Monarch to finish.
690 while (atomic_read(&mce_executing
) != 0) {
691 if (mce_timed_out(&timeout
))
697 * Don't reset anything. That's done by the Monarch.
703 * Reset all global state.
706 atomic_set(&global_nwo
, 0);
707 atomic_set(&mce_callin
, 0);
711 * Let others run again.
713 atomic_set(&mce_executing
, 0);
717 static void mce_clear_state(unsigned long *toclear
)
721 for (i
= 0; i
< banks
; i
++) {
722 if (test_bit(i
, toclear
))
723 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
728 * The actual machine check handler. This only handles real
729 * exceptions when something got corrupted coming in through int 18.
731 * This is executed in NMI context not subject to normal locking rules. This
732 * implies that most kernel services cannot be safely used. Don't even
733 * think about putting a printk in there!
735 * On Intel systems this is entered on all CPUs in parallel through
736 * MCE broadcast. However some CPUs might be broken beyond repair,
737 * so be always careful when synchronizing with others.
739 void do_machine_check(struct pt_regs
*regs
, long error_code
)
741 struct mce m
, *final
;
746 * Establish sequential order between the CPUs entering the machine
752 * If no_way_out gets set, there is no safe way to recover from this
753 * MCE. If tolerant is cranked up, we'll try anyway.
757 * If kill_it gets set, there might be a way to recover from this
761 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
762 char *msg
= "Unknown";
764 atomic_inc(&mce_entry
);
766 __get_cpu_var(mce_exception_count
)++;
768 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
769 18, SIGKILL
) == NOTIFY_STOP
)
774 order
= atomic_add_return(1, &mce_callin
);
777 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
778 no_way_out
= mce_no_way_out(&m
, &msg
);
780 final
= &__get_cpu_var(mces_seen
);
786 * Go through all the banks in exclusion of the other CPUs.
787 * This way we don't report duplicated events on shared banks
788 * because the first one to see it will clear it.
790 no_way_out
= mce_start(no_way_out
, &order
);
791 for (i
= 0; i
< banks
; i
++) {
792 __clear_bit(i
, toclear
);
800 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
801 if ((m
.status
& MCI_STATUS_VAL
) == 0)
805 * Non uncorrected errors are handled by machine_check_poll
806 * Leave them alone, unless this panics.
808 if ((m
.status
& MCI_STATUS_UC
) == 0 && !no_way_out
)
812 * Set taint even when machine check was not enabled.
814 add_taint(TAINT_MACHINE_CHECK
);
816 __set_bit(i
, toclear
);
818 if (m
.status
& MCI_STATUS_EN
) {
820 * If this error was uncorrectable and there was
821 * an overflow, we're in trouble. If no overflow,
822 * we might get away with just killing a task.
824 if (m
.status
& MCI_STATUS_UC
)
828 * Machine check event was not enabled. Clear, but
834 if (m
.status
& MCI_STATUS_MISCV
)
835 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
836 if (m
.status
& MCI_STATUS_ADDRV
)
837 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
839 mce_get_rip(&m
, regs
);
842 severity
= mce_severity(&m
, tolerant
, NULL
);
843 if (severity
> worst
) {
850 mce_clear_state(toclear
);
853 * Do most of the synchronization with other CPUs.
854 * When there's any problem use only local no_way_out state.
856 if (mce_end(order
) < 0)
857 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
860 * If we have decided that we just CAN'T continue, and the user
861 * has not set tolerant to an insane level, give up and die.
863 * This is mainly used in the case when the system doesn't
864 * support MCE broadcasting or it has been disabled.
866 if (no_way_out
&& tolerant
< 3)
867 mce_panic("Fatal machine check on current CPU", final
, msg
);
870 * If the error seems to be unrecoverable, something should be
871 * done. Try to kill as little as possible. If we can kill just
872 * one task, do that. If the user has set the tolerance very
873 * high, don't try to do anything at all.
875 if (kill_it
&& tolerant
< 3) {
879 * If the EIPV bit is set, it means the saved IP is the
880 * instruction which caused the MCE.
882 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
883 user_space
= final
->ip
&& (final
->cs
& 3);
886 * If we know that the error was in user space, send a
887 * SIGBUS. Otherwise, panic if tolerance is low.
889 * force_sig() takes an awful lot of locks and has a slight
890 * risk of deadlocking.
893 force_sig(SIGBUS
, current
);
894 } else if (panic_on_oops
|| tolerant
< 2) {
895 mce_panic("Uncorrected machine check", final
, msg
);
899 /* notify userspace ASAP */
900 set_thread_flag(TIF_MCE_NOTIFY
);
903 mce_report_event(regs
);
904 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
906 atomic_dec(&mce_entry
);
909 EXPORT_SYMBOL_GPL(do_machine_check
);
911 #ifdef CONFIG_X86_MCE_INTEL
913 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
914 * @cpu: The CPU on which the event occurred.
915 * @status: Event status information
917 * This function should be called by the thermal interrupt after the
918 * event has been processed and the decision was made to log the event
921 * The status parameter will be saved to the 'status' field of 'struct mce'
922 * and historically has been the register value of the
923 * MSR_IA32_THERMAL_STATUS (Intel) msr.
925 void mce_log_therm_throt_event(__u64 status
)
930 m
.bank
= MCE_THERMAL_BANK
;
934 #endif /* CONFIG_X86_MCE_INTEL */
937 * Periodic polling timer for "silent" machine check errors. If the
938 * poller finds an MCE, poll 2x faster. When the poller finds no more
939 * errors, poll 2x slower (up to check_interval seconds).
941 static int check_interval
= 5 * 60; /* 5 minutes */
943 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
944 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
946 static void mcheck_timer(unsigned long data
)
948 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
951 WARN_ON(smp_processor_id() != data
);
953 if (mce_available(¤t_cpu_data
)) {
954 machine_check_poll(MCP_TIMESTAMP
,
955 &__get_cpu_var(mce_poll_banks
));
959 * Alert userspace if needed. If we logged an MCE, reduce the
960 * polling interval, otherwise increase the polling interval.
962 n
= &__get_cpu_var(next_interval
);
963 if (mce_notify_user())
964 *n
= max(*n
/2, HZ
/100);
966 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
968 t
->expires
= jiffies
+ *n
;
972 static void mce_do_trigger(struct work_struct
*work
)
974 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
977 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
980 * Notify the user(s) about new machine check events.
981 * Can be called from interrupt context, but not from machine check/NMI
984 int mce_notify_user(void)
986 /* Not more than two messages every minute */
987 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
989 clear_thread_flag(TIF_MCE_NOTIFY
);
991 if (test_and_clear_bit(0, ¬ify_user
)) {
992 wake_up_interruptible(&mce_wait
);
995 * There is no risk of missing notifications because
996 * work_pending is always cleared before the function is
999 if (trigger
[0] && !work_pending(&mce_trigger_work
))
1000 schedule_work(&mce_trigger_work
);
1002 if (__ratelimit(&ratelimit
))
1003 printk(KERN_INFO
"Machine check events logged\n");
1009 EXPORT_SYMBOL_GPL(mce_notify_user
);
1012 * Initialize Machine Checks for a CPU.
1014 static int mce_cap_init(void)
1019 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1021 b
= cap
& MCG_BANKCNT_MASK
;
1022 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1024 if (b
> MAX_NR_BANKS
) {
1026 "MCE: Using only %u machine check banks out of %u\n",
1031 /* Don't support asymmetric configurations today */
1032 WARN_ON(banks
!= 0 && b
!= banks
);
1035 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
1038 memset(bank
, 0xff, banks
* sizeof(u64
));
1041 /* Use accurate RIP reporting if available. */
1042 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1043 rip_msr
= MSR_IA32_MCG_EIP
;
1048 static void mce_init(void)
1050 mce_banks_t all_banks
;
1055 * Log the machine checks left over from the previous reset.
1057 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1058 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1060 set_in_cr4(X86_CR4_MCE
);
1062 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1063 if (cap
& MCG_CTL_P
)
1064 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1066 for (i
= 0; i
< banks
; i
++) {
1067 if (skip_bank_init(i
))
1069 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
1070 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
1074 /* Add per CPU specific workarounds here */
1075 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
1077 /* This should be disabled by the BIOS, but isn't always */
1078 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1079 if (c
->x86
== 15 && banks
> 4) {
1081 * disable GART TBL walk error reporting, which
1082 * trips off incorrectly with the IOMMU & 3ware
1085 clear_bit(10, (unsigned long *)&bank
[4]);
1087 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1089 * Lots of broken BIOS around that don't clear them
1090 * by default and leave crap in there. Don't log:
1095 * Various K7s with broken bank 0 around. Always disable
1102 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1104 * SDM documents that on family 6 bank 0 should not be written
1105 * because it aliases to another special BIOS controlled
1107 * But it's not aliased anymore on model 0x1a+
1108 * Don't ignore bank 0 completely because there could be a
1109 * valid event later, merely don't write CTL0.
1112 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
1113 __set_bit(0, &dont_init_banks
);
1116 * All newer Intel systems support MCE broadcasting. Enable
1117 * synchronization with a one second timeout.
1119 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1120 monarch_timeout
< 0)
1121 monarch_timeout
= USEC_PER_SEC
;
1123 if (monarch_timeout
< 0)
1124 monarch_timeout
= 0;
1125 if (mce_bootlog
!= 0)
1126 mce_panic_timeout
= 30;
1129 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
1133 switch (c
->x86_vendor
) {
1134 case X86_VENDOR_INTEL
:
1135 if (mce_p5_enabled())
1136 intel_p5_mcheck_init(c
);
1138 case X86_VENDOR_CENTAUR
:
1139 winchip_mcheck_init(c
);
1144 static void mce_cpu_features(struct cpuinfo_x86
*c
)
1146 switch (c
->x86_vendor
) {
1147 case X86_VENDOR_INTEL
:
1148 mce_intel_feature_init(c
);
1150 case X86_VENDOR_AMD
:
1151 mce_amd_feature_init(c
);
1158 static void mce_init_timer(void)
1160 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1161 int *n
= &__get_cpu_var(next_interval
);
1163 *n
= check_interval
* HZ
;
1166 setup_timer(t
, mcheck_timer
, smp_processor_id());
1167 t
->expires
= round_jiffies(jiffies
+ *n
);
1172 * Called for each booted CPU to set up machine checks.
1173 * Must be called with preempt off:
1175 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
1180 mce_ancient_init(c
);
1182 if (!mce_available(c
))
1185 if (mce_cap_init() < 0) {
1191 machine_check_vector
= do_machine_check
;
1194 mce_cpu_features(c
);
1199 * Character device to read and clear the MCE log.
1202 static DEFINE_SPINLOCK(mce_state_lock
);
1203 static int open_count
; /* #times opened */
1204 static int open_exclu
; /* already open exclusive? */
1206 static int mce_open(struct inode
*inode
, struct file
*file
)
1208 spin_lock(&mce_state_lock
);
1210 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
1211 spin_unlock(&mce_state_lock
);
1216 if (file
->f_flags
& O_EXCL
)
1220 spin_unlock(&mce_state_lock
);
1222 return nonseekable_open(inode
, file
);
1225 static int mce_release(struct inode
*inode
, struct file
*file
)
1227 spin_lock(&mce_state_lock
);
1232 spin_unlock(&mce_state_lock
);
1237 static void collect_tscs(void *data
)
1239 unsigned long *cpu_tsc
= (unsigned long *)data
;
1241 rdtscll(cpu_tsc
[smp_processor_id()]);
1244 static DEFINE_MUTEX(mce_read_mutex
);
1246 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
1249 char __user
*buf
= ubuf
;
1250 unsigned long *cpu_tsc
;
1251 unsigned prev
, next
;
1254 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1258 mutex_lock(&mce_read_mutex
);
1259 next
= rcu_dereference(mcelog
.next
);
1261 /* Only supports full reads right now */
1262 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
1263 mutex_unlock(&mce_read_mutex
);
1272 for (i
= prev
; i
< next
; i
++) {
1273 unsigned long start
= jiffies
;
1275 while (!mcelog
.entry
[i
].finished
) {
1276 if (time_after_eq(jiffies
, start
+ 2)) {
1277 memset(mcelog
.entry
+ i
, 0,
1278 sizeof(struct mce
));
1284 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
1285 sizeof(struct mce
));
1286 buf
+= sizeof(struct mce
);
1291 memset(mcelog
.entry
+ prev
, 0,
1292 (next
- prev
) * sizeof(struct mce
));
1294 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1295 } while (next
!= prev
);
1297 synchronize_sched();
1300 * Collect entries that were still getting written before the
1303 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1305 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1306 if (mcelog
.entry
[i
].finished
&&
1307 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1308 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1309 sizeof(struct mce
));
1311 buf
+= sizeof(struct mce
);
1312 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1315 mutex_unlock(&mce_read_mutex
);
1318 return err
? -EFAULT
: buf
- ubuf
;
1321 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1323 poll_wait(file
, &mce_wait
, wait
);
1324 if (rcu_dereference(mcelog
.next
))
1325 return POLLIN
| POLLRDNORM
;
1329 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1331 int __user
*p
= (int __user
*)arg
;
1333 if (!capable(CAP_SYS_ADMIN
))
1337 case MCE_GET_RECORD_LEN
:
1338 return put_user(sizeof(struct mce
), p
);
1339 case MCE_GET_LOG_LEN
:
1340 return put_user(MCE_LOG_LEN
, p
);
1341 case MCE_GETCLEAR_FLAGS
: {
1345 flags
= mcelog
.flags
;
1346 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1348 return put_user(flags
, p
);
1355 /* Modified in mce-inject.c, so not static or const */
1356 struct file_operations mce_chrdev_ops
= {
1358 .release
= mce_release
,
1361 .unlocked_ioctl
= mce_ioctl
,
1363 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1365 static struct miscdevice mce_log_device
= {
1372 * mce=off disables machine check
1373 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1374 * monarchtimeout is how long to wait for other CPUs on machine
1375 * check, or 0 to not wait
1376 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1377 * mce=nobootlog Don't log MCEs from before booting.
1379 static int __init
mcheck_enable(char *str
)
1385 if (!strcmp(str
, "off"))
1387 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1388 mce_bootlog
= (str
[0] == 'b');
1389 else if (isdigit(str
[0])) {
1390 get_option(&str
, &tolerant
);
1393 get_option(&str
, &monarch_timeout
);
1396 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1402 __setup("mce", mcheck_enable
);
1409 * Disable machine checks on suspend and shutdown. We can't really handle
1412 static int mce_disable(void)
1416 for (i
= 0; i
< banks
; i
++) {
1417 if (!skip_bank_init(i
))
1418 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1423 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1425 return mce_disable();
1428 static int mce_shutdown(struct sys_device
*dev
)
1430 return mce_disable();
1434 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1435 * Only one CPU is active at this time, the others get re-added later using
1438 static int mce_resume(struct sys_device
*dev
)
1441 mce_cpu_features(¤t_cpu_data
);
1446 static void mce_cpu_restart(void *data
)
1448 del_timer_sync(&__get_cpu_var(mce_timer
));
1449 if (mce_available(¤t_cpu_data
))
1454 /* Reinit MCEs after user configuration changes */
1455 static void mce_restart(void)
1457 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1460 static struct sysdev_class mce_sysclass
= {
1461 .suspend
= mce_suspend
,
1462 .shutdown
= mce_shutdown
,
1463 .resume
= mce_resume
,
1464 .name
= "machinecheck",
1467 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1470 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1472 static struct sysdev_attribute
*bank_attrs
;
1474 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1477 u64 b
= bank
[attr
- bank_attrs
];
1479 return sprintf(buf
, "%llx\n", b
);
1482 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1483 const char *buf
, size_t size
)
1487 if (strict_strtoull(buf
, 0, &new) < 0)
1490 bank
[attr
- bank_attrs
] = new;
1497 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1499 strcpy(buf
, trigger
);
1501 return strlen(trigger
) + 1;
1504 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1505 const char *buf
, size_t siz
)
1510 strncpy(trigger
, buf
, sizeof(trigger
));
1511 trigger
[sizeof(trigger
)-1] = 0;
1512 len
= strlen(trigger
);
1513 p
= strchr(trigger
, '\n');
1521 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1522 struct sysdev_attribute
*attr
,
1523 const char *buf
, size_t size
)
1525 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1530 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1531 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1532 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1534 static struct sysdev_ext_attribute attr_check_interval
= {
1535 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1536 store_int_with_restart
),
1540 static struct sysdev_attribute
*mce_attrs
[] = {
1541 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1542 &attr_monarch_timeout
.attr
,
1546 static cpumask_var_t mce_dev_initialized
;
1548 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1549 static __cpuinit
int mce_create_device(unsigned int cpu
)
1554 if (!mce_available(&boot_cpu_data
))
1557 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1558 per_cpu(mce_dev
, cpu
).id
= cpu
;
1559 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1561 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1565 for (i
= 0; mce_attrs
[i
]; i
++) {
1566 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1570 for (i
= 0; i
< banks
; i
++) {
1571 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1576 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1581 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1584 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1586 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1591 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1595 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1598 for (i
= 0; mce_attrs
[i
]; i
++)
1599 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1601 for (i
= 0; i
< banks
; i
++)
1602 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1604 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1605 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1608 /* Make sure there are no machine checks on offlined CPUs. */
1609 static void mce_disable_cpu(void *h
)
1611 unsigned long action
= *(unsigned long *)h
;
1614 if (!mce_available(¤t_cpu_data
))
1616 if (!(action
& CPU_TASKS_FROZEN
))
1618 for (i
= 0; i
< banks
; i
++) {
1619 if (!skip_bank_init(i
))
1620 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1624 static void mce_reenable_cpu(void *h
)
1626 unsigned long action
= *(unsigned long *)h
;
1629 if (!mce_available(¤t_cpu_data
))
1632 if (!(action
& CPU_TASKS_FROZEN
))
1634 for (i
= 0; i
< banks
; i
++) {
1635 if (!skip_bank_init(i
))
1636 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1640 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1641 static int __cpuinit
1642 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1644 unsigned int cpu
= (unsigned long)hcpu
;
1645 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1649 case CPU_ONLINE_FROZEN
:
1650 mce_create_device(cpu
);
1651 if (threshold_cpu_callback
)
1652 threshold_cpu_callback(action
, cpu
);
1655 case CPU_DEAD_FROZEN
:
1656 if (threshold_cpu_callback
)
1657 threshold_cpu_callback(action
, cpu
);
1658 mce_remove_device(cpu
);
1660 case CPU_DOWN_PREPARE
:
1661 case CPU_DOWN_PREPARE_FROZEN
:
1663 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1665 case CPU_DOWN_FAILED
:
1666 case CPU_DOWN_FAILED_FROZEN
:
1667 t
->expires
= round_jiffies(jiffies
+
1668 __get_cpu_var(next_interval
));
1669 add_timer_on(t
, cpu
);
1670 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1673 /* intentionally ignoring frozen here */
1674 cmci_rediscover(cpu
);
1680 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1681 .notifier_call
= mce_cpu_callback
,
1684 static __init
int mce_init_banks(void)
1688 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1693 for (i
= 0; i
< banks
; i
++) {
1694 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1696 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1700 a
->attr
.mode
= 0644;
1701 a
->show
= show_bank
;
1702 a
->store
= set_bank
;
1708 kfree(bank_attrs
[i
].attr
.name
);
1715 static __init
int mce_init_device(void)
1720 if (!mce_available(&boot_cpu_data
))
1723 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1725 err
= mce_init_banks();
1729 err
= sysdev_class_register(&mce_sysclass
);
1733 for_each_online_cpu(i
) {
1734 err
= mce_create_device(i
);
1739 register_hotcpu_notifier(&mce_cpu_notifier
);
1740 misc_register(&mce_log_device
);
1745 device_initcall(mce_init_device
);
1747 #else /* CONFIG_X86_OLD_MCE: */
1750 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1752 /* This has to be run for each processor */
1753 void mcheck_init(struct cpuinfo_x86
*c
)
1755 if (mce_disabled
== 1)
1758 switch (c
->x86_vendor
) {
1759 case X86_VENDOR_AMD
:
1763 case X86_VENDOR_INTEL
:
1765 intel_p5_mcheck_init(c
);
1767 intel_p6_mcheck_init(c
);
1769 intel_p4_mcheck_init(c
);
1772 case X86_VENDOR_CENTAUR
:
1774 winchip_mcheck_init(c
);
1780 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1783 static int __init
mcheck_enable(char *str
)
1789 __setup("mce", mcheck_enable
);
1791 #endif /* CONFIG_X86_OLD_MCE */
1794 * Old style boot options parsing. Only for compatibility.
1796 static int __init
mcheck_disable(char *str
)
1801 __setup("nomce", mcheck_disable
);