2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/kernel.h>
13 #include <linux/vmalloc.h>
14 #include <linux/pagemap.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/kdebug.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
24 #include <asm/bitext.h>
26 #include <asm/pgalloc.h>
27 #include <asm/pgtable.h>
29 #include <asm/vaddrs.h>
30 #include <asm/traps.h>
33 #include <asm/cache.h>
34 #include <asm/oplib.h>
37 #include <asm/mmu_context.h>
38 #include <asm/io-unit.h>
39 #include <asm/cacheflush.h>
40 #include <asm/tlbflush.h>
42 /* Now the cpu specific definitions. */
43 #include <asm/viking.h>
46 #include <asm/tsunami.h>
47 #include <asm/swift.h>
48 #include <asm/turbosparc.h>
53 enum mbus_module srmmu_modtype
;
54 static unsigned int hwbug_bitmask
;
58 struct ctx_list
*ctx_list_pool
;
59 struct ctx_list ctx_free
;
60 struct ctx_list ctx_used
;
62 extern struct resource sparc_iomap
;
64 extern unsigned long last_valid_pfn
;
66 static pgd_t
*srmmu_swapper_pg_dir
;
68 const struct sparc32_cachetlb_ops
*sparc32_cachetlb_ops
;
71 const struct sparc32_cachetlb_ops
*local_ops
;
73 #define FLUSH_BEGIN(mm)
76 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
80 int flush_page_for_dma_global
= 1;
84 ctxd_t
*srmmu_ctx_table_phys
;
85 static ctxd_t
*srmmu_context_table
;
87 int viking_mxcc_present
;
88 static DEFINE_SPINLOCK(srmmu_context_spinlock
);
90 static int is_hypersparc
;
92 static int srmmu_cache_pagetables
;
94 /* these will be initialized in srmmu_nocache_calcsize() */
95 static unsigned long srmmu_nocache_size
;
96 static unsigned long srmmu_nocache_end
;
98 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
99 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
101 /* The context table is a nocache user with the biggest alignment needs. */
102 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
104 void *srmmu_nocache_pool
;
105 void *srmmu_nocache_bitmap
;
106 static struct bit_map srmmu_nocache_map
;
108 static inline int srmmu_pmd_none(pmd_t pmd
)
109 { return !(pmd_val(pmd
) & 0xFFFFFFF); }
111 /* XXX should we hyper_flush_whole_icache here - Anton */
112 static inline void srmmu_ctxd_set(ctxd_t
*ctxp
, pgd_t
*pgdp
)
113 { set_pte((pte_t
*)ctxp
, (SRMMU_ET_PTD
| (__nocache_pa((unsigned long) pgdp
) >> 4))); }
115 void pmd_set(pmd_t
*pmdp
, pte_t
*ptep
)
117 unsigned long ptp
; /* Physical address, shifted right by 4 */
120 ptp
= __nocache_pa((unsigned long) ptep
) >> 4;
121 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
122 set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
123 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
127 void pmd_populate(struct mm_struct
*mm
, pmd_t
*pmdp
, struct page
*ptep
)
129 unsigned long ptp
; /* Physical address, shifted right by 4 */
132 ptp
= page_to_pfn(ptep
) << (PAGE_SHIFT
-4); /* watch for overflow */
133 for (i
= 0; i
< PTRS_PER_PTE
/SRMMU_REAL_PTRS_PER_PTE
; i
++) {
134 set_pte((pte_t
*)&pmdp
->pmdv
[i
], SRMMU_ET_PTD
| ptp
);
135 ptp
+= (SRMMU_REAL_PTRS_PER_PTE
*sizeof(pte_t
) >> 4);
139 /* Find an entry in the third-level page table.. */
140 pte_t
*pte_offset_kernel(pmd_t
* dir
, unsigned long address
)
144 pte
= __nocache_va((dir
->pmdv
[0] & SRMMU_PTD_PMASK
) << 4);
145 return (pte_t
*) pte
+
146 ((address
>> PAGE_SHIFT
) & (PTRS_PER_PTE
- 1));
150 * size: bytes to allocate in the nocache area.
151 * align: bytes, number to align at.
152 * Returns the virtual address of the allocated area.
154 static unsigned long __srmmu_get_nocache(int size
, int align
)
158 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
159 printk("Size 0x%x too small for nocache request\n", size
);
160 size
= SRMMU_NOCACHE_BITMAP_SHIFT
;
162 if (size
& (SRMMU_NOCACHE_BITMAP_SHIFT
-1)) {
163 printk("Size 0x%x unaligned int nocache request\n", size
);
164 size
+= SRMMU_NOCACHE_BITMAP_SHIFT
-1;
166 BUG_ON(align
> SRMMU_NOCACHE_ALIGN_MAX
);
168 offset
= bit_map_string_get(&srmmu_nocache_map
,
169 size
>> SRMMU_NOCACHE_BITMAP_SHIFT
,
170 align
>> SRMMU_NOCACHE_BITMAP_SHIFT
);
172 printk("srmmu: out of nocache %d: %d/%d\n",
173 size
, (int) srmmu_nocache_size
,
174 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
178 return (SRMMU_NOCACHE_VADDR
+ (offset
<< SRMMU_NOCACHE_BITMAP_SHIFT
));
181 unsigned long srmmu_get_nocache(int size
, int align
)
185 tmp
= __srmmu_get_nocache(size
, align
);
188 memset((void *)tmp
, 0, size
);
193 void srmmu_free_nocache(unsigned long vaddr
, int size
)
197 if (vaddr
< SRMMU_NOCACHE_VADDR
) {
198 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
199 vaddr
, (unsigned long)SRMMU_NOCACHE_VADDR
);
202 if (vaddr
+size
> srmmu_nocache_end
) {
203 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
204 vaddr
, srmmu_nocache_end
);
207 if (!is_power_of_2(size
)) {
208 printk("Size 0x%x is not a power of 2\n", size
);
211 if (size
< SRMMU_NOCACHE_BITMAP_SHIFT
) {
212 printk("Size 0x%x is too small\n", size
);
215 if (vaddr
& (size
-1)) {
216 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr
, size
);
220 offset
= (vaddr
- SRMMU_NOCACHE_VADDR
) >> SRMMU_NOCACHE_BITMAP_SHIFT
;
221 size
= size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
223 bit_map_clear(&srmmu_nocache_map
, offset
, size
);
226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start
,
229 extern unsigned long probe_memory(void); /* in fault.c */
232 * Reserve nocache dynamically proportionally to the amount of
233 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
235 static void srmmu_nocache_calcsize(void)
237 unsigned long sysmemavail
= probe_memory() / 1024;
238 int srmmu_nocache_npages
;
240 srmmu_nocache_npages
=
241 sysmemavail
/ SRMMU_NOCACHE_ALCRATIO
/ 1024 * 256;
243 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
244 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
245 if (srmmu_nocache_npages
< SRMMU_MIN_NOCACHE_PAGES
)
246 srmmu_nocache_npages
= SRMMU_MIN_NOCACHE_PAGES
;
248 /* anything above 1280 blows up */
249 if (srmmu_nocache_npages
> SRMMU_MAX_NOCACHE_PAGES
)
250 srmmu_nocache_npages
= SRMMU_MAX_NOCACHE_PAGES
;
252 srmmu_nocache_size
= srmmu_nocache_npages
* PAGE_SIZE
;
253 srmmu_nocache_end
= SRMMU_NOCACHE_VADDR
+ srmmu_nocache_size
;
256 static void __init
srmmu_nocache_init(void)
258 unsigned int bitmap_bits
;
262 unsigned long paddr
, vaddr
;
263 unsigned long pteval
;
265 bitmap_bits
= srmmu_nocache_size
>> SRMMU_NOCACHE_BITMAP_SHIFT
;
267 srmmu_nocache_pool
= __alloc_bootmem(srmmu_nocache_size
,
268 SRMMU_NOCACHE_ALIGN_MAX
, 0UL);
269 memset(srmmu_nocache_pool
, 0, srmmu_nocache_size
);
271 srmmu_nocache_bitmap
= __alloc_bootmem(bitmap_bits
>> 3, SMP_CACHE_BYTES
, 0UL);
272 bit_map_init(&srmmu_nocache_map
, srmmu_nocache_bitmap
, bitmap_bits
);
274 srmmu_swapper_pg_dir
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
275 memset(__nocache_fix(srmmu_swapper_pg_dir
), 0, SRMMU_PGD_TABLE_SIZE
);
276 init_mm
.pgd
= srmmu_swapper_pg_dir
;
278 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR
, srmmu_nocache_end
);
280 paddr
= __pa((unsigned long)srmmu_nocache_pool
);
281 vaddr
= SRMMU_NOCACHE_VADDR
;
283 while (vaddr
< srmmu_nocache_end
) {
284 pgd
= pgd_offset_k(vaddr
);
285 pmd
= pmd_offset(__nocache_fix(pgd
), vaddr
);
286 pte
= pte_offset_kernel(__nocache_fix(pmd
), vaddr
);
288 pteval
= ((paddr
>> 4) | SRMMU_ET_PTE
| SRMMU_PRIV
);
290 if (srmmu_cache_pagetables
)
291 pteval
|= SRMMU_CACHE
;
293 set_pte(__nocache_fix(pte
), __pte(pteval
));
303 pgd_t
*get_pgd_fast(void)
307 pgd
= (pgd_t
*)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE
, SRMMU_PGD_TABLE_SIZE
);
309 pgd_t
*init
= pgd_offset_k(0);
310 memset(pgd
, 0, USER_PTRS_PER_PGD
* sizeof(pgd_t
));
311 memcpy(pgd
+ USER_PTRS_PER_PGD
, init
+ USER_PTRS_PER_PGD
,
312 (PTRS_PER_PGD
- USER_PTRS_PER_PGD
) * sizeof(pgd_t
));
319 * Hardware needs alignment to 256 only, but we align to whole page size
320 * to reduce fragmentation problems due to the buddy principle.
321 * XXX Provide actual fragmentation statistics in /proc.
323 * Alignments up to the page size are the same for physical and virtual
324 * addresses of the nocache area.
326 pgtable_t
pte_alloc_one(struct mm_struct
*mm
, unsigned long address
)
331 if ((pte
= (unsigned long)pte_alloc_one_kernel(mm
, address
)) == 0)
333 page
= pfn_to_page( __nocache_pa(pte
) >> PAGE_SHIFT
);
334 pgtable_page_ctor(page
);
338 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
342 pgtable_page_dtor(pte
);
343 p
= (unsigned long)page_address(pte
); /* Cached address (for test) */
346 p
= page_to_pfn(pte
) << PAGE_SHIFT
; /* Physical address */
347 p
= (unsigned long) __nocache_va(p
); /* Nocached virtual */
348 srmmu_free_nocache(p
, PTE_SIZE
);
353 static inline void alloc_context(struct mm_struct
*old_mm
, struct mm_struct
*mm
)
355 struct ctx_list
*ctxp
;
357 ctxp
= ctx_free
.next
;
358 if(ctxp
!= &ctx_free
) {
359 remove_from_ctx_list(ctxp
);
360 add_to_used_ctxlist(ctxp
);
361 mm
->context
= ctxp
->ctx_number
;
365 ctxp
= ctx_used
.next
;
366 if(ctxp
->ctx_mm
== old_mm
)
368 if(ctxp
== &ctx_used
)
369 panic("out of mmu contexts");
370 flush_cache_mm(ctxp
->ctx_mm
);
371 flush_tlb_mm(ctxp
->ctx_mm
);
372 remove_from_ctx_list(ctxp
);
373 add_to_used_ctxlist(ctxp
);
374 ctxp
->ctx_mm
->context
= NO_CONTEXT
;
376 mm
->context
= ctxp
->ctx_number
;
379 static inline void free_context(int context
)
381 struct ctx_list
*ctx_old
;
383 ctx_old
= ctx_list_pool
+ context
;
384 remove_from_ctx_list(ctx_old
);
385 add_to_free_ctxlist(ctx_old
);
389 void switch_mm(struct mm_struct
*old_mm
, struct mm_struct
*mm
,
390 struct task_struct
*tsk
)
392 if(mm
->context
== NO_CONTEXT
) {
393 spin_lock(&srmmu_context_spinlock
);
394 alloc_context(old_mm
, mm
);
395 spin_unlock(&srmmu_context_spinlock
);
396 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], mm
->pgd
);
399 if (sparc_cpu_model
== sparc_leon
)
403 hyper_flush_whole_icache();
405 srmmu_set_context(mm
->context
);
408 /* Low level IO area allocation on the SRMMU. */
409 static inline void srmmu_mapioaddr(unsigned long physaddr
,
410 unsigned long virt_addr
, int bus_type
)
417 physaddr
&= PAGE_MASK
;
418 pgdp
= pgd_offset_k(virt_addr
);
419 pmdp
= pmd_offset(pgdp
, virt_addr
);
420 ptep
= pte_offset_kernel(pmdp
, virt_addr
);
421 tmp
= (physaddr
>> 4) | SRMMU_ET_PTE
;
424 * I need to test whether this is consistent over all
425 * sun4m's. The bus_type represents the upper 4 bits of
426 * 36-bit physical address on the I/O space lines...
428 tmp
|= (bus_type
<< 28);
430 __flush_page_to_ram(virt_addr
);
431 set_pte(ptep
, __pte(tmp
));
434 void srmmu_mapiorange(unsigned int bus
, unsigned long xpa
,
435 unsigned long xva
, unsigned int len
)
439 srmmu_mapioaddr(xpa
, xva
, bus
);
446 static inline void srmmu_unmapioaddr(unsigned long virt_addr
)
452 pgdp
= pgd_offset_k(virt_addr
);
453 pmdp
= pmd_offset(pgdp
, virt_addr
);
454 ptep
= pte_offset_kernel(pmdp
, virt_addr
);
456 /* No need to flush uncacheable page. */
460 void srmmu_unmapiorange(unsigned long virt_addr
, unsigned int len
)
464 srmmu_unmapioaddr(virt_addr
);
465 virt_addr
+= PAGE_SIZE
;
471 extern void tsunami_flush_cache_all(void);
472 extern void tsunami_flush_cache_mm(struct mm_struct
*mm
);
473 extern void tsunami_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
474 extern void tsunami_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
475 extern void tsunami_flush_page_to_ram(unsigned long page
);
476 extern void tsunami_flush_page_for_dma(unsigned long page
);
477 extern void tsunami_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
478 extern void tsunami_flush_tlb_all(void);
479 extern void tsunami_flush_tlb_mm(struct mm_struct
*mm
);
480 extern void tsunami_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
481 extern void tsunami_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
482 extern void tsunami_setup_blockops(void);
485 extern void swift_flush_cache_all(void);
486 extern void swift_flush_cache_mm(struct mm_struct
*mm
);
487 extern void swift_flush_cache_range(struct vm_area_struct
*vma
,
488 unsigned long start
, unsigned long end
);
489 extern void swift_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
490 extern void swift_flush_page_to_ram(unsigned long page
);
491 extern void swift_flush_page_for_dma(unsigned long page
);
492 extern void swift_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
493 extern void swift_flush_tlb_all(void);
494 extern void swift_flush_tlb_mm(struct mm_struct
*mm
);
495 extern void swift_flush_tlb_range(struct vm_area_struct
*vma
,
496 unsigned long start
, unsigned long end
);
497 extern void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
499 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
500 void swift_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
505 if ((ctx1
= vma
->vm_mm
->context
) != -1) {
506 cctx
= srmmu_get_context();
507 /* Is context # ever different from current context? P3 */
509 printk("flush ctx %02x curr %02x\n", ctx1
, cctx
);
510 srmmu_set_context(ctx1
);
511 swift_flush_page(page
);
512 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
513 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
514 srmmu_set_context(cctx
);
516 /* Rm. prot. bits from virt. c. */
517 /* swift_flush_cache_all(); */
518 /* swift_flush_cache_page(vma, page); */
519 swift_flush_page(page
);
521 __asm__
__volatile__("sta %%g0, [%0] %1\n\t" : :
522 "r" (page
), "i" (ASI_M_FLUSH_PROBE
));
523 /* same as above: srmmu_flush_tlb_page() */
530 * The following are all MBUS based SRMMU modules, and therefore could
531 * be found in a multiprocessor configuration. On the whole, these
532 * chips seems to be much more touchy about DVMA and page tables
533 * with respect to cache coherency.
537 extern void viking_flush_cache_all(void);
538 extern void viking_flush_cache_mm(struct mm_struct
*mm
);
539 extern void viking_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
,
541 extern void viking_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
542 extern void viking_flush_page_to_ram(unsigned long page
);
543 extern void viking_flush_page_for_dma(unsigned long page
);
544 extern void viking_flush_sig_insns(struct mm_struct
*mm
, unsigned long addr
);
545 extern void viking_flush_page(unsigned long page
);
546 extern void viking_mxcc_flush_page(unsigned long page
);
547 extern void viking_flush_tlb_all(void);
548 extern void viking_flush_tlb_mm(struct mm_struct
*mm
);
549 extern void viking_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
551 extern void viking_flush_tlb_page(struct vm_area_struct
*vma
,
553 extern void sun4dsmp_flush_tlb_all(void);
554 extern void sun4dsmp_flush_tlb_mm(struct mm_struct
*mm
);
555 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
,
557 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct
*vma
,
561 extern void hypersparc_flush_cache_all(void);
562 extern void hypersparc_flush_cache_mm(struct mm_struct
*mm
);
563 extern void hypersparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
564 extern void hypersparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
);
565 extern void hypersparc_flush_page_to_ram(unsigned long page
);
566 extern void hypersparc_flush_page_for_dma(unsigned long page
);
567 extern void hypersparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
);
568 extern void hypersparc_flush_tlb_all(void);
569 extern void hypersparc_flush_tlb_mm(struct mm_struct
*mm
);
570 extern void hypersparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
);
571 extern void hypersparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
);
572 extern void hypersparc_setup_blockops(void);
575 * NOTE: All of this startup code assumes the low 16mb (approx.) of
576 * kernel mappings are done with one single contiguous chunk of
577 * ram. On small ram machines (classics mainly) we only get
578 * around 8mb mapped for us.
581 static void __init
early_pgtable_allocfail(char *type
)
583 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type
);
587 static void __init
srmmu_early_allocate_ptable_skeleton(unsigned long start
,
595 pgdp
= pgd_offset_k(start
);
596 if (pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
597 pmdp
= (pmd_t
*) __srmmu_get_nocache(
598 SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
600 early_pgtable_allocfail("pmd");
601 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
602 pgd_set(__nocache_fix(pgdp
), pmdp
);
604 pmdp
= pmd_offset(__nocache_fix(pgdp
), start
);
605 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
606 ptep
= (pte_t
*)__srmmu_get_nocache(PTE_SIZE
, PTE_SIZE
);
608 early_pgtable_allocfail("pte");
609 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
610 pmd_set(__nocache_fix(pmdp
), ptep
);
612 if (start
> (0xffffffffUL
- PMD_SIZE
))
614 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
618 static void __init
srmmu_allocate_ptable_skeleton(unsigned long start
,
626 pgdp
= pgd_offset_k(start
);
627 if (pgd_none(*pgdp
)) {
628 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
630 early_pgtable_allocfail("pmd");
631 memset(pmdp
, 0, SRMMU_PMD_TABLE_SIZE
);
634 pmdp
= pmd_offset(pgdp
, start
);
635 if(srmmu_pmd_none(*pmdp
)) {
636 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
639 early_pgtable_allocfail("pte");
640 memset(ptep
, 0, PTE_SIZE
);
643 if (start
> (0xffffffffUL
- PMD_SIZE
))
645 start
= (start
+ PMD_SIZE
) & PMD_MASK
;
650 * This is much cleaner than poking around physical address space
651 * looking at the prom's page table directly which is what most
652 * other OS's do. Yuck... this is much better.
654 static void __init
srmmu_inherit_prom_mappings(unsigned long start
,
660 int what
= 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
661 unsigned long prompte
;
663 while(start
<= end
) {
665 break; /* probably wrap around */
666 if(start
== 0xfef00000)
667 start
= KADB_DEBUGGER_BEGVM
;
668 if(!(prompte
= srmmu_hwprobe(start
))) {
673 /* A red snapper, see what it really is. */
676 if(!(start
& ~(SRMMU_REAL_PMD_MASK
))) {
677 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_REAL_PMD_SIZE
) == prompte
)
681 if(!(start
& ~(SRMMU_PGDIR_MASK
))) {
682 if(srmmu_hwprobe((start
-PAGE_SIZE
) + SRMMU_PGDIR_SIZE
) ==
687 pgdp
= pgd_offset_k(start
);
689 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(prompte
);
690 start
+= SRMMU_PGDIR_SIZE
;
693 if (pgd_none(*(pgd_t
*)__nocache_fix(pgdp
))) {
694 pmdp
= (pmd_t
*)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE
, SRMMU_PMD_TABLE_SIZE
);
696 early_pgtable_allocfail("pmd");
697 memset(__nocache_fix(pmdp
), 0, SRMMU_PMD_TABLE_SIZE
);
698 pgd_set(__nocache_fix(pgdp
), pmdp
);
700 pmdp
= pmd_offset(__nocache_fix(pgdp
), start
);
701 if(srmmu_pmd_none(*(pmd_t
*)__nocache_fix(pmdp
))) {
702 ptep
= (pte_t
*) __srmmu_get_nocache(PTE_SIZE
,
705 early_pgtable_allocfail("pte");
706 memset(__nocache_fix(ptep
), 0, PTE_SIZE
);
707 pmd_set(__nocache_fix(pmdp
), ptep
);
711 * We bend the rule where all 16 PTPs in a pmd_t point
712 * inside the same PTE page, and we leak a perfectly
713 * good hardware PTE piece. Alternatives seem worse.
715 unsigned int x
; /* Index of HW PMD in soft cluster */
716 x
= (start
>> PMD_SHIFT
) & 15;
717 *(unsigned long *)__nocache_fix(&pmdp
->pmdv
[x
]) = prompte
;
718 start
+= SRMMU_REAL_PMD_SIZE
;
721 ptep
= pte_offset_kernel(__nocache_fix(pmdp
), start
);
722 *(pte_t
*)__nocache_fix(ptep
) = __pte(prompte
);
727 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
729 /* Create a third-level SRMMU 16MB page mapping. */
730 static void __init
do_large_mapping(unsigned long vaddr
, unsigned long phys_base
)
732 pgd_t
*pgdp
= pgd_offset_k(vaddr
);
733 unsigned long big_pte
;
735 big_pte
= KERNEL_PTE(phys_base
>> 4);
736 *(pgd_t
*)__nocache_fix(pgdp
) = __pgd(big_pte
);
739 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
740 static unsigned long __init
map_spbank(unsigned long vbase
, int sp_entry
)
742 unsigned long pstart
= (sp_banks
[sp_entry
].base_addr
& SRMMU_PGDIR_MASK
);
743 unsigned long vstart
= (vbase
& SRMMU_PGDIR_MASK
);
744 unsigned long vend
= SRMMU_PGDIR_ALIGN(vbase
+ sp_banks
[sp_entry
].num_bytes
);
745 /* Map "low" memory only */
746 const unsigned long min_vaddr
= PAGE_OFFSET
;
747 const unsigned long max_vaddr
= PAGE_OFFSET
+ SRMMU_MAXMEM
;
749 if (vstart
< min_vaddr
|| vstart
>= max_vaddr
)
752 if (vend
> max_vaddr
|| vend
< min_vaddr
)
755 while(vstart
< vend
) {
756 do_large_mapping(vstart
, pstart
);
757 vstart
+= SRMMU_PGDIR_SIZE
; pstart
+= SRMMU_PGDIR_SIZE
;
762 static inline void map_kernel(void)
767 do_large_mapping(PAGE_OFFSET
, phys_base
);
770 for (i
= 0; sp_banks
[i
].num_bytes
!= 0; i
++) {
771 map_spbank((unsigned long)__va(sp_banks
[i
].base_addr
), i
);
775 /* Paging initialization on the Sparc Reference MMU. */
776 extern void sparc_context_init(int);
778 void (*poke_srmmu
)(void) __cpuinitdata
= NULL
;
780 extern unsigned long bootmem_init(unsigned long *pages_avail
);
782 void __init
srmmu_paging_init(void)
790 unsigned long pages_avail
;
792 sparc_iomap
.start
= SUN4M_IOBASE_VADDR
; /* 16MB of IOSPACE on all sun4m's. */
794 if (sparc_cpu_model
== sun4d
)
795 num_contexts
= 65536; /* We know it is Viking */
797 /* Find the number of contexts on the srmmu. */
798 cpunode
= prom_getchild(prom_root_node
);
800 while(cpunode
!= 0) {
801 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
802 if(!strcmp(node_str
, "cpu")) {
803 num_contexts
= prom_getintdefault(cpunode
, "mmu-nctx", 0x8);
806 cpunode
= prom_getsibling(cpunode
);
811 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
816 last_valid_pfn
= bootmem_init(&pages_avail
);
818 srmmu_nocache_calcsize();
819 srmmu_nocache_init();
820 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM
-PAGE_SIZE
));
823 /* ctx table has to be physically aligned to its size */
824 srmmu_context_table
= (ctxd_t
*)__srmmu_get_nocache(num_contexts
*sizeof(ctxd_t
), num_contexts
*sizeof(ctxd_t
));
825 srmmu_ctx_table_phys
= (ctxd_t
*)__nocache_pa((unsigned long)srmmu_context_table
);
827 for(i
= 0; i
< num_contexts
; i
++)
828 srmmu_ctxd_set((ctxd_t
*)__nocache_fix(&srmmu_context_table
[i
]), srmmu_swapper_pg_dir
);
831 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys
);
833 /* Stop from hanging here... */
834 local_ops
->tlb_all();
840 srmmu_allocate_ptable_skeleton(sparc_iomap
.start
, IOBASE_END
);
841 srmmu_allocate_ptable_skeleton(DVMA_VADDR
, DVMA_END
);
843 srmmu_allocate_ptable_skeleton(
844 __fix_to_virt(__end_of_fixed_addresses
- 1), FIXADDR_TOP
);
845 srmmu_allocate_ptable_skeleton(PKMAP_BASE
, PKMAP_END
);
847 pgd
= pgd_offset_k(PKMAP_BASE
);
848 pmd
= pmd_offset(pgd
, PKMAP_BASE
);
849 pte
= pte_offset_kernel(pmd
, PKMAP_BASE
);
850 pkmap_page_table
= pte
;
855 sparc_context_init(num_contexts
);
860 unsigned long zones_size
[MAX_NR_ZONES
];
861 unsigned long zholes_size
[MAX_NR_ZONES
];
862 unsigned long npages
;
865 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
866 zones_size
[znum
] = zholes_size
[znum
] = 0;
868 npages
= max_low_pfn
- pfn_base
;
870 zones_size
[ZONE_DMA
] = npages
;
871 zholes_size
[ZONE_DMA
] = npages
- pages_avail
;
873 npages
= highend_pfn
- max_low_pfn
;
874 zones_size
[ZONE_HIGHMEM
] = npages
;
875 zholes_size
[ZONE_HIGHMEM
] = npages
- calc_highpages();
877 free_area_init_node(0, zones_size
, pfn_base
, zholes_size
);
881 void mmu_info(struct seq_file
*m
)
886 "nocache total\t: %ld\n"
887 "nocache used\t: %d\n",
891 srmmu_nocache_map
.used
<< SRMMU_NOCACHE_BITMAP_SHIFT
);
894 void destroy_context(struct mm_struct
*mm
)
897 if(mm
->context
!= NO_CONTEXT
) {
899 srmmu_ctxd_set(&srmmu_context_table
[mm
->context
], srmmu_swapper_pg_dir
);
901 spin_lock(&srmmu_context_spinlock
);
902 free_context(mm
->context
);
903 spin_unlock(&srmmu_context_spinlock
);
904 mm
->context
= NO_CONTEXT
;
908 /* Init various srmmu chip types. */
909 static void __init
srmmu_is_bad(void)
911 prom_printf("Could not determine SRMMU chip type.\n");
915 static void __init
init_vac_layout(void)
922 unsigned long max_size
= 0;
923 unsigned long min_line_size
= 0x10000000;
926 nd
= prom_getchild(prom_root_node
);
927 while((nd
= prom_getsibling(nd
)) != 0) {
928 prom_getstring(nd
, "device_type", node_str
, sizeof(node_str
));
929 if(!strcmp(node_str
, "cpu")) {
930 vac_line_size
= prom_getint(nd
, "cache-line-size");
931 if (vac_line_size
== -1) {
932 prom_printf("can't determine cache-line-size, "
936 cache_lines
= prom_getint(nd
, "cache-nlines");
937 if (cache_lines
== -1) {
938 prom_printf("can't determine cache-nlines, halting.\n");
942 vac_cache_size
= cache_lines
* vac_line_size
;
944 if(vac_cache_size
> max_size
)
945 max_size
= vac_cache_size
;
946 if(vac_line_size
< min_line_size
)
947 min_line_size
= vac_line_size
;
948 //FIXME: cpus not contiguous!!
950 if (cpu
>= nr_cpu_ids
|| !cpu_online(cpu
))
958 prom_printf("No CPU nodes found, halting.\n");
962 vac_cache_size
= max_size
;
963 vac_line_size
= min_line_size
;
965 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
966 (int)vac_cache_size
, (int)vac_line_size
);
969 static void __cpuinit
poke_hypersparc(void)
971 volatile unsigned long clear
;
972 unsigned long mreg
= srmmu_get_mmureg();
974 hyper_flush_unconditional_combined();
976 mreg
&= ~(HYPERSPARC_CWENABLE
);
977 mreg
|= (HYPERSPARC_CENABLE
| HYPERSPARC_WBENABLE
);
978 mreg
|= (HYPERSPARC_CMODE
);
980 srmmu_set_mmureg(mreg
);
982 #if 0 /* XXX I think this is bad news... -DaveM */
983 hyper_clear_all_tags();
986 put_ross_icr(HYPERSPARC_ICCR_FTD
| HYPERSPARC_ICCR_ICE
);
987 hyper_flush_whole_icache();
988 clear
= srmmu_get_faddr();
989 clear
= srmmu_get_fstatus();
992 static const struct sparc32_cachetlb_ops hypersparc_ops
= {
993 .cache_all
= hypersparc_flush_cache_all
,
994 .cache_mm
= hypersparc_flush_cache_mm
,
995 .cache_page
= hypersparc_flush_cache_page
,
996 .cache_range
= hypersparc_flush_cache_range
,
997 .tlb_all
= hypersparc_flush_tlb_all
,
998 .tlb_mm
= hypersparc_flush_tlb_mm
,
999 .tlb_page
= hypersparc_flush_tlb_page
,
1000 .tlb_range
= hypersparc_flush_tlb_range
,
1001 .page_to_ram
= hypersparc_flush_page_to_ram
,
1002 .sig_insns
= hypersparc_flush_sig_insns
,
1003 .page_for_dma
= hypersparc_flush_page_for_dma
,
1006 static void __init
init_hypersparc(void)
1008 srmmu_name
= "ROSS HyperSparc";
1009 srmmu_modtype
= HyperSparc
;
1014 sparc32_cachetlb_ops
= &hypersparc_ops
;
1016 poke_srmmu
= poke_hypersparc
;
1018 hypersparc_setup_blockops();
1021 static void __cpuinit
poke_swift(void)
1025 /* Clear any crap from the cache or else... */
1026 swift_flush_cache_all();
1028 /* Enable I & D caches */
1029 mreg
= srmmu_get_mmureg();
1030 mreg
|= (SWIFT_IE
| SWIFT_DE
);
1032 * The Swift branch folding logic is completely broken. At
1033 * trap time, if things are just right, if can mistakenly
1034 * think that a trap is coming from kernel mode when in fact
1035 * it is coming from user mode (it mis-executes the branch in
1036 * the trap code). So you see things like crashme completely
1037 * hosing your machine which is completely unacceptable. Turn
1038 * this shit off... nice job Fujitsu.
1040 mreg
&= ~(SWIFT_BF
);
1041 srmmu_set_mmureg(mreg
);
1044 static const struct sparc32_cachetlb_ops swift_ops
= {
1045 .cache_all
= swift_flush_cache_all
,
1046 .cache_mm
= swift_flush_cache_mm
,
1047 .cache_page
= swift_flush_cache_page
,
1048 .cache_range
= swift_flush_cache_range
,
1049 .tlb_all
= swift_flush_tlb_all
,
1050 .tlb_mm
= swift_flush_tlb_mm
,
1051 .tlb_page
= swift_flush_tlb_page
,
1052 .tlb_range
= swift_flush_tlb_range
,
1053 .page_to_ram
= swift_flush_page_to_ram
,
1054 .sig_insns
= swift_flush_sig_insns
,
1055 .page_for_dma
= swift_flush_page_for_dma
,
1058 #define SWIFT_MASKID_ADDR 0x10003018
1059 static void __init
init_swift(void)
1061 unsigned long swift_rev
;
1063 __asm__
__volatile__("lda [%1] %2, %0\n\t"
1064 "srl %0, 0x18, %0\n\t" :
1066 "r" (SWIFT_MASKID_ADDR
), "i" (ASI_M_BYPASS
));
1067 srmmu_name
= "Fujitsu Swift";
1073 srmmu_modtype
= Swift_lots_o_bugs
;
1074 hwbug_bitmask
|= (HWBUG_KERN_ACCBROKEN
| HWBUG_KERN_CBITBROKEN
);
1076 * Gee george, I wonder why Sun is so hush hush about
1077 * this hardware bug... really braindamage stuff going
1078 * on here. However I think we can find a way to avoid
1079 * all of the workaround overhead under Linux. Basically,
1080 * any page fault can cause kernel pages to become user
1081 * accessible (the mmu gets confused and clears some of
1082 * the ACC bits in kernel ptes). Aha, sounds pretty
1083 * horrible eh? But wait, after extensive testing it appears
1084 * that if you use pgd_t level large kernel pte's (like the
1085 * 4MB pages on the Pentium) the bug does not get tripped
1086 * at all. This avoids almost all of the major overhead.
1087 * Welcome to a world where your vendor tells you to,
1088 * "apply this kernel patch" instead of "sorry for the
1089 * broken hardware, send it back and we'll give you
1090 * properly functioning parts"
1095 srmmu_modtype
= Swift_bad_c
;
1096 hwbug_bitmask
|= HWBUG_KERN_CBITBROKEN
;
1098 * You see Sun allude to this hardware bug but never
1099 * admit things directly, they'll say things like,
1100 * "the Swift chip cache problems" or similar.
1104 srmmu_modtype
= Swift_ok
;
1108 sparc32_cachetlb_ops
= &swift_ops
;
1109 flush_page_for_dma_global
= 0;
1112 * Are you now convinced that the Swift is one of the
1113 * biggest VLSI abortions of all time? Bravo Fujitsu!
1114 * Fujitsu, the !#?!%$'d up processor people. I bet if
1115 * you examined the microcode of the Swift you'd find
1116 * XXX's all over the place.
1118 poke_srmmu
= poke_swift
;
1121 static void turbosparc_flush_cache_all(void)
1123 flush_user_windows();
1124 turbosparc_idflash_clear();
1127 static void turbosparc_flush_cache_mm(struct mm_struct
*mm
)
1130 flush_user_windows();
1131 turbosparc_idflash_clear();
1135 static void turbosparc_flush_cache_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1137 FLUSH_BEGIN(vma
->vm_mm
)
1138 flush_user_windows();
1139 turbosparc_idflash_clear();
1143 static void turbosparc_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
1145 FLUSH_BEGIN(vma
->vm_mm
)
1146 flush_user_windows();
1147 if (vma
->vm_flags
& VM_EXEC
)
1148 turbosparc_flush_icache();
1149 turbosparc_flush_dcache();
1153 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1154 static void turbosparc_flush_page_to_ram(unsigned long page
)
1156 #ifdef TURBOSPARC_WRITEBACK
1157 volatile unsigned long clear
;
1159 if (srmmu_hwprobe(page
))
1160 turbosparc_flush_page_cache(page
);
1161 clear
= srmmu_get_fstatus();
1165 static void turbosparc_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
1169 static void turbosparc_flush_page_for_dma(unsigned long page
)
1171 turbosparc_flush_dcache();
1174 static void turbosparc_flush_tlb_all(void)
1176 srmmu_flush_whole_tlb();
1179 static void turbosparc_flush_tlb_mm(struct mm_struct
*mm
)
1182 srmmu_flush_whole_tlb();
1186 static void turbosparc_flush_tlb_range(struct vm_area_struct
*vma
, unsigned long start
, unsigned long end
)
1188 FLUSH_BEGIN(vma
->vm_mm
)
1189 srmmu_flush_whole_tlb();
1193 static void turbosparc_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
1195 FLUSH_BEGIN(vma
->vm_mm
)
1196 srmmu_flush_whole_tlb();
1201 static void __cpuinit
poke_turbosparc(void)
1203 unsigned long mreg
= srmmu_get_mmureg();
1204 unsigned long ccreg
;
1206 /* Clear any crap from the cache or else... */
1207 turbosparc_flush_cache_all();
1208 mreg
&= ~(TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* Temporarily disable I & D caches */
1209 mreg
&= ~(TURBOSPARC_PCENABLE
); /* Don't check parity */
1210 srmmu_set_mmureg(mreg
);
1212 ccreg
= turbosparc_get_ccreg();
1214 #ifdef TURBOSPARC_WRITEBACK
1215 ccreg
|= (TURBOSPARC_SNENABLE
); /* Do DVMA snooping in Dcache */
1216 ccreg
&= ~(TURBOSPARC_uS2
| TURBOSPARC_WTENABLE
);
1217 /* Write-back D-cache, emulate VLSI
1218 * abortion number three, not number one */
1220 /* For now let's play safe, optimize later */
1221 ccreg
|= (TURBOSPARC_SNENABLE
| TURBOSPARC_WTENABLE
);
1222 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1223 ccreg
&= ~(TURBOSPARC_uS2
);
1224 /* Emulate VLSI abortion number three, not number one */
1227 switch (ccreg
& 7) {
1228 case 0: /* No SE cache */
1229 case 7: /* Test mode */
1232 ccreg
|= (TURBOSPARC_SCENABLE
);
1234 turbosparc_set_ccreg (ccreg
);
1236 mreg
|= (TURBOSPARC_ICENABLE
| TURBOSPARC_DCENABLE
); /* I & D caches on */
1237 mreg
|= (TURBOSPARC_ICSNOOP
); /* Icache snooping on */
1238 srmmu_set_mmureg(mreg
);
1241 static const struct sparc32_cachetlb_ops turbosparc_ops
= {
1242 .cache_all
= turbosparc_flush_cache_all
,
1243 .cache_mm
= turbosparc_flush_cache_mm
,
1244 .cache_page
= turbosparc_flush_cache_page
,
1245 .cache_range
= turbosparc_flush_cache_range
,
1246 .tlb_all
= turbosparc_flush_tlb_all
,
1247 .tlb_mm
= turbosparc_flush_tlb_mm
,
1248 .tlb_page
= turbosparc_flush_tlb_page
,
1249 .tlb_range
= turbosparc_flush_tlb_range
,
1250 .page_to_ram
= turbosparc_flush_page_to_ram
,
1251 .sig_insns
= turbosparc_flush_sig_insns
,
1252 .page_for_dma
= turbosparc_flush_page_for_dma
,
1255 static void __init
init_turbosparc(void)
1257 srmmu_name
= "Fujitsu TurboSparc";
1258 srmmu_modtype
= TurboSparc
;
1259 sparc32_cachetlb_ops
= &turbosparc_ops
;
1260 poke_srmmu
= poke_turbosparc
;
1263 static void __cpuinit
poke_tsunami(void)
1265 unsigned long mreg
= srmmu_get_mmureg();
1267 tsunami_flush_icache();
1268 tsunami_flush_dcache();
1269 mreg
&= ~TSUNAMI_ITD
;
1270 mreg
|= (TSUNAMI_IENAB
| TSUNAMI_DENAB
);
1271 srmmu_set_mmureg(mreg
);
1274 static const struct sparc32_cachetlb_ops tsunami_ops
= {
1275 .cache_all
= tsunami_flush_cache_all
,
1276 .cache_mm
= tsunami_flush_cache_mm
,
1277 .cache_page
= tsunami_flush_cache_page
,
1278 .cache_range
= tsunami_flush_cache_range
,
1279 .tlb_all
= tsunami_flush_tlb_all
,
1280 .tlb_mm
= tsunami_flush_tlb_mm
,
1281 .tlb_page
= tsunami_flush_tlb_page
,
1282 .tlb_range
= tsunami_flush_tlb_range
,
1283 .page_to_ram
= tsunami_flush_page_to_ram
,
1284 .sig_insns
= tsunami_flush_sig_insns
,
1285 .page_for_dma
= tsunami_flush_page_for_dma
,
1288 static void __init
init_tsunami(void)
1291 * Tsunami's pretty sane, Sun and TI actually got it
1292 * somewhat right this time. Fujitsu should have
1293 * taken some lessons from them.
1296 srmmu_name
= "TI Tsunami";
1297 srmmu_modtype
= Tsunami
;
1298 sparc32_cachetlb_ops
= &tsunami_ops
;
1299 poke_srmmu
= poke_tsunami
;
1301 tsunami_setup_blockops();
1304 static void __cpuinit
poke_viking(void)
1306 unsigned long mreg
= srmmu_get_mmureg();
1307 static int smp_catch
;
1309 if (viking_mxcc_present
) {
1310 unsigned long mxcc_control
= mxcc_get_creg();
1312 mxcc_control
|= (MXCC_CTL_ECE
| MXCC_CTL_PRE
| MXCC_CTL_MCE
);
1313 mxcc_control
&= ~(MXCC_CTL_RRC
);
1314 mxcc_set_creg(mxcc_control
);
1317 * We don't need memory parity checks.
1318 * XXX This is a mess, have to dig out later. ecd.
1319 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1322 /* We do cache ptables on MXCC. */
1323 mreg
|= VIKING_TCENABLE
;
1325 unsigned long bpreg
;
1327 mreg
&= ~(VIKING_TCENABLE
);
1329 /* Must disable mixed-cmd mode here for other cpu's. */
1330 bpreg
= viking_get_bpreg();
1331 bpreg
&= ~(VIKING_ACTION_MIX
);
1332 viking_set_bpreg(bpreg
);
1334 /* Just in case PROM does something funny. */
1339 mreg
|= VIKING_SPENABLE
;
1340 mreg
|= (VIKING_ICENABLE
| VIKING_DCENABLE
);
1341 mreg
|= VIKING_SBENABLE
;
1342 mreg
&= ~(VIKING_ACENABLE
);
1343 srmmu_set_mmureg(mreg
);
1346 static struct sparc32_cachetlb_ops viking_ops
= {
1347 .cache_all
= viking_flush_cache_all
,
1348 .cache_mm
= viking_flush_cache_mm
,
1349 .cache_page
= viking_flush_cache_page
,
1350 .cache_range
= viking_flush_cache_range
,
1351 .tlb_all
= viking_flush_tlb_all
,
1352 .tlb_mm
= viking_flush_tlb_mm
,
1353 .tlb_page
= viking_flush_tlb_page
,
1354 .tlb_range
= viking_flush_tlb_range
,
1355 .page_to_ram
= viking_flush_page_to_ram
,
1356 .sig_insns
= viking_flush_sig_insns
,
1357 .page_for_dma
= viking_flush_page_for_dma
,
1361 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1362 * perform the local TLB flush and all the other cpus will see it.
1363 * But, unfortunately, there is a bug in the sun4d XBUS backplane
1364 * that requires that we add some synchronization to these flushes.
1366 * The bug is that the fifo which keeps track of all the pending TLB
1367 * broadcasts in the system is an entry or two too small, so if we
1368 * have too many going at once we'll overflow that fifo and lose a TLB
1369 * flush resulting in corruption.
1371 * Our workaround is to take a global spinlock around the TLB flushes,
1372 * which guarentees we won't ever have too many pending. It's a big
1373 * hammer, but a semaphore like system to make sure we only have N TLB
1374 * flushes going at once will require SMP locking anyways so there's
1375 * no real value in trying any harder than this.
1377 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops
= {
1378 .cache_all
= viking_flush_cache_all
,
1379 .cache_mm
= viking_flush_cache_mm
,
1380 .cache_page
= viking_flush_cache_page
,
1381 .cache_range
= viking_flush_cache_range
,
1382 .tlb_all
= sun4dsmp_flush_tlb_all
,
1383 .tlb_mm
= sun4dsmp_flush_tlb_mm
,
1384 .tlb_page
= sun4dsmp_flush_tlb_page
,
1385 .tlb_range
= sun4dsmp_flush_tlb_range
,
1386 .page_to_ram
= viking_flush_page_to_ram
,
1387 .sig_insns
= viking_flush_sig_insns
,
1388 .page_for_dma
= viking_flush_page_for_dma
,
1392 static void __init
init_viking(void)
1394 unsigned long mreg
= srmmu_get_mmureg();
1396 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1397 if(mreg
& VIKING_MMODE
) {
1398 srmmu_name
= "TI Viking";
1399 viking_mxcc_present
= 0;
1403 * We need this to make sure old viking takes no hits
1404 * on it's cache for dma snoops to workaround the
1405 * "load from non-cacheable memory" interrupt bug.
1406 * This is only necessary because of the new way in
1407 * which we use the IOMMU.
1409 viking_ops
.page_for_dma
= viking_flush_page
;
1411 viking_sun4d_smp_ops
.page_for_dma
= viking_flush_page
;
1413 flush_page_for_dma_global
= 0;
1415 srmmu_name
= "TI Viking/MXCC";
1416 viking_mxcc_present
= 1;
1417 srmmu_cache_pagetables
= 1;
1420 sparc32_cachetlb_ops
= (const struct sparc32_cachetlb_ops
*)
1423 if (sparc_cpu_model
== sun4d
)
1424 sparc32_cachetlb_ops
= (const struct sparc32_cachetlb_ops
*)
1425 &viking_sun4d_smp_ops
;
1428 poke_srmmu
= poke_viking
;
1431 /* Probe for the srmmu chip version. */
1432 static void __init
get_srmmu_type(void)
1434 unsigned long mreg
, psr
;
1435 unsigned long mod_typ
, mod_rev
, psr_typ
, psr_vers
;
1437 srmmu_modtype
= SRMMU_INVAL_MOD
;
1440 mreg
= srmmu_get_mmureg(); psr
= get_psr();
1441 mod_typ
= (mreg
& 0xf0000000) >> 28;
1442 mod_rev
= (mreg
& 0x0f000000) >> 24;
1443 psr_typ
= (psr
>> 28) & 0xf;
1444 psr_vers
= (psr
>> 24) & 0xf;
1446 /* First, check for sparc-leon. */
1447 if (sparc_cpu_model
== sparc_leon
) {
1452 /* Second, check for HyperSparc or Cypress. */
1456 /* UP or MP Hypersparc */
1468 prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1476 * Now Fujitsu TurboSparc. It might happen that it is
1477 * in Swift emulation mode, so we will check later...
1479 if (psr_typ
== 0 && psr_vers
== 5) {
1484 /* Next check for Fujitsu Swift. */
1485 if(psr_typ
== 0 && psr_vers
== 4) {
1489 /* Look if it is not a TurboSparc emulating Swift... */
1490 cpunode
= prom_getchild(prom_root_node
);
1491 while((cpunode
= prom_getsibling(cpunode
)) != 0) {
1492 prom_getstring(cpunode
, "device_type", node_str
, sizeof(node_str
));
1493 if(!strcmp(node_str
, "cpu")) {
1494 if (!prom_getintdefault(cpunode
, "psr-implementation", 1) &&
1495 prom_getintdefault(cpunode
, "psr-version", 1) == 5) {
1507 /* Now the Viking family of srmmu. */
1510 ((psr_vers
== 1) && (mod_typ
== 0) && (mod_rev
== 0)))) {
1515 /* Finally the Tsunami. */
1516 if(psr_typ
== 4 && psr_vers
== 1 && (mod_typ
|| mod_rev
)) {
1526 /* Local cross-calls. */
1527 static void smp_flush_page_for_dma(unsigned long page
)
1529 xc1((smpfunc_t
) local_ops
->page_for_dma
, page
);
1530 local_ops
->page_for_dma(page
);
1533 static void smp_flush_cache_all(void)
1535 xc0((smpfunc_t
) local_ops
->cache_all
);
1536 local_ops
->cache_all();
1539 static void smp_flush_tlb_all(void)
1541 xc0((smpfunc_t
) local_ops
->tlb_all
);
1542 local_ops
->tlb_all();
1545 static void smp_flush_cache_mm(struct mm_struct
*mm
)
1547 if (mm
->context
!= NO_CONTEXT
) {
1549 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1550 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1551 if (!cpumask_empty(&cpu_mask
))
1552 xc1((smpfunc_t
) local_ops
->cache_mm
, (unsigned long) mm
);
1553 local_ops
->cache_mm(mm
);
1557 static void smp_flush_tlb_mm(struct mm_struct
*mm
)
1559 if (mm
->context
!= NO_CONTEXT
) {
1561 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1562 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1563 if (!cpumask_empty(&cpu_mask
)) {
1564 xc1((smpfunc_t
) local_ops
->tlb_mm
, (unsigned long) mm
);
1565 if (atomic_read(&mm
->mm_users
) == 1 && current
->active_mm
== mm
)
1566 cpumask_copy(mm_cpumask(mm
),
1567 cpumask_of(smp_processor_id()));
1569 local_ops
->tlb_mm(mm
);
1573 static void smp_flush_cache_range(struct vm_area_struct
*vma
,
1574 unsigned long start
,
1577 struct mm_struct
*mm
= vma
->vm_mm
;
1579 if (mm
->context
!= NO_CONTEXT
) {
1581 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1582 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1583 if (!cpumask_empty(&cpu_mask
))
1584 xc3((smpfunc_t
) local_ops
->cache_range
,
1585 (unsigned long) vma
, start
, end
);
1586 local_ops
->cache_range(vma
, start
, end
);
1590 static void smp_flush_tlb_range(struct vm_area_struct
*vma
,
1591 unsigned long start
,
1594 struct mm_struct
*mm
= vma
->vm_mm
;
1596 if (mm
->context
!= NO_CONTEXT
) {
1598 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1599 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1600 if (!cpumask_empty(&cpu_mask
))
1601 xc3((smpfunc_t
) local_ops
->tlb_range
,
1602 (unsigned long) vma
, start
, end
);
1603 local_ops
->tlb_range(vma
, start
, end
);
1607 static void smp_flush_cache_page(struct vm_area_struct
*vma
, unsigned long page
)
1609 struct mm_struct
*mm
= vma
->vm_mm
;
1611 if (mm
->context
!= NO_CONTEXT
) {
1613 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1614 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1615 if (!cpumask_empty(&cpu_mask
))
1616 xc2((smpfunc_t
) local_ops
->cache_page
,
1617 (unsigned long) vma
, page
);
1618 local_ops
->cache_page(vma
, page
);
1622 static void smp_flush_tlb_page(struct vm_area_struct
*vma
, unsigned long page
)
1624 struct mm_struct
*mm
= vma
->vm_mm
;
1626 if (mm
->context
!= NO_CONTEXT
) {
1628 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1629 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1630 if (!cpumask_empty(&cpu_mask
))
1631 xc2((smpfunc_t
) local_ops
->tlb_page
,
1632 (unsigned long) vma
, page
);
1633 local_ops
->tlb_page(vma
, page
);
1637 static void smp_flush_page_to_ram(unsigned long page
)
1639 /* Current theory is that those who call this are the one's
1640 * who have just dirtied their cache with the pages contents
1641 * in kernel space, therefore we only run this on local cpu.
1643 * XXX This experiment failed, research further... -DaveM
1646 xc1((smpfunc_t
) local_ops
->page_to_ram
, page
);
1648 local_ops
->page_to_ram(page
);
1651 static void smp_flush_sig_insns(struct mm_struct
*mm
, unsigned long insn_addr
)
1654 cpumask_copy(&cpu_mask
, mm_cpumask(mm
));
1655 cpumask_clear_cpu(smp_processor_id(), &cpu_mask
);
1656 if (!cpumask_empty(&cpu_mask
))
1657 xc2((smpfunc_t
) local_ops
->sig_insns
,
1658 (unsigned long) mm
, insn_addr
);
1659 local_ops
->sig_insns(mm
, insn_addr
);
1662 static struct sparc32_cachetlb_ops smp_cachetlb_ops
= {
1663 .cache_all
= smp_flush_cache_all
,
1664 .cache_mm
= smp_flush_cache_mm
,
1665 .cache_page
= smp_flush_cache_page
,
1666 .cache_range
= smp_flush_cache_range
,
1667 .tlb_all
= smp_flush_tlb_all
,
1668 .tlb_mm
= smp_flush_tlb_mm
,
1669 .tlb_page
= smp_flush_tlb_page
,
1670 .tlb_range
= smp_flush_tlb_range
,
1671 .page_to_ram
= smp_flush_page_to_ram
,
1672 .sig_insns
= smp_flush_sig_insns
,
1673 .page_for_dma
= smp_flush_page_for_dma
,
1677 /* Load up routines and constants for sun4m and sun4d mmu */
1678 void __init
load_mmu(void)
1680 extern void ld_mmu_iommu(void);
1681 extern void ld_mmu_iounit(void);
1687 /* El switcheroo... */
1688 local_ops
= sparc32_cachetlb_ops
;
1690 if (sparc_cpu_model
== sun4d
|| sparc_cpu_model
== sparc_leon
) {
1691 smp_cachetlb_ops
.tlb_all
= local_ops
->tlb_all
;
1692 smp_cachetlb_ops
.tlb_mm
= local_ops
->tlb_mm
;
1693 smp_cachetlb_ops
.tlb_range
= local_ops
->tlb_range
;
1694 smp_cachetlb_ops
.tlb_page
= local_ops
->tlb_page
;
1697 if (poke_srmmu
== poke_viking
) {
1698 /* Avoid unnecessary cross calls. */
1699 smp_cachetlb_ops
.cache_all
= local_ops
->cache_all
;
1700 smp_cachetlb_ops
.cache_mm
= local_ops
->cache_mm
;
1701 smp_cachetlb_ops
.cache_range
= local_ops
->cache_range
;
1702 smp_cachetlb_ops
.cache_page
= local_ops
->cache_page
;
1704 smp_cachetlb_ops
.page_to_ram
= local_ops
->page_to_ram
;
1705 smp_cachetlb_ops
.sig_insns
= local_ops
->sig_insns
;
1706 smp_cachetlb_ops
.page_for_dma
= local_ops
->page_for_dma
;
1709 /* It really is const after this point. */
1710 sparc32_cachetlb_ops
= (const struct sparc32_cachetlb_ops
*)
1714 if (sparc_cpu_model
== sun4d
)
1719 if (sparc_cpu_model
== sun4d
)
1721 else if (sparc_cpu_model
== sparc_leon
)