?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ASoC: max98090: add an of_match table
[linux-2.6/btrfs-unstable.git] / sound / soc / codecs / max98090.c
blob83a773c11ddb0f055b28b70ccbd4062d77b55d06
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 #define DEBUG
27 #define EXTMIC_METHOD
28 #define EXTMIC_METHOD_TEST
29
30 /* Allows for sparsely populated register maps */
31 static struct reg_default max98090_reg[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
46
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
97
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
253 };
254
255 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256 {
257 switch (reg) {
258 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID:
261 return true;
262 default:
263 return false;
264 }
265 }
266
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
268 {
269 switch (reg) {
270 case M98090_REG_DEVICE_STATUS:
271 case M98090_REG_JACK_STATUS:
272 case M98090_REG_INTERRUPT_S:
273 case M98090_REG_RESERVED:
274 case M98090_REG_LINE_INPUT_CONFIG:
275 case M98090_REG_LINE_INPUT_LEVEL:
276 case M98090_REG_INPUT_MODE:
277 case M98090_REG_MIC1_INPUT_LEVEL:
278 case M98090_REG_MIC2_INPUT_LEVEL:
279 case M98090_REG_MIC_BIAS_VOLTAGE:
280 case M98090_REG_DIGITAL_MIC_ENABLE:
281 case M98090_REG_DIGITAL_MIC_CONFIG:
282 case M98090_REG_LEFT_ADC_MIXER:
283 case M98090_REG_RIGHT_ADC_MIXER:
284 case M98090_REG_LEFT_ADC_LEVEL:
285 case M98090_REG_RIGHT_ADC_LEVEL:
286 case M98090_REG_ADC_BIQUAD_LEVEL:
287 case M98090_REG_ADC_SIDETONE:
288 case M98090_REG_SYSTEM_CLOCK:
289 case M98090_REG_CLOCK_MODE:
290 case M98090_REG_CLOCK_RATIO_NI_MSB:
291 case M98090_REG_CLOCK_RATIO_NI_LSB:
292 case M98090_REG_CLOCK_RATIO_MI_MSB:
293 case M98090_REG_CLOCK_RATIO_MI_LSB:
294 case M98090_REG_MASTER_MODE:
295 case M98090_REG_INTERFACE_FORMAT:
296 case M98090_REG_TDM_CONTROL:
297 case M98090_REG_TDM_FORMAT:
298 case M98090_REG_IO_CONFIGURATION:
299 case M98090_REG_FILTER_CONFIG:
300 case M98090_REG_DAI_PLAYBACK_LEVEL:
301 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
302 case M98090_REG_LEFT_HP_MIXER:
303 case M98090_REG_RIGHT_HP_MIXER:
304 case M98090_REG_HP_CONTROL:
305 case M98090_REG_LEFT_HP_VOLUME:
306 case M98090_REG_RIGHT_HP_VOLUME:
307 case M98090_REG_LEFT_SPK_MIXER:
308 case M98090_REG_RIGHT_SPK_MIXER:
309 case M98090_REG_SPK_CONTROL:
310 case M98090_REG_LEFT_SPK_VOLUME:
311 case M98090_REG_RIGHT_SPK_VOLUME:
312 case M98090_REG_DRC_TIMING:
313 case M98090_REG_DRC_COMPRESSOR:
314 case M98090_REG_DRC_EXPANDER:
315 case M98090_REG_DRC_GAIN:
316 case M98090_REG_RCV_LOUTL_MIXER:
317 case M98090_REG_RCV_LOUTL_CONTROL:
318 case M98090_REG_RCV_LOUTL_VOLUME:
319 case M98090_REG_LOUTR_MIXER:
320 case M98090_REG_LOUTR_CONTROL:
321 case M98090_REG_LOUTR_VOLUME:
322 case M98090_REG_JACK_DETECT:
323 case M98090_REG_INPUT_ENABLE:
324 case M98090_REG_OUTPUT_ENABLE:
325 case M98090_REG_LEVEL_CONTROL:
326 case M98090_REG_DSP_FILTER_ENABLE:
327 case M98090_REG_BIAS_CONTROL:
328 case M98090_REG_DAC_CONTROL:
329 case M98090_REG_ADC_CONTROL:
330 case M98090_REG_DEVICE_SHUTDOWN:
331 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
332 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
333 case M98090_REG_DMIC3_VOLUME:
334 case M98090_REG_DMIC4_VOLUME:
335 case M98090_REG_DMIC34_BQ_PREATTEN:
336 case M98090_REG_RECORD_TDM_SLOT:
337 case M98090_REG_SAMPLE_RATE:
338 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
339 return true;
340 default:
341 return false;
342 }
343 }
344
345 static int max98090_reset(struct max98090_priv *max98090)
346 {
347 int ret;
348
349 /* Reset the codec by writing to this write-only reset register */
350 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
351 M98090_SWRESET_MASK);
352 if (ret < 0) {
353 dev_err(max98090->codec->dev,
354 "Failed to reset codec: %d\n", ret);
355 return ret;
356 }
357
358 msleep(20);
359 return ret;
360 }
361
362 static const unsigned int max98090_micboost_tlv[] = {
363 TLV_DB_RANGE_HEAD(2),
364 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
365 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
366 };
367
368 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
369
370 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
371 -600, 600, 0);
372
373 static const unsigned int max98090_line_tlv[] = {
374 TLV_DB_RANGE_HEAD(2),
375 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
376 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
377 };
378
379 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
380 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
381
382 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
383 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
384
385 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
386
387 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
388 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
389 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
391
392 static const unsigned int max98090_mixout_tlv[] = {
393 TLV_DB_RANGE_HEAD(2),
394 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
395 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
396 };
397
398 static const unsigned int max98090_hp_tlv[] = {
399 TLV_DB_RANGE_HEAD(5),
400 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
401 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
402 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
403 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
404 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
405 };
406
407 static const unsigned int max98090_spk_tlv[] = {
408 TLV_DB_RANGE_HEAD(5),
409 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
410 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
411 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
412 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
413 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
414 };
415
416 static const unsigned int max98090_rcv_lout_tlv[] = {
417 TLV_DB_RANGE_HEAD(5),
418 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
419 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
420 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
421 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
422 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
423 };
424
425 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
430 struct soc_mixer_control *mc =
431 (struct soc_mixer_control *)kcontrol->private_value;
432 unsigned int mask = (1 << fls(mc->max)) - 1;
433 unsigned int val = snd_soc_read(codec, mc->reg);
434 unsigned int *select;
435
436 switch (mc->reg) {
437 case M98090_REG_MIC1_INPUT_LEVEL:
438 select = &(max98090->pa1en);
439 break;
440 case M98090_REG_MIC2_INPUT_LEVEL:
441 select = &(max98090->pa2en);
442 break;
443 case M98090_REG_ADC_SIDETONE:
444 select = &(max98090->sidetone);
445 break;
446 default:
447 return -EINVAL;
448 }
449
450 val = (val >> mc->shift) & mask;
451
452 if (val >= 1) {
453 /* If on, return the volume */
454 val = val - 1;
455 *select = val;
456 } else {
457 /* If off, return last stored value */
458 val = *select;
459 }
460
461 ucontrol->value.integer.value[0] = val;
462 return 0;
463 }
464
465 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
466 struct snd_ctl_elem_value *ucontrol)
467 {
468 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
469 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
470 struct soc_mixer_control *mc =
471 (struct soc_mixer_control *)kcontrol->private_value;
472 unsigned int mask = (1 << fls(mc->max)) - 1;
473 unsigned int sel = ucontrol->value.integer.value[0];
474 unsigned int val = snd_soc_read(codec, mc->reg);
475 unsigned int *select;
476
477 switch (mc->reg) {
478 case M98090_REG_MIC1_INPUT_LEVEL:
479 select = &(max98090->pa1en);
480 break;
481 case M98090_REG_MIC2_INPUT_LEVEL:
482 select = &(max98090->pa2en);
483 break;
484 case M98090_REG_ADC_SIDETONE:
485 select = &(max98090->sidetone);
486 break;
487 default:
488 return -EINVAL;
489 }
490
491 val = (val >> mc->shift) & mask;
492
493 *select = sel;
494
495 /* Setting a volume is only valid if it is already On */
496 if (val >= 1) {
497 sel = sel + 1;
498 } else {
499 /* Write what was already there */
500 sel = val;
501 }
502
503 snd_soc_update_bits(codec, mc->reg,
504 mask << mc->shift,
505 sel << mc->shift);
506
507 return 0;
508 }
509
510 static const char *max98090_perf_pwr_text[] =
511 { "High Performance", "Low Power" };
512 static const char *max98090_pwr_perf_text[] =
513 { "Low Power", "High Performance" };
514
515 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
516 M98090_REG_BIAS_CONTROL,
517 M98090_VCM_MODE_SHIFT,
518 max98090_pwr_perf_text);
519
520 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
521
522 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
523 M98090_REG_ADC_CONTROL,
524 M98090_OSR128_SHIFT,
525 max98090_osr128_text);
526
527 static const char *max98090_mode_text[] = { "Voice", "Music" };
528
529 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
530 M98090_REG_FILTER_CONFIG,
531 M98090_MODE_SHIFT,
532 max98090_mode_text);
533
534 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
535 M98090_REG_FILTER_CONFIG,
536 M98090_FLT_DMIC34MODE_SHIFT,
537 max98090_mode_text);
538
539 static const char *max98090_drcatk_text[] =
540 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
541
542 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
543 M98090_REG_DRC_TIMING,
544 M98090_DRCATK_SHIFT,
545 max98090_drcatk_text);
546
547 static const char *max98090_drcrls_text[] =
548 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
549
550 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
551 M98090_REG_DRC_TIMING,
552 M98090_DRCRLS_SHIFT,
553 max98090_drcrls_text);
554
555 static const char *max98090_alccmp_text[] =
556 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
557
558 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
559 M98090_REG_DRC_COMPRESSOR,
560 M98090_DRCCMP_SHIFT,
561 max98090_alccmp_text);
562
563 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
564
565 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
566 M98090_REG_DRC_EXPANDER,
567 M98090_DRCEXP_SHIFT,
568 max98090_drcexp_text);
569
570 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
571 M98090_REG_DAC_CONTROL,
572 M98090_PERFMODE_SHIFT,
573 max98090_perf_pwr_text);
574
575 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
576 M98090_REG_DAC_CONTROL,
577 M98090_DACHP_SHIFT,
578 max98090_pwr_perf_text);
579
580 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
581 M98090_REG_ADC_CONTROL,
582 M98090_ADCHP_SHIFT,
583 max98090_pwr_perf_text);
584
585 static const struct snd_kcontrol_new max98090_snd_controls[] = {
586 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
587
588 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
589 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
590
591 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
592 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
593 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
594 max98090_put_enab_tlv, max98090_micboost_tlv),
595
596 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
597 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
598 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
599 max98090_put_enab_tlv, max98090_micboost_tlv),
600
601 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
602 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
603 max98090_mic_tlv),
604
605 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
606 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
607 max98090_mic_tlv),
608
609 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
610 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
611 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
612
613 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
614 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
615 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
616
617 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
618 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
619 max98090_line_tlv),
620
621 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
622 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
623 max98090_line_tlv),
624
625 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
626 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
627 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
628 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
629
630 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
631 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
632 max98090_avg_tlv),
633 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
634 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
635 max98090_avg_tlv),
636
637 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
638 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
639 max98090_av_tlv),
640 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
641 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
642 max98090_av_tlv),
643
644 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
645 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
646 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
647 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
648
649 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
650 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
651 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
652 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
653 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
654 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
655 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
656 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
657 SOC_ENUM("Filter Mode", max98090_mode_enum),
658 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
659 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
660 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
661 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
662 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
663 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
664 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
665 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
666 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
667 max98090_put_enab_tlv, max98090_micboost_tlv),
668 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
669 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
670 max98090_dvg_tlv),
671 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
672 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
673 max98090_dv_tlv),
674 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
675 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
676 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
677 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
678 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
679 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
680 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
681 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
682 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
683 1),
684 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
685 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
686 max98090_dv_tlv),
687
688 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
689 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
690 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
691 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
692 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
693 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
694 max98090_alcmakeup_tlv),
695 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
696 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
697 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
698 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
699 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
700 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
701 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
702 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
703
704 SOC_ENUM("DAC HP Playback Performance Mode",
705 max98090_dac_perfmode_enum),
706 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
707
708 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
709 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
710 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
711 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
712 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
713 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
714
715 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
716 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
717 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
718 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
719 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
720 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
721
722 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
723 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
724 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
725 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
726 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
727 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
728
729 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
730 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
731 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
732
733 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
734 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
735 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
736 0, max98090_spk_tlv),
737
738 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
739 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
740 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
741
742 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
743 M98090_HPLM_SHIFT, 1, 1),
744 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
745 M98090_HPRM_SHIFT, 1, 1),
746
747 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
748 M98090_SPLM_SHIFT, 1, 1),
749 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
750 M98090_SPRM_SHIFT, 1, 1),
751
752 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
753 M98090_RCVLM_SHIFT, 1, 1),
754 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
755 M98090_RCVRM_SHIFT, 1, 1),
756
757 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
758 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
759 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
760 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
761 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
762 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
763
764 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
765 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
766 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
767 };
768
769 static const struct snd_kcontrol_new max98091_snd_controls[] = {
770
771 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
772 M98090_DMIC34_ZEROPAD_SHIFT,
773 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
774
775 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
776 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
777 M98090_FLT_DMIC34HPF_SHIFT,
778 M98090_FLT_DMIC34HPF_NUM - 1, 0),
779
780 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
781 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
782 max98090_avg_tlv),
783 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
784 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
785 max98090_avg_tlv),
786
787 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
788 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
789 max98090_av_tlv),
790 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
791 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
792 max98090_av_tlv),
793
794 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
795 M98090_REG_DMIC34_BIQUAD_BASE, 15),
796 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
797 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
798
799 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
800 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
801 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
802 };
803
804 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806 {
807 struct snd_soc_codec *codec = w->codec;
808 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
809
810 unsigned int val = snd_soc_read(codec, w->reg);
811
812 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
813 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
814 else
815 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
816
817
818 if (val >= 1) {
819 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
820 max98090->pa1en = val - 1; /* Update for volatile */
821 } else {
822 max98090->pa2en = val - 1; /* Update for volatile */
823 }
824 }
825
826 switch (event) {
827 case SND_SOC_DAPM_POST_PMU:
828 /* If turning on, set to most recently selected volume */
829 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
830 val = max98090->pa1en + 1;
831 else
832 val = max98090->pa2en + 1;
833 break;
834 case SND_SOC_DAPM_POST_PMD:
835 /* If turning off, turn off */
836 val = 0;
837 break;
838 default:
839 return -EINVAL;
840 }
841
842 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
843 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
844 val << M98090_MIC_PA1EN_SHIFT);
845 else
846 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
847 val << M98090_MIC_PA2EN_SHIFT);
848
849 return 0;
850 }
851
852 static const char *mic1_mux_text[] = { "IN12", "IN56" };
853
854 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
855 M98090_REG_INPUT_MODE,
856 M98090_EXTMIC1_SHIFT,
857 mic1_mux_text);
858
859 static const struct snd_kcontrol_new max98090_mic1_mux =
860 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
861
862 static const char *mic2_mux_text[] = { "IN34", "IN56" };
863
864 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
865 M98090_REG_INPUT_MODE,
866 M98090_EXTMIC2_SHIFT,
867 mic2_mux_text);
868
869 static const struct snd_kcontrol_new max98090_mic2_mux =
870 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
871
872 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
873
874 static SOC_ENUM_SINGLE_EXT_DECL(dmic_mux_enum, dmic_mux_text);
875
876 static const struct snd_kcontrol_new max98090_dmic_mux =
877 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum);
878
879 static const char *max98090_micpre_text[] = { "Off", "On" };
880
881 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
882 M98090_REG_MIC1_INPUT_LEVEL,
883 M98090_MIC_PA1EN_SHIFT,
884 max98090_micpre_text);
885
886 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
887 M98090_REG_MIC2_INPUT_LEVEL,
888 M98090_MIC_PA2EN_SHIFT,
889 max98090_micpre_text);
890
891 /* LINEA mixer switch */
892 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
893 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
894 M98090_IN1SEEN_SHIFT, 1, 0),
895 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
896 M98090_IN3SEEN_SHIFT, 1, 0),
897 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
898 M98090_IN5SEEN_SHIFT, 1, 0),
899 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
900 M98090_IN34DIFF_SHIFT, 1, 0),
901 };
902
903 /* LINEB mixer switch */
904 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
905 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
906 M98090_IN2SEEN_SHIFT, 1, 0),
907 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
908 M98090_IN4SEEN_SHIFT, 1, 0),
909 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
910 M98090_IN6SEEN_SHIFT, 1, 0),
911 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
912 M98090_IN56DIFF_SHIFT, 1, 0),
913 };
914
915 /* Left ADC mixer switch */
916 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
917 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
918 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
919 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
920 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
921 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
922 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
923 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
924 M98090_MIXADL_LINEA_SHIFT, 1, 0),
925 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
926 M98090_MIXADL_LINEB_SHIFT, 1, 0),
927 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
928 M98090_MIXADL_MIC1_SHIFT, 1, 0),
929 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
930 M98090_MIXADL_MIC2_SHIFT, 1, 0),
931 };
932
933 /* Right ADC mixer switch */
934 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
935 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
936 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
937 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
938 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
939 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
940 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
941 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
942 M98090_MIXADR_LINEA_SHIFT, 1, 0),
943 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
944 M98090_MIXADR_LINEB_SHIFT, 1, 0),
945 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
946 M98090_MIXADR_MIC1_SHIFT, 1, 0),
947 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
948 M98090_MIXADR_MIC2_SHIFT, 1, 0),
949 };
950
951 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
952
953 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
954 M98090_REG_IO_CONFIGURATION,
955 M98090_LTEN_SHIFT,
956 lten_mux_text);
957
958 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
959 M98090_REG_IO_CONFIGURATION,
960 M98090_LTEN_SHIFT,
961 lten_mux_text);
962
963 static const struct snd_kcontrol_new max98090_ltenl_mux =
964 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
965
966 static const struct snd_kcontrol_new max98090_ltenr_mux =
967 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
968
969 static const char *lben_mux_text[] = { "Normal", "Loopback" };
970
971 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
972 M98090_REG_IO_CONFIGURATION,
973 M98090_LBEN_SHIFT,
974 lben_mux_text);
975
976 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
977 M98090_REG_IO_CONFIGURATION,
978 M98090_LBEN_SHIFT,
979 lben_mux_text);
980
981 static const struct snd_kcontrol_new max98090_lbenl_mux =
982 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
983
984 static const struct snd_kcontrol_new max98090_lbenr_mux =
985 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
986
987 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
988
989 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
990
991 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
992 M98090_REG_ADC_SIDETONE,
993 M98090_DSTSL_SHIFT,
994 stenl_mux_text);
995
996 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
997 M98090_REG_ADC_SIDETONE,
998 M98090_DSTSR_SHIFT,
999 stenr_mux_text);
1000
1001 static const struct snd_kcontrol_new max98090_stenl_mux =
1002 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1003
1004 static const struct snd_kcontrol_new max98090_stenr_mux =
1005 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1006
1007 /* Left speaker mixer switch */
1008 static const struct
1009 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1010 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1011 M98090_MIXSPL_DACL_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1013 M98090_MIXSPL_DACR_SHIFT, 1, 0),
1014 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1015 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1017 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1019 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1021 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1022 };
1023
1024 /* Right speaker mixer switch */
1025 static const struct
1026 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1027 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1028 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1029 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1030 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1031 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1032 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1033 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1034 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1035 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1036 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1037 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1038 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1039 };
1040
1041 /* Left headphone mixer switch */
1042 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1043 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1044 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1045 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1046 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1047 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1048 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1049 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1050 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1051 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1052 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1053 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1054 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1055 };
1056
1057 /* Right headphone mixer switch */
1058 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1059 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1060 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1061 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1062 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1063 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1064 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1065 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1066 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1067 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1068 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1069 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1070 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1071 };
1072
1073 /* Left receiver mixer switch */
1074 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1075 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1076 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1077 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1078 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1079 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1080 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1081 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1082 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1083 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1084 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1085 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1086 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1087 };
1088
1089 /* Right receiver mixer switch */
1090 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1091 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1092 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1093 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1094 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1095 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1096 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1097 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1098 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1099 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1100 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1101 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1102 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1103 };
1104
1105 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1106
1107 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1108 M98090_REG_LOUTR_MIXER,
1109 M98090_LINMOD_SHIFT,
1110 linmod_mux_text);
1111
1112 static const struct snd_kcontrol_new max98090_linmod_mux =
1113 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1114
1115 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1116
1117 /*
1118 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1119 */
1120 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1121 M98090_REG_HP_CONTROL,
1122 M98090_MIXHPLSEL_SHIFT,
1123 mixhpsel_mux_text);
1124
1125 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1126 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1127
1128 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1129 M98090_REG_HP_CONTROL,
1130 M98090_MIXHPRSEL_SHIFT,
1131 mixhpsel_mux_text);
1132
1133 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1134 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1135
1136 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1137
1138 SND_SOC_DAPM_INPUT("MIC1"),
1139 SND_SOC_DAPM_INPUT("MIC2"),
1140 SND_SOC_DAPM_INPUT("DMICL"),
1141 SND_SOC_DAPM_INPUT("DMICR"),
1142 SND_SOC_DAPM_INPUT("IN1"),
1143 SND_SOC_DAPM_INPUT("IN2"),
1144 SND_SOC_DAPM_INPUT("IN3"),
1145 SND_SOC_DAPM_INPUT("IN4"),
1146 SND_SOC_DAPM_INPUT("IN5"),
1147 SND_SOC_DAPM_INPUT("IN6"),
1148 SND_SOC_DAPM_INPUT("IN12"),
1149 SND_SOC_DAPM_INPUT("IN34"),
1150 SND_SOC_DAPM_INPUT("IN56"),
1151
1152 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1153 M98090_MBEN_SHIFT, 0, NULL, 0),
1154 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1155 M98090_SHDNN_SHIFT, 0, NULL, 0),
1156 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1157 M98090_SDIEN_SHIFT, 0, NULL, 0),
1158 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1159 M98090_SDOEN_SHIFT, 0, NULL, 0),
1160 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1161 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1162 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1163 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1164 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1165 M98090_AHPF_SHIFT, 0, NULL, 0),
1166
1167 /*
1168 * Note: Sysclk and misc power supplies are taken care of by SHDN
1169 */
1170
1171 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1172 0, 0, &max98090_mic1_mux),
1173
1174 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1175 0, 0, &max98090_mic2_mux),
1176
1177 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM,
1178 0, 0, &max98090_dmic_mux),
1179
1180 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1181 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1182 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1183
1184 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1185 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1186 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1187
1188 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1189 &max98090_linea_mixer_controls[0],
1190 ARRAY_SIZE(max98090_linea_mixer_controls)),
1191
1192 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1193 &max98090_lineb_mixer_controls[0],
1194 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1195
1196 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1197 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1198 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1199 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1200
1201 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1202 &max98090_left_adc_mixer_controls[0],
1203 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1204
1205 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1206 &max98090_right_adc_mixer_controls[0],
1207 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1208
1209 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1210 M98090_ADLEN_SHIFT, 0),
1211 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1212 M98090_ADREN_SHIFT, 0),
1213
1214 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1215 SND_SOC_NOPM, 0, 0),
1216 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1217 SND_SOC_NOPM, 0, 0),
1218
1219 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1220 0, 0, &max98090_lbenl_mux),
1221
1222 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1223 0, 0, &max98090_lbenr_mux),
1224
1225 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1226 0, 0, &max98090_ltenl_mux),
1227
1228 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1229 0, 0, &max98090_ltenr_mux),
1230
1231 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1232 0, 0, &max98090_stenl_mux),
1233
1234 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1235 0, 0, &max98090_stenr_mux),
1236
1237 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1238 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1239
1240 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1241 M98090_DALEN_SHIFT, 0),
1242 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1243 M98090_DAREN_SHIFT, 0),
1244
1245 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1246 &max98090_left_hp_mixer_controls[0],
1247 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1248
1249 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1250 &max98090_right_hp_mixer_controls[0],
1251 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1252
1253 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1254 &max98090_left_speaker_mixer_controls[0],
1255 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1256
1257 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1258 &max98090_right_speaker_mixer_controls[0],
1259 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1260
1261 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1262 &max98090_left_rcv_mixer_controls[0],
1263 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1264
1265 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1266 &max98090_right_rcv_mixer_controls[0],
1267 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1268
1269 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1270 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1271
1272 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1273 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1274
1275 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1276 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1277
1278 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1279 M98090_HPLEN_SHIFT, 0, NULL, 0),
1280 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1281 M98090_HPREN_SHIFT, 0, NULL, 0),
1282
1283 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1284 M98090_SPLEN_SHIFT, 0, NULL, 0),
1285 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1286 M98090_SPREN_SHIFT, 0, NULL, 0),
1287
1288 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1289 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1290 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1291 M98090_RCVREN_SHIFT, 0, NULL, 0),
1292
1293 SND_SOC_DAPM_OUTPUT("HPL"),
1294 SND_SOC_DAPM_OUTPUT("HPR"),
1295 SND_SOC_DAPM_OUTPUT("SPKL"),
1296 SND_SOC_DAPM_OUTPUT("SPKR"),
1297 SND_SOC_DAPM_OUTPUT("RCVL"),
1298 SND_SOC_DAPM_OUTPUT("RCVR"),
1299 };
1300
1301 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1302
1303 SND_SOC_DAPM_INPUT("DMIC3"),
1304 SND_SOC_DAPM_INPUT("DMIC4"),
1305
1306 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1307 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1308 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1309 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1310 };
1311
1312 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1313
1314 {"MIC1 Input", NULL, "MIC1"},
1315 {"MIC2 Input", NULL, "MIC2"},
1316
1317 {"DMICL", NULL, "DMICL_ENA"},
1318 {"DMICR", NULL, "DMICR_ENA"},
1319 {"DMICL", NULL, "AHPF"},
1320 {"DMICR", NULL, "AHPF"},
1321
1322 /* MIC1 input mux */
1323 {"MIC1 Mux", "IN12", "IN12"},
1324 {"MIC1 Mux", "IN56", "IN56"},
1325
1326 /* MIC2 input mux */
1327 {"MIC2 Mux", "IN34", "IN34"},
1328 {"MIC2 Mux", "IN56", "IN56"},
1329
1330 {"MIC1 Input", NULL, "MIC1 Mux"},
1331 {"MIC2 Input", NULL, "MIC2 Mux"},
1332
1333 /* Left ADC input mixer */
1334 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1335 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1336 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1337 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1338 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1339 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1340 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1341
1342 /* Right ADC input mixer */
1343 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1344 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1345 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1346 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1347 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1348 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1349 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1350
1351 /* Line A input mixer */
1352 {"LINEA Mixer", "IN1 Switch", "IN1"},
1353 {"LINEA Mixer", "IN3 Switch", "IN3"},
1354 {"LINEA Mixer", "IN5 Switch", "IN5"},
1355 {"LINEA Mixer", "IN34 Switch", "IN34"},
1356
1357 /* Line B input mixer */
1358 {"LINEB Mixer", "IN2 Switch", "IN2"},
1359 {"LINEB Mixer", "IN4 Switch", "IN4"},
1360 {"LINEB Mixer", "IN6 Switch", "IN6"},
1361 {"LINEB Mixer", "IN56 Switch", "IN56"},
1362
1363 {"LINEA Input", NULL, "LINEA Mixer"},
1364 {"LINEB Input", NULL, "LINEB Mixer"},
1365
1366 /* Inputs */
1367 {"ADCL", NULL, "Left ADC Mixer"},
1368 {"ADCR", NULL, "Right ADC Mixer"},
1369 {"ADCL", NULL, "SHDN"},
1370 {"ADCR", NULL, "SHDN"},
1371
1372 {"DMIC Mux", "ADC", "ADCL"},
1373 {"DMIC Mux", "ADC", "ADCR"},
1374 {"DMIC Mux", "DMIC", "DMICL"},
1375 {"DMIC Mux", "DMIC", "DMICR"},
1376
1377 {"LBENL Mux", "Normal", "DMIC Mux"},
1378 {"LBENL Mux", "Loopback", "LTENL Mux"},
1379 {"LBENR Mux", "Normal", "DMIC Mux"},
1380 {"LBENR Mux", "Loopback", "LTENR Mux"},
1381
1382 {"AIFOUTL", NULL, "LBENL Mux"},
1383 {"AIFOUTR", NULL, "LBENR Mux"},
1384 {"AIFOUTL", NULL, "SHDN"},
1385 {"AIFOUTR", NULL, "SHDN"},
1386 {"AIFOUTL", NULL, "SDOEN"},
1387 {"AIFOUTR", NULL, "SDOEN"},
1388
1389 {"LTENL Mux", "Normal", "AIFINL"},
1390 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1391 {"LTENR Mux", "Normal", "AIFINR"},
1392 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1393
1394 {"DACL", NULL, "LTENL Mux"},
1395 {"DACR", NULL, "LTENR Mux"},
1396
1397 {"STENL Mux", "Sidetone Left", "ADCL"},
1398 {"STENL Mux", "Sidetone Left", "DMICL"},
1399 {"STENR Mux", "Sidetone Right", "ADCR"},
1400 {"STENR Mux", "Sidetone Right", "DMICR"},
1401 {"DACL", "NULL", "STENL Mux"},
1402 {"DACR", "NULL", "STENL Mux"},
1403
1404 {"AIFINL", NULL, "SHDN"},
1405 {"AIFINR", NULL, "SHDN"},
1406 {"AIFINL", NULL, "SDIEN"},
1407 {"AIFINR", NULL, "SDIEN"},
1408 {"DACL", NULL, "SHDN"},
1409 {"DACR", NULL, "SHDN"},
1410
1411 /* Left headphone output mixer */
1412 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1413 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1414 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1415 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1416 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1417 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1418
1419 /* Right headphone output mixer */
1420 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1421 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1422 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1423 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1424 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1425 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1426
1427 /* Left speaker output mixer */
1428 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1429 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1430 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1431 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1432 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1433 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1434
1435 /* Right speaker output mixer */
1436 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1437 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1438 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1439 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1440 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1441 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1442
1443 /* Left Receiver output mixer */
1444 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1445 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1446 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1447 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1448 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1449 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1450
1451 /* Right Receiver output mixer */
1452 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1453 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1454 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1455 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1456 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1457 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1458
1459 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1460
1461 /*
1462 * Disable this for lowest power if bypassing
1463 * the DAC with an analog signal
1464 */
1465 {"HP Left Out", NULL, "DACL"},
1466 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1467
1468 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1469
1470 /*
1471 * Disable this for lowest power if bypassing
1472 * the DAC with an analog signal
1473 */
1474 {"HP Right Out", NULL, "DACR"},
1475 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1476
1477 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1478 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1479 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1480
1481 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1482 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1483 {"RCV Right Out", NULL, "LINMOD Mux"},
1484
1485 {"HPL", NULL, "HP Left Out"},
1486 {"HPR", NULL, "HP Right Out"},
1487 {"SPKL", NULL, "SPK Left Out"},
1488 {"SPKR", NULL, "SPK Right Out"},
1489 {"RCVL", NULL, "RCV Left Out"},
1490 {"RCVR", NULL, "RCV Right Out"},
1491
1492 };
1493
1494 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1495
1496 /* DMIC inputs */
1497 {"DMIC3", NULL, "DMIC3_ENA"},
1498 {"DMIC4", NULL, "DMIC4_ENA"},
1499 {"DMIC3", NULL, "AHPF"},
1500 {"DMIC4", NULL, "AHPF"},
1501
1502 };
1503
1504 static int max98090_add_widgets(struct snd_soc_codec *codec)
1505 {
1506 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1507 struct snd_soc_dapm_context *dapm = &codec->dapm;
1508
1509 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1510 ARRAY_SIZE(max98090_snd_controls));
1511
1512 if (max98090->devtype == MAX98091) {
1513 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1514 ARRAY_SIZE(max98091_snd_controls));
1515 }
1516
1517 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1518 ARRAY_SIZE(max98090_dapm_widgets));
1519
1520 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1521 ARRAY_SIZE(max98090_dapm_routes));
1522
1523 if (max98090->devtype == MAX98091) {
1524 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1525 ARRAY_SIZE(max98091_dapm_widgets));
1526
1527 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1528 ARRAY_SIZE(max98091_dapm_routes));
1529
1530 }
1531
1532 return 0;
1533 }
1534
1535 static const int pclk_rates[] = {
1536 12000000, 12000000, 13000000, 13000000,
1537 16000000, 16000000, 19200000, 19200000
1538 };
1539
1540 static const int lrclk_rates[] = {
1541 8000, 16000, 8000, 16000,
1542 8000, 16000, 8000, 16000
1543 };
1544
1545 static const int user_pclk_rates[] = {
1546 13000000, 13000000
1547 };
1548
1549 static const int user_lrclk_rates[] = {
1550 44100, 48000
1551 };
1552
1553 static const unsigned long long ni_value[] = {
1554 3528, 768
1555 };
1556
1557 static const unsigned long long mi_value[] = {
1558 8125, 1625
1559 };
1560
1561 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1562 {
1563 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1564 unsigned long long ni;
1565 int i;
1566
1567 if (!max98090->sysclk) {
1568 dev_err(codec->dev, "No SYSCLK configured\n");
1569 return;
1570 }
1571
1572 if (!max98090->bclk || !max98090->lrclk) {
1573 dev_err(codec->dev, "No audio clocks configured\n");
1574 return;
1575 }
1576
1577 /* Skip configuration when operating as slave */
1578 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1579 M98090_MAS_MASK)) {
1580 return;
1581 }
1582
1583 /* Check for supported PCLK to LRCLK ratios */
1584 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1585 if ((pclk_rates[i] == max98090->sysclk) &&
1586 (lrclk_rates[i] == max98090->lrclk)) {
1587 dev_dbg(codec->dev,
1588 "Found supported PCLK to LRCLK rates 0x%x\n",
1589 i + 0x8);
1590
1591 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1592 M98090_FREQ_MASK,
1593 (i + 0x8) << M98090_FREQ_SHIFT);
1594 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1595 M98090_USE_M1_MASK, 0);
1596 return;
1597 }
1598 }
1599
1600 /* Check for user calculated MI and NI ratios */
1601 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1602 if ((user_pclk_rates[i] == max98090->sysclk) &&
1603 (user_lrclk_rates[i] == max98090->lrclk)) {
1604 dev_dbg(codec->dev,
1605 "Found user supported PCLK to LRCLK rates\n");
1606 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1607 i, ni_value[i], mi_value[i]);
1608
1609 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1610 M98090_FREQ_MASK, 0);
1611 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1612 M98090_USE_M1_MASK,
1613 1 << M98090_USE_M1_SHIFT);
1614
1615 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1616 (ni_value[i] >> 8) & 0x7F);
1617 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1618 ni_value[i] & 0xFF);
1619 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1620 (mi_value[i] >> 8) & 0x7F);
1621 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1622 mi_value[i] & 0xFF);
1623
1624 return;
1625 }
1626 }
1627
1628 /*
1629 * Calculate based on MI = 65536 (not as good as either method above)
1630 */
1631 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1632 M98090_FREQ_MASK, 0);
1633 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1634 M98090_USE_M1_MASK, 0);
1635
1636 /*
1637 * Configure NI when operating as master
1638 * Note: There is a small, but significant audio quality improvement
1639 * by calculating ni and mi.
1640 */
1641 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1642 * (unsigned long long int)max98090->lrclk;
1643 do_div(ni, (unsigned long long int)max98090->sysclk);
1644 dev_info(codec->dev, "No better method found\n");
1645 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1646 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1647 (ni >> 8) & 0x7F);
1648 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1649 }
1650
1651 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1652 unsigned int fmt)
1653 {
1654 struct snd_soc_codec *codec = codec_dai->codec;
1655 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1656 struct max98090_cdata *cdata;
1657 u8 regval;
1658
1659 max98090->dai_fmt = fmt;
1660 cdata = &max98090->dai[0];
1661
1662 if (fmt != cdata->fmt) {
1663 cdata->fmt = fmt;
1664
1665 regval = 0;
1666 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1667 case SND_SOC_DAIFMT_CBS_CFS:
1668 /* Set to slave mode PLL - MAS mode off */
1669 snd_soc_write(codec,
1670 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1671 snd_soc_write(codec,
1672 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1673 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1674 M98090_USE_M1_MASK, 0);
1675 break;
1676 case SND_SOC_DAIFMT_CBM_CFM:
1677 /* Set to master mode */
1678 if (max98090->tdm_slots == 4) {
1679 /* TDM */
1680 regval |= M98090_MAS_MASK |
1681 M98090_BSEL_64;
1682 } else if (max98090->tdm_slots == 3) {
1683 /* TDM */
1684 regval |= M98090_MAS_MASK |
1685 M98090_BSEL_48;
1686 } else {
1687 /* Few TDM slots, or No TDM */
1688 regval |= M98090_MAS_MASK |
1689 M98090_BSEL_32;
1690 }
1691 break;
1692 case SND_SOC_DAIFMT_CBS_CFM:
1693 case SND_SOC_DAIFMT_CBM_CFS:
1694 default:
1695 dev_err(codec->dev, "DAI clock mode unsupported");
1696 return -EINVAL;
1697 }
1698 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1699
1700 regval = 0;
1701 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1702 case SND_SOC_DAIFMT_I2S:
1703 regval |= M98090_DLY_MASK;
1704 break;
1705 case SND_SOC_DAIFMT_LEFT_J:
1706 break;
1707 case SND_SOC_DAIFMT_RIGHT_J:
1708 regval |= M98090_RJ_MASK;
1709 break;
1710 case SND_SOC_DAIFMT_DSP_A:
1711 /* Not supported mode */
1712 default:
1713 dev_err(codec->dev, "DAI format unsupported");
1714 return -EINVAL;
1715 }
1716
1717 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1718 case SND_SOC_DAIFMT_NB_NF:
1719 break;
1720 case SND_SOC_DAIFMT_NB_IF:
1721 regval |= M98090_WCI_MASK;
1722 break;
1723 case SND_SOC_DAIFMT_IB_NF:
1724 regval |= M98090_BCI_MASK;
1725 break;
1726 case SND_SOC_DAIFMT_IB_IF:
1727 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1728 break;
1729 default:
1730 dev_err(codec->dev, "DAI invert mode unsupported");
1731 return -EINVAL;
1732 }
1733
1734 /*
1735 * This accommodates an inverted logic in the MAX98090 chip
1736 * for Bit Clock Invert (BCI). The inverted logic is only
1737 * seen for the case of TDM mode. The remaining cases have
1738 * normal logic.
1739 */
1740 if (max98090->tdm_slots > 1)
1741 regval ^= M98090_BCI_MASK;
1742
1743 snd_soc_write(codec,
1744 M98090_REG_INTERFACE_FORMAT, regval);
1745 }
1746
1747 return 0;
1748 }
1749
1750 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1751 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1752 {
1753 struct snd_soc_codec *codec = codec_dai->codec;
1754 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1755 struct max98090_cdata *cdata;
1756 cdata = &max98090->dai[0];
1757
1758 if (slots < 0 || slots > 4)
1759 return -EINVAL;
1760
1761 max98090->tdm_slots = slots;
1762 max98090->tdm_width = slot_width;
1763
1764 if (max98090->tdm_slots > 1) {
1765 /* SLOTL SLOTR SLOTDLY */
1766 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1767 0 << M98090_TDM_SLOTL_SHIFT |
1768 1 << M98090_TDM_SLOTR_SHIFT |
1769 0 << M98090_TDM_SLOTDLY_SHIFT);
1770
1771 /* FSW TDM */
1772 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1773 M98090_TDM_MASK,
1774 M98090_TDM_MASK);
1775 }
1776
1777 /*
1778 * Normally advisable to set TDM first, but this permits either order
1779 */
1780 cdata->fmt = 0;
1781 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1782
1783 return 0;
1784 }
1785
1786 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1787 enum snd_soc_bias_level level)
1788 {
1789 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1790 int ret;
1791
1792 switch (level) {
1793 case SND_SOC_BIAS_ON:
1794 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1795 ret = regcache_sync(max98090->regmap);
1796
1797 if (ret != 0) {
1798 dev_err(codec->dev,
1799 "Failed to sync cache: %d\n", ret);
1800 return ret;
1801 }
1802 }
1803
1804 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1805 /*
1806 * Set to normal bias level.
1807 */
1808 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1809 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1810 }
1811 break;
1812
1813 case SND_SOC_BIAS_PREPARE:
1814 break;
1815
1816 case SND_SOC_BIAS_STANDBY:
1817 case SND_SOC_BIAS_OFF:
1818 /* Set internal pull-up to lowest power mode */
1819 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1820 M98090_JDWK_MASK, M98090_JDWK_MASK);
1821 regcache_mark_dirty(max98090->regmap);
1822 break;
1823 }
1824 codec->dapm.bias_level = level;
1825 return 0;
1826 }
1827
1828 static const int comp_pclk_rates[] = {
1829 11289600, 12288000, 12000000, 13000000, 19200000
1830 };
1831
1832 static const int dmic_micclk[] = {
1833 2, 2, 2, 2, 4, 2
1834 };
1835
1836 static const int comp_lrclk_rates[] = {
1837 8000, 16000, 32000, 44100, 48000, 96000
1838 };
1839
1840 static const int dmic_comp[6][6] = {
1841 {7, 8, 3, 3, 3, 3},
1842 {7, 8, 3, 3, 3, 3},
1843 {7, 8, 3, 3, 3, 3},
1844 {7, 8, 3, 1, 1, 1},
1845 {7, 8, 3, 1, 2, 2},
1846 {7, 8, 3, 3, 3, 3}
1847 };
1848
1849 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1850 struct snd_pcm_hw_params *params,
1851 struct snd_soc_dai *dai)
1852 {
1853 struct snd_soc_codec *codec = dai->codec;
1854 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1855 struct max98090_cdata *cdata;
1856 int i, j;
1857
1858 cdata = &max98090->dai[0];
1859 max98090->bclk = snd_soc_params_to_bclk(params);
1860 if (params_channels(params) == 1)
1861 max98090->bclk *= 2;
1862
1863 max98090->lrclk = params_rate(params);
1864
1865 switch (params_width(params)) {
1866 case 16:
1867 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1868 M98090_WS_MASK, 0);
1869 break;
1870 default:
1871 return -EINVAL;
1872 }
1873
1874 max98090_configure_bclk(codec);
1875
1876 cdata->rate = max98090->lrclk;
1877
1878 /* Update filter mode */
1879 if (max98090->lrclk < 24000)
1880 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1881 M98090_MODE_MASK, 0);
1882 else
1883 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1884 M98090_MODE_MASK, M98090_MODE_MASK);
1885
1886 /* Update sample rate mode */
1887 if (max98090->lrclk < 50000)
1888 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1889 M98090_DHF_MASK, 0);
1890 else
1891 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1892 M98090_DHF_MASK, M98090_DHF_MASK);
1893
1894 /* Check for supported PCLK to LRCLK ratios */
1895 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1896 if (comp_pclk_rates[j] == max98090->sysclk) {
1897 break;
1898 }
1899 }
1900
1901 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1902 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1903 comp_lrclk_rates[i + 1]) / 2) {
1904 break;
1905 }
1906 }
1907
1908 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1909 M98090_MICCLK_MASK,
1910 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1911
1912 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1913 M98090_DMIC_COMP_MASK,
1914 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1915
1916 return 0;
1917 }
1918
1919 /*
1920 * PLL / Sysclk
1921 */
1922 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1923 int clk_id, unsigned int freq, int dir)
1924 {
1925 struct snd_soc_codec *codec = dai->codec;
1926 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1927
1928 /* Requested clock frequency is already setup */
1929 if (freq == max98090->sysclk)
1930 return 0;
1931
1932 /* Setup clocks for slave mode, and using the PLL
1933 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1934 * 0x02 (when master clk is 20MHz to 40MHz)..
1935 * 0x03 (when master clk is 40MHz to 60MHz)..
1936 */
1937 if ((freq >= 10000000) && (freq < 20000000)) {
1938 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1939 M98090_PSCLK_DIV1);
1940 } else if ((freq >= 20000000) && (freq < 40000000)) {
1941 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1942 M98090_PSCLK_DIV2);
1943 } else if ((freq >= 40000000) && (freq < 60000000)) {
1944 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1945 M98090_PSCLK_DIV4);
1946 } else {
1947 dev_err(codec->dev, "Invalid master clock frequency\n");
1948 return -EINVAL;
1949 }
1950
1951 max98090->sysclk = freq;
1952
1953 max98090_configure_bclk(codec);
1954
1955 return 0;
1956 }
1957
1958 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1959 {
1960 struct snd_soc_codec *codec = codec_dai->codec;
1961 int regval;
1962
1963 regval = mute ? M98090_DVM_MASK : 0;
1964 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1965 M98090_DVM_MASK, regval);
1966
1967 return 0;
1968 }
1969
1970 static void max98090_jack_work(struct work_struct *work)
1971 {
1972 struct max98090_priv *max98090 = container_of(work,
1973 struct max98090_priv,
1974 jack_work.work);
1975 struct snd_soc_codec *codec = max98090->codec;
1976 struct snd_soc_dapm_context *dapm = &codec->dapm;
1977 int status = 0;
1978 int reg;
1979
1980 /* Read a second time */
1981 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1982
1983 /* Strong pull up allows mic detection */
1984 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1985 M98090_JDWK_MASK, 0);
1986
1987 msleep(50);
1988
1989 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1990
1991 /* Weak pull up allows only insertion detection */
1992 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1993 M98090_JDWK_MASK, M98090_JDWK_MASK);
1994 } else {
1995 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1996 }
1997
1998 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1999
2000 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2001 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2002 dev_dbg(codec->dev, "No Headset Detected\n");
2003
2004 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2005
2006 status |= 0;
2007
2008 break;
2009
2010 case 0:
2011 if (max98090->jack_state ==
2012 M98090_JACK_STATE_HEADSET) {
2013
2014 dev_dbg(codec->dev,
2015 "Headset Button Down Detected\n");
2016
2017 /*
2018 * max98090_headset_button_event(codec)
2019 * could be defined, then called here.
2020 */
2021
2022 status |= SND_JACK_HEADSET;
2023 status |= SND_JACK_BTN_0;
2024
2025 break;
2026 }
2027
2028 /* Line is reported as Headphone */
2029 /* Nokia Headset is reported as Headphone */
2030 /* Mono Headphone is reported as Headphone */
2031 dev_dbg(codec->dev, "Headphone Detected\n");
2032
2033 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2034
2035 status |= SND_JACK_HEADPHONE;
2036
2037 break;
2038
2039 case M98090_JKSNS_MASK:
2040 dev_dbg(codec->dev, "Headset Detected\n");
2041
2042 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2043
2044 status |= SND_JACK_HEADSET;
2045
2046 break;
2047
2048 default:
2049 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2050 break;
2051 }
2052
2053 snd_soc_jack_report(max98090->jack, status,
2054 SND_JACK_HEADSET | SND_JACK_BTN_0);
2055
2056 snd_soc_dapm_sync(dapm);
2057 }
2058
2059 static irqreturn_t max98090_interrupt(int irq, void *data)
2060 {
2061 struct snd_soc_codec *codec = data;
2062 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2063 int ret;
2064 unsigned int mask;
2065 unsigned int active;
2066
2067 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2068
2069 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2070
2071 if (ret != 0) {
2072 dev_err(codec->dev,
2073 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2074 ret);
2075 return IRQ_NONE;
2076 }
2077
2078 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2079
2080 if (ret != 0) {
2081 dev_err(codec->dev,
2082 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2083 ret);
2084 return IRQ_NONE;
2085 }
2086
2087 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2088 active, mask, active & mask);
2089
2090 active &= mask;
2091
2092 if (!active)
2093 return IRQ_NONE;
2094
2095 if (active & M98090_CLD_MASK)
2096 dev_err(codec->dev, "M98090_CLD_MASK\n");
2097
2098 if (active & M98090_SLD_MASK)
2099 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2100
2101 if (active & M98090_ULK_MASK)
2102 dev_err(codec->dev, "M98090_ULK_MASK\n");
2103
2104 if (active & M98090_JDET_MASK) {
2105 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2106
2107 pm_wakeup_event(codec->dev, 100);
2108
2109 queue_delayed_work(system_power_efficient_wq,
2110 &max98090->jack_work,
2111 msecs_to_jiffies(100));
2112 }
2113
2114 if (active & M98090_DRCACT_MASK)
2115 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2116
2117 if (active & M98090_DRCCLP_MASK)
2118 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2119
2120 return IRQ_HANDLED;
2121 }
2122
2123 /**
2124 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2125 *
2126 * @codec: MAX98090 codec
2127 * @jack: jack to report detection events on
2128 *
2129 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2130 * being used to bring out signals to the processor then only platform
2131 * data configuration is needed for MAX98090 and processor GPIOs should
2132 * be configured using snd_soc_jack_add_gpios() instead.
2133 *
2134 * If no jack is supplied detection will be disabled.
2135 */
2136 int max98090_mic_detect(struct snd_soc_codec *codec,
2137 struct snd_soc_jack *jack)
2138 {
2139 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2140
2141 dev_dbg(codec->dev, "max98090_mic_detect\n");
2142
2143 max98090->jack = jack;
2144 if (jack) {
2145 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2146 M98090_IJDET_MASK,
2147 1 << M98090_IJDET_SHIFT);
2148 } else {
2149 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2150 M98090_IJDET_MASK,
2151 0);
2152 }
2153
2154 /* Send an initial empty report */
2155 snd_soc_jack_report(max98090->jack, 0,
2156 SND_JACK_HEADSET | SND_JACK_BTN_0);
2157
2158 queue_delayed_work(system_power_efficient_wq,
2159 &max98090->jack_work,
2160 msecs_to_jiffies(100));
2161
2162 return 0;
2163 }
2164 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2165
2166 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2167 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2168
2169 static struct snd_soc_dai_ops max98090_dai_ops = {
2170 .set_sysclk = max98090_dai_set_sysclk,
2171 .set_fmt = max98090_dai_set_fmt,
2172 .set_tdm_slot = max98090_set_tdm_slot,
2173 .hw_params = max98090_dai_hw_params,
2174 .digital_mute = max98090_dai_digital_mute,
2175 };
2176
2177 static struct snd_soc_dai_driver max98090_dai[] = {
2178 {
2179 .name = "HiFi",
2180 .playback = {
2181 .stream_name = "HiFi Playback",
2182 .channels_min = 2,
2183 .channels_max = 2,
2184 .rates = MAX98090_RATES,
2185 .formats = MAX98090_FORMATS,
2186 },
2187 .capture = {
2188 .stream_name = "HiFi Capture",
2189 .channels_min = 1,
2190 .channels_max = 2,
2191 .rates = MAX98090_RATES,
2192 .formats = MAX98090_FORMATS,
2193 },
2194 .ops = &max98090_dai_ops,
2195 }
2196 };
2197
2198 static void max98090_handle_pdata(struct snd_soc_codec *codec)
2199 {
2200 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2201 struct max98090_pdata *pdata = max98090->pdata;
2202
2203 if (!pdata) {
2204 dev_err(codec->dev, "No platform data\n");
2205 return;
2206 }
2207
2208 }
2209
2210 static int max98090_probe(struct snd_soc_codec *codec)
2211 {
2212 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2213 struct max98090_cdata *cdata;
2214 int ret = 0;
2215
2216 dev_dbg(codec->dev, "max98090_probe\n");
2217
2218 max98090->codec = codec;
2219
2220 codec->control_data = max98090->regmap;
2221
2222 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
2223 if (ret != 0) {
2224 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2225 return ret;
2226 }
2227
2228 /* Reset the codec, the DSP core, and disable all interrupts */
2229 max98090_reset(max98090);
2230
2231 /* Initialize private data */
2232
2233 max98090->sysclk = (unsigned)-1;
2234
2235 cdata = &max98090->dai[0];
2236 cdata->rate = (unsigned)-1;
2237 cdata->fmt = (unsigned)-1;
2238
2239 max98090->lin_state = 0;
2240 max98090->pa1en = 0;
2241 max98090->pa2en = 0;
2242 max98090->extmic_mux = 0;
2243
2244 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2245 if (ret < 0) {
2246 dev_err(codec->dev, "Failed to read device revision: %d\n",
2247 ret);
2248 goto err_access;
2249 }
2250
2251 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2252 max98090->devtype = MAX98090;
2253 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2254 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2255 max98090->devtype = MAX98091;
2256 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2257 } else {
2258 max98090->devtype = MAX98090;
2259 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2260 }
2261
2262 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2263
2264 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2265
2266 /* Enable jack detection */
2267 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2268 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2269
2270 /* Register for interrupts */
2271 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2272
2273 ret = request_threaded_irq(max98090->irq, NULL,
2274 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2275 "max98090_interrupt", codec);
2276 if (ret < 0) {
2277 dev_err(codec->dev, "request_irq failed: %d\n",
2278 ret);
2279 }
2280
2281 /*
2282 * Clear any old interrupts.
2283 * An old interrupt ocurring prior to installing the ISR
2284 * can keep a new interrupt from generating a trigger.
2285 */
2286 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2287
2288 /* High Performance is default */
2289 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2290 M98090_DACHP_MASK,
2291 1 << M98090_DACHP_SHIFT);
2292 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2293 M98090_PERFMODE_MASK,
2294 0 << M98090_PERFMODE_SHIFT);
2295 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2296 M98090_ADCHP_MASK,
2297 1 << M98090_ADCHP_SHIFT);
2298
2299 /* Turn on VCM bandgap reference */
2300 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2301 M98090_VCM_MODE_MASK);
2302
2303 max98090_handle_pdata(codec);
2304
2305 max98090_add_widgets(codec);
2306
2307 err_access:
2308 return ret;
2309 }
2310
2311 static int max98090_remove(struct snd_soc_codec *codec)
2312 {
2313 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2314
2315 cancel_delayed_work_sync(&max98090->jack_work);
2316
2317 return 0;
2318 }
2319
2320 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2321 .probe = max98090_probe,
2322 .remove = max98090_remove,
2323 .set_bias_level = max98090_set_bias_level,
2324 };
2325
2326 static const struct regmap_config max98090_regmap = {
2327 .reg_bits = 8,
2328 .val_bits = 8,
2329
2330 .max_register = MAX98090_MAX_REGISTER,
2331 .reg_defaults = max98090_reg,
2332 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2333 .volatile_reg = max98090_volatile_register,
2334 .readable_reg = max98090_readable_register,
2335 .cache_type = REGCACHE_RBTREE,
2336 };
2337
2338 static int max98090_i2c_probe(struct i2c_client *i2c,
2339 const struct i2c_device_id *id)
2340 {
2341 struct max98090_priv *max98090;
2342 int ret;
2343
2344 pr_debug("max98090_i2c_probe\n");
2345
2346 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2347 GFP_KERNEL);
2348 if (max98090 == NULL)
2349 return -ENOMEM;
2350
2351 max98090->devtype = id->driver_data;
2352 i2c_set_clientdata(i2c, max98090);
2353 max98090->pdata = i2c->dev.platform_data;
2354 max98090->irq = i2c->irq;
2355
2356 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2357 if (IS_ERR(max98090->regmap)) {
2358 ret = PTR_ERR(max98090->regmap);
2359 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2360 goto err_enable;
2361 }
2362
2363 ret = snd_soc_register_codec(&i2c->dev,
2364 &soc_codec_dev_max98090, max98090_dai,
2365 ARRAY_SIZE(max98090_dai));
2366 err_enable:
2367 return ret;
2368 }
2369
2370 static int max98090_i2c_remove(struct i2c_client *client)
2371 {
2372 snd_soc_unregister_codec(&client->dev);
2373 return 0;
2374 }
2375
2376 #ifdef CONFIG_PM_RUNTIME
2377 static int max98090_runtime_resume(struct device *dev)
2378 {
2379 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2380
2381 regcache_cache_only(max98090->regmap, false);
2382
2383 regcache_sync(max98090->regmap);
2384
2385 return 0;
2386 }
2387
2388 static int max98090_runtime_suspend(struct device *dev)
2389 {
2390 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2391
2392 regcache_cache_only(max98090->regmap, true);
2393
2394 return 0;
2395 }
2396 #endif
2397
2398 static const struct dev_pm_ops max98090_pm = {
2399 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2400 max98090_runtime_resume, NULL)
2401 };
2402
2403 static const struct i2c_device_id max98090_i2c_id[] = {
2404 { "max98090", MAX98090 },
2405 { }
2406 };
2407 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2408
2409 static const struct of_device_id max98090_of_match[] = {
2410 { .compatible = "maxim,max98090", },
2411 { }
2412 };
2413 MODULE_DEVICE_TABLE(of, max98090_of_match);
2414
2415 static struct i2c_driver max98090_i2c_driver = {
2416 .driver = {
2417 .name = "max98090",
2418 .owner = THIS_MODULE,
2419 .pm = &max98090_pm,
2420 .of_match_table = of_match_ptr(max98090_of_match),
2421 },
2422 .probe = max98090_i2c_probe,
2423 .remove = max98090_i2c_remove,
2424 .id_table = max98090_i2c_id,
2425 };
2426
2427 module_i2c_driver(max98090_i2c_driver);
2428
2429 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2430 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2431 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree