drivers/staging/rtl8723au/include/rtw_io.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #ifndef _RTW_IO_H_
  17 #define _RTW_IO_H_
  18
  19 #include <osdep_service.h>
  20 #include <osdep_intf.h>
  21
  22 #include <asm/byteorder.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/list.h>
  25 /* include <linux/smp_lock.h> */
  26 #include <linux/spinlock.h>
  27 #include <asm/atomic.h>
  28
  29 #include <linux/usb.h>
  30 #include <linux/usb/ch9.h>
  31
  32 #define rtw_usb_buffer_alloc(dev, size, dma) usb_alloc_coherent((dev), (size), (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), (dma))
  33 #define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma))
  34
  35 #define NUM_IOREQ               8
  36
  37 #define MAX_PROT_SZ     (64-16)
  38
  39 #define _IOREADY                        0
  40 #define _IO_WAIT_COMPLETE   1
  41 #define _IO_WAIT_RSP        2
  42
  43 /*  IO COMMAND TYPE */
  44 #define _IOSZ_MASK_             (0x7F)
  45 #define _IO_WRITE_              BIT(7)
  46 #define _IO_FIXED_              BIT(8)
  47 #define _IO_BURST_              BIT(9)
  48 #define _IO_BYTE_               BIT(10)
  49 #define _IO_HW_                 BIT(11)
  50 #define _IO_WORD_               BIT(12)
  51 #define _IO_SYNC_               BIT(13)
  52 #define _IO_CMDMASK_    (0x1F80)
  53
  54
  55 /*
  56         For prompt mode accessing, caller shall free io_req
  57         Otherwise, io_handler will free io_req
  58 */
  59
  60
  61
  62 /*  IO STATUS TYPE */
  63 #define _IO_ERR_                BIT(2)
  64 #define _IO_SUCCESS_    BIT(1)
  65 #define _IO_DONE_               BIT(0)
  66
  67
  68 #define IO_RD32                 (_IO_SYNC_ | _IO_WORD_)
  69 #define IO_RD16                 (_IO_SYNC_ | _IO_HW_)
  70 #define IO_RD8                  (_IO_SYNC_ | _IO_BYTE_)
  71
  72 #define IO_RD32_ASYNC   (_IO_WORD_)
  73 #define IO_RD16_ASYNC   (_IO_HW_)
  74 #define IO_RD8_ASYNC    (_IO_BYTE_)
  75
  76 #define IO_WR32                 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_)
  77 #define IO_WR16                 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_)
  78 #define IO_WR8                  (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_)
  79
  80 #define IO_WR32_ASYNC   (_IO_WRITE_ | _IO_WORD_)
  81 #define IO_WR16_ASYNC   (_IO_WRITE_ | _IO_HW_)
  82 #define IO_WR8_ASYNC    (_IO_WRITE_ | _IO_BYTE_)
  83
  84 /*
  85
  86         Only Sync. burst accessing is provided.
  87
  88 */
  89
  90 #define IO_WR_BURST(x)          (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
  91 #define IO_RD_BURST(x)          (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_))
  92
  93
  94
  95 /* below is for the intf_option bit defition... */
  96
  97 #define _INTF_ASYNC_    BIT(0)  /* support async io */
  98
  99 struct intf_priv;
 100
 101 struct _io_ops
 102 {
 103         u8 (*_read8)(struct rtw_adapter *adapter, u32 addr);
 104         u16 (*_read16)(struct rtw_adapter *adapter, u32 addr);
 105         u32 (*_read32)(struct rtw_adapter *adapter, u32 addr);
 106
 107         int (*_write8)(struct rtw_adapter *adapter, u32 addr, u8 val);
 108         int (*_write16)(struct rtw_adapter *adapter, u32 addr, u16 val);
 109         int (*_write32)(struct rtw_adapter *adapter, u32 addr, u32 val);
 110         int (*_writeN)(struct rtw_adapter *adapter, u32 addr, u32 length, u8 *pdata);
 111
 112         void (*_read_mem)(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 113         void (*_write_mem)(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 114
 115         u32 (*_read_interrupt)(struct rtw_adapter *adapter, u32 addr);
 116
 117         u32 (*_read_port)(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct recv_buf *rbuf);
 118         u32 (*_write_port)(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct xmit_buf *pmem);
 119
 120         void (*_read_port_cancel)(struct rtw_adapter *adapter);
 121         void (*_write_port_cancel)(struct rtw_adapter *adapter);
 122 };
 123
 124 struct io_req {
 125         struct list_head        list;
 126         u32     addr;
 127         volatile u32    val;
 128         u32     command;
 129         u32     status;
 130         u8      *pbuf;
 131         struct semaphore        sema;
 132
 133         void (*_async_io_callback)(struct rtw_adapter *padater, struct io_req *pio_req, u8 *cnxt);
 134         u8 *cnxt;
 135 };
 136
 137 struct reg_protocol_rd {
 138
 139 #ifdef __LITTLE_ENDIAN
 140
 141         /* DW1 */
 142         u32             NumOfTrans:4;
 143         u32             Reserved1:4;
 144         u32             Reserved2:24;
 145         /* DW2 */
 146         u32             ByteCount:7;
 147         u32             WriteEnable:1;          /* 0:read, 1:write */
 148         u32             FixOrContinuous:1;      /* 0:continuous, 1: Fix */
 149         u32             BurstMode:1;
 150         u32             Byte1Access:1;
 151         u32             Byte2Access:1;
 152         u32             Byte4Access:1;
 153         u32             Reserved3:3;
 154         u32             Reserved4:16;
 155         /* DW3 */
 156         u32             BusAddress;
 157         /* DW4 */
 158         /* u32          Value; */
 159 #else
 160
 161
 162 /* DW1 */
 163         u32 Reserved1  :4;
 164         u32 NumOfTrans :4;
 165
 166         u32 Reserved2  :24;
 167
 168         /* DW2 */
 169         u32 WriteEnable : 1;
 170         u32 ByteCount :7;
 171
 172
 173         u32 Reserved3 : 3;
 174         u32 Byte4Access : 1;
 175
 176         u32 Byte2Access : 1;
 177         u32 Byte1Access : 1;
 178         u32 BurstMode :1 ;
 179         u32 FixOrContinuous : 1;
 180
 181         u32 Reserved4 : 16;
 182
 183         /* DW3 */
 184         u32             BusAddress;
 185
 186         /* DW4 */
 187         /* u32          Value; */
 188
 189 #endif
 190
 191 };
 192
 193
 194 struct reg_protocol_wt {
 195
 196
 197 #ifdef __LITTLE_ENDIAN
 198
 199         /* DW1 */
 200         u32             NumOfTrans:4;
 201         u32             Reserved1:4;
 202         u32             Reserved2:24;
 203         /* DW2 */
 204         u32             ByteCount:7;
 205         u32             WriteEnable:1;          /* 0:read, 1:write */
 206         u32             FixOrContinuous:1;      /* 0:continuous, 1: Fix */
 207         u32             BurstMode:1;
 208         u32             Byte1Access:1;
 209         u32             Byte2Access:1;
 210         u32             Byte4Access:1;
 211         u32             Reserved3:3;
 212         u32             Reserved4:16;
 213         /* DW3 */
 214         u32             BusAddress;
 215         /* DW4 */
 216         u32             Value;
 217
 218 #else
 219         /* DW1 */
 220         u32 Reserved1  :4;
 221         u32 NumOfTrans :4;
 222
 223         u32 Reserved2  :24;
 224
 225         /* DW2 */
 226         u32 WriteEnable : 1;
 227         u32 ByteCount :7;
 228
 229         u32 Reserved3 : 3;
 230         u32 Byte4Access : 1;
 231
 232         u32 Byte2Access : 1;
 233         u32 Byte1Access : 1;
 234         u32 BurstMode :1 ;
 235         u32 FixOrContinuous : 1;
 236
 237         u32 Reserved4 : 16;
 238
 239         /* DW3 */
 240         u32             BusAddress;
 241
 242         /* DW4 */
 243         u32             Value;
 244
 245 #endif
 246
 247 };
 248
 249
 250 void _rtw_attrib_read(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 251 void _rtw_attrib_write(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 252
 253 u8 _rtw_read823a(struct rtw_adapter *adapter, u32 addr);
 254 u16 _rtw_read1623a(struct rtw_adapter *adapter, u32 addr);
 255 u32 _rtw_read3223a(struct rtw_adapter *adapter, u32 addr);
 256 void _rtw_read_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 257 void _rtw_read_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct recv_buf *rbuf);
 258 void _rtw_read_port23a_cancel(struct rtw_adapter *adapter);
 259
 260 int _rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val);
 261 int _rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val);
 262 int _rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val);
 263 int _rtw_writeN23a(struct rtw_adapter *adapter, u32 addr, u32 length, u8 *pdata);
 264
 265 void _rtw_write_mem23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, u8 *pmem);
 266 u32 _rtw_write_port23a(struct rtw_adapter *adapter, u32 addr, u32 cnt, struct xmit_buf *pmem);
 267 void _rtw_write_port23a_cancel(struct rtw_adapter *adapter);
 268
 269 #ifdef DBG_IO
 270 bool match_read_sniff_ranges(u16 addr, u16 len);
 271 bool match_write_sniff_ranges(u16 addr, u16 len);
 272
 273 u8 dbg_rtw_read823a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line);
 274 u16 dbg_rtw_read1623a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line);
 275 u32 dbg_rtw_read3223a(struct rtw_adapter *adapter, u32 addr, const char *caller, const int line);
 276
 277 int dbg_rtw_write823a(struct rtw_adapter *adapter, u32 addr, u8 val, const char *caller, const int line);
 278 int dbg_rtw_write1623a(struct rtw_adapter *adapter, u32 addr, u16 val, const char *caller, const int line);
 279 int dbg_rtw_write3223a(struct rtw_adapter *adapter, u32 addr, u32 val, const char *caller, const int line);
 280 int dbg_rtw_writeN23a(struct rtw_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line);
 281
 282 #define rtw_read8(adapter, addr) dbg_rtw_read823a((adapter), (addr), __FUNCTION__, __LINE__)
 283 #define rtw_read16(adapter, addr) dbg_rtw_read1623a((adapter), (addr), __FUNCTION__, __LINE__)
 284 #define rtw_read32(adapter, addr) dbg_rtw_read3223a((adapter), (addr), __FUNCTION__, __LINE__)
 285 #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem23a((adapter), (addr), (cnt), (mem))
 286 #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port23a((adapter), (addr), (cnt), (mem))
 287 #define rtw_read_port_cancel(adapter) _rtw_read_port23a_cancel((adapter))
 288
 289 #define  rtw_write8(adapter, addr, val) dbg_rtw_write823a((adapter), (addr), (val), __FUNCTION__, __LINE__)
 290 #define  rtw_write16(adapter, addr, val) dbg_rtw_write1623a((adapter), (addr), (val), __FUNCTION__, __LINE__)
 291 #define  rtw_write32(adapter, addr, val) dbg_rtw_write3223a((adapter), (addr), (val), __FUNCTION__, __LINE__)
 292 #define  rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN23a((adapter), (addr), (length), (data), __FUNCTION__, __LINE__)
 293
 294 #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem23a((adapter), addr, cnt, mem)
 295 #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port23a(adapter, addr, cnt, mem)
 296 #define rtw_write_port_cancel(adapter) _rtw_write_port23a_cancel(adapter)
 297 #else /* DBG_IO */
 298 #define rtw_read8(adapter, addr) _rtw_read823a((adapter), (addr))
 299 #define rtw_read16(adapter, addr) _rtw_read1623a((adapter), (addr))
 300 #define rtw_read32(adapter, addr) _rtw_read3223a((adapter), (addr))
 301 #define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem23a((adapter), (addr), (cnt), (mem))
 302 #define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port23a((adapter), (addr), (cnt), (mem))
 303 #define rtw_read_port_cancel(adapter) _rtw_read_port23a_cancel((adapter))
 304
 305 #define  rtw_write8(adapter, addr, val) _rtw_write823a((adapter), (addr), (val))
 306 #define  rtw_write16(adapter, addr, val) _rtw_write1623a((adapter), (addr), (val))
 307 #define  rtw_write32(adapter, addr, val) _rtw_write3223a((adapter), (addr), (val))
 308 #define  rtw_writeN(adapter, addr, length, data) _rtw_writeN23a((adapter), (addr), (length), (data))
 309
 310 #define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem23a((adapter), (addr), (cnt), (mem))
 311 #define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port23a((adapter), (addr), (cnt), (mem))
 312 #define rtw_write_port_cancel(adapter) _rtw_write_port23a_cancel((adapter))
 313 #endif /* DBG_IO */
 314
 315 #define PlatformEFIOWrite1Byte(_a,_b,_c)                \
 316         rtw_write8(_a,_b,_c)
 317 #define PlatformEFIOWrite2Byte(_a,_b,_c)                \
 318         rtw_write16(_a,_b,_c)
 319 #define PlatformEFIOWrite4Byte(_a,_b,_c)                \
 320         rtw_write32(_a,_b,_c)
 321
 322 #define PlatformEFIORead1Byte(_a,_b)            \
 323                 rtw_read8(_a,_b)
 324 #define PlatformEFIORead2Byte(_a,_b)            \
 325                 rtw_read16(_a,_b)
 326 #define PlatformEFIORead4Byte(_a,_b)            \
 327                 rtw_read32(_a,_b)
 328
 329 #endif  /* _RTL8711_IO_H_ */