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iommu/amd: Split IOMMU Group topology walk
[linux-2.6/btrfs-unstable.git] / drivers / iommu / amd_iommu.c
blob6edbd0edcae74108ad07fd72f79a18dfafbb0881
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49
50 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
52 #define LOOP_TIMEOUT 100000
53
54 /*
55 * This bitmap is used to advertise the page sizes our hardware support
56 * to the IOMMU core, which will then use this information to split
57 * physically contiguous memory regions it is mapping into page sizes
58 * that we support.
59 *
60 * Traditionally the IOMMU core just handed us the mappings directly,
61 * after making sure the size is an order of a 4KiB page and that the
62 * mapping has natural alignment.
63 *
64 * To retain this behavior, we currently advertise that we support
65 * all page sizes that are an order of 4KiB.
66 *
67 * If at some point we'd like to utilize the IOMMU core's new behavior,
68 * we could change this to advertise the real page sizes we support.
69 */
70 #define AMD_IOMMU_PGSIZES (~0xFFFUL)
71
72 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
73
74 /* A list of preallocated protection domains */
75 static LIST_HEAD(iommu_pd_list);
76 static DEFINE_SPINLOCK(iommu_pd_list_lock);
77
78 /* List of all available dev_data structures */
79 static LIST_HEAD(dev_data_list);
80 static DEFINE_SPINLOCK(dev_data_list_lock);
81
82 LIST_HEAD(ioapic_map);
83 LIST_HEAD(hpet_map);
84
85 /*
86 * Domain for untranslated devices - only allocated
87 * if iommu=pt passed on kernel cmd line.
88 */
89 static struct protection_domain *pt_domain;
90
91 static struct iommu_ops amd_iommu_ops;
92
93 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
94 int amd_iommu_max_glx_val = -1;
95
96 static struct dma_map_ops amd_iommu_dma_ops;
97
98 /*
99 * general struct to manage commands send to an IOMMU
100 */
101 struct iommu_cmd {
102 u32 data[4];
103 };
104
105 struct kmem_cache *amd_iommu_irq_cache;
106
107 static void update_domain(struct protection_domain *domain);
108 static int __init alloc_passthrough_domain(void);
109
110 /****************************************************************************
111 *
112 * Helper functions
113 *
114 ****************************************************************************/
115
116 static struct iommu_dev_data *alloc_dev_data(u16 devid)
117 {
118 struct iommu_dev_data *dev_data;
119 unsigned long flags;
120
121 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
122 if (!dev_data)
123 return NULL;
124
125 dev_data->devid = devid;
126 atomic_set(&dev_data->bind, 0);
127
128 spin_lock_irqsave(&dev_data_list_lock, flags);
129 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
130 spin_unlock_irqrestore(&dev_data_list_lock, flags);
131
132 return dev_data;
133 }
134
135 static void free_dev_data(struct iommu_dev_data *dev_data)
136 {
137 unsigned long flags;
138
139 spin_lock_irqsave(&dev_data_list_lock, flags);
140 list_del(&dev_data->dev_data_list);
141 spin_unlock_irqrestore(&dev_data_list_lock, flags);
142
143 kfree(dev_data);
144 }
145
146 static struct iommu_dev_data *search_dev_data(u16 devid)
147 {
148 struct iommu_dev_data *dev_data;
149 unsigned long flags;
150
151 spin_lock_irqsave(&dev_data_list_lock, flags);
152 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
153 if (dev_data->devid == devid)
154 goto out_unlock;
155 }
156
157 dev_data = NULL;
158
159 out_unlock:
160 spin_unlock_irqrestore(&dev_data_list_lock, flags);
161
162 return dev_data;
163 }
164
165 static struct iommu_dev_data *find_dev_data(u16 devid)
166 {
167 struct iommu_dev_data *dev_data;
168
169 dev_data = search_dev_data(devid);
170
171 if (dev_data == NULL)
172 dev_data = alloc_dev_data(devid);
173
174 return dev_data;
175 }
176
177 static inline u16 get_device_id(struct device *dev)
178 {
179 struct pci_dev *pdev = to_pci_dev(dev);
180
181 return calc_devid(pdev->bus->number, pdev->devfn);
182 }
183
184 static struct iommu_dev_data *get_dev_data(struct device *dev)
185 {
186 return dev->archdata.iommu;
187 }
188
189 static bool pci_iommuv2_capable(struct pci_dev *pdev)
190 {
191 static const int caps[] = {
192 PCI_EXT_CAP_ID_ATS,
193 PCI_EXT_CAP_ID_PRI,
194 PCI_EXT_CAP_ID_PASID,
195 };
196 int i, pos;
197
198 for (i = 0; i < 3; ++i) {
199 pos = pci_find_ext_capability(pdev, caps[i]);
200 if (pos == 0)
201 return false;
202 }
203
204 return true;
205 }
206
207 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
208 {
209 struct iommu_dev_data *dev_data;
210
211 dev_data = get_dev_data(&pdev->dev);
212
213 return dev_data->errata & (1 << erratum) ? true : false;
214 }
215
216 /*
217 * In this function the list of preallocated protection domains is traversed to
218 * find the domain for a specific device
219 */
220 static struct dma_ops_domain *find_protection_domain(u16 devid)
221 {
222 struct dma_ops_domain *entry, *ret = NULL;
223 unsigned long flags;
224 u16 alias = amd_iommu_alias_table[devid];
225
226 if (list_empty(&iommu_pd_list))
227 return NULL;
228
229 spin_lock_irqsave(&iommu_pd_list_lock, flags);
230
231 list_for_each_entry(entry, &iommu_pd_list, list) {
232 if (entry->target_dev == devid ||
233 entry->target_dev == alias) {
234 ret = entry;
235 break;
236 }
237 }
238
239 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
240
241 return ret;
242 }
243
244 /*
245 * This function checks if the driver got a valid device from the caller to
246 * avoid dereferencing invalid pointers.
247 */
248 static bool check_device(struct device *dev)
249 {
250 u16 devid;
251
252 if (!dev || !dev->dma_mask)
253 return false;
254
255 /* No device or no PCI device */
256 if (dev->bus != &pci_bus_type)
257 return false;
258
259 devid = get_device_id(dev);
260
261 /* Out of our scope? */
262 if (devid > amd_iommu_last_bdf)
263 return false;
264
265 if (amd_iommu_rlookup_table[devid] == NULL)
266 return false;
267
268 return true;
269 }
270
271 static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
272 {
273 pci_dev_put(*from);
274 *from = to;
275 }
276
277 #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
278
279 static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
280 {
281 struct pci_dev *dma_pdev = pdev;
282
283 /* Account for quirked devices */
284 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
285
286 /*
287 * If it's a multifunction device that does not support our
288 * required ACS flags, add to the same group as function 0.
289 */
290 if (dma_pdev->multifunction &&
291 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
292 swap_pci_ref(&dma_pdev,
293 pci_get_slot(dma_pdev->bus,
294 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
295 0)));
296
297 /*
298 * Devices on the root bus go through the iommu. If that's not us,
299 * find the next upstream device and test ACS up to the root bus.
300 * Finding the next device may require skipping virtual buses.
301 */
302 while (!pci_is_root_bus(dma_pdev->bus)) {
303 struct pci_bus *bus = dma_pdev->bus;
304
305 while (!bus->self) {
306 if (!pci_is_root_bus(bus))
307 bus = bus->parent;
308 else
309 goto root_bus;
310 }
311
312 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
313 break;
314
315 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
316 }
317
318 root_bus:
319 return dma_pdev;
320 }
321
322 static int init_iommu_group(struct device *dev)
323 {
324 struct iommu_dev_data *dev_data;
325 struct iommu_group *group;
326 struct pci_dev *dma_pdev = NULL;
327 int ret;
328
329 group = iommu_group_get(dev);
330 if (group) {
331 iommu_group_put(group);
332 return 0;
333 }
334
335 dev_data = find_dev_data(get_device_id(dev));
336 if (!dev_data)
337 return -ENOMEM;
338
339 if (dev_data->alias_data) {
340 u16 alias;
341
342 alias = amd_iommu_alias_table[dev_data->devid];
343 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
344 }
345
346 if (!dma_pdev)
347 dma_pdev = pci_dev_get(to_pci_dev(dev));
348
349 dma_pdev = get_isolation_root(dma_pdev);
350 group = iommu_group_get(&dma_pdev->dev);
351 pci_dev_put(dma_pdev);
352 if (!group) {
353 group = iommu_group_alloc();
354 if (IS_ERR(group))
355 return PTR_ERR(group);
356 }
357
358 ret = iommu_group_add_device(group, dev);
359
360 iommu_group_put(group);
361
362 return ret;
363 }
364
365 static int iommu_init_device(struct device *dev)
366 {
367 struct pci_dev *pdev = to_pci_dev(dev);
368 struct iommu_dev_data *dev_data;
369 u16 alias;
370 int ret;
371
372 if (dev->archdata.iommu)
373 return 0;
374
375 dev_data = find_dev_data(get_device_id(dev));
376 if (!dev_data)
377 return -ENOMEM;
378
379 alias = amd_iommu_alias_table[dev_data->devid];
380 if (alias != dev_data->devid) {
381 struct iommu_dev_data *alias_data;
382
383 alias_data = find_dev_data(alias);
384 if (alias_data == NULL) {
385 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
386 dev_name(dev));
387 free_dev_data(dev_data);
388 return -ENOTSUPP;
389 }
390 dev_data->alias_data = alias_data;
391 }
392
393 ret = init_iommu_group(dev);
394 if (ret)
395 return ret;
396
397 if (pci_iommuv2_capable(pdev)) {
398 struct amd_iommu *iommu;
399
400 iommu = amd_iommu_rlookup_table[dev_data->devid];
401 dev_data->iommu_v2 = iommu->is_iommu_v2;
402 }
403
404 dev->archdata.iommu = dev_data;
405
406 return 0;
407 }
408
409 static void iommu_ignore_device(struct device *dev)
410 {
411 u16 devid, alias;
412
413 devid = get_device_id(dev);
414 alias = amd_iommu_alias_table[devid];
415
416 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
417 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
418
419 amd_iommu_rlookup_table[devid] = NULL;
420 amd_iommu_rlookup_table[alias] = NULL;
421 }
422
423 static void iommu_uninit_device(struct device *dev)
424 {
425 iommu_group_remove_device(dev);
426
427 /*
428 * Nothing to do here - we keep dev_data around for unplugged devices
429 * and reuse it when the device is re-plugged - not doing so would
430 * introduce a ton of races.
431 */
432 }
433
434 void __init amd_iommu_uninit_devices(void)
435 {
436 struct iommu_dev_data *dev_data, *n;
437 struct pci_dev *pdev = NULL;
438
439 for_each_pci_dev(pdev) {
440
441 if (!check_device(&pdev->dev))
442 continue;
443
444 iommu_uninit_device(&pdev->dev);
445 }
446
447 /* Free all of our dev_data structures */
448 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
449 free_dev_data(dev_data);
450 }
451
452 int __init amd_iommu_init_devices(void)
453 {
454 struct pci_dev *pdev = NULL;
455 int ret = 0;
456
457 for_each_pci_dev(pdev) {
458
459 if (!check_device(&pdev->dev))
460 continue;
461
462 ret = iommu_init_device(&pdev->dev);
463 if (ret == -ENOTSUPP)
464 iommu_ignore_device(&pdev->dev);
465 else if (ret)
466 goto out_free;
467 }
468
469 return 0;
470
471 out_free:
472
473 amd_iommu_uninit_devices();
474
475 return ret;
476 }
477 #ifdef CONFIG_AMD_IOMMU_STATS
478
479 /*
480 * Initialization code for statistics collection
481 */
482
483 DECLARE_STATS_COUNTER(compl_wait);
484 DECLARE_STATS_COUNTER(cnt_map_single);
485 DECLARE_STATS_COUNTER(cnt_unmap_single);
486 DECLARE_STATS_COUNTER(cnt_map_sg);
487 DECLARE_STATS_COUNTER(cnt_unmap_sg);
488 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
489 DECLARE_STATS_COUNTER(cnt_free_coherent);
490 DECLARE_STATS_COUNTER(cross_page);
491 DECLARE_STATS_COUNTER(domain_flush_single);
492 DECLARE_STATS_COUNTER(domain_flush_all);
493 DECLARE_STATS_COUNTER(alloced_io_mem);
494 DECLARE_STATS_COUNTER(total_map_requests);
495 DECLARE_STATS_COUNTER(complete_ppr);
496 DECLARE_STATS_COUNTER(invalidate_iotlb);
497 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
498 DECLARE_STATS_COUNTER(pri_requests);
499
500 static struct dentry *stats_dir;
501 static struct dentry *de_fflush;
502
503 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
504 {
505 if (stats_dir == NULL)
506 return;
507
508 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
509 &cnt->value);
510 }
511
512 static void amd_iommu_stats_init(void)
513 {
514 stats_dir = debugfs_create_dir("amd-iommu", NULL);
515 if (stats_dir == NULL)
516 return;
517
518 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
519 &amd_iommu_unmap_flush);
520
521 amd_iommu_stats_add(&compl_wait);
522 amd_iommu_stats_add(&cnt_map_single);
523 amd_iommu_stats_add(&cnt_unmap_single);
524 amd_iommu_stats_add(&cnt_map_sg);
525 amd_iommu_stats_add(&cnt_unmap_sg);
526 amd_iommu_stats_add(&cnt_alloc_coherent);
527 amd_iommu_stats_add(&cnt_free_coherent);
528 amd_iommu_stats_add(&cross_page);
529 amd_iommu_stats_add(&domain_flush_single);
530 amd_iommu_stats_add(&domain_flush_all);
531 amd_iommu_stats_add(&alloced_io_mem);
532 amd_iommu_stats_add(&total_map_requests);
533 amd_iommu_stats_add(&complete_ppr);
534 amd_iommu_stats_add(&invalidate_iotlb);
535 amd_iommu_stats_add(&invalidate_iotlb_all);
536 amd_iommu_stats_add(&pri_requests);
537 }
538
539 #endif
540
541 /****************************************************************************
542 *
543 * Interrupt handling functions
544 *
545 ****************************************************************************/
546
547 static void dump_dte_entry(u16 devid)
548 {
549 int i;
550
551 for (i = 0; i < 4; ++i)
552 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
553 amd_iommu_dev_table[devid].data[i]);
554 }
555
556 static void dump_command(unsigned long phys_addr)
557 {
558 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
559 int i;
560
561 for (i = 0; i < 4; ++i)
562 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
563 }
564
565 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
566 {
567 int type, devid, domid, flags;
568 volatile u32 *event = __evt;
569 int count = 0;
570 u64 address;
571
572 retry:
573 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
574 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
575 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
576 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
577 address = (u64)(((u64)event[3]) << 32) | event[2];
578
579 if (type == 0) {
580 /* Did we hit the erratum? */
581 if (++count == LOOP_TIMEOUT) {
582 pr_err("AMD-Vi: No event written to event log\n");
583 return;
584 }
585 udelay(1);
586 goto retry;
587 }
588
589 printk(KERN_ERR "AMD-Vi: Event logged [");
590
591 switch (type) {
592 case EVENT_TYPE_ILL_DEV:
593 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
594 "address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
596 address, flags);
597 dump_dte_entry(devid);
598 break;
599 case EVENT_TYPE_IO_FAULT:
600 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
601 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
602 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
603 domid, address, flags);
604 break;
605 case EVENT_TYPE_DEV_TAB_ERR:
606 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
607 "address=0x%016llx flags=0x%04x]\n",
608 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 address, flags);
610 break;
611 case EVENT_TYPE_PAGE_TAB_ERR:
612 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
613 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
614 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
615 domid, address, flags);
616 break;
617 case EVENT_TYPE_ILL_CMD:
618 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
619 dump_command(address);
620 break;
621 case EVENT_TYPE_CMD_HARD_ERR:
622 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
623 "flags=0x%04x]\n", address, flags);
624 break;
625 case EVENT_TYPE_IOTLB_INV_TO:
626 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
627 "address=0x%016llx]\n",
628 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
629 address);
630 break;
631 case EVENT_TYPE_INV_DEV_REQ:
632 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
633 "address=0x%016llx flags=0x%04x]\n",
634 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
635 address, flags);
636 break;
637 default:
638 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
639 }
640
641 memset(__evt, 0, 4 * sizeof(u32));
642 }
643
644 static void iommu_poll_events(struct amd_iommu *iommu)
645 {
646 u32 head, tail;
647 unsigned long flags;
648
649 spin_lock_irqsave(&iommu->lock, flags);
650
651 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
652 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
653
654 while (head != tail) {
655 iommu_print_event(iommu, iommu->evt_buf + head);
656 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
657 }
658
659 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
660
661 spin_unlock_irqrestore(&iommu->lock, flags);
662 }
663
664 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
665 {
666 struct amd_iommu_fault fault;
667
668 INC_STATS_COUNTER(pri_requests);
669
670 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
671 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
672 return;
673 }
674
675 fault.address = raw[1];
676 fault.pasid = PPR_PASID(raw[0]);
677 fault.device_id = PPR_DEVID(raw[0]);
678 fault.tag = PPR_TAG(raw[0]);
679 fault.flags = PPR_FLAGS(raw[0]);
680
681 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
682 }
683
684 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
685 {
686 unsigned long flags;
687 u32 head, tail;
688
689 if (iommu->ppr_log == NULL)
690 return;
691
692 /* enable ppr interrupts again */
693 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
694
695 spin_lock_irqsave(&iommu->lock, flags);
696
697 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
698 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
699
700 while (head != tail) {
701 volatile u64 *raw;
702 u64 entry[2];
703 int i;
704
705 raw = (u64 *)(iommu->ppr_log + head);
706
707 /*
708 * Hardware bug: Interrupt may arrive before the entry is
709 * written to memory. If this happens we need to wait for the
710 * entry to arrive.
711 */
712 for (i = 0; i < LOOP_TIMEOUT; ++i) {
713 if (PPR_REQ_TYPE(raw[0]) != 0)
714 break;
715 udelay(1);
716 }
717
718 /* Avoid memcpy function-call overhead */
719 entry[0] = raw[0];
720 entry[1] = raw[1];
721
722 /*
723 * To detect the hardware bug we need to clear the entry
724 * back to zero.
725 */
726 raw[0] = raw[1] = 0UL;
727
728 /* Update head pointer of hardware ring-buffer */
729 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
730 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
731
732 /*
733 * Release iommu->lock because ppr-handling might need to
734 * re-acquire it
735 */
736 spin_unlock_irqrestore(&iommu->lock, flags);
737
738 /* Handle PPR entry */
739 iommu_handle_ppr_entry(iommu, entry);
740
741 spin_lock_irqsave(&iommu->lock, flags);
742
743 /* Refresh ring-buffer information */
744 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
745 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
746 }
747
748 spin_unlock_irqrestore(&iommu->lock, flags);
749 }
750
751 irqreturn_t amd_iommu_int_thread(int irq, void *data)
752 {
753 struct amd_iommu *iommu;
754
755 for_each_iommu(iommu) {
756 iommu_poll_events(iommu);
757 iommu_poll_ppr_log(iommu);
758 }
759
760 return IRQ_HANDLED;
761 }
762
763 irqreturn_t amd_iommu_int_handler(int irq, void *data)
764 {
765 return IRQ_WAKE_THREAD;
766 }
767
768 /****************************************************************************
769 *
770 * IOMMU command queuing functions
771 *
772 ****************************************************************************/
773
774 static int wait_on_sem(volatile u64 *sem)
775 {
776 int i = 0;
777
778 while (*sem == 0 && i < LOOP_TIMEOUT) {
779 udelay(1);
780 i += 1;
781 }
782
783 if (i == LOOP_TIMEOUT) {
784 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
785 return -EIO;
786 }
787
788 return 0;
789 }
790
791 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
792 struct iommu_cmd *cmd,
793 u32 tail)
794 {
795 u8 *target;
796
797 target = iommu->cmd_buf + tail;
798 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
799
800 /* Copy command to buffer */
801 memcpy(target, cmd, sizeof(*cmd));
802
803 /* Tell the IOMMU about it */
804 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
805 }
806
807 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
808 {
809 WARN_ON(address & 0x7ULL);
810
811 memset(cmd, 0, sizeof(*cmd));
812 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
813 cmd->data[1] = upper_32_bits(__pa(address));
814 cmd->data[2] = 1;
815 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
816 }
817
818 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
819 {
820 memset(cmd, 0, sizeof(*cmd));
821 cmd->data[0] = devid;
822 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
823 }
824
825 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
826 size_t size, u16 domid, int pde)
827 {
828 u64 pages;
829 int s;
830
831 pages = iommu_num_pages(address, size, PAGE_SIZE);
832 s = 0;
833
834 if (pages > 1) {
835 /*
836 * If we have to flush more than one page, flush all
837 * TLB entries for this domain
838 */
839 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
840 s = 1;
841 }
842
843 address &= PAGE_MASK;
844
845 memset(cmd, 0, sizeof(*cmd));
846 cmd->data[1] |= domid;
847 cmd->data[2] = lower_32_bits(address);
848 cmd->data[3] = upper_32_bits(address);
849 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
850 if (s) /* size bit - we flush more than one 4kb page */
851 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
852 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
853 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
854 }
855
856 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
857 u64 address, size_t size)
858 {
859 u64 pages;
860 int s;
861
862 pages = iommu_num_pages(address, size, PAGE_SIZE);
863 s = 0;
864
865 if (pages > 1) {
866 /*
867 * If we have to flush more than one page, flush all
868 * TLB entries for this domain
869 */
870 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
871 s = 1;
872 }
873
874 address &= PAGE_MASK;
875
876 memset(cmd, 0, sizeof(*cmd));
877 cmd->data[0] = devid;
878 cmd->data[0] |= (qdep & 0xff) << 24;
879 cmd->data[1] = devid;
880 cmd->data[2] = lower_32_bits(address);
881 cmd->data[3] = upper_32_bits(address);
882 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
883 if (s)
884 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
885 }
886
887 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
888 u64 address, bool size)
889 {
890 memset(cmd, 0, sizeof(*cmd));
891
892 address &= ~(0xfffULL);
893
894 cmd->data[0] = pasid & PASID_MASK;
895 cmd->data[1] = domid;
896 cmd->data[2] = lower_32_bits(address);
897 cmd->data[3] = upper_32_bits(address);
898 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
899 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
900 if (size)
901 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
902 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
903 }
904
905 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
906 int qdep, u64 address, bool size)
907 {
908 memset(cmd, 0, sizeof(*cmd));
909
910 address &= ~(0xfffULL);
911
912 cmd->data[0] = devid;
913 cmd->data[0] |= (pasid & 0xff) << 16;
914 cmd->data[0] |= (qdep & 0xff) << 24;
915 cmd->data[1] = devid;
916 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
917 cmd->data[2] = lower_32_bits(address);
918 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
919 cmd->data[3] = upper_32_bits(address);
920 if (size)
921 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
922 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
923 }
924
925 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
926 int status, int tag, bool gn)
927 {
928 memset(cmd, 0, sizeof(*cmd));
929
930 cmd->data[0] = devid;
931 if (gn) {
932 cmd->data[1] = pasid & PASID_MASK;
933 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
934 }
935 cmd->data[3] = tag & 0x1ff;
936 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
937
938 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
939 }
940
941 static void build_inv_all(struct iommu_cmd *cmd)
942 {
943 memset(cmd, 0, sizeof(*cmd));
944 CMD_SET_TYPE(cmd, CMD_INV_ALL);
945 }
946
947 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
948 {
949 memset(cmd, 0, sizeof(*cmd));
950 cmd->data[0] = devid;
951 CMD_SET_TYPE(cmd, CMD_INV_IRT);
952 }
953
954 /*
955 * Writes the command to the IOMMUs command buffer and informs the
956 * hardware about the new command.
957 */
958 static int iommu_queue_command_sync(struct amd_iommu *iommu,
959 struct iommu_cmd *cmd,
960 bool sync)
961 {
962 u32 left, tail, head, next_tail;
963 unsigned long flags;
964
965 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
966
967 again:
968 spin_lock_irqsave(&iommu->lock, flags);
969
970 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
971 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
972 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
973 left = (head - next_tail) % iommu->cmd_buf_size;
974
975 if (left <= 2) {
976 struct iommu_cmd sync_cmd;
977 volatile u64 sem = 0;
978 int ret;
979
980 build_completion_wait(&sync_cmd, (u64)&sem);
981 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
982
983 spin_unlock_irqrestore(&iommu->lock, flags);
984
985 if ((ret = wait_on_sem(&sem)) != 0)
986 return ret;
987
988 goto again;
989 }
990
991 copy_cmd_to_buffer(iommu, cmd, tail);
992
993 /* We need to sync now to make sure all commands are processed */
994 iommu->need_sync = sync;
995
996 spin_unlock_irqrestore(&iommu->lock, flags);
997
998 return 0;
999 }
1000
1001 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1002 {
1003 return iommu_queue_command_sync(iommu, cmd, true);
1004 }
1005
1006 /*
1007 * This function queues a completion wait command into the command
1008 * buffer of an IOMMU
1009 */
1010 static int iommu_completion_wait(struct amd_iommu *iommu)
1011 {
1012 struct iommu_cmd cmd;
1013 volatile u64 sem = 0;
1014 int ret;
1015
1016 if (!iommu->need_sync)
1017 return 0;
1018
1019 build_completion_wait(&cmd, (u64)&sem);
1020
1021 ret = iommu_queue_command_sync(iommu, &cmd, false);
1022 if (ret)
1023 return ret;
1024
1025 return wait_on_sem(&sem);
1026 }
1027
1028 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1029 {
1030 struct iommu_cmd cmd;
1031
1032 build_inv_dte(&cmd, devid);
1033
1034 return iommu_queue_command(iommu, &cmd);
1035 }
1036
1037 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1038 {
1039 u32 devid;
1040
1041 for (devid = 0; devid <= 0xffff; ++devid)
1042 iommu_flush_dte(iommu, devid);
1043
1044 iommu_completion_wait(iommu);
1045 }
1046
1047 /*
1048 * This function uses heavy locking and may disable irqs for some time. But
1049 * this is no issue because it is only called during resume.
1050 */
1051 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1052 {
1053 u32 dom_id;
1054
1055 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1056 struct iommu_cmd cmd;
1057 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1058 dom_id, 1);
1059 iommu_queue_command(iommu, &cmd);
1060 }
1061
1062 iommu_completion_wait(iommu);
1063 }
1064
1065 static void iommu_flush_all(struct amd_iommu *iommu)
1066 {
1067 struct iommu_cmd cmd;
1068
1069 build_inv_all(&cmd);
1070
1071 iommu_queue_command(iommu, &cmd);
1072 iommu_completion_wait(iommu);
1073 }
1074
1075 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1076 {
1077 struct iommu_cmd cmd;
1078
1079 build_inv_irt(&cmd, devid);
1080
1081 iommu_queue_command(iommu, &cmd);
1082 }
1083
1084 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1085 {
1086 u32 devid;
1087
1088 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1089 iommu_flush_irt(iommu, devid);
1090
1091 iommu_completion_wait(iommu);
1092 }
1093
1094 void iommu_flush_all_caches(struct amd_iommu *iommu)
1095 {
1096 if (iommu_feature(iommu, FEATURE_IA)) {
1097 iommu_flush_all(iommu);
1098 } else {
1099 iommu_flush_dte_all(iommu);
1100 iommu_flush_irt_all(iommu);
1101 iommu_flush_tlb_all(iommu);
1102 }
1103 }
1104
1105 /*
1106 * Command send function for flushing on-device TLB
1107 */
1108 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1109 u64 address, size_t size)
1110 {
1111 struct amd_iommu *iommu;
1112 struct iommu_cmd cmd;
1113 int qdep;
1114
1115 qdep = dev_data->ats.qdep;
1116 iommu = amd_iommu_rlookup_table[dev_data->devid];
1117
1118 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1119
1120 return iommu_queue_command(iommu, &cmd);
1121 }
1122
1123 /*
1124 * Command send function for invalidating a device table entry
1125 */
1126 static int device_flush_dte(struct iommu_dev_data *dev_data)
1127 {
1128 struct amd_iommu *iommu;
1129 int ret;
1130
1131 iommu = amd_iommu_rlookup_table[dev_data->devid];
1132
1133 ret = iommu_flush_dte(iommu, dev_data->devid);
1134 if (ret)
1135 return ret;
1136
1137 if (dev_data->ats.enabled)
1138 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1139
1140 return ret;
1141 }
1142
1143 /*
1144 * TLB invalidation function which is called from the mapping functions.
1145 * It invalidates a single PTE if the range to flush is within a single
1146 * page. Otherwise it flushes the whole TLB of the IOMMU.
1147 */
1148 static void __domain_flush_pages(struct protection_domain *domain,
1149 u64 address, size_t size, int pde)
1150 {
1151 struct iommu_dev_data *dev_data;
1152 struct iommu_cmd cmd;
1153 int ret = 0, i;
1154
1155 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1156
1157 for (i = 0; i < amd_iommus_present; ++i) {
1158 if (!domain->dev_iommu[i])
1159 continue;
1160
1161 /*
1162 * Devices of this domain are behind this IOMMU
1163 * We need a TLB flush
1164 */
1165 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1166 }
1167
1168 list_for_each_entry(dev_data, &domain->dev_list, list) {
1169
1170 if (!dev_data->ats.enabled)
1171 continue;
1172
1173 ret |= device_flush_iotlb(dev_data, address, size);
1174 }
1175
1176 WARN_ON(ret);
1177 }
1178
1179 static void domain_flush_pages(struct protection_domain *domain,
1180 u64 address, size_t size)
1181 {
1182 __domain_flush_pages(domain, address, size, 0);
1183 }
1184
1185 /* Flush the whole IO/TLB for a given protection domain */
1186 static void domain_flush_tlb(struct protection_domain *domain)
1187 {
1188 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1189 }
1190
1191 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1192 static void domain_flush_tlb_pde(struct protection_domain *domain)
1193 {
1194 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1195 }
1196
1197 static void domain_flush_complete(struct protection_domain *domain)
1198 {
1199 int i;
1200
1201 for (i = 0; i < amd_iommus_present; ++i) {
1202 if (!domain->dev_iommu[i])
1203 continue;
1204
1205 /*
1206 * Devices of this domain are behind this IOMMU
1207 * We need to wait for completion of all commands.
1208 */
1209 iommu_completion_wait(amd_iommus[i]);
1210 }
1211 }
1212
1213
1214 /*
1215 * This function flushes the DTEs for all devices in domain
1216 */
1217 static void domain_flush_devices(struct protection_domain *domain)
1218 {
1219 struct iommu_dev_data *dev_data;
1220
1221 list_for_each_entry(dev_data, &domain->dev_list, list)
1222 device_flush_dte(dev_data);
1223 }
1224
1225 /****************************************************************************
1226 *
1227 * The functions below are used the create the page table mappings for
1228 * unity mapped regions.
1229 *
1230 ****************************************************************************/
1231
1232 /*
1233 * This function is used to add another level to an IO page table. Adding
1234 * another level increases the size of the address space by 9 bits to a size up
1235 * to 64 bits.
1236 */
1237 static bool increase_address_space(struct protection_domain *domain,
1238 gfp_t gfp)
1239 {
1240 u64 *pte;
1241
1242 if (domain->mode == PAGE_MODE_6_LEVEL)
1243 /* address space already 64 bit large */
1244 return false;
1245
1246 pte = (void *)get_zeroed_page(gfp);
1247 if (!pte)
1248 return false;
1249
1250 *pte = PM_LEVEL_PDE(domain->mode,
1251 virt_to_phys(domain->pt_root));
1252 domain->pt_root = pte;
1253 domain->mode += 1;
1254 domain->updated = true;
1255
1256 return true;
1257 }
1258
1259 static u64 *alloc_pte(struct protection_domain *domain,
1260 unsigned long address,
1261 unsigned long page_size,
1262 u64 **pte_page,
1263 gfp_t gfp)
1264 {
1265 int level, end_lvl;
1266 u64 *pte, *page;
1267
1268 BUG_ON(!is_power_of_2(page_size));
1269
1270 while (address > PM_LEVEL_SIZE(domain->mode))
1271 increase_address_space(domain, gfp);
1272
1273 level = domain->mode - 1;
1274 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1275 address = PAGE_SIZE_ALIGN(address, page_size);
1276 end_lvl = PAGE_SIZE_LEVEL(page_size);
1277
1278 while (level > end_lvl) {
1279 if (!IOMMU_PTE_PRESENT(*pte)) {
1280 page = (u64 *)get_zeroed_page(gfp);
1281 if (!page)
1282 return NULL;
1283 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1284 }
1285
1286 /* No level skipping support yet */
1287 if (PM_PTE_LEVEL(*pte) != level)
1288 return NULL;
1289
1290 level -= 1;
1291
1292 pte = IOMMU_PTE_PAGE(*pte);
1293
1294 if (pte_page && level == end_lvl)
1295 *pte_page = pte;
1296
1297 pte = &pte[PM_LEVEL_INDEX(level, address)];
1298 }
1299
1300 return pte;
1301 }
1302
1303 /*
1304 * This function checks if there is a PTE for a given dma address. If
1305 * there is one, it returns the pointer to it.
1306 */
1307 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1308 {
1309 int level;
1310 u64 *pte;
1311
1312 if (address > PM_LEVEL_SIZE(domain->mode))
1313 return NULL;
1314
1315 level = domain->mode - 1;
1316 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1317
1318 while (level > 0) {
1319
1320 /* Not Present */
1321 if (!IOMMU_PTE_PRESENT(*pte))
1322 return NULL;
1323
1324 /* Large PTE */
1325 if (PM_PTE_LEVEL(*pte) == 0x07) {
1326 unsigned long pte_mask, __pte;
1327
1328 /*
1329 * If we have a series of large PTEs, make
1330 * sure to return a pointer to the first one.
1331 */
1332 pte_mask = PTE_PAGE_SIZE(*pte);
1333 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1334 __pte = ((unsigned long)pte) & pte_mask;
1335
1336 return (u64 *)__pte;
1337 }
1338
1339 /* No level skipping support yet */
1340 if (PM_PTE_LEVEL(*pte) != level)
1341 return NULL;
1342
1343 level -= 1;
1344
1345 /* Walk to the next level */
1346 pte = IOMMU_PTE_PAGE(*pte);
1347 pte = &pte[PM_LEVEL_INDEX(level, address)];
1348 }
1349
1350 return pte;
1351 }
1352
1353 /*
1354 * Generic mapping functions. It maps a physical address into a DMA
1355 * address space. It allocates the page table pages if necessary.
1356 * In the future it can be extended to a generic mapping function
1357 * supporting all features of AMD IOMMU page tables like level skipping
1358 * and full 64 bit address spaces.
1359 */
1360 static int iommu_map_page(struct protection_domain *dom,
1361 unsigned long bus_addr,
1362 unsigned long phys_addr,
1363 int prot,
1364 unsigned long page_size)
1365 {
1366 u64 __pte, *pte;
1367 int i, count;
1368
1369 if (!(prot & IOMMU_PROT_MASK))
1370 return -EINVAL;
1371
1372 bus_addr = PAGE_ALIGN(bus_addr);
1373 phys_addr = PAGE_ALIGN(phys_addr);
1374 count = PAGE_SIZE_PTE_COUNT(page_size);
1375 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1376
1377 for (i = 0; i < count; ++i)
1378 if (IOMMU_PTE_PRESENT(pte[i]))
1379 return -EBUSY;
1380
1381 if (page_size > PAGE_SIZE) {
1382 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1383 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1384 } else
1385 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1386
1387 if (prot & IOMMU_PROT_IR)
1388 __pte |= IOMMU_PTE_IR;
1389 if (prot & IOMMU_PROT_IW)
1390 __pte |= IOMMU_PTE_IW;
1391
1392 for (i = 0; i < count; ++i)
1393 pte[i] = __pte;
1394
1395 update_domain(dom);
1396
1397 return 0;
1398 }
1399
1400 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1401 unsigned long bus_addr,
1402 unsigned long page_size)
1403 {
1404 unsigned long long unmap_size, unmapped;
1405 u64 *pte;
1406
1407 BUG_ON(!is_power_of_2(page_size));
1408
1409 unmapped = 0;
1410
1411 while (unmapped < page_size) {
1412
1413 pte = fetch_pte(dom, bus_addr);
1414
1415 if (!pte) {
1416 /*
1417 * No PTE for this address
1418 * move forward in 4kb steps
1419 */
1420 unmap_size = PAGE_SIZE;
1421 } else if (PM_PTE_LEVEL(*pte) == 0) {
1422 /* 4kb PTE found for this address */
1423 unmap_size = PAGE_SIZE;
1424 *pte = 0ULL;
1425 } else {
1426 int count, i;
1427
1428 /* Large PTE found which maps this address */
1429 unmap_size = PTE_PAGE_SIZE(*pte);
1430 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1431 for (i = 0; i < count; i++)
1432 pte[i] = 0ULL;
1433 }
1434
1435 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1436 unmapped += unmap_size;
1437 }
1438
1439 BUG_ON(!is_power_of_2(unmapped));
1440
1441 return unmapped;
1442 }
1443
1444 /*
1445 * This function checks if a specific unity mapping entry is needed for
1446 * this specific IOMMU.
1447 */
1448 static int iommu_for_unity_map(struct amd_iommu *iommu,
1449 struct unity_map_entry *entry)
1450 {
1451 u16 bdf, i;
1452
1453 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1454 bdf = amd_iommu_alias_table[i];
1455 if (amd_iommu_rlookup_table[bdf] == iommu)
1456 return 1;
1457 }
1458
1459 return 0;
1460 }
1461
1462 /*
1463 * This function actually applies the mapping to the page table of the
1464 * dma_ops domain.
1465 */
1466 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1467 struct unity_map_entry *e)
1468 {
1469 u64 addr;
1470 int ret;
1471
1472 for (addr = e->address_start; addr < e->address_end;
1473 addr += PAGE_SIZE) {
1474 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1475 PAGE_SIZE);
1476 if (ret)
1477 return ret;
1478 /*
1479 * if unity mapping is in aperture range mark the page
1480 * as allocated in the aperture
1481 */
1482 if (addr < dma_dom->aperture_size)
1483 __set_bit(addr >> PAGE_SHIFT,
1484 dma_dom->aperture[0]->bitmap);
1485 }
1486
1487 return 0;
1488 }
1489
1490 /*
1491 * Init the unity mappings for a specific IOMMU in the system
1492 *
1493 * Basically iterates over all unity mapping entries and applies them to
1494 * the default domain DMA of that IOMMU if necessary.
1495 */
1496 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1497 {
1498 struct unity_map_entry *entry;
1499 int ret;
1500
1501 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1502 if (!iommu_for_unity_map(iommu, entry))
1503 continue;
1504 ret = dma_ops_unity_map(iommu->default_dom, entry);
1505 if (ret)
1506 return ret;
1507 }
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * Inits the unity mappings required for a specific device
1514 */
1515 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1516 u16 devid)
1517 {
1518 struct unity_map_entry *e;
1519 int ret;
1520
1521 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1522 if (!(devid >= e->devid_start && devid <= e->devid_end))
1523 continue;
1524 ret = dma_ops_unity_map(dma_dom, e);
1525 if (ret)
1526 return ret;
1527 }
1528
1529 return 0;
1530 }
1531
1532 /****************************************************************************
1533 *
1534 * The next functions belong to the address allocator for the dma_ops
1535 * interface functions. They work like the allocators in the other IOMMU
1536 * drivers. Its basically a bitmap which marks the allocated pages in
1537 * the aperture. Maybe it could be enhanced in the future to a more
1538 * efficient allocator.
1539 *
1540 ****************************************************************************/
1541
1542 /*
1543 * The address allocator core functions.
1544 *
1545 * called with domain->lock held
1546 */
1547
1548 /*
1549 * Used to reserve address ranges in the aperture (e.g. for exclusion
1550 * ranges.
1551 */
1552 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1553 unsigned long start_page,
1554 unsigned int pages)
1555 {
1556 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1557
1558 if (start_page + pages > last_page)
1559 pages = last_page - start_page;
1560
1561 for (i = start_page; i < start_page + pages; ++i) {
1562 int index = i / APERTURE_RANGE_PAGES;
1563 int page = i % APERTURE_RANGE_PAGES;
1564 __set_bit(page, dom->aperture[index]->bitmap);
1565 }
1566 }
1567
1568 /*
1569 * This function is used to add a new aperture range to an existing
1570 * aperture in case of dma_ops domain allocation or address allocation
1571 * failure.
1572 */
1573 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1574 bool populate, gfp_t gfp)
1575 {
1576 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1577 struct amd_iommu *iommu;
1578 unsigned long i, old_size;
1579
1580 #ifdef CONFIG_IOMMU_STRESS
1581 populate = false;
1582 #endif
1583
1584 if (index >= APERTURE_MAX_RANGES)
1585 return -ENOMEM;
1586
1587 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1588 if (!dma_dom->aperture[index])
1589 return -ENOMEM;
1590
1591 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1592 if (!dma_dom->aperture[index]->bitmap)
1593 goto out_free;
1594
1595 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1596
1597 if (populate) {
1598 unsigned long address = dma_dom->aperture_size;
1599 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1600 u64 *pte, *pte_page;
1601
1602 for (i = 0; i < num_ptes; ++i) {
1603 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1604 &pte_page, gfp);
1605 if (!pte)
1606 goto out_free;
1607
1608 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1609
1610 address += APERTURE_RANGE_SIZE / 64;
1611 }
1612 }
1613
1614 old_size = dma_dom->aperture_size;
1615 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1616
1617 /* Reserve address range used for MSI messages */
1618 if (old_size < MSI_ADDR_BASE_LO &&
1619 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1620 unsigned long spage;
1621 int pages;
1622
1623 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1624 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1625
1626 dma_ops_reserve_addresses(dma_dom, spage, pages);
1627 }
1628
1629 /* Initialize the exclusion range if necessary */
1630 for_each_iommu(iommu) {
1631 if (iommu->exclusion_start &&
1632 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1633 && iommu->exclusion_start < dma_dom->aperture_size) {
1634 unsigned long startpage;
1635 int pages = iommu_num_pages(iommu->exclusion_start,
1636 iommu->exclusion_length,
1637 PAGE_SIZE);
1638 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1639 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1640 }
1641 }
1642
1643 /*
1644 * Check for areas already mapped as present in the new aperture
1645 * range and mark those pages as reserved in the allocator. Such
1646 * mappings may already exist as a result of requested unity
1647 * mappings for devices.
1648 */
1649 for (i = dma_dom->aperture[index]->offset;
1650 i < dma_dom->aperture_size;
1651 i += PAGE_SIZE) {
1652 u64 *pte = fetch_pte(&dma_dom->domain, i);
1653 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1654 continue;
1655
1656 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1657 }
1658
1659 update_domain(&dma_dom->domain);
1660
1661 return 0;
1662
1663 out_free:
1664 update_domain(&dma_dom->domain);
1665
1666 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1667
1668 kfree(dma_dom->aperture[index]);
1669 dma_dom->aperture[index] = NULL;
1670
1671 return -ENOMEM;
1672 }
1673
1674 static unsigned long dma_ops_area_alloc(struct device *dev,
1675 struct dma_ops_domain *dom,
1676 unsigned int pages,
1677 unsigned long align_mask,
1678 u64 dma_mask,
1679 unsigned long start)
1680 {
1681 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1682 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1683 int i = start >> APERTURE_RANGE_SHIFT;
1684 unsigned long boundary_size;
1685 unsigned long address = -1;
1686 unsigned long limit;
1687
1688 next_bit >>= PAGE_SHIFT;
1689
1690 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1691 PAGE_SIZE) >> PAGE_SHIFT;
1692
1693 for (;i < max_index; ++i) {
1694 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1695
1696 if (dom->aperture[i]->offset >= dma_mask)
1697 break;
1698
1699 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1700 dma_mask >> PAGE_SHIFT);
1701
1702 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1703 limit, next_bit, pages, 0,
1704 boundary_size, align_mask);
1705 if (address != -1) {
1706 address = dom->aperture[i]->offset +
1707 (address << PAGE_SHIFT);
1708 dom->next_address = address + (pages << PAGE_SHIFT);
1709 break;
1710 }
1711
1712 next_bit = 0;
1713 }
1714
1715 return address;
1716 }
1717
1718 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1719 struct dma_ops_domain *dom,
1720 unsigned int pages,
1721 unsigned long align_mask,
1722 u64 dma_mask)
1723 {
1724 unsigned long address;
1725
1726 #ifdef CONFIG_IOMMU_STRESS
1727 dom->next_address = 0;
1728 dom->need_flush = true;
1729 #endif
1730
1731 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1732 dma_mask, dom->next_address);
1733
1734 if (address == -1) {
1735 dom->next_address = 0;
1736 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1737 dma_mask, 0);
1738 dom->need_flush = true;
1739 }
1740
1741 if (unlikely(address == -1))
1742 address = DMA_ERROR_CODE;
1743
1744 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1745
1746 return address;
1747 }
1748
1749 /*
1750 * The address free function.
1751 *
1752 * called with domain->lock held
1753 */
1754 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1755 unsigned long address,
1756 unsigned int pages)
1757 {
1758 unsigned i = address >> APERTURE_RANGE_SHIFT;
1759 struct aperture_range *range = dom->aperture[i];
1760
1761 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1762
1763 #ifdef CONFIG_IOMMU_STRESS
1764 if (i < 4)
1765 return;
1766 #endif
1767
1768 if (address >= dom->next_address)
1769 dom->need_flush = true;
1770
1771 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1772
1773 bitmap_clear(range->bitmap, address, pages);
1774
1775 }
1776
1777 /****************************************************************************
1778 *
1779 * The next functions belong to the domain allocation. A domain is
1780 * allocated for every IOMMU as the default domain. If device isolation
1781 * is enabled, every device get its own domain. The most important thing
1782 * about domains is the page table mapping the DMA address space they
1783 * contain.
1784 *
1785 ****************************************************************************/
1786
1787 /*
1788 * This function adds a protection domain to the global protection domain list
1789 */
1790 static void add_domain_to_list(struct protection_domain *domain)
1791 {
1792 unsigned long flags;
1793
1794 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1795 list_add(&domain->list, &amd_iommu_pd_list);
1796 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1797 }
1798
1799 /*
1800 * This function removes a protection domain to the global
1801 * protection domain list
1802 */
1803 static void del_domain_from_list(struct protection_domain *domain)
1804 {
1805 unsigned long flags;
1806
1807 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1808 list_del(&domain->list);
1809 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1810 }
1811
1812 static u16 domain_id_alloc(void)
1813 {
1814 unsigned long flags;
1815 int id;
1816
1817 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1818 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1819 BUG_ON(id == 0);
1820 if (id > 0 && id < MAX_DOMAIN_ID)
1821 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1822 else
1823 id = 0;
1824 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1825
1826 return id;
1827 }
1828
1829 static void domain_id_free(int id)
1830 {
1831 unsigned long flags;
1832
1833 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1834 if (id > 0 && id < MAX_DOMAIN_ID)
1835 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1836 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1837 }
1838
1839 static void free_pagetable(struct protection_domain *domain)
1840 {
1841 int i, j;
1842 u64 *p1, *p2, *p3;
1843
1844 p1 = domain->pt_root;
1845
1846 if (!p1)
1847 return;
1848
1849 for (i = 0; i < 512; ++i) {
1850 if (!IOMMU_PTE_PRESENT(p1[i]))
1851 continue;
1852
1853 p2 = IOMMU_PTE_PAGE(p1[i]);
1854 for (j = 0; j < 512; ++j) {
1855 if (!IOMMU_PTE_PRESENT(p2[j]))
1856 continue;
1857 p3 = IOMMU_PTE_PAGE(p2[j]);
1858 free_page((unsigned long)p3);
1859 }
1860
1861 free_page((unsigned long)p2);
1862 }
1863
1864 free_page((unsigned long)p1);
1865
1866 domain->pt_root = NULL;
1867 }
1868
1869 static void free_gcr3_tbl_level1(u64 *tbl)
1870 {
1871 u64 *ptr;
1872 int i;
1873
1874 for (i = 0; i < 512; ++i) {
1875 if (!(tbl[i] & GCR3_VALID))
1876 continue;
1877
1878 ptr = __va(tbl[i] & PAGE_MASK);
1879
1880 free_page((unsigned long)ptr);
1881 }
1882 }
1883
1884 static void free_gcr3_tbl_level2(u64 *tbl)
1885 {
1886 u64 *ptr;
1887 int i;
1888
1889 for (i = 0; i < 512; ++i) {
1890 if (!(tbl[i] & GCR3_VALID))
1891 continue;
1892
1893 ptr = __va(tbl[i] & PAGE_MASK);
1894
1895 free_gcr3_tbl_level1(ptr);
1896 }
1897 }
1898
1899 static void free_gcr3_table(struct protection_domain *domain)
1900 {
1901 if (domain->glx == 2)
1902 free_gcr3_tbl_level2(domain->gcr3_tbl);
1903 else if (domain->glx == 1)
1904 free_gcr3_tbl_level1(domain->gcr3_tbl);
1905 else if (domain->glx != 0)
1906 BUG();
1907
1908 free_page((unsigned long)domain->gcr3_tbl);
1909 }
1910
1911 /*
1912 * Free a domain, only used if something went wrong in the
1913 * allocation path and we need to free an already allocated page table
1914 */
1915 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1916 {
1917 int i;
1918
1919 if (!dom)
1920 return;
1921
1922 del_domain_from_list(&dom->domain);
1923
1924 free_pagetable(&dom->domain);
1925
1926 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1927 if (!dom->aperture[i])
1928 continue;
1929 free_page((unsigned long)dom->aperture[i]->bitmap);
1930 kfree(dom->aperture[i]);
1931 }
1932
1933 kfree(dom);
1934 }
1935
1936 /*
1937 * Allocates a new protection domain usable for the dma_ops functions.
1938 * It also initializes the page table and the address allocator data
1939 * structures required for the dma_ops interface
1940 */
1941 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1942 {
1943 struct dma_ops_domain *dma_dom;
1944
1945 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1946 if (!dma_dom)
1947 return NULL;
1948
1949 spin_lock_init(&dma_dom->domain.lock);
1950
1951 dma_dom->domain.id = domain_id_alloc();
1952 if (dma_dom->domain.id == 0)
1953 goto free_dma_dom;
1954 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1955 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1956 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1957 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1958 dma_dom->domain.priv = dma_dom;
1959 if (!dma_dom->domain.pt_root)
1960 goto free_dma_dom;
1961
1962 dma_dom->need_flush = false;
1963 dma_dom->target_dev = 0xffff;
1964
1965 add_domain_to_list(&dma_dom->domain);
1966
1967 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1968 goto free_dma_dom;
1969
1970 /*
1971 * mark the first page as allocated so we never return 0 as
1972 * a valid dma-address. So we can use 0 as error value
1973 */
1974 dma_dom->aperture[0]->bitmap[0] = 1;
1975 dma_dom->next_address = 0;
1976
1977
1978 return dma_dom;
1979
1980 free_dma_dom:
1981 dma_ops_domain_free(dma_dom);
1982
1983 return NULL;
1984 }
1985
1986 /*
1987 * little helper function to check whether a given protection domain is a
1988 * dma_ops domain
1989 */
1990 static bool dma_ops_domain(struct protection_domain *domain)
1991 {
1992 return domain->flags & PD_DMA_OPS_MASK;
1993 }
1994
1995 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1996 {
1997 u64 pte_root = 0;
1998 u64 flags = 0;
1999
2000 if (domain->mode != PAGE_MODE_NONE)
2001 pte_root = virt_to_phys(domain->pt_root);
2002
2003 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2004 << DEV_ENTRY_MODE_SHIFT;
2005 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2006
2007 flags = amd_iommu_dev_table[devid].data[1];
2008
2009 if (ats)
2010 flags |= DTE_FLAG_IOTLB;
2011
2012 if (domain->flags & PD_IOMMUV2_MASK) {
2013 u64 gcr3 = __pa(domain->gcr3_tbl);
2014 u64 glx = domain->glx;
2015 u64 tmp;
2016
2017 pte_root |= DTE_FLAG_GV;
2018 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2019
2020 /* First mask out possible old values for GCR3 table */
2021 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2022 flags &= ~tmp;
2023
2024 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2025 flags &= ~tmp;
2026
2027 /* Encode GCR3 table into DTE */
2028 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2029 pte_root |= tmp;
2030
2031 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2032 flags |= tmp;
2033
2034 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2035 flags |= tmp;
2036 }
2037
2038 flags &= ~(0xffffUL);
2039 flags |= domain->id;
2040
2041 amd_iommu_dev_table[devid].data[1] = flags;
2042 amd_iommu_dev_table[devid].data[0] = pte_root;
2043 }
2044
2045 static void clear_dte_entry(u16 devid)
2046 {
2047 /* remove entry from the device table seen by the hardware */
2048 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2049 amd_iommu_dev_table[devid].data[1] = 0;
2050
2051 amd_iommu_apply_erratum_63(devid);
2052 }
2053
2054 static void do_attach(struct iommu_dev_data *dev_data,
2055 struct protection_domain *domain)
2056 {
2057 struct amd_iommu *iommu;
2058 bool ats;
2059
2060 iommu = amd_iommu_rlookup_table[dev_data->devid];
2061 ats = dev_data->ats.enabled;
2062
2063 /* Update data structures */
2064 dev_data->domain = domain;
2065 list_add(&dev_data->list, &domain->dev_list);
2066 set_dte_entry(dev_data->devid, domain, ats);
2067
2068 /* Do reference counting */
2069 domain->dev_iommu[iommu->index] += 1;
2070 domain->dev_cnt += 1;
2071
2072 /* Flush the DTE entry */
2073 device_flush_dte(dev_data);
2074 }
2075
2076 static void do_detach(struct iommu_dev_data *dev_data)
2077 {
2078 struct amd_iommu *iommu;
2079
2080 iommu = amd_iommu_rlookup_table[dev_data->devid];
2081
2082 /* decrease reference counters */
2083 dev_data->domain->dev_iommu[iommu->index] -= 1;
2084 dev_data->domain->dev_cnt -= 1;
2085
2086 /* Update data structures */
2087 dev_data->domain = NULL;
2088 list_del(&dev_data->list);
2089 clear_dte_entry(dev_data->devid);
2090
2091 /* Flush the DTE entry */
2092 device_flush_dte(dev_data);
2093 }
2094
2095 /*
2096 * If a device is not yet associated with a domain, this function does
2097 * assigns it visible for the hardware
2098 */
2099 static int __attach_device(struct iommu_dev_data *dev_data,
2100 struct protection_domain *domain)
2101 {
2102 int ret;
2103
2104 /* lock domain */
2105 spin_lock(&domain->lock);
2106
2107 if (dev_data->alias_data != NULL) {
2108 struct iommu_dev_data *alias_data = dev_data->alias_data;
2109
2110 /* Some sanity checks */
2111 ret = -EBUSY;
2112 if (alias_data->domain != NULL &&
2113 alias_data->domain != domain)
2114 goto out_unlock;
2115
2116 if (dev_data->domain != NULL &&
2117 dev_data->domain != domain)
2118 goto out_unlock;
2119
2120 /* Do real assignment */
2121 if (alias_data->domain == NULL)
2122 do_attach(alias_data, domain);
2123
2124 atomic_inc(&alias_data->bind);
2125 }
2126
2127 if (dev_data->domain == NULL)
2128 do_attach(dev_data, domain);
2129
2130 atomic_inc(&dev_data->bind);
2131
2132 ret = 0;
2133
2134 out_unlock:
2135
2136 /* ready */
2137 spin_unlock(&domain->lock);
2138
2139 return ret;
2140 }
2141
2142
2143 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2144 {
2145 pci_disable_ats(pdev);
2146 pci_disable_pri(pdev);
2147 pci_disable_pasid(pdev);
2148 }
2149
2150 /* FIXME: Change generic reset-function to do the same */
2151 static int pri_reset_while_enabled(struct pci_dev *pdev)
2152 {
2153 u16 control;
2154 int pos;
2155
2156 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2157 if (!pos)
2158 return -EINVAL;
2159
2160 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2161 control |= PCI_PRI_CTRL_RESET;
2162 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2163
2164 return 0;
2165 }
2166
2167 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2168 {
2169 bool reset_enable;
2170 int reqs, ret;
2171
2172 /* FIXME: Hardcode number of outstanding requests for now */
2173 reqs = 32;
2174 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2175 reqs = 1;
2176 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2177
2178 /* Only allow access to user-accessible pages */
2179 ret = pci_enable_pasid(pdev, 0);
2180 if (ret)
2181 goto out_err;
2182
2183 /* First reset the PRI state of the device */
2184 ret = pci_reset_pri(pdev);
2185 if (ret)
2186 goto out_err;
2187
2188 /* Enable PRI */
2189 ret = pci_enable_pri(pdev, reqs);
2190 if (ret)
2191 goto out_err;
2192
2193 if (reset_enable) {
2194 ret = pri_reset_while_enabled(pdev);
2195 if (ret)
2196 goto out_err;
2197 }
2198
2199 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2200 if (ret)
2201 goto out_err;
2202
2203 return 0;
2204
2205 out_err:
2206 pci_disable_pri(pdev);
2207 pci_disable_pasid(pdev);
2208
2209 return ret;
2210 }
2211
2212 /* FIXME: Move this to PCI code */
2213 #define PCI_PRI_TLP_OFF (1 << 15)
2214
2215 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2216 {
2217 u16 status;
2218 int pos;
2219
2220 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2221 if (!pos)
2222 return false;
2223
2224 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2225
2226 return (status & PCI_PRI_TLP_OFF) ? true : false;
2227 }
2228
2229 /*
2230 * If a device is not yet associated with a domain, this function
2231 * assigns it visible for the hardware
2232 */
2233 static int attach_device(struct device *dev,
2234 struct protection_domain *domain)
2235 {
2236 struct pci_dev *pdev = to_pci_dev(dev);
2237 struct iommu_dev_data *dev_data;
2238 unsigned long flags;
2239 int ret;
2240
2241 dev_data = get_dev_data(dev);
2242
2243 if (domain->flags & PD_IOMMUV2_MASK) {
2244 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2245 return -EINVAL;
2246
2247 if (pdev_iommuv2_enable(pdev) != 0)
2248 return -EINVAL;
2249
2250 dev_data->ats.enabled = true;
2251 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2252 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2253 } else if (amd_iommu_iotlb_sup &&
2254 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2255 dev_data->ats.enabled = true;
2256 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2257 }
2258
2259 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2260 ret = __attach_device(dev_data, domain);
2261 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2262
2263 /*
2264 * We might boot into a crash-kernel here. The crashed kernel
2265 * left the caches in the IOMMU dirty. So we have to flush
2266 * here to evict all dirty stuff.
2267 */
2268 domain_flush_tlb_pde(domain);
2269
2270 return ret;
2271 }
2272
2273 /*
2274 * Removes a device from a protection domain (unlocked)
2275 */
2276 static void __detach_device(struct iommu_dev_data *dev_data)
2277 {
2278 struct protection_domain *domain;
2279 unsigned long flags;
2280
2281 BUG_ON(!dev_data->domain);
2282
2283 domain = dev_data->domain;
2284
2285 spin_lock_irqsave(&domain->lock, flags);
2286
2287 if (dev_data->alias_data != NULL) {
2288 struct iommu_dev_data *alias_data = dev_data->alias_data;
2289
2290 if (atomic_dec_and_test(&alias_data->bind))
2291 do_detach(alias_data);
2292 }
2293
2294 if (atomic_dec_and_test(&dev_data->bind))
2295 do_detach(dev_data);
2296
2297 spin_unlock_irqrestore(&domain->lock, flags);
2298
2299 /*
2300 * If we run in passthrough mode the device must be assigned to the
2301 * passthrough domain if it is detached from any other domain.
2302 * Make sure we can deassign from the pt_domain itself.
2303 */
2304 if (dev_data->passthrough &&
2305 (dev_data->domain == NULL && domain != pt_domain))
2306 __attach_device(dev_data, pt_domain);
2307 }
2308
2309 /*
2310 * Removes a device from a protection domain (with devtable_lock held)
2311 */
2312 static void detach_device(struct device *dev)
2313 {
2314 struct protection_domain *domain;
2315 struct iommu_dev_data *dev_data;
2316 unsigned long flags;
2317
2318 dev_data = get_dev_data(dev);
2319 domain = dev_data->domain;
2320
2321 /* lock device table */
2322 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2323 __detach_device(dev_data);
2324 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2325
2326 if (domain->flags & PD_IOMMUV2_MASK)
2327 pdev_iommuv2_disable(to_pci_dev(dev));
2328 else if (dev_data->ats.enabled)
2329 pci_disable_ats(to_pci_dev(dev));
2330
2331 dev_data->ats.enabled = false;
2332 }
2333
2334 /*
2335 * Find out the protection domain structure for a given PCI device. This
2336 * will give us the pointer to the page table root for example.
2337 */
2338 static struct protection_domain *domain_for_device(struct device *dev)
2339 {
2340 struct iommu_dev_data *dev_data;
2341 struct protection_domain *dom = NULL;
2342 unsigned long flags;
2343
2344 dev_data = get_dev_data(dev);
2345
2346 if (dev_data->domain)
2347 return dev_data->domain;
2348
2349 if (dev_data->alias_data != NULL) {
2350 struct iommu_dev_data *alias_data = dev_data->alias_data;
2351
2352 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2353 if (alias_data->domain != NULL) {
2354 __attach_device(dev_data, alias_data->domain);
2355 dom = alias_data->domain;
2356 }
2357 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2358 }
2359
2360 return dom;
2361 }
2362
2363 static int device_change_notifier(struct notifier_block *nb,
2364 unsigned long action, void *data)
2365 {
2366 struct dma_ops_domain *dma_domain;
2367 struct protection_domain *domain;
2368 struct iommu_dev_data *dev_data;
2369 struct device *dev = data;
2370 struct amd_iommu *iommu;
2371 unsigned long flags;
2372 u16 devid;
2373
2374 if (!check_device(dev))
2375 return 0;
2376
2377 devid = get_device_id(dev);
2378 iommu = amd_iommu_rlookup_table[devid];
2379 dev_data = get_dev_data(dev);
2380
2381 switch (action) {
2382 case BUS_NOTIFY_UNBOUND_DRIVER:
2383
2384 domain = domain_for_device(dev);
2385
2386 if (!domain)
2387 goto out;
2388 if (dev_data->passthrough)
2389 break;
2390 detach_device(dev);
2391 break;
2392 case BUS_NOTIFY_ADD_DEVICE:
2393
2394 iommu_init_device(dev);
2395
2396 /*
2397 * dev_data is still NULL and
2398 * got initialized in iommu_init_device
2399 */
2400 dev_data = get_dev_data(dev);
2401
2402 if (iommu_pass_through || dev_data->iommu_v2) {
2403 dev_data->passthrough = true;
2404 attach_device(dev, pt_domain);
2405 break;
2406 }
2407
2408 domain = domain_for_device(dev);
2409
2410 /* allocate a protection domain if a device is added */
2411 dma_domain = find_protection_domain(devid);
2412 if (dma_domain)
2413 goto out;
2414 dma_domain = dma_ops_domain_alloc();
2415 if (!dma_domain)
2416 goto out;
2417 dma_domain->target_dev = devid;
2418
2419 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2420 list_add_tail(&dma_domain->list, &iommu_pd_list);
2421 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2422
2423 dev_data = get_dev_data(dev);
2424
2425 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2426
2427 break;
2428 case BUS_NOTIFY_DEL_DEVICE:
2429
2430 iommu_uninit_device(dev);
2431
2432 default:
2433 goto out;
2434 }
2435
2436 iommu_completion_wait(iommu);
2437
2438 out:
2439 return 0;
2440 }
2441
2442 static struct notifier_block device_nb = {
2443 .notifier_call = device_change_notifier,
2444 };
2445
2446 void amd_iommu_init_notifier(void)
2447 {
2448 bus_register_notifier(&pci_bus_type, &device_nb);
2449 }
2450
2451 /*****************************************************************************
2452 *
2453 * The next functions belong to the dma_ops mapping/unmapping code.
2454 *
2455 *****************************************************************************/
2456
2457 /*
2458 * In the dma_ops path we only have the struct device. This function
2459 * finds the corresponding IOMMU, the protection domain and the
2460 * requestor id for a given device.
2461 * If the device is not yet associated with a domain this is also done
2462 * in this function.
2463 */
2464 static struct protection_domain *get_domain(struct device *dev)
2465 {
2466 struct protection_domain *domain;
2467 struct dma_ops_domain *dma_dom;
2468 u16 devid = get_device_id(dev);
2469
2470 if (!check_device(dev))
2471 return ERR_PTR(-EINVAL);
2472
2473 domain = domain_for_device(dev);
2474 if (domain != NULL && !dma_ops_domain(domain))
2475 return ERR_PTR(-EBUSY);
2476
2477 if (domain != NULL)
2478 return domain;
2479
2480 /* Device not bound yet - bind it */
2481 dma_dom = find_protection_domain(devid);
2482 if (!dma_dom)
2483 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2484 attach_device(dev, &dma_dom->domain);
2485 DUMP_printk("Using protection domain %d for device %s\n",
2486 dma_dom->domain.id, dev_name(dev));
2487
2488 return &dma_dom->domain;
2489 }
2490
2491 static void update_device_table(struct protection_domain *domain)
2492 {
2493 struct iommu_dev_data *dev_data;
2494
2495 list_for_each_entry(dev_data, &domain->dev_list, list)
2496 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2497 }
2498
2499 static void update_domain(struct protection_domain *domain)
2500 {
2501 if (!domain->updated)
2502 return;
2503
2504 update_device_table(domain);
2505
2506 domain_flush_devices(domain);
2507 domain_flush_tlb_pde(domain);
2508
2509 domain->updated = false;
2510 }
2511
2512 /*
2513 * This function fetches the PTE for a given address in the aperture
2514 */
2515 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2516 unsigned long address)
2517 {
2518 struct aperture_range *aperture;
2519 u64 *pte, *pte_page;
2520
2521 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2522 if (!aperture)
2523 return NULL;
2524
2525 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2526 if (!pte) {
2527 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2528 GFP_ATOMIC);
2529 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2530 } else
2531 pte += PM_LEVEL_INDEX(0, address);
2532
2533 update_domain(&dom->domain);
2534
2535 return pte;
2536 }
2537
2538 /*
2539 * This is the generic map function. It maps one 4kb page at paddr to
2540 * the given address in the DMA address space for the domain.
2541 */
2542 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2543 unsigned long address,
2544 phys_addr_t paddr,
2545 int direction)
2546 {
2547 u64 *pte, __pte;
2548
2549 WARN_ON(address > dom->aperture_size);
2550
2551 paddr &= PAGE_MASK;
2552
2553 pte = dma_ops_get_pte(dom, address);
2554 if (!pte)
2555 return DMA_ERROR_CODE;
2556
2557 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2558
2559 if (direction == DMA_TO_DEVICE)
2560 __pte |= IOMMU_PTE_IR;
2561 else if (direction == DMA_FROM_DEVICE)
2562 __pte |= IOMMU_PTE_IW;
2563 else if (direction == DMA_BIDIRECTIONAL)
2564 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2565
2566 WARN_ON(*pte);
2567
2568 *pte = __pte;
2569
2570 return (dma_addr_t)address;
2571 }
2572
2573 /*
2574 * The generic unmapping function for on page in the DMA address space.
2575 */
2576 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2577 unsigned long address)
2578 {
2579 struct aperture_range *aperture;
2580 u64 *pte;
2581
2582 if (address >= dom->aperture_size)
2583 return;
2584
2585 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2586 if (!aperture)
2587 return;
2588
2589 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2590 if (!pte)
2591 return;
2592
2593 pte += PM_LEVEL_INDEX(0, address);
2594
2595 WARN_ON(!*pte);
2596
2597 *pte = 0ULL;
2598 }
2599
2600 /*
2601 * This function contains common code for mapping of a physically
2602 * contiguous memory region into DMA address space. It is used by all
2603 * mapping functions provided with this IOMMU driver.
2604 * Must be called with the domain lock held.
2605 */
2606 static dma_addr_t __map_single(struct device *dev,
2607 struct dma_ops_domain *dma_dom,
2608 phys_addr_t paddr,
2609 size_t size,
2610 int dir,
2611 bool align,
2612 u64 dma_mask)
2613 {
2614 dma_addr_t offset = paddr & ~PAGE_MASK;
2615 dma_addr_t address, start, ret;
2616 unsigned int pages;
2617 unsigned long align_mask = 0;
2618 int i;
2619
2620 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2621 paddr &= PAGE_MASK;
2622
2623 INC_STATS_COUNTER(total_map_requests);
2624
2625 if (pages > 1)
2626 INC_STATS_COUNTER(cross_page);
2627
2628 if (align)
2629 align_mask = (1UL << get_order(size)) - 1;
2630
2631 retry:
2632 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2633 dma_mask);
2634 if (unlikely(address == DMA_ERROR_CODE)) {
2635 /*
2636 * setting next_address here will let the address
2637 * allocator only scan the new allocated range in the
2638 * first run. This is a small optimization.
2639 */
2640 dma_dom->next_address = dma_dom->aperture_size;
2641
2642 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2643 goto out;
2644
2645 /*
2646 * aperture was successfully enlarged by 128 MB, try
2647 * allocation again
2648 */
2649 goto retry;
2650 }
2651
2652 start = address;
2653 for (i = 0; i < pages; ++i) {
2654 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2655 if (ret == DMA_ERROR_CODE)
2656 goto out_unmap;
2657
2658 paddr += PAGE_SIZE;
2659 start += PAGE_SIZE;
2660 }
2661 address += offset;
2662
2663 ADD_STATS_COUNTER(alloced_io_mem, size);
2664
2665 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2666 domain_flush_tlb(&dma_dom->domain);
2667 dma_dom->need_flush = false;
2668 } else if (unlikely(amd_iommu_np_cache))
2669 domain_flush_pages(&dma_dom->domain, address, size);
2670
2671 out:
2672 return address;
2673
2674 out_unmap:
2675
2676 for (--i; i >= 0; --i) {
2677 start -= PAGE_SIZE;
2678 dma_ops_domain_unmap(dma_dom, start);
2679 }
2680
2681 dma_ops_free_addresses(dma_dom, address, pages);
2682
2683 return DMA_ERROR_CODE;
2684 }
2685
2686 /*
2687 * Does the reverse of the __map_single function. Must be called with
2688 * the domain lock held too
2689 */
2690 static void __unmap_single(struct dma_ops_domain *dma_dom,
2691 dma_addr_t dma_addr,
2692 size_t size,
2693 int dir)
2694 {
2695 dma_addr_t flush_addr;
2696 dma_addr_t i, start;
2697 unsigned int pages;
2698
2699 if ((dma_addr == DMA_ERROR_CODE) ||
2700 (dma_addr + size > dma_dom->aperture_size))
2701 return;
2702
2703 flush_addr = dma_addr;
2704 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2705 dma_addr &= PAGE_MASK;
2706 start = dma_addr;
2707
2708 for (i = 0; i < pages; ++i) {
2709 dma_ops_domain_unmap(dma_dom, start);
2710 start += PAGE_SIZE;
2711 }
2712
2713 SUB_STATS_COUNTER(alloced_io_mem, size);
2714
2715 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2716
2717 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2718 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2719 dma_dom->need_flush = false;
2720 }
2721 }
2722
2723 /*
2724 * The exported map_single function for dma_ops.
2725 */
2726 static dma_addr_t map_page(struct device *dev, struct page *page,
2727 unsigned long offset, size_t size,
2728 enum dma_data_direction dir,
2729 struct dma_attrs *attrs)
2730 {
2731 unsigned long flags;
2732 struct protection_domain *domain;
2733 dma_addr_t addr;
2734 u64 dma_mask;
2735 phys_addr_t paddr = page_to_phys(page) + offset;
2736
2737 INC_STATS_COUNTER(cnt_map_single);
2738
2739 domain = get_domain(dev);
2740 if (PTR_ERR(domain) == -EINVAL)
2741 return (dma_addr_t)paddr;
2742 else if (IS_ERR(domain))
2743 return DMA_ERROR_CODE;
2744
2745 dma_mask = *dev->dma_mask;
2746
2747 spin_lock_irqsave(&domain->lock, flags);
2748
2749 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2750 dma_mask);
2751 if (addr == DMA_ERROR_CODE)
2752 goto out;
2753
2754 domain_flush_complete(domain);
2755
2756 out:
2757 spin_unlock_irqrestore(&domain->lock, flags);
2758
2759 return addr;
2760 }
2761
2762 /*
2763 * The exported unmap_single function for dma_ops.
2764 */
2765 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2766 enum dma_data_direction dir, struct dma_attrs *attrs)
2767 {
2768 unsigned long flags;
2769 struct protection_domain *domain;
2770
2771 INC_STATS_COUNTER(cnt_unmap_single);
2772
2773 domain = get_domain(dev);
2774 if (IS_ERR(domain))
2775 return;
2776
2777 spin_lock_irqsave(&domain->lock, flags);
2778
2779 __unmap_single(domain->priv, dma_addr, size, dir);
2780
2781 domain_flush_complete(domain);
2782
2783 spin_unlock_irqrestore(&domain->lock, flags);
2784 }
2785
2786 /*
2787 * This is a special map_sg function which is used if we should map a
2788 * device which is not handled by an AMD IOMMU in the system.
2789 */
2790 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2791 int nelems, int dir)
2792 {
2793 struct scatterlist *s;
2794 int i;
2795
2796 for_each_sg(sglist, s, nelems, i) {
2797 s->dma_address = (dma_addr_t)sg_phys(s);
2798 s->dma_length = s->length;
2799 }
2800
2801 return nelems;
2802 }
2803
2804 /*
2805 * The exported map_sg function for dma_ops (handles scatter-gather
2806 * lists).
2807 */
2808 static int map_sg(struct device *dev, struct scatterlist *sglist,
2809 int nelems, enum dma_data_direction dir,
2810 struct dma_attrs *attrs)
2811 {
2812 unsigned long flags;
2813 struct protection_domain *domain;
2814 int i;
2815 struct scatterlist *s;
2816 phys_addr_t paddr;
2817 int mapped_elems = 0;
2818 u64 dma_mask;
2819
2820 INC_STATS_COUNTER(cnt_map_sg);
2821
2822 domain = get_domain(dev);
2823 if (PTR_ERR(domain) == -EINVAL)
2824 return map_sg_no_iommu(dev, sglist, nelems, dir);
2825 else if (IS_ERR(domain))
2826 return 0;
2827
2828 dma_mask = *dev->dma_mask;
2829
2830 spin_lock_irqsave(&domain->lock, flags);
2831
2832 for_each_sg(sglist, s, nelems, i) {
2833 paddr = sg_phys(s);
2834
2835 s->dma_address = __map_single(dev, domain->priv,
2836 paddr, s->length, dir, false,
2837 dma_mask);
2838
2839 if (s->dma_address) {
2840 s->dma_length = s->length;
2841 mapped_elems++;
2842 } else
2843 goto unmap;
2844 }
2845
2846 domain_flush_complete(domain);
2847
2848 out:
2849 spin_unlock_irqrestore(&domain->lock, flags);
2850
2851 return mapped_elems;
2852 unmap:
2853 for_each_sg(sglist, s, mapped_elems, i) {
2854 if (s->dma_address)
2855 __unmap_single(domain->priv, s->dma_address,
2856 s->dma_length, dir);
2857 s->dma_address = s->dma_length = 0;
2858 }
2859
2860 mapped_elems = 0;
2861
2862 goto out;
2863 }
2864
2865 /*
2866 * The exported map_sg function for dma_ops (handles scatter-gather
2867 * lists).
2868 */
2869 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2870 int nelems, enum dma_data_direction dir,
2871 struct dma_attrs *attrs)
2872 {
2873 unsigned long flags;
2874 struct protection_domain *domain;
2875 struct scatterlist *s;
2876 int i;
2877
2878 INC_STATS_COUNTER(cnt_unmap_sg);
2879
2880 domain = get_domain(dev);
2881 if (IS_ERR(domain))
2882 return;
2883
2884 spin_lock_irqsave(&domain->lock, flags);
2885
2886 for_each_sg(sglist, s, nelems, i) {
2887 __unmap_single(domain->priv, s->dma_address,
2888 s->dma_length, dir);
2889 s->dma_address = s->dma_length = 0;
2890 }
2891
2892 domain_flush_complete(domain);
2893
2894 spin_unlock_irqrestore(&domain->lock, flags);
2895 }
2896
2897 /*
2898 * The exported alloc_coherent function for dma_ops.
2899 */
2900 static void *alloc_coherent(struct device *dev, size_t size,
2901 dma_addr_t *dma_addr, gfp_t flag,
2902 struct dma_attrs *attrs)
2903 {
2904 unsigned long flags;
2905 void *virt_addr;
2906 struct protection_domain *domain;
2907 phys_addr_t paddr;
2908 u64 dma_mask = dev->coherent_dma_mask;
2909
2910 INC_STATS_COUNTER(cnt_alloc_coherent);
2911
2912 domain = get_domain(dev);
2913 if (PTR_ERR(domain) == -EINVAL) {
2914 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2915 *dma_addr = __pa(virt_addr);
2916 return virt_addr;
2917 } else if (IS_ERR(domain))
2918 return NULL;
2919
2920 dma_mask = dev->coherent_dma_mask;
2921 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2922 flag |= __GFP_ZERO;
2923
2924 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2925 if (!virt_addr)
2926 return NULL;
2927
2928 paddr = virt_to_phys(virt_addr);
2929
2930 if (!dma_mask)
2931 dma_mask = *dev->dma_mask;
2932
2933 spin_lock_irqsave(&domain->lock, flags);
2934
2935 *dma_addr = __map_single(dev, domain->priv, paddr,
2936 size, DMA_BIDIRECTIONAL, true, dma_mask);
2937
2938 if (*dma_addr == DMA_ERROR_CODE) {
2939 spin_unlock_irqrestore(&domain->lock, flags);
2940 goto out_free;
2941 }
2942
2943 domain_flush_complete(domain);
2944
2945 spin_unlock_irqrestore(&domain->lock, flags);
2946
2947 return virt_addr;
2948
2949 out_free:
2950
2951 free_pages((unsigned long)virt_addr, get_order(size));
2952
2953 return NULL;
2954 }
2955
2956 /*
2957 * The exported free_coherent function for dma_ops.
2958 */
2959 static void free_coherent(struct device *dev, size_t size,
2960 void *virt_addr, dma_addr_t dma_addr,
2961 struct dma_attrs *attrs)
2962 {
2963 unsigned long flags;
2964 struct protection_domain *domain;
2965
2966 INC_STATS_COUNTER(cnt_free_coherent);
2967
2968 domain = get_domain(dev);
2969 if (IS_ERR(domain))
2970 goto free_mem;
2971
2972 spin_lock_irqsave(&domain->lock, flags);
2973
2974 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2975
2976 domain_flush_complete(domain);
2977
2978 spin_unlock_irqrestore(&domain->lock, flags);
2979
2980 free_mem:
2981 free_pages((unsigned long)virt_addr, get_order(size));
2982 }
2983
2984 /*
2985 * This function is called by the DMA layer to find out if we can handle a
2986 * particular device. It is part of the dma_ops.
2987 */
2988 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2989 {
2990 return check_device(dev);
2991 }
2992
2993 /*
2994 * The function for pre-allocating protection domains.
2995 *
2996 * If the driver core informs the DMA layer if a driver grabs a device
2997 * we don't need to preallocate the protection domains anymore.
2998 * For now we have to.
2999 */
3000 static void __init prealloc_protection_domains(void)
3001 {
3002 struct iommu_dev_data *dev_data;
3003 struct dma_ops_domain *dma_dom;
3004 struct pci_dev *dev = NULL;
3005 u16 devid;
3006
3007 for_each_pci_dev(dev) {
3008
3009 /* Do we handle this device? */
3010 if (!check_device(&dev->dev))
3011 continue;
3012
3013 dev_data = get_dev_data(&dev->dev);
3014 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3015 /* Make sure passthrough domain is allocated */
3016 alloc_passthrough_domain();
3017 dev_data->passthrough = true;
3018 attach_device(&dev->dev, pt_domain);
3019 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3020 dev_name(&dev->dev));
3021 }
3022
3023 /* Is there already any domain for it? */
3024 if (domain_for_device(&dev->dev))
3025 continue;
3026
3027 devid = get_device_id(&dev->dev);
3028
3029 dma_dom = dma_ops_domain_alloc();
3030 if (!dma_dom)
3031 continue;
3032 init_unity_mappings_for_device(dma_dom, devid);
3033 dma_dom->target_dev = devid;
3034
3035 attach_device(&dev->dev, &dma_dom->domain);
3036
3037 list_add_tail(&dma_dom->list, &iommu_pd_list);
3038 }
3039 }
3040
3041 static struct dma_map_ops amd_iommu_dma_ops = {
3042 .alloc = alloc_coherent,
3043 .free = free_coherent,
3044 .map_page = map_page,
3045 .unmap_page = unmap_page,
3046 .map_sg = map_sg,
3047 .unmap_sg = unmap_sg,
3048 .dma_supported = amd_iommu_dma_supported,
3049 };
3050
3051 static unsigned device_dma_ops_init(void)
3052 {
3053 struct iommu_dev_data *dev_data;
3054 struct pci_dev *pdev = NULL;
3055 unsigned unhandled = 0;
3056
3057 for_each_pci_dev(pdev) {
3058 if (!check_device(&pdev->dev)) {
3059
3060 iommu_ignore_device(&pdev->dev);
3061
3062 unhandled += 1;
3063 continue;
3064 }
3065
3066 dev_data = get_dev_data(&pdev->dev);
3067
3068 if (!dev_data->passthrough)
3069 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3070 else
3071 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3072 }
3073
3074 return unhandled;
3075 }
3076
3077 /*
3078 * The function which clues the AMD IOMMU driver into dma_ops.
3079 */
3080
3081 void __init amd_iommu_init_api(void)
3082 {
3083 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3084 }
3085
3086 int __init amd_iommu_init_dma_ops(void)
3087 {
3088 struct amd_iommu *iommu;
3089 int ret, unhandled;
3090
3091 /*
3092 * first allocate a default protection domain for every IOMMU we
3093 * found in the system. Devices not assigned to any other
3094 * protection domain will be assigned to the default one.
3095 */
3096 for_each_iommu(iommu) {
3097 iommu->default_dom = dma_ops_domain_alloc();
3098 if (iommu->default_dom == NULL)
3099 return -ENOMEM;
3100 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3101 ret = iommu_init_unity_mappings(iommu);
3102 if (ret)
3103 goto free_domains;
3104 }
3105
3106 /*
3107 * Pre-allocate the protection domains for each device.
3108 */
3109 prealloc_protection_domains();
3110
3111 iommu_detected = 1;
3112 swiotlb = 0;
3113
3114 /* Make the driver finally visible to the drivers */
3115 unhandled = device_dma_ops_init();
3116 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3117 /* There are unhandled devices - initialize swiotlb for them */
3118 swiotlb = 1;
3119 }
3120
3121 amd_iommu_stats_init();
3122
3123 if (amd_iommu_unmap_flush)
3124 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3125 else
3126 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3127
3128 return 0;
3129
3130 free_domains:
3131
3132 for_each_iommu(iommu) {
3133 if (iommu->default_dom)
3134 dma_ops_domain_free(iommu->default_dom);
3135 }
3136
3137 return ret;
3138 }
3139
3140 /*****************************************************************************
3141 *
3142 * The following functions belong to the exported interface of AMD IOMMU
3143 *
3144 * This interface allows access to lower level functions of the IOMMU
3145 * like protection domain handling and assignement of devices to domains
3146 * which is not possible with the dma_ops interface.
3147 *
3148 *****************************************************************************/
3149
3150 static void cleanup_domain(struct protection_domain *domain)
3151 {
3152 struct iommu_dev_data *dev_data, *next;
3153 unsigned long flags;
3154
3155 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3156
3157 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
3158 __detach_device(dev_data);
3159 atomic_set(&dev_data->bind, 0);
3160 }
3161
3162 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3163 }
3164
3165 static void protection_domain_free(struct protection_domain *domain)
3166 {
3167 if (!domain)
3168 return;
3169
3170 del_domain_from_list(domain);
3171
3172 if (domain->id)
3173 domain_id_free(domain->id);
3174
3175 kfree(domain);
3176 }
3177
3178 static struct protection_domain *protection_domain_alloc(void)
3179 {
3180 struct protection_domain *domain;
3181
3182 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3183 if (!domain)
3184 return NULL;
3185
3186 spin_lock_init(&domain->lock);
3187 mutex_init(&domain->api_lock);
3188 domain->id = domain_id_alloc();
3189 if (!domain->id)
3190 goto out_err;
3191 INIT_LIST_HEAD(&domain->dev_list);
3192
3193 add_domain_to_list(domain);
3194
3195 return domain;
3196
3197 out_err:
3198 kfree(domain);
3199
3200 return NULL;
3201 }
3202
3203 static int __init alloc_passthrough_domain(void)
3204 {
3205 if (pt_domain != NULL)
3206 return 0;
3207
3208 /* allocate passthrough domain */
3209 pt_domain = protection_domain_alloc();
3210 if (!pt_domain)
3211 return -ENOMEM;
3212
3213 pt_domain->mode = PAGE_MODE_NONE;
3214
3215 return 0;
3216 }
3217 static int amd_iommu_domain_init(struct iommu_domain *dom)
3218 {
3219 struct protection_domain *domain;
3220
3221 domain = protection_domain_alloc();
3222 if (!domain)
3223 goto out_free;
3224
3225 domain->mode = PAGE_MODE_3_LEVEL;
3226 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3227 if (!domain->pt_root)
3228 goto out_free;
3229
3230 domain->iommu_domain = dom;
3231
3232 dom->priv = domain;
3233
3234 dom->geometry.aperture_start = 0;
3235 dom->geometry.aperture_end = ~0ULL;
3236 dom->geometry.force_aperture = true;
3237
3238 return 0;
3239
3240 out_free:
3241 protection_domain_free(domain);
3242
3243 return -ENOMEM;
3244 }
3245
3246 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3247 {
3248 struct protection_domain *domain = dom->priv;
3249
3250 if (!domain)
3251 return;
3252
3253 if (domain->dev_cnt > 0)
3254 cleanup_domain(domain);
3255
3256 BUG_ON(domain->dev_cnt != 0);
3257
3258 if (domain->mode != PAGE_MODE_NONE)
3259 free_pagetable(domain);
3260
3261 if (domain->flags & PD_IOMMUV2_MASK)
3262 free_gcr3_table(domain);
3263
3264 protection_domain_free(domain);
3265
3266 dom->priv = NULL;
3267 }
3268
3269 static void amd_iommu_detach_device(struct iommu_domain *dom,
3270 struct device *dev)
3271 {
3272 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3273 struct amd_iommu *iommu;
3274 u16 devid;
3275
3276 if (!check_device(dev))
3277 return;
3278
3279 devid = get_device_id(dev);
3280
3281 if (dev_data->domain != NULL)
3282 detach_device(dev);
3283
3284 iommu = amd_iommu_rlookup_table[devid];
3285 if (!iommu)
3286 return;
3287
3288 iommu_completion_wait(iommu);
3289 }
3290
3291 static int amd_iommu_attach_device(struct iommu_domain *dom,
3292 struct device *dev)
3293 {
3294 struct protection_domain *domain = dom->priv;
3295 struct iommu_dev_data *dev_data;
3296 struct amd_iommu *iommu;
3297 int ret;
3298
3299 if (!check_device(dev))
3300 return -EINVAL;
3301
3302 dev_data = dev->archdata.iommu;
3303
3304 iommu = amd_iommu_rlookup_table[dev_data->devid];
3305 if (!iommu)
3306 return -EINVAL;
3307
3308 if (dev_data->domain)
3309 detach_device(dev);
3310
3311 ret = attach_device(dev, domain);
3312
3313 iommu_completion_wait(iommu);
3314
3315 return ret;
3316 }
3317
3318 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3319 phys_addr_t paddr, size_t page_size, int iommu_prot)
3320 {
3321 struct protection_domain *domain = dom->priv;
3322 int prot = 0;
3323 int ret;
3324
3325 if (domain->mode == PAGE_MODE_NONE)
3326 return -EINVAL;
3327
3328 if (iommu_prot & IOMMU_READ)
3329 prot |= IOMMU_PROT_IR;
3330 if (iommu_prot & IOMMU_WRITE)
3331 prot |= IOMMU_PROT_IW;
3332
3333 mutex_lock(&domain->api_lock);
3334 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3335 mutex_unlock(&domain->api_lock);
3336
3337 return ret;
3338 }
3339
3340 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3341 size_t page_size)
3342 {
3343 struct protection_domain *domain = dom->priv;
3344 size_t unmap_size;
3345
3346 if (domain->mode == PAGE_MODE_NONE)
3347 return -EINVAL;
3348
3349 mutex_lock(&domain->api_lock);
3350 unmap_size = iommu_unmap_page(domain, iova, page_size);
3351 mutex_unlock(&domain->api_lock);
3352
3353 domain_flush_tlb_pde(domain);
3354
3355 return unmap_size;
3356 }
3357
3358 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3359 unsigned long iova)
3360 {
3361 struct protection_domain *domain = dom->priv;
3362 unsigned long offset_mask;
3363 phys_addr_t paddr;
3364 u64 *pte, __pte;
3365
3366 if (domain->mode == PAGE_MODE_NONE)
3367 return iova;
3368
3369 pte = fetch_pte(domain, iova);
3370
3371 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3372 return 0;
3373
3374 if (PM_PTE_LEVEL(*pte) == 0)
3375 offset_mask = PAGE_SIZE - 1;
3376 else
3377 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3378
3379 __pte = *pte & PM_ADDR_MASK;
3380 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3381
3382 return paddr;
3383 }
3384
3385 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3386 unsigned long cap)
3387 {
3388 switch (cap) {
3389 case IOMMU_CAP_CACHE_COHERENCY:
3390 return 1;
3391 case IOMMU_CAP_INTR_REMAP:
3392 return irq_remapping_enabled;
3393 }
3394
3395 return 0;
3396 }
3397
3398 static struct iommu_ops amd_iommu_ops = {
3399 .domain_init = amd_iommu_domain_init,
3400 .domain_destroy = amd_iommu_domain_destroy,
3401 .attach_dev = amd_iommu_attach_device,
3402 .detach_dev = amd_iommu_detach_device,
3403 .map = amd_iommu_map,
3404 .unmap = amd_iommu_unmap,
3405 .iova_to_phys = amd_iommu_iova_to_phys,
3406 .domain_has_cap = amd_iommu_domain_has_cap,
3407 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3408 };
3409
3410 /*****************************************************************************
3411 *
3412 * The next functions do a basic initialization of IOMMU for pass through
3413 * mode
3414 *
3415 * In passthrough mode the IOMMU is initialized and enabled but not used for
3416 * DMA-API translation.
3417 *
3418 *****************************************************************************/
3419
3420 int __init amd_iommu_init_passthrough(void)
3421 {
3422 struct iommu_dev_data *dev_data;
3423 struct pci_dev *dev = NULL;
3424 struct amd_iommu *iommu;
3425 u16 devid;
3426 int ret;
3427
3428 ret = alloc_passthrough_domain();
3429 if (ret)
3430 return ret;
3431
3432 for_each_pci_dev(dev) {
3433 if (!check_device(&dev->dev))
3434 continue;
3435
3436 dev_data = get_dev_data(&dev->dev);
3437 dev_data->passthrough = true;
3438
3439 devid = get_device_id(&dev->dev);
3440
3441 iommu = amd_iommu_rlookup_table[devid];
3442 if (!iommu)
3443 continue;
3444
3445 attach_device(&dev->dev, pt_domain);
3446 }
3447
3448 amd_iommu_stats_init();
3449
3450 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3451
3452 return 0;
3453 }
3454
3455 /* IOMMUv2 specific functions */
3456 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3457 {
3458 return atomic_notifier_chain_register(&ppr_notifier, nb);
3459 }
3460 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3461
3462 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3463 {
3464 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3465 }
3466 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3467
3468 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3469 {
3470 struct protection_domain *domain = dom->priv;
3471 unsigned long flags;
3472
3473 spin_lock_irqsave(&domain->lock, flags);
3474
3475 /* Update data structure */
3476 domain->mode = PAGE_MODE_NONE;
3477 domain->updated = true;
3478
3479 /* Make changes visible to IOMMUs */
3480 update_domain(domain);
3481
3482 /* Page-table is not visible to IOMMU anymore, so free it */
3483 free_pagetable(domain);
3484
3485 spin_unlock_irqrestore(&domain->lock, flags);
3486 }
3487 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3488
3489 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3490 {
3491 struct protection_domain *domain = dom->priv;
3492 unsigned long flags;
3493 int levels, ret;
3494
3495 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3496 return -EINVAL;
3497
3498 /* Number of GCR3 table levels required */
3499 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3500 levels += 1;
3501
3502 if (levels > amd_iommu_max_glx_val)
3503 return -EINVAL;
3504
3505 spin_lock_irqsave(&domain->lock, flags);
3506
3507 /*
3508 * Save us all sanity checks whether devices already in the
3509 * domain support IOMMUv2. Just force that the domain has no
3510 * devices attached when it is switched into IOMMUv2 mode.
3511 */
3512 ret = -EBUSY;
3513 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3514 goto out;
3515
3516 ret = -ENOMEM;
3517 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3518 if (domain->gcr3_tbl == NULL)
3519 goto out;
3520
3521 domain->glx = levels;
3522 domain->flags |= PD_IOMMUV2_MASK;
3523 domain->updated = true;
3524
3525 update_domain(domain);
3526
3527 ret = 0;
3528
3529 out:
3530 spin_unlock_irqrestore(&domain->lock, flags);
3531
3532 return ret;
3533 }
3534 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3535
3536 static int __flush_pasid(struct protection_domain *domain, int pasid,
3537 u64 address, bool size)
3538 {
3539 struct iommu_dev_data *dev_data;
3540 struct iommu_cmd cmd;
3541 int i, ret;
3542
3543 if (!(domain->flags & PD_IOMMUV2_MASK))
3544 return -EINVAL;
3545
3546 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3547
3548 /*
3549 * IOMMU TLB needs to be flushed before Device TLB to
3550 * prevent device TLB refill from IOMMU TLB
3551 */
3552 for (i = 0; i < amd_iommus_present; ++i) {
3553 if (domain->dev_iommu[i] == 0)
3554 continue;
3555
3556 ret = iommu_queue_command(amd_iommus[i], &cmd);
3557 if (ret != 0)
3558 goto out;
3559 }
3560
3561 /* Wait until IOMMU TLB flushes are complete */
3562 domain_flush_complete(domain);
3563
3564 /* Now flush device TLBs */
3565 list_for_each_entry(dev_data, &domain->dev_list, list) {
3566 struct amd_iommu *iommu;
3567 int qdep;
3568
3569 BUG_ON(!dev_data->ats.enabled);
3570
3571 qdep = dev_data->ats.qdep;
3572 iommu = amd_iommu_rlookup_table[dev_data->devid];
3573
3574 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3575 qdep, address, size);
3576
3577 ret = iommu_queue_command(iommu, &cmd);
3578 if (ret != 0)
3579 goto out;
3580 }
3581
3582 /* Wait until all device TLBs are flushed */
3583 domain_flush_complete(domain);
3584
3585 ret = 0;
3586
3587 out:
3588
3589 return ret;
3590 }
3591
3592 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3593 u64 address)
3594 {
3595 INC_STATS_COUNTER(invalidate_iotlb);
3596
3597 return __flush_pasid(domain, pasid, address, false);
3598 }
3599
3600 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3601 u64 address)
3602 {
3603 struct protection_domain *domain = dom->priv;
3604 unsigned long flags;
3605 int ret;
3606
3607 spin_lock_irqsave(&domain->lock, flags);
3608 ret = __amd_iommu_flush_page(domain, pasid, address);
3609 spin_unlock_irqrestore(&domain->lock, flags);
3610
3611 return ret;
3612 }
3613 EXPORT_SYMBOL(amd_iommu_flush_page);
3614
3615 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3616 {
3617 INC_STATS_COUNTER(invalidate_iotlb_all);
3618
3619 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3620 true);
3621 }
3622
3623 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3624 {
3625 struct protection_domain *domain = dom->priv;
3626 unsigned long flags;
3627 int ret;
3628
3629 spin_lock_irqsave(&domain->lock, flags);
3630 ret = __amd_iommu_flush_tlb(domain, pasid);
3631 spin_unlock_irqrestore(&domain->lock, flags);
3632
3633 return ret;
3634 }
3635 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3636
3637 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3638 {
3639 int index;
3640 u64 *pte;
3641
3642 while (true) {
3643
3644 index = (pasid >> (9 * level)) & 0x1ff;
3645 pte = &root[index];
3646
3647 if (level == 0)
3648 break;
3649
3650 if (!(*pte & GCR3_VALID)) {
3651 if (!alloc)
3652 return NULL;
3653
3654 root = (void *)get_zeroed_page(GFP_ATOMIC);
3655 if (root == NULL)
3656 return NULL;
3657
3658 *pte = __pa(root) | GCR3_VALID;
3659 }
3660
3661 root = __va(*pte & PAGE_MASK);
3662
3663 level -= 1;
3664 }
3665
3666 return pte;
3667 }
3668
3669 static int __set_gcr3(struct protection_domain *domain, int pasid,
3670 unsigned long cr3)
3671 {
3672 u64 *pte;
3673
3674 if (domain->mode != PAGE_MODE_NONE)
3675 return -EINVAL;
3676
3677 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3678 if (pte == NULL)
3679 return -ENOMEM;
3680
3681 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3682
3683 return __amd_iommu_flush_tlb(domain, pasid);
3684 }
3685
3686 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3687 {
3688 u64 *pte;
3689
3690 if (domain->mode != PAGE_MODE_NONE)
3691 return -EINVAL;
3692
3693 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3694 if (pte == NULL)
3695 return 0;
3696
3697 *pte = 0;
3698
3699 return __amd_iommu_flush_tlb(domain, pasid);
3700 }
3701
3702 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3703 unsigned long cr3)
3704 {
3705 struct protection_domain *domain = dom->priv;
3706 unsigned long flags;
3707 int ret;
3708
3709 spin_lock_irqsave(&domain->lock, flags);
3710 ret = __set_gcr3(domain, pasid, cr3);
3711 spin_unlock_irqrestore(&domain->lock, flags);
3712
3713 return ret;
3714 }
3715 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3716
3717 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3718 {
3719 struct protection_domain *domain = dom->priv;
3720 unsigned long flags;
3721 int ret;
3722
3723 spin_lock_irqsave(&domain->lock, flags);
3724 ret = __clear_gcr3(domain, pasid);
3725 spin_unlock_irqrestore(&domain->lock, flags);
3726
3727 return ret;
3728 }
3729 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3730
3731 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3732 int status, int tag)
3733 {
3734 struct iommu_dev_data *dev_data;
3735 struct amd_iommu *iommu;
3736 struct iommu_cmd cmd;
3737
3738 INC_STATS_COUNTER(complete_ppr);
3739
3740 dev_data = get_dev_data(&pdev->dev);
3741 iommu = amd_iommu_rlookup_table[dev_data->devid];
3742
3743 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3744 tag, dev_data->pri_tlp);
3745
3746 return iommu_queue_command(iommu, &cmd);
3747 }
3748 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3749
3750 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3751 {
3752 struct protection_domain *domain;
3753
3754 domain = get_domain(&pdev->dev);
3755 if (IS_ERR(domain))
3756 return NULL;
3757
3758 /* Only return IOMMUv2 domains */
3759 if (!(domain->flags & PD_IOMMUV2_MASK))
3760 return NULL;
3761
3762 return domain->iommu_domain;
3763 }
3764 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3765
3766 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3767 {
3768 struct iommu_dev_data *dev_data;
3769
3770 if (!amd_iommu_v2_supported())
3771 return;
3772
3773 dev_data = get_dev_data(&pdev->dev);
3774 dev_data->errata |= (1 << erratum);
3775 }
3776 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3777
3778 int amd_iommu_device_info(struct pci_dev *pdev,
3779 struct amd_iommu_device_info *info)
3780 {
3781 int max_pasids;
3782 int pos;
3783
3784 if (pdev == NULL || info == NULL)
3785 return -EINVAL;
3786
3787 if (!amd_iommu_v2_supported())
3788 return -EINVAL;
3789
3790 memset(info, 0, sizeof(*info));
3791
3792 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3793 if (pos)
3794 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3795
3796 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3797 if (pos)
3798 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3799
3800 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3801 if (pos) {
3802 int features;
3803
3804 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3805 max_pasids = min(max_pasids, (1 << 20));
3806
3807 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3808 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3809
3810 features = pci_pasid_features(pdev);
3811 if (features & PCI_PASID_CAP_EXEC)
3812 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3813 if (features & PCI_PASID_CAP_PRIV)
3814 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3815 }
3816
3817 return 0;
3818 }
3819 EXPORT_SYMBOL(amd_iommu_device_info);
3820
3821 #ifdef CONFIG_IRQ_REMAP
3822
3823 /*****************************************************************************
3824 *
3825 * Interrupt Remapping Implementation
3826 *
3827 *****************************************************************************/
3828
3829 union irte {
3830 u32 val;
3831 struct {
3832 u32 valid : 1,
3833 no_fault : 1,
3834 int_type : 3,
3835 rq_eoi : 1,
3836 dm : 1,
3837 rsvd_1 : 1,
3838 destination : 8,
3839 vector : 8,
3840 rsvd_2 : 8;
3841 } fields;
3842 };
3843
3844 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3845 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3846 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3847 #define DTE_IRQ_REMAP_ENABLE 1ULL
3848
3849 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3850 {
3851 u64 dte;
3852
3853 dte = amd_iommu_dev_table[devid].data[2];
3854 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3855 dte |= virt_to_phys(table->table);
3856 dte |= DTE_IRQ_REMAP_INTCTL;
3857 dte |= DTE_IRQ_TABLE_LEN;
3858 dte |= DTE_IRQ_REMAP_ENABLE;
3859
3860 amd_iommu_dev_table[devid].data[2] = dte;
3861 }
3862
3863 #define IRTE_ALLOCATED (~1U)
3864
3865 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3866 {
3867 struct irq_remap_table *table = NULL;
3868 struct amd_iommu *iommu;
3869 unsigned long flags;
3870 u16 alias;
3871
3872 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3873
3874 iommu = amd_iommu_rlookup_table[devid];
3875 if (!iommu)
3876 goto out_unlock;
3877
3878 table = irq_lookup_table[devid];
3879 if (table)
3880 goto out;
3881
3882 alias = amd_iommu_alias_table[devid];
3883 table = irq_lookup_table[alias];
3884 if (table) {
3885 irq_lookup_table[devid] = table;
3886 set_dte_irq_entry(devid, table);
3887 iommu_flush_dte(iommu, devid);
3888 goto out;
3889 }
3890
3891 /* Nothing there yet, allocate new irq remapping table */
3892 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3893 if (!table)
3894 goto out;
3895
3896 if (ioapic)
3897 /* Keep the first 32 indexes free for IOAPIC interrupts */
3898 table->min_index = 32;
3899
3900 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3901 if (!table->table) {
3902 kfree(table);
3903 table = NULL;
3904 goto out;
3905 }
3906
3907 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3908
3909 if (ioapic) {
3910 int i;
3911
3912 for (i = 0; i < 32; ++i)
3913 table->table[i] = IRTE_ALLOCATED;
3914 }
3915
3916 irq_lookup_table[devid] = table;
3917 set_dte_irq_entry(devid, table);
3918 iommu_flush_dte(iommu, devid);
3919 if (devid != alias) {
3920 irq_lookup_table[alias] = table;
3921 set_dte_irq_entry(devid, table);
3922 iommu_flush_dte(iommu, alias);
3923 }
3924
3925 out:
3926 iommu_completion_wait(iommu);
3927
3928 out_unlock:
3929 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3930
3931 return table;
3932 }
3933
3934 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3935 {
3936 struct irq_remap_table *table;
3937 unsigned long flags;
3938 int index, c;
3939
3940 table = get_irq_table(devid, false);
3941 if (!table)
3942 return -ENODEV;
3943
3944 spin_lock_irqsave(&table->lock, flags);
3945
3946 /* Scan table for free entries */
3947 for (c = 0, index = table->min_index;
3948 index < MAX_IRQS_PER_TABLE;
3949 ++index) {
3950 if (table->table[index] == 0)
3951 c += 1;
3952 else
3953 c = 0;
3954
3955 if (c == count) {
3956 struct irq_2_iommu *irte_info;
3957
3958 for (; c != 0; --c)
3959 table->table[index - c + 1] = IRTE_ALLOCATED;
3960
3961 index -= count - 1;
3962
3963 irte_info = &cfg->irq_2_iommu;
3964 irte_info->sub_handle = devid;
3965 irte_info->irte_index = index;
3966 irte_info->iommu = (void *)cfg;
3967
3968 goto out;
3969 }
3970 }
3971
3972 index = -ENOSPC;
3973
3974 out:
3975 spin_unlock_irqrestore(&table->lock, flags);
3976
3977 return index;
3978 }
3979
3980 static int get_irte(u16 devid, int index, union irte *irte)
3981 {
3982 struct irq_remap_table *table;
3983 unsigned long flags;
3984
3985 table = get_irq_table(devid, false);
3986 if (!table)
3987 return -ENOMEM;
3988
3989 spin_lock_irqsave(&table->lock, flags);
3990 irte->val = table->table[index];
3991 spin_unlock_irqrestore(&table->lock, flags);
3992
3993 return 0;
3994 }
3995
3996 static int modify_irte(u16 devid, int index, union irte irte)
3997 {
3998 struct irq_remap_table *table;
3999 struct amd_iommu *iommu;
4000 unsigned long flags;
4001
4002 iommu = amd_iommu_rlookup_table[devid];
4003 if (iommu == NULL)
4004 return -EINVAL;
4005
4006 table = get_irq_table(devid, false);
4007 if (!table)
4008 return -ENOMEM;
4009
4010 spin_lock_irqsave(&table->lock, flags);
4011 table->table[index] = irte.val;
4012 spin_unlock_irqrestore(&table->lock, flags);
4013
4014 iommu_flush_irt(iommu, devid);
4015 iommu_completion_wait(iommu);
4016
4017 return 0;
4018 }
4019
4020 static void free_irte(u16 devid, int index)
4021 {
4022 struct irq_remap_table *table;
4023 struct amd_iommu *iommu;
4024 unsigned long flags;
4025
4026 iommu = amd_iommu_rlookup_table[devid];
4027 if (iommu == NULL)
4028 return;
4029
4030 table = get_irq_table(devid, false);
4031 if (!table)
4032 return;
4033
4034 spin_lock_irqsave(&table->lock, flags);
4035 table->table[index] = 0;
4036 spin_unlock_irqrestore(&table->lock, flags);
4037
4038 iommu_flush_irt(iommu, devid);
4039 iommu_completion_wait(iommu);
4040 }
4041
4042 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4043 unsigned int destination, int vector,
4044 struct io_apic_irq_attr *attr)
4045 {
4046 struct irq_remap_table *table;
4047 struct irq_2_iommu *irte_info;
4048 struct irq_cfg *cfg;
4049 union irte irte;
4050 int ioapic_id;
4051 int index;
4052 int devid;
4053 int ret;
4054
4055 cfg = irq_get_chip_data(irq);
4056 if (!cfg)
4057 return -EINVAL;
4058
4059 irte_info = &cfg->irq_2_iommu;
4060 ioapic_id = mpc_ioapic_id(attr->ioapic);
4061 devid = get_ioapic_devid(ioapic_id);
4062
4063 if (devid < 0)
4064 return devid;
4065
4066 table = get_irq_table(devid, true);
4067 if (table == NULL)
4068 return -ENOMEM;
4069
4070 index = attr->ioapic_pin;
4071
4072 /* Setup IRQ remapping info */
4073 irte_info->sub_handle = devid;
4074 irte_info->irte_index = index;
4075 irte_info->iommu = (void *)cfg;
4076
4077 /* Setup IRTE for IOMMU */
4078 irte.val = 0;
4079 irte.fields.vector = vector;
4080 irte.fields.int_type = apic->irq_delivery_mode;
4081 irte.fields.destination = destination;
4082 irte.fields.dm = apic->irq_dest_mode;
4083 irte.fields.valid = 1;
4084
4085 ret = modify_irte(devid, index, irte);
4086 if (ret)
4087 return ret;
4088
4089 /* Setup IOAPIC entry */
4090 memset(entry, 0, sizeof(*entry));
4091
4092 entry->vector = index;
4093 entry->mask = 0;
4094 entry->trigger = attr->trigger;
4095 entry->polarity = attr->polarity;
4096
4097 /*
4098 * Mask level triggered irqs.
4099 */
4100 if (attr->trigger)
4101 entry->mask = 1;
4102
4103 return 0;
4104 }
4105
4106 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4107 bool force)
4108 {
4109 struct irq_2_iommu *irte_info;
4110 unsigned int dest, irq;
4111 struct irq_cfg *cfg;
4112 union irte irte;
4113 int err;
4114
4115 if (!config_enabled(CONFIG_SMP))
4116 return -1;
4117
4118 cfg = data->chip_data;
4119 irq = data->irq;
4120 irte_info = &cfg->irq_2_iommu;
4121
4122 if (!cpumask_intersects(mask, cpu_online_mask))
4123 return -EINVAL;
4124
4125 if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte))
4126 return -EBUSY;
4127
4128 if (assign_irq_vector(irq, cfg, mask))
4129 return -EBUSY;
4130
4131 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4132 if (err) {
4133 if (assign_irq_vector(irq, cfg, data->affinity))
4134 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4135 return err;
4136 }
4137
4138 irte.fields.vector = cfg->vector;
4139 irte.fields.destination = dest;
4140
4141 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4142
4143 if (cfg->move_in_progress)
4144 send_cleanup_vector(cfg);
4145
4146 cpumask_copy(data->affinity, mask);
4147
4148 return 0;
4149 }
4150
4151 static int free_irq(int irq)
4152 {
4153 struct irq_2_iommu *irte_info;
4154 struct irq_cfg *cfg;
4155
4156 cfg = irq_get_chip_data(irq);
4157 if (!cfg)
4158 return -EINVAL;
4159
4160 irte_info = &cfg->irq_2_iommu;
4161
4162 free_irte(irte_info->sub_handle, irte_info->irte_index);
4163
4164 return 0;
4165 }
4166
4167 static void compose_msi_msg(struct pci_dev *pdev,
4168 unsigned int irq, unsigned int dest,
4169 struct msi_msg *msg, u8 hpet_id)
4170 {
4171 struct irq_2_iommu *irte_info;
4172 struct irq_cfg *cfg;
4173 union irte irte;
4174
4175 cfg = irq_get_chip_data(irq);
4176 if (!cfg)
4177 return;
4178
4179 irte_info = &cfg->irq_2_iommu;
4180
4181 irte.val = 0;
4182 irte.fields.vector = cfg->vector;
4183 irte.fields.int_type = apic->irq_delivery_mode;
4184 irte.fields.destination = dest;
4185 irte.fields.dm = apic->irq_dest_mode;
4186 irte.fields.valid = 1;
4187
4188 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4189
4190 msg->address_hi = MSI_ADDR_BASE_HI;
4191 msg->address_lo = MSI_ADDR_BASE_LO;
4192 msg->data = irte_info->irte_index;
4193 }
4194
4195 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4196 {
4197 struct irq_cfg *cfg;
4198 int index;
4199 u16 devid;
4200
4201 if (!pdev)
4202 return -EINVAL;
4203
4204 cfg = irq_get_chip_data(irq);
4205 if (!cfg)
4206 return -EINVAL;
4207
4208 devid = get_device_id(&pdev->dev);
4209 index = alloc_irq_index(cfg, devid, nvec);
4210
4211 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4212 }
4213
4214 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4215 int index, int offset)
4216 {
4217 struct irq_2_iommu *irte_info;
4218 struct irq_cfg *cfg;
4219 u16 devid;
4220
4221 if (!pdev)
4222 return -EINVAL;
4223
4224 cfg = irq_get_chip_data(irq);
4225 if (!cfg)
4226 return -EINVAL;
4227
4228 if (index >= MAX_IRQS_PER_TABLE)
4229 return 0;
4230
4231 devid = get_device_id(&pdev->dev);
4232 irte_info = &cfg->irq_2_iommu;
4233
4234 irte_info->sub_handle = devid;
4235 irte_info->irte_index = index + offset;
4236 irte_info->iommu = (void *)cfg;
4237
4238 return 0;
4239 }
4240
4241 static int setup_hpet_msi(unsigned int irq, unsigned int id)
4242 {
4243 struct irq_2_iommu *irte_info;
4244 struct irq_cfg *cfg;
4245 int index, devid;
4246
4247 cfg = irq_get_chip_data(irq);
4248 if (!cfg)
4249 return -EINVAL;
4250
4251 irte_info = &cfg->irq_2_iommu;
4252 devid = get_hpet_devid(id);
4253 if (devid < 0)
4254 return devid;
4255
4256 index = alloc_irq_index(cfg, devid, 1);
4257 if (index < 0)
4258 return index;
4259
4260 irte_info->sub_handle = devid;
4261 irte_info->irte_index = index;
4262 irte_info->iommu = (void *)cfg;
4263
4264 return 0;
4265 }
4266
4267 struct irq_remap_ops amd_iommu_irq_ops = {
4268 .supported = amd_iommu_supported,
4269 .prepare = amd_iommu_prepare,
4270 .enable = amd_iommu_enable,
4271 .disable = amd_iommu_disable,
4272 .reenable = amd_iommu_reenable,
4273 .enable_faulting = amd_iommu_enable_faulting,
4274 .setup_ioapic_entry = setup_ioapic_entry,
4275 .set_affinity = set_affinity,
4276 .free_irq = free_irq,
4277 .compose_msi_msg = compose_msi_msg,
4278 .msi_alloc_irq = msi_alloc_irq,
4279 .msi_setup_irq = msi_setup_irq,
4280 .setup_hpet_msi = setup_hpet_msi,
4281 };
4282 #endif
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